MAX16070 [MAXIM]
12-Channel/8-Channel, Flash-Configurable System Monitors with Nonvolatile Fault Registers; 12通道/ 8通道，闪存配置系统监测器，提供非易失故障寄存器
| 型号： | MAX16070 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Channel/8-Channel, Flash-Configurable System Monitors with Nonvolatile Fault Registers |
| 文件： | 总52页 (文件大小：1946K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5003; Rev 3; 8/11
12-Channel/8-Channel, Flash-Configurable System
Monitors with Nonvolatile Fault Registers
General Description
Features
The MAX16070/MAX16071 flash-configurable sys-
tem monitors supervise multiple system voltages. The
MAX16070/MAX16071 can also accurately monitor
(Q2.5%) one current channel using a dedicated high-
side current-sense amplifier. The MAX16070 monitors
up to twelve system voltages simultaneously, and the
MAX16071 monitors up to eight supply voltages. These
devices integrate a selectable differential or single-end-
ed analog-to-digital converter (ADC). Device configura-
tion information, including overvoltage and undervoltage
limits and timing settings are stored in nonvolatile flash
memory. During a fault condition, fault flags and channel
voltages can be automatically stored in the nonvolatile
flash memory for later read-back.
S Operate from 2.8V to 14V
2.5% Current-Monitoring Accuracy
S
S 1% Accurate 10-Bit ADC Monitors 12/8 Voltage
Inputs
S Single-Ended or Differential ADC for System
Voltage/Current Monitoring
S Integrated High-Side, Current-Sense Amplifier
S 12/8 Monitored Inputs with Overvoltage/
Undervoltage/Early Warning Limit
S Nonvolatile Fault Event Logger
S Two Programmable Fault Outputs and One Reset
Output
The internal 1% accurate 10-bit ADC measures each
input and compares the result to one overvoltage, one
undervoltage, and one early warning limit that can be
configured as either undervoltage or overvoltage. A fault
signal asserts when a monitored voltage falls outside the
set limits. Up to three independent fault output signals
are configurable to assert under various fault conditions.
S Eight General-Purpose Inputs/Outputs
Configurable as:
Dedicated Fault Outputs
Watchdog Timer Function
Manual Reset
Margin Enable
S SMBus (with Timeout) or JTAG Interface
S Flash Configurable Time Delays and Thresholds
S -40NC to +85NC Operating Temperature Range
Because the MAX16070/MAX16071 support a power-
supply voltage of up to 14V, they can be powered
directly from the 12V intermediate bus in many systems.
The MAX16070/MAX16071 include eight/six program-
mable general-purpose inputs/outputs (GPIOs). GPIOs
are flash configurable as dedicated fault outputs, as a
watchdog input or output, or as a manual reset.
Ordering Information
PART
TEMP RANGE
-40NC to +85NC
-40NC to +85NC
PIN-PACKAGE
40 TQFN-EP*
40 TQFN-EP*
MAX16070ETL+
MAX16071ETL+
The MAX16070/MAX16071 feature nonvolatile fault mem-
ory for recording information during system shutdown
events. The fault logger records a failure in the internal
flash and sets a lock bit protecting the stored fault data
from accidental erasure. An SMBus™ or a JTAG serial
interface configures the MAX16070/MAX16071. The
MAX16070/MAX16071 are available in a 40-pin, 6mm x
6mm, TQFN package. Both devices are fully specified
from -40NC to +85NC.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Applications
Networking Equipment
Telecom Equipment (Base Stations, Access)
Storage/RAID Systems
Servers
Pin Configuration and Typical Operating Circuits appear at
end of data sheet.
SMBus is a trademark of Intel Corp.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ABSOLUTE MAXIMUM RATINGS
V
CC
, CSP, CSM to GND........................................-0.3V to +15V
Input/Output Current .........................................................20mA
CSP to CSM..........................................................-0.7V to +0.7V
MON_, GPIO_, SCL, SDA, A0, RESET to GND
(programmed as open-drain outputs).................-0.3V to +6V
EN, TCK, TMS, TDI to GND ....................................-0.3V to +4V
Continuous Power Dissipation (T = +70NC)
A
40-Pin TQFN (derate 26.3mW/NC above +70NC).......2105mW
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature ....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
DBP, ABP to GND...-0.3V to the lower of +3V and (V
TDO, GPIO_, RESET
+ 0.3V)
CC
(programmed as push-pull outputs) .... -0.3V to (V
+ 0.3V)
DBP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.8V to 14V, T = -40NC to +85NC, unless otherwise specified. Typical values are at V
= V
= V = 3.3V, T = +25NC.)
CC A
A
ABP
DBP
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
Reset output asserted low
(Note 2)
MIN
TYP
MAX
UNITS
1.2
2.8
Operating Voltage Range
V
CC
V
14
Minimum voltage on V
device is flash configurable
to ensure the
CC
Undervoltage Lockout (Rising)
Undervoltage Lockout Hysteresis
V
2.7
V
mV
V
UVLO
V
100
UVLO_HYS
Minimum Flash Operating
Voltage
Minimum voltage on V
to ensure flash
CC
V
2.7
flash
erase and write operations
No load on output pins
During flash writing cycle
4.5
10
3
7
Supply Current
I
mA
CC
14
ABP Regulator Voltage
DBP Regulator Voltage
Boot Time
V
V
C
C
= 1μF, no load, V
= 1μF, no load, V
= 5V
= 5V
2.85
2.8
3.15
3.1
350
V
V
ABP
ABP
DBP
CC
CC
CC
3
DBP
t
V
> V
200
122
μs
ms
%
BOOT
UVLO
Flash Writing Time
Internal Timing Accuracy
8-byte word
(Note 3)
-8
+8
V
EN voltage rising
EN voltage falling
1.41
1.39
TH_EN_R
EN Input Voltage
V
V
1.365
-0.5
0
1.415
+0.5
5.5
TH_EN_F
EN Input Current
I
μA
V
EN
Input Voltage Range
2
______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.8V to 14V, T = -40NC to +85NC, unless otherwise specified. Typical values are at V
= V
= V = 3.3V, T = +25NC.)
CC A
A
ABP
DBP
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC ACCURACY
Resolution
10
0.35
0.70
1
Bits
%
T
T
= +25°C
= -40°C to +85°C
A
A
Gain Error
ADC
GAIN
Offset Error
ADC
LSB
LSB
LSB
μs
OFF
Integral Nonlinearity
Differential Nonlinearity
ADC Total Monitoring Cycle Time
ADC
1
1
INL
DNL
ADC
t
No MON_ fault detected
1 LSB = 5.43mV
40
50
CYCLE
5.56
2.78
1.39
ADC IN_ Ranges
1 LSB = 2.72mV
V
1 LSB = 1.36mV
CURRENT SENSE
CSP Input-Voltage Range
V
3
14
25
V
CSP
I
14
3
CSP
Input Bias Current
μA
I
V
= V
CSM
5
CSM
CSP
CSP Total Unadjusted Error
CSP
(Note 4)
2
%FSR
ERR
Gain = 48
21.5
46
25
51
30.5
56
Gain = 24
Gain = 12
Gain = 6
Overcurrent Differential
Threshold
V
V
-
CSP
CSM
OVC
mV
TH
94
101
202
108
210
190
V
Fault Threshold
SENSE
OVC
OVC
0.5
%OVC
ms
HYS
DEL
TH
Hysteresis
r73h[6:5] = ‘00’
r73h[6:5] = ‘01’
r73h[6:5] = ‘10’
r73h[6:5] = ‘11’
Gain = 6
0
4
3
5
Secondary Overcurrent Threshold
Timeout
12
50
16
20
60
64
232
116
58
Gain = 12
V
Ranges
mV
SENSE
Gain = 24
Gain = 48
29
V
V
V
V
V
= 150mV (gain = 6 only)
= 50mV, gain = 12
= 25mV, gain = 24
= 10mV, gain = 48
-2.5
-4
Q0.2
Q0.2
Q0.5
Q1
+2.5
+4
SENSE
SENSE
SENSE
SENSE
SENSE
ADC Current Measurement
Accuracy
%
%
= 20mV to 100mV, V
= 5V,
CSP
Gain Accuracy
-1.5
+1.5
gain = 6
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
CMRR
V
CSP
> 4V
80
80
dB
dB
SNS
PSRR
SNS
_______________________________________________________________________________________
3
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.8V to 14V, T = -40NC to +85NC, unless otherwise specified. Typical values are at V
= V
= V = 3.3V, T = +25NC.)
CC A
A
ABP
DBP
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS (RESET, GPIO_)
I
I
= 2mA
0.4
0.7
0.3
SINK
SINK
Output-Voltage Low
V
OL
= 10mA, GPIO_ only
= 1.2V, I = 100μA (RESET only)
V
V
CC
SINK
Total current into RESET, GPIO_,
= 3.3V
Maximum Output Sink Current
30
mA
V
CC
Output-Voltage High (Push-Pull)
Output Leakage (Open Drain)
SMBus INTERFACE
Logic-Input Low Voltage
Logic-Input High Voltage
Input Leakage Current
Output Sink Current
Input Capacitance
I
= 100μA
2.4
V
SOURCE
1
μA
V
Input voltage falling
Input voltage rising
0.8
V
V
IL
V
IH
2.0
-1
IN = GND or V
CC
+1
μA
V
V
OL
I
= 3mA
SINK
0.4
C
5
pF
ms
IN
TIMEOUT
SMBus Timeout
t
SCL time low for reset
25
35
INPUTS (A0, GPIO_)
Input Logic-Low
V
IL
0.8
V
Input Logic-High
V
2.0
100
1
V
IH
WDI Pulse Width
t
ns
μs
μs
ns
WDI
t
MR Pulse Width
MR
0.5
MR to RESET Delay
MR Glitch Rejection
SMBus TIMING
100
Serial Clock Frequency
f
400
kHz
μs
SCL
BUF
Bus Free Time Between STOP
and START Condition
t
1.3
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
t
0.6
0.6
0.6
1.3
0.6
100
μs
μs
μs
μs
μs
ns
SU:STA
HD:STA
SU:STO
t
t
t
LOW
Clock High Period
t
HIGH
Data Setup Time
t
SU:DAT
4
______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.8V to 14V, T = -40NC to +85NC, unless otherwise specified. Typical values are at V
= V
= V = 3.3V, T = +25NC.)
CC A
A
ABP
DBP
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
= 10pF to 400pF
MIN
0.3
TYP
MAX
250
0.9
UNITS
ns
Output Fall Time
t
C
BUS
OF
HD:DAT
Data Hold Time
t
From 50% SCL falling to SDA change
μs
Pulse Width of Spike Suppressed
JTAG INTERFACE
t
SP
30
ns
TDI, TMS, TCK Logic-Low Input
Voltage
V
Input voltage falling
Input voltage rising
0.8
V
V
IL
TDI, TMS, TCK Logic-High Input
Voltage
V
IH
2
TDO Logic-Output Low Voltage
TDO Logic-Output High Voltage
TDI, TMS Pullup Resistors
I/O Capacitance
V
I
I
= 3mA
0.4
60
V
V
OL
SINK
V
OH
= 200μA
2.4
40
SOURCE
R
C
Pullup to DBP
50
5
kω
pF
ns
ns
ns
ns
ns
ns
PU
I/O
TCK Clock Period
t
1000
1
TCK High/Low Time
t
t
50
15
10
500
2, 3
TCK to TMS, TDI Setup Time
TCK to TMS, TDI Hold Time
TCK to TDO Delay
t
t
t
t
4
5
6
7
500
500
TCK to TDO High-Z Delay
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at T
=
A
+25NC and T = +85NC. Specifications at T = -40NC are guaranteed by design.
A
A
Note 2: For 3.3V V
applications, connect V , DBP, and ABP together. For higher supply applications, connect V
only to the
CC
CC
CC
supply rail.
Note 3: Applies to RESET, fault, autoretry, sequence delays, and watchdog timeout.
Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
_______________________________________________________________________________________
5
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
SDA
t
BUF
t
SU:DAT
t
SU:STA
t
t
SU:STO
HD:DAT
t
t
LOW
HD:STA
SCL
t
HIGH
t
HD:STA
t
t
R
F
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED START
CONDITION
Figure 1. SMBus Timing Diagram
t
1
t
t
3
2
TCK
t
t
4
5
TDI, TMS
t
6
t
7
TDO
Figure 2. JTAG Timing Diagram
6
______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Typical Operating Characteristics
(Typical values are at V
CC
= 3.3V, T = +25°C, unless otherwise noted.)
A
V
SUPPLY CURRENT
CC
NORMALIZED MON_ THRESHOLD
vs. TEMPERATURE
NORMALIZED EN THRESHOLD
vs. TEMPERATURE
CC
vs. V SUPPLY VOLTAGE
1.2
1.0
0.8
0.6
0.4
0.2
0
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
6
5
4
3
2
1
0
ABP AND DBP CONNECTED TO V
CC
+85NC
+25NC
-40NC
ABP AND DBP
REGULATORS ACTIVE
5.6V RANGE,
HALF SCALE,
PUV THRESHOLD
FOR LOW-VOLTAGE APPLICATIONS
V
< 3.6V CONNECT ABP AND
CC
DBP TO V
CC
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
0
2
4
6
8
10
12
14
TEMPERATURE (NC)
TEMPERATURE (NC)
V
(V)
CC
TRANSIENT DURATION
vs. THRESHOLD OVERDRIVE (EN)
NORMALIZED TIMING ACCURACY
vs. TEMPERATURE
MON_ DEGLITCH
vs. TRANSIENT DURATION
160
140
120
100
80
0.986
0.984
0.982
0.980
0.978
0.976
0.974
0.972
120
100
80
60
40
20
0
60
40
20
0
1
10
100
-40
-20
0
20
40
60
80
2
4
8
16
EN OVERDRIVE (mV)
TEMPERATURE (NC)
DEGLITCH VALUE
OUTPUT VOLTAGE
vs. SINK CURRENT (OUT = LOW)
OUTPUT-VOLTAGE HIGH vs.
SOURCE CURRENT (PUSH-PULL OUTPUT)
MR TO RESET PROPAGATION DELAY
vs. TEMPERATURE
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
MAX
GPIO_
GPIO_
MIN
RESET
RESET
500
0
1000
1500
0
5
10
(mA)
15
20
-40
-20
0
20
40
60
80
I
(µA)
I
TEMPERATURE (NC)
OUT
OUT
_______________________________________________________________________________________
7
12-Channel/8-Channel Flash-Configurable System
Monitors with Nonvolatile Fault Registers
Typical Operating Characteristics (continued)
(Typical values are at V
CC
= 3.3V, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY vs. CODE
DIFFERENTIAL NONLINEARITY vs. CODE
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
128 256 384 512 640 768 896 1024
CODE (LSB)
0
0
0
128 256 384 512 640 768 896 1024
CODE (LSB)
CURRENT-SENSE ACCURACY
vs. CSP-CSM VOLTAGE
NORMALIZED CURRENT-SENSE
ACCURACY vs. TEMPERATURE
1.0
0.8
1.05
1.03
1.01
0.99
0.97
0.95
0.6
0.4
200mV
25mV
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
100mV
5
10
15
20
25
30
-40
10
60
CSP-CSM VOLTAGE (mV)
TEMPERATURE (NC)
RESET OUTPUT CURRENT
vs. SUPPLY VOLTAGE
CURRENT-SENSE TRANSIENT DURATION
vs. CSP-CSM OVERDRIVE
18
16
14
12
10
8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
ABP AND DBP
CONNECTED TO V
CC
ABP AND DBP
REGULATORS ACTIVE
6
4
2
V
= 0.3V
RESET
0
2
4
6
8
10
12
14
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
CSP-CSM OVERDRIVE (mV)
8
______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Pin Description
PIN
NAME
FUNCTION
MAX16070
MAX16071
MON2–MON6, Monitor Voltage Input 1–Monitor Voltage Input 8. Set monitor voltage range
MON7, MON8, through configuration registers. Measured value written to the ADC register
1–5, 34, 35,
40
1–5, 36, 37,
40
MON1
can be read back through the SMBus or JTAG interface.
Current-Sense Amplifier Positive Input. Connect CSP to the source side of the
external sense resistor.
6
7
6
7
CSP
Current-Sense Amplifier Negative Input. Connect CSM to the load side of the
external sense resistor.
CSM
8
9
8
9
RESET
TMS
TDI
Configurable Reset Output
JTAG Test Mode Select
10
10
JTAG Test Data Input
11
11
TCK
TDO
SDA
A0
JTAG Test Clock
12
12
JTAG Test Data Output
13
13
SMBus Serial-Data Open-Drain Input/Output
Four-State SMBus Address. Address sampled upon POR.
SMBus Serial Clock Input
Ground
14
14
15
15
SCL
GND
16, 33
16, 35
General-Purpose Input/Output 7 and General-Purpose Input/Output 8.
GPIO_s can be configured to act as a TTL input, a push-pull, open-drain, or
high-impedance output or a pulldown circuit during a fault event or reverse
sequencing.
17, 18
19–24
—
GPIO7, GPIO8
General-Purpose Input/Output 1–General-Purpose Input/Output 6. GPIO_s
GPIO1–GPIO6 can be configured to act as a TTL input, a push-pull, open-drain, or high-
impedance output or a pulldown circuit during a fault event.
17–22
23–28,
30, 38, 39
25, 26, 27, 29
N.C.
EN
No Connection. Not internally connected.
Analog Enable Input. All outputs deassert when V is below the enable
EN
threshold.
28
30
29
Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with
a 1FF capacitor to GND.
31, 32
DBP
Device Power Supply. Connect V
to a voltage from 2.8V to 14V. Bypass
CC
31
32
33
34
V
CC
V
with a 10FF capacitor to GND.
CC
ABP
Analog Bypass. Bypass ABP with a 1FF ceramic capacitor to GND.
Monitor Voltage Input 9–Monitor Voltage Input 12. Set monitor voltage range
through configuration registers. Measured value written to the ADC register
can be read back through the SMBus or JTAG interface.
MON9–
MON12
36–39
—
—
—
Exposed Pad. Internally connected to GND. Connect to ground, but do not
use as the main ground connection.
EP
_______________________________________________________________________________________
9
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Functional Diagram
V
ABP
DBP
CC
OVERC
RESET
RESET
GPIO1
MAX16070
MAX16071
ANY_FAULT
FAULT1
G
P
I
DECODE
LOGIC
GPIO2
O
FAULT2
MR
GPIO3
GPIO4
GPIO5
C
O
N
T
EN
MARGIN
1.4V
R
O
L
WDI
CSP
WATCHDOG
TIMER
A
V
WDO
GPIO6
CSM
V
CSTH
GPIO7
GPIO8
GPIO1–GPIO8
REF
VOLTAGE
SCALING
AND
MON1–
MON12
10-BIT ADC
(SAR)
DIGITAL
COMPARATORS
ADC
REGISTERS
MUX
RAM
REGISTERS
JTAG
INTERFACE
FLASH
MEMORY
SMBus INTERFACE
GND
TDO
TDI
TCK
TMS
AO
SCL
SDA
10 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
from initiating faults and flash contents are copied to
Detailed Description
the respective register locations. During boot-up, the
The MAX16070 monitors up to twelve system power sup-
MAX16070/MAX16071 are not accessible through the
plies and the MAX16071 can monitor up to eight system
power supplies. After boot-up, if EN is high and the soft-
ware enable bit is set to ‘1,’ monitoring begins based on
serial interface. The boot-up sequence takes up to
150Fs, after which the device is ready for normal opera-
tion. RESET is asserted low up to the boot-up phase and
the configuration stored in flash. An internal multiplexer
remains asserted for its programmed timeout period once
cycles through each MON_ input. At each multiplexer
sequencing is completed and all monitored channels
stop, the 10-bit ADC converts the monitored analog volt-
are within their respective thresholds. Up to the boot-up
age to a digital result and stores the result in a register.
phase, the GPIO_s are high impedance.
Each time a conversion cycle (50Fs, max) completes,
Power
internal logic circuitry compares the conversion results
to the overvoltage and undervoltage thresholds stored in
memory. When a result violates a programmed threshold,
the conversion can be configured to generate a fault.
GPIO_ can be programmed to assert on combinations
of faults. Additionally, faults can be configured to shut off
the system and trigger the nonvolatile fault logger, which
writes all fault information automatically to the flash and
write-protects the data to prevent accidental erasure.
Apply 2.8V to 14V to V
to power the MAX16070/
CC
MAX16071. Bypass V
to ground with a 10FF capaci-
CC
tor. Two internal voltage regulators, ABP and DBP,
supply power to the analog and digital circuitry within
the device. For operation at 3.6V or lower, disable the
regulators by connecting ABP and DBP to V
.
CC
ABP is a 3.0V (typ) voltage regulator that powers the inter-
nal analog circuitry. Bypass ABP to GND with a 1FF ceram-
ic capacitor installed as close to the device as possible.
The MAX16070/MAX16071 contain both SMBus and
JTAG serial interfaces for accessing registers and flash.
Use only one interface at any given time. For more infor-
mation on how to access the internal memory through
these interfaces, see the SMBus-Compatible Interface
and JTAG Serial Interface sections. The memory map
is divided into three pages with access controlled by
special SMBus and JTAG commands.
DBP is an internal 3.0V (typ) voltage regulator. DBP pow-
ers flash and digital circuitry. All push-pull outputs refer to
DBP. Bypass the DBP output to GND with a 1FF ceramic
capacitor installed as close as possible to the device.
Do not power external circuitry from ABP or DBP.
Enable
To enable monitoring, the voltage at EN must be above
1.4V and the software enable bit in r73h[0] must be set
to ‘1.’ To power down and disable monitoring, either pull
EN below 1.35V or set the Software Enable bit to ‘0.’
See Table 1 for the software enable bit configurations.
Connect EN to ABP if not used.
The factory-default values at POR (power-on reset) for all
RAM registers are ‘0’s. POR occurs when V
reaches
CC
the undervoltage-lockout threshold (UVLO) of 2.8V (max).
At POR, the device begins a boot-up sequence. During
the boot-up sequence, all monitored inputs are masked
Table 1. Software Enable Configurations
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
[0]
[1]
[2]
Software enable
Reserved
1 = Margin mode enabled
Early warning threshold select
0 = Early warning is undervoltage
1 = Early warning is overvoltage
73h
273h
[3]
[4]
Independent watchdog mode enable
1 = Watchdog timer is independent of sequencer
0 = Watchdog timer boots after sequence completes
______________________________________________________________________________________ 11
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
When in the monitoring state, a register bit, ENRESET,
is set to a ‘1’ when EN falls below the undervoltage
threshold. This register bit latches and must be cleared
through software. This bit indicates if RESET asserted
low due to EN going under the threshold. The POR state
of ENRESET is ‘0’. The bit is only set on a falling edge
of the EN comparator output or the software enable bit.
The three programmable thresholds for each monitored
voltage include an overvoltage, an undervoltage, and a
secondary warning threshold that can be set in r73h[3]
to be either an undervoltage or overvoltage threshold.
See the Faults section for more information on setting
overvoltage and undervoltage thresholds. All voltage
thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC
conversion result are compared to these overvoltage
and undervoltage thresholds.
Voltage/Current Monitoring
The MAX16070/MAX16071 feature an internal 10-bit
ADC that monitors the MON_ voltage inputs. An internal
multiplexer cycles through each of the enabled inputs,
taking less than 40Fs for a complete monitoring cycle.
Each acquisition takes approximately 3.2Fs. At each
multiplexer stop, the 10-bit ADC converts the analog
input to a digital result and stores the result in a register.
ADC conversion results are stored in registers r00h to
r1Ah (see Table 6). Use the SMBus or JTAG serial inter-
face to read ADC conversion results.
Inputs that are not enabled are not converted by the
ADC; they contain the last value acquired before that
channel was disabled.
The ADC conversion result registers are reset to 00h at
boot-up. These registers are not reset when a reboot
command is executed.
Configure the MAX16070/MAX16071 for differential
mode in r46h (Table 5). The possible differential pairs
are MON1/MON2, MON3/MON4, MON5/MON6, MON7/
MON8, MON9/MON10, MON11/MON12 with the first
input always being at a higher voltage than the second.
Use differential voltage sensing to eliminate voltage off-
sets or measure supply current. See Figure 3. In differ-
ential mode, the odd-numbered MON_ input measures
the absolute voltage with respect to GND while the result
of the even input is the difference between the odd and
even inputs. See Figure 3 for the typical differential mea-
surement circuit.
The MAX16070 provides twelve inputs, MON1 to MON12,
for voltage monitoring. The MAX16071 provides eight
inputs, MON1 to MON8, for voltage monitoring. Each
input voltage range is programmable in registers r43h to
r45h (see Table 5). When MON_ configuration registers
are set to ’11,’ MON_ voltages are not monitored, and
the multiplexer does not stop at these inputs, decreasing
the total cycle time. These inputs cannot be configured
to trigger fault conditions.
R
S
I
LOAD
POWER
SUPPLY
V
MON
CSP
-
TO ADC MUX
MON
MON
EVEN
ODD
CSM
*A
V
+
R
SENSE
MAX16070
MAX16071
MAX16070
LOAD
-
MON
MON
ODD
EVEN
+
OVERC
+
-
*V
CSTH
POWER
SUPPLY
LOAD
*ADJUSTABLE BY r47h [3:2]
Figure 3. Differential Measurement Connections
Figure 4. Current-Sense Amplifier
12 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
In addition, there are two programmable current-sense
trip thresholds: primary overcurrent and secondary over-
current. For fast fault detection, the primary overcurrent
threshold is implemented with an analog comparator
connected to the internal OVERC signal. The OVERC
signal can be output on one of the GPIO_s. See the
General-Purpose Inputs/Outputs section for configur-
ing the GPIO_ to output the OVERC signal. The primary
threshold is set by:
Boot-Up Delay
Once EN is above its threshold and the software-enable
bit is set, a boot-up delay occurs before monitoring
begins. This delay is configured in register r77h[3:0] as
shown in Tables 2 and 3.
Internal Current-Sense Amplifier
The current-sense inputs, CSP/CSM, and a current-
sense amplifier facilitate power monitoring (see Figure
4). The voltage on CSP relative to GND is also monitored
by the ADC when the current-sense amplifier is enabled
with r47h[0]. The conversion results are located in regis-
ters r19h and r1Ah (see Table 6). There are two select-
able voltage ranges for CSP set by r47h[1], see Table
4. Although the voltage can be monitored over SMBus
or JTAG, this voltage has no threshold comparators and
cannot trigger any faults. Regarding the current-sense
amplifier, there are four selectable ranges and the ADC
output for a current-sense conversion is:
I
= V
/R
TH
CSTH SENSE
where I
is the current threshold to be set, V
is
TH
CSTH
the threshold set by r47h[3:2], and R
is the value
SENSE
of the sense resistor. See Table 4 for a description of
r47h. OVERC depends only on the primary overcurrent
threshold. The secondary overcurrent threshold is imple-
mented through ADC conversions and digital compari-
son set by r6Ch. The secondary overcurrent threshold
includes programmable time delay options located in
r73h[6:5]. Primary and secondary current-sense faults
are enabled/disabled through r47h[0].
8
X
ADC
= (V
x A )/1.4V x (2 - 1)
SENSE
V
where X
is the 8-bit decimal ADC result in register
ADC
r18h, V
is V
- V and A is the current-
CSM, V
SENSE
CSP
sense voltage gain set by r47h[3:2].
Table 2. Boot-Up Delay Register
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
[3:0]
[7:0]
Boot-up delay
Reserved
77h
277h
Table 3. Boot-Up Delay Values
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VALUE
25Fs
500Fs
1ms
2ms
3ms
4ms
6ms
8ms
10ms
12ms
25ms
100ms
200ms
400ms
800ms
1.6s
______________________________________________________________________________________ 13
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 4. Overcurrent Primary Threshold and Current-Sense Control
REGISTER
ADDRESS
FLASH
ADDRESS
BIT
RANGE
DESCRIPTION
1 = Current sense is enabled
0 = Current sense is disabled
[0]
[1]
1 = CSP full-scale range is 14V
0 = CSP full-scale range is 7V
47h
73h
247h
273h
Overcurrent primary threshold and current-sense gain setting
00 = 200mV threshold, A = 6V/V
01 = 100mV threshold, A = 12V/V
V
V
[3:2]
[6:5]
10 = 50mV threshold, A = 24V/V
V
11 = 25mV threshold, A = 48V/V
V
Overcurrent secondary threshold deglitch
00 = No delay
01 = 14ms
10 = 15ms
11 = 60ms
Table 5. ADC Configuration Registers
FLASH
ADDRESS
REGISTER ADDRESS
BIT RANGE
DESCRIPTION
ADC1 full-scale range
00 = 5.6V
[1:0]
[3:2]
[5:4]
[7:6]
01 = 2.8V
10 = 1.4V
11 = Channel not converted
ADC2 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
43h
243h
ADC3 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
ADC4 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
14 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 5. ADC Configuration Registers (continued)
FLASH
ADDRESS
REGISTER ADDRESS
BIT RANGE
DESCRIPTION
ADC5 full-scale range
00 = 5.6V
[1:0]
01 = 2.8V
10 = 1.4V
11 = Channel not converted
ADC6 full-scale range
00 = 5.6V
[3:2]
[5:4]
[7:6]
[1:0]
[3:2]
[5:4]
[7:6]
01 = 2.8V
10 = 1.4V
11 = Channel not converted
44h
244h
ADC7 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
ADC8 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
ADC9 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
ADC10 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
45h
245h
ADC11 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
ADC12 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
______________________________________________________________________________________ 15
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 5. ADC Configuration Registers (continued)
FLASH
ADDRESS
REGISTER ADDRESS
BIT RANGE
DESCRIPTION
Differential conversion ADC1, ADC2
[0]
0 = Disabled
1 = Enabled
Differential conversion ADC3, ADC4
0 = Disabled
1 = Enabled
[1]
[2]
[3]
[4]
[5]
Differential conversion ADC5, ADC6
0 = Disabled
1 = Enabled
46h
246h
Differential conversion ADC7, ADC8
0 = Disabled
1 = Enabled
Differential conversion ADC9, ADC10
0 = Disabled
1 = Enabled
Differential conversion ADC11, ADC12
0 = Disabled
1 = Enabled
16 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 6. ADC Conversion Results (Read Only)
REGISTER ADDRESS
BIT RANGE
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:6]
[7:0]
[7:0]
[7:6]
DESCRIPTION
ADC1 result (MSB) bits 9–2
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
ADC1 result (LSB) bits 1, 0
ADC2 result (MSB) bits 9–2
ADC2 result (LSB) bits 1, 0
ADC3 result (MSB) bits 9–2
ADC3 result (LSB) bits 1, 0
ADC4 result (MSB) bits 9–2
ADC4 result (LSB) bits 1, 0
ADC5 result (MSB) bits 9–2
ADC5 result (LSB) bits 1, 0
ADC6 result (MSB) bits 9–2
ADC6 result (LSB) bits 1, 0
ADC7 result (MSB) bits 9–2
ADC7 result (LSB) bits 1, 0
ADC8 result (MSB) bits 9–2
ADC8 result (LSB) bits 1, 0
ADC9 result (MSB) bits 9–2
ADC9 result (LSB) bits 1, 0
ADC10 result (MSB) bits 9–2
ADC10 result (LSB) bits 1, 0
ADC11 result (MSB) bits 9–2
ADC11 result (LSB) bits 1, 0
ADC12 result (MSB) bits 9–2
ADC12 result (LSB) bits 1, 0
Current-sense ADC result
CSP ADC output (MSB) bits 9–2
CSP ADC output (LSB) bits 1, 0
______________________________________________________________________________________ 17
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
When GPIO1 to GPIO8 are configured as general-pur-
pose inputs/outputs, read values from the GPIO_ ports
through r1Eh and write values to GPIO_s through r3Eh.
Note that r3Eh has a corresponding flash register, which
programs the default state of a general-purpose output.
See Table 7 for more information on reading and writing
to the GPIO_.
General-Purpose Inputs/Outputs
GPIO1 to GPIO8 are programmable general-purpose
inputs/outputs. GPIO1–GPIO8 are configurable as a
manual reset input, a watchdog timer input and output,
logic inputs/outputs, fault-dependent outputs. When pro-
grammed as outputs, GPIO_s are open drain or push-
pull. See Tables 8 and 9 for more detailed information on
configuring GPIO1 to GPIO8.
Table 7. GPIO_ State Registers
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
GPIO1 input state
GPIO2 input state
GPIO3 input state
GPIO4 input state
GPIO5 input state
GPIO6 input state
GPIO7 input state
GPIO8 input state
GPIO1 output state
GPIO2 output state
GPIO3 output state
GPIO4 output state
GPIO5 output state
GPIO6 output state
GPIO7 output state
GPIO8 output state
1Eh
—
3Eh
23Eh
Table 8. GPIO_ Configuration Registers
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
[2:0]
[5:3]
[7:6]
[0]
GPIO1 configuration
3Fh
40h
41h
23Fh
240h
241h
GPIO2 configuration
GPIO3 configuration (LSB)
GPIO3 configuration (MSB)
GPIO4 configuration
[3:1]
[6:4]
[7]
GPIO5 configuration
GPIO6 configuration (LSB)
GPIO6 configuration (MSB)
GPIO7 configuration
[1:0]
[4:2]
[7:5]
GPIO8 configuration
18 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 8. GPIO_ Configuration Registers (continued)
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
Output configuration for GPIO1
[0]
0 = Push-pull
1 = Open drain
Output configuration for GPIO2
0 = Push-pull
1 = Open drain
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Output configuration for GPIO3
0 = Push-pull
1 = Open drain
Output configuration for GPIO4
0 = Push-pull
1 = Open drain
42h
242h
Output configuration for GPIO5
0 = Push-pull
1 = Open drain
Output configuration for GPIO6
0 = Push-pull
1 = Open drain
Output configuration for GPIO7
0 = Push-pull
1 = Open drain
Output configuration for GPIO8
0 = Push-pull
1 = Open drain
Table 9. GPIO_ Function Configuration Bits
CODE
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
Logic
input
Logic
input
000
Logic input
Logic input
Logic input
Logic input
Logic input
Logic input
Logic
output
Logic
output
001
010
011
100
101
110
111
Logic output
Fault2 output
Fault1 output
Logic output
Logic output
Logic output
Logic output
Fault2 output
Fault1 output
Logic output
Fault2
output
Fault2
output
Fault2
output
Fault2 output Fault2 output Fault2 output
Fault1
output
Fault1
output
—
Fault1 output Fault1 output
—
—
ANY_FAULT
ANY_FAULT
ANY_FAULT
ANY_FAULT
ANY_FAULT
—
—
output
output
output
output
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
WDO
output
WDO
output
MR input
MR input
WDO output
MR input
MR input
WDO output
EXTFAULT
input/output
MARGIN
input
EXTFAULT
input/output
WDI input
—
—
—
—
______________________________________________________________________________________ 19
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Fault1 and Fault2
GPIO1 to GPIO8 are configurable as dedicated fault out-
puts, Fault1 or Fault2. Fault outputs can assert on one or
more overvoltage, undervoltage, or early warning condi-
tions for selected inputs, as well as the secondary over-
current comparator. Fault1 and Fault2 dependencies
are set using registers r36h to r3Ah. See Table 10. When
a fault output depends on more than one MON_, the
fault output asserts when one or more MON_ exceeds a
programmed threshold voltage. These fault outputs act
independently of the critical fault system, described in
the Critical Faults section.
Table 10. Fault1 and Fault2 Dependencies
REGISTER
ADDRESS
FLASH
ADDRESS
BIT
RANGE
DESCRIPTION
0
1
2
3
4
5
6
7
0
1
2
3
1 = Fault1 depends on MON1
1 = Fault1 depends on MON2
1 = Fault1 depends on MON3
1 = Fault1 depends on MON4
1 = Fault1 depends on MON5
1 = Fault1 depends on MON6
1 = Fault1 depends on MON7
1 = Fault1 depends on MON8
1 = Fault1 depends on MON9
1 = Fault1 depends on MON10
1 = Fault1 depends on MON11
1 = Fault1 depends on MON12
36h
37h
38h
236h
237h
238h
1 = Fault1 depends on the overvoltage thresholds of the inputs selected by
r36h and r37h[3:0]
4
5
6
7
1 = Fault1 depends on the undervoltage thresholds of the inputs selected by
r36h and r37h[3:0]
1 = Fault1 depends on the early warning thresholds of the inputs selected by
r36h and r37h[3:0]
0 = Fault1 is an active-low digital output
1 = Fault1 is an active-high digital output
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1 = Fault2 depends on MON1
1 = Fault2 depends on MON2
1 = Fault2 depends on MON3
1 = Fault2 depends on MON4
1 = Fault2 depends on MON5
1 = Fault2 depends on MON6
1 = Fault2 depends on MON7
1 = Fault2 depends on MON8
20 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 10. Fault1 and Fault2 Dependencies (continued)
REGISTER
ADDRESS
FLASH
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
[1]
[2]
[3]
1 = Fault2 depends on MON9
1 = Fault2 depends on MON10
1 = Fault2 depends on MON11
1 = Fault2 depends on MON12
1 = Fault2 depends on the overvoltage thresholds of the inputs selected by
r38h and r39h[3:0]
[4]
[5]
[6]
[7]
39h
239h
1 = Fault2 depends on the undervoltage thresholds of the inputs selected by
r38h and r39h[3:0]
1 = Fault2 depends on the early warning thresholds of the inputs selected by
r38h and r39h[3:0]
0 = Fault2 is an active-low digital output
1 = Fault2 is an active-high digital output
[0]
[1]
1 = Fault1 depends on secondary overcurrent comparator
1 = Fault2 depends on secondary overcurrent comparator
Reserved
3Ah
23Ah
[7:2]
One configuration bit determines the behavior of the
MAX16070/MAX16071 when EXTFAULT is pulled low by
some other device. If register bit r6Dh[2] is set, EXTFAULT
going low triggers a nonvolatile fault log operation.
ANY_FAULT
GPIO1, GPIO3, GPIO4, GPIO5, and GPIO7 are configu-
rable to assert low during any fault condition.
Overcurrent Comparator (OVERC)
GPIO1 to GPIO8 are configurable to assert low when
the voltage across CSP and CSM exceed the primary
overcurrent threshold. See the Internal Current-Sense
Amplifier section for more details.
Faults
The MAX16070/MAX16071 monitor the input (MON_)
channels and compare the results with an overvoltage
threshold, an undervoltage threshold, and a selectable
overvoltage or undervoltage early warning threshold.
Based on these conditions, the MAX16070/MAX16071
assert various fault outputs and save specific informa-
tion about the channel conditions and voltages into the
nonvolatile flash. Once a critical fault event occurs, the
failing channel condition, ADC conversions at the time of
the fault, or both can be saved by configuring the event
logger. The event logger records a single failure in the
internal flash and sets a lock bit that protects the stored
fault data from accidental erasure on a subsequent
power-up.
Manual Reset (MR)
GPIO1, GPIO3, GPIO5, and GPIO7 are configurable to act
as an active-low manual reset input, MR. Drive MR low to
assert RESET. RESET remains asserted for the selected
reset timeout period after MR transitions from low to high.
Watchdog Input (WDI) and Output (WDO)
GPIO2, GPIO4, GPIO6, and GPIO8 are configurable as
the watchdog timer output, WDO. GPIO1 is configurable
as WDI. See Table 17 for configuration details. WDO is an
active-low output. See the Watchdog Timer section for more
information about the operation of the watchdog timer.
An overvoltage event occurs when the voltage at a moni-
tored input exceeds the overvoltage threshold for that
input. An undervoltage event occurs when the voltage
at a monitored input falls below the undervoltage thresh-
old. Fault thresholds are set in registers r48h to r6Ch as
shown in Table 11. Disabled inputs are not monitored for
fault conditions and are skipped over by the input mul-
tiplexer. Only the upper 8 bits of a conversion result are
compared with the programmed fault thresholds.
External Fault (EXTFAULT)
GPIO4 and GPIO8 are configurable as the external fault
input/output. When configured as push-pull, EXTFAULT
signals that a critical fault has occurred on one or more
monitored voltages or current. When configured as
open-drain, EXTFAULT can be asserted low by an exter-
nal circuit to trigger a critical fault. This signal can be
used to cascade multiple MAX16070/MAX16071s.
______________________________________________________________________________________ 21
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 11. Fault Threshold Registers
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
248h
249h
24Ah
24Bh
24Ch
24Dh
24Eh
24Fh
250h
251h
252h
253h
254h
255h
256h
257h
258h
259h
25Ah
25Bh
25Ch
25Dh
25Eh
25Fh
260h
261h
262h
263h
264h
265h
266h
267h
268h
269h
26Ah
26Bh
26Ch
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
MON1 secondary threshold
MON1 overvoltage threshold
MON1 undervoltage threshold
MON2 secondary threshold
MON2 overvoltage threshold
MON2 undervoltage threshold
MON3 secondary threshold
MON3 overvoltage threshold
MON3 undervoltage threshold
MON4 secondary threshold
MON4 overvoltage threshold
MON4 undervoltage threshold
MON5 secondary threshold
MON5 overvoltage threshold
MON5 undervoltage threshold
MON6 secondary threshold
MON6 overvoltage threshold
MON6 undervoltage threshold
MON7 secondary threshold
MON7 overvoltage threshold
MON7 undervoltage threshold
MON8 secondary threshold
MON8 overvoltage threshold
MON8 undervoltage threshold
MON9 secondary threshold
MON9 overvoltage threshold
MON9 undervoltage threshold
MON10 secondary threshold
MON10 overvoltage threshold
MON10 undervoltage threshold
MON11 secondary threshold
MON11 overvoltage threshold
MON11 undervoltage threshold
MON12 secondary threshold
MON12 overvoltage threshold
MON12 undervoltage threshold
Secondary overcurrent threshold
22 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The general-purpose inputs/outputs (GPIO1 to GPIO8)
can be configured as ANY_FAULT outputs or dedicated
Fault1 and Fault2 outputs to indicate fault conditions.
These fault outputs are not masked by the critical fault
enable bits shown in Table 14. See the General-Purpose
Inputs/Outputs section for more information on configur-
ing GPIO_s as fault outputs.
outside the threshold for a certain number of acquisitions
as determined by the deglitch setting in r73h[6:5] and
r74h[6:5] (see Table 12).
Fault Flags
Fault flags indicate the fault status of a particular input.
The fault flag of any monitored input in the device can be
read at any time from registers r1Bh and r1Ch, as shown
in Table 13. Clear a fault flag by writing a ‘1’ to the appro-
priate bit in the flag register. Unlike the fault signals sent
to the fault outputs, these bits are masked by the Critical
Fault Enable bits (see Table 14). The fault flag is only set
when the matching enable bit in the critical fault enable
register is also set.
Deglitch
Fault conditions are detected at the end of each conver-
sion. When the voltage on an input falls outside a moni-
tored threshold for one acquisition, the input multiplexer
remains on that channel and performs several succes-
sive conversions. To trigger a fault, the input must stay
Table 12. Deglitch Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
Overcurrent comparator deglitch time
00 = No deglitch
01 = 4ms
10 = 15ms
11 = 60ms
73h
74h
273h
274h
[6:5]
Voltage comparator deglitch configuration
00 = 2 cycles
01 = 4 cycles
[6:5]
10 = 8 cycles
11 = 16 cycles
Table 13. Fault Flags
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
MON1
MON2
MON3
MON4
1Bh
MON5
MON6
MON7
MON8
MON9
MON10
MON11
MON12
Overcurrent
1Ch
External fault (EXTFAULT)
SMB alert
______________________________________________________________________________________ 23
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 14. Critical Fault Configuration
REGISTER
ADDRESS ADDRESS
FLASH
BIT
RANGE
DESCRIPTION
Fault information to log
00 = Save failed line flags and ADC values in flash
01 = Save only failed line flags in flash
10 = Save only ADC values in flash
11 = Do not save anything
[1:0]
6Dh
26Dh
[2]
[7:3]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1 = Fault log triggered when EXTFAULT is pulled low externally
Not used
1 = Fault log triggered when MON1 is below its undervoltage threshold
1 = Fault log triggered when MON2 is below its undervoltage threshold
1 = Fault log triggered when MON3 is below its undervoltage threshold
1 = Fault log triggered when MON4 is below its undervoltage threshold
1 = Fault log triggered when MON5 is below its undervoltage threshold
1 = Fault log triggered when MON6 is below its undervoltage threshold
1 = Fault log triggered when MON7 is below its undervoltage threshold
1 = Fault log triggered when MON8 is below its undervoltage threshold
1 = Fault log triggered when MON9 is below its undervoltage threshold
1 = Fault log triggered when MON10 is below its undervoltage threshold
1 = Fault log triggered when MON11 is below its undervoltage threshold
1 = Fault log triggered when MON12 is below its undervoltage threshold
1 = Fault log triggered when MON1 is above its overvoltage threshold
1 = Fault log triggered when MON2 is above its overvoltage threshold
1 = Fault log triggered when MON3 is above its overvoltage threshold
1 = Fault log triggered when MON4 is above its overvoltage threshold
1 = Fault log triggered when MON5 is above its overvoltage threshold
1 = Fault log triggered when MON6 is above its overvoltage threshold
1 = Fault log triggered when MON7 is above its overvoltage threshold
1 = Fault log triggered when MON8 is above its overvoltage threshold
1 = Fault log triggered when MON9 is above its overvoltage threshold
1 = Fault log triggered when MON10 is above its overvoltage threshold
1 = Fault log triggered when MON11 is above its overvoltage threshold
1 = Fault log triggered when MON12 is above its overvoltage threshold
1 = Fault log triggered when MON1 is above/below the early threshold warning
1 = Fault log triggered when MON2 is above/below the early threshold warning
1 = Fault log triggered when MON3 is above/below the early threshold warning
1 = Fault log triggered when MON4 is above/below the early threshold warning
1 = Fault log triggered when MON5 is above/below the early threshold warning
1 = Fault log triggered when MON6 is above/below the early threshold warning
1 = Fault log triggered when MON7 is above/below the early threshold warning
1 = Fault log triggered when MON8 is above/below the early threshold warning
6Eh
26Eh
6Fh
70h
71h
26Fh
270h
271h
24 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 14. Critical Fault Configuration (continued)
REGISTER
ADDRESS ADDRESS
FLASH
BIT
RANGE
DESCRIPTION
[0]
[1]
1 = Fault log triggered when MON9 is above/below the early threshold warning
1 = Fault log triggered when MON10 is above/below the early threshold warning
1 = Fault log triggered when MON11 is above/below the early threshold warning
1 = Fault log triggered when MON12 is above/below the early threshold warning
1 = Fault log triggered when overcurrent early threshold is exceeded
Reserved, must be set to ‘1’
[2]
72h
272h
[3]
[4]
[5]
[7:6]
Reserved
If a GPIO_ is configured as an open-drain EXTFAULT
input/output, and EXTFAULT is pulled low by an external
circuit, bit r1Ch[5] is set.
Logged fault information is stored in flash registers r200h
to r20Fh (see Table 15). After fault information is logged,
the flash is locked and must be unlocked to enable a
new fault log to be stored. Write a ‘0’ to r8Ch[1] to unlock
the fault flash. Fault information can be configured to
store ADC conversion results and/or fault flags in reg-
isters. Select the critical fault configuration in r6Dh[1:0].
Set r6Dh[1:0] to ‘11’ to turn off the fault logger. All stored
ADC results are 8 bits wide.
The SMB Alert bit is set if the MAX16070/MAX16071
have asserted the SMBus Alert output. Clear by writing a
‘1’. See SMBALERT section for more details.
Critical Faults
During normal operation, a fault condition can be con-
figured to store fault information in the flash memory by
setting the appropriate critical fault enable bits. Set the
appropriate critical fault enable bits in registers r6Eh to r72h
(see Table 14) for a fault condition to trigger a critical fault.
Table 15. Nonvolatile Fault Log Registers
FLASH ADDRESS
BIT RANGE
DESCRIPTION
200h
—
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[7:6]
Reserved
Fault log triggered on MON1
Fault log triggered on MON2
Fault log triggered on MON3
Fault log triggered on MON4
Fault log triggered on MON5
Fault log triggered on MON6
Fault log triggered on MON7
Fault log triggered on MON8
Fault log triggered on MON9
Fault log triggered on MON10
Fault log triggered on MON11
Fault log triggered on MON12
Fault log triggered on overcurrent
201h
202h
Fault log triggered on EXTFAULT
Not used
______________________________________________________________________________________ 25
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 15. Nonvolatile Fault Log Registers (continued)
FLASH ADDRESS
203h
BIT RANGE
[7:0]
DESCRIPTION
MON1 ADC output
MON2 ADC output
MON3 ADC output
MON4 ADC output
MON5 ADC output
MON6 ADC output
MON7 ADC output
MON8 ADC output
MON9 ADC output
MON10 ADC output
MON11 ADC output
MON12 ADC output
Current-sense ADC output
204h
[7:0]
205h
[7:0]
206h
[7:0]
207h
[7:0]
208h
[7:0]
209h
[7:0]
20Ah
[7:0]
20Bh
[7:0]
20Ch
[7:0]
20Dh
[7:0]
20Eh
[7:0]
20Fh
[7:0]
independent mode, the watchdog timer activates imme-
Reset Output
The reset output, RESET, indicates the status of the moni-
tored inputs.
diately after V
exceeds the UVLO threshold and the
CC
boot phase is complete. Set r73h[4] to ‘0’ to configure
the watchdog in dependent mode. Set r73h[4] to ‘1’ to
configure the watchdog in independent mode. See Table
17 for more information on configuring the watchdog
timer in dependent or independent mode.
During normal monitoring, RESET can be configured to
assert when any combination of MON_ inputs violates
configurable combinations of thresholds: undervoltage,
overvoltage, or early warning. Select the combination of
thresholds using r3Bh[1:0], and select the combination
of MON_ inputs using r3Ch[7:1] and r3Dh[4:0]. Note that
MON_ inputs configured as critical faults will always cause
RESET to assert regardless of these configuration bits.
Dependent Watchdog Timer Operation
Use the watchdog timer to monitor FP activity in two
modes. Flexible timeout architecture provides an adjust-
able watchdog startup delay of up to 300s, allow-
ing complicated systems to complete lengthy boot-up
routines. An adjustable watchdog timeout allows the
supervisor to provide quick alerts when processor activ-
RESET can be configured as push-pull or open drain
using r3Bh[3], and active-high or active-low using
r3Bh[2]. Select the reset timeout by loading a value from
Table 16 into r3Bh[7:4]. RESET can be forced to assert
by writing a ‘1’ into r3Ch[0]. RESET remains asserted
for the reset timeout period after a ‘0’ is written into
r3Ch[0]. See Table 16. The current state of RESET can
be checked by reading r20h[0].
ity fails. After each reset event (V
drops below UVLO
CC
then returns above UVLO, software reboot, manual reset
(MR), EN input going low then high, or watchdog reset),
the watchdog startup delay provides an extended time
for the system to power up and fully initialize all FP and
system components before assuming responsibility for
routine watchdog updates. Set r76h[6:4] to a value other
than ‘000’ to enable the watchdog startup delay. Set
r76h[6:4] to ‘000’ to disable the watchdog startup delay.
Watchdog Timer
The watchdog timer operates together with or indepen-
dently of the MAX16070/MAX16071. When operating in
dependent mode, the watchdog is not activated until EN
goes high and RESET is deasserted. When operating in
26 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 16. Reset Output Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
Reset output depends on:
00 = Undervoltage threshold violations
01 = Early warning threshold violations
10 = Overvoltage threshold violations
[1:0]
11 = Undervoltage or overvoltage threshold violations
0 = Active-low
1 = Active-high
[2]
[3]
1 = Push-pull
0 = Open drain
Reset timeout period
0000 = 25μs
0001 = 1.5ms
0010 = 2.5ms
0011 = 4ms
3Bh
23Bh
0100 = 6ms
0101 = 10ms
0110 = 15ms
0111 = 25ms
1000 = 40ms
1001 = 60ms
1010 = 100ms
1011 = 150ms
1100 = 250ms
1101 = 400ms
1110 = 600ms
1111 = 1s
[7:4]
Reset soft trigger
[0]
0 = Normal RESET behavior
1 = Force RESET to assert
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[7:5]
1 = RESET depends on MON1
1 = RESET depends on MON2
1 = RESET depends on MON3
1 = RESET depends on MON4
1 = RESET depends on MON5
1 = RESET depends on MON6
1 = RESET depends on MON7
1 = RESET depends on MON8
1 = RESET depends on MON9
1 = RESET depends on MON10
1 = RESET depends on MON11
1 = RESET depends on MON12
Reserved
3Ch
23Ch
3Dh
23Dh
______________________________________________________________________________________ 27
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 17. Watchdog Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
1 = Independent mode
0 = Dependent mode
73h
273h
[4]
[7]
1 = Watchdog affects RESET output
0 = Watchdog does not affect RESET output
Watchdog startup delay
000 = No initial timeout
001 = 30s
010 = 40s
[6:4]
011 = 80s
100 = 120s
101 = 160s
110 = 220s
111 = 300s
Watchdog timeout
0000 = Watchdog disabled
0001 = 1ms
76h
276h
0010 = 2ms
0011 = 4ms
0100 = 8ms
0101 = 14ms
0110 = 27ms
0111 = 50ms
1000 = 100ms
1001 = 200ms
1010 = 400ms
1011 = 750ms
1100 = 1.4s
[3:0]
1101 = 2.7s
1110 = 5s
1111 = 10s
The normal watchdog timeout period, t
, begins after
WDI
The watchdog can be configured to control the RESET
the first transition on WDI before the conclusion of the
long startup watchdog period, t (Figure 5).
output as well as the WDO output. RESET asserts for
the reset timeout, t , when the watchdog timer expires
WDI_STARTUP
RP
During the normal operating mode, WDO asserts if the
FP does not toggle WDI with a valid transition (high-to-
low or low-to-high) within the standard timeout period,
and the Watchdog Reset Output Enable bit (r76h[7]) is
set to ‘1.’ When RESET is asserted, the watchdog timer
is cleared and WDO is deasserted, therefore, WDO
pulses low for a short time (approximately 1Fs) when
the watchdog timer expires. RESET is not affected by
the watchdog timer when the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘0.’ If a RESET is asserted
by the watchdog timeout, the WDRESET bit is set to ‘1’. A
connected processor can check this bit to see the reset
was due to a watchdog timeout. See Table 17 for more
information on configuring watchdog functionality.
t
. WDO remains asserted until WDI is toggled or
WDI
RESET is asserted (Figure 6).
While EN is low, the watchdog timer is in reset. The
watchdog timer does not begin counting until RESET is
deasserted. The watchdog timer is reset and WDO deas-
serts any time RESET is asserted (Figure 7). The watch-
dog timer will be held in reset while RESET is asserted.
28 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
V
TH
LAST MON_
< t
WDI
t
WDI
WDI_STARTUP
< t
WDI
t
RP
RESET
Figure 5. Normal Watchdog Startup Sequence
V
CC
< t
WDI
> t
WDI
< t
WDI
WDI
< t
WDI
< t
WDI
< t
WDI
< t
WDI
0V
CC
t
WDI
V
WDO
0V
Figure 6. Watchdog Timer Operation
V
CC
< t
WDI
< t
WDI
t
t
RP
< t
WDI_STARTUP
WDI
WDI
0V
CC
V
RESET
0V
V
CC
WDO
0V
1µs
Figure 7. Watchdog Startup Sequence with Watchdog Reset Output Enable Bit Set to ‘1’
______________________________________________________________________________________ 29
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Independent Watchdog Timer Operation
When r73h[4] is ‘1’ the watchdog timer operates in
the independent mode. In the independent mode, the
watchdog timer operates as if it were a separate device.
SMBus-Compatible Interface
The MAX16070/MAX16071 feature an SMBus-
compatible, 2-wire serial interface consisting of a serial-
data line (SDA) and a serial-clock line (SCL). SDA and
SCL facilitate bidirectional communication between the
MAX16070/MAX16071 and the master device at clock
rates up to 400kHz. Figure 1 shows the 2-wire interface
timing diagram. The MAX16070/MAX16071 are transmit/
receive slave-only devices, relying upon a master device
to generate a clock signal. The master device (typically
a microcontroller) initiates a data transfer on the bus and
generates SCL to permit that transfer.
The watchdog timer is activated immediately upon V
CC
exceeding UVLO and once the boot-up sequence is fin-
ished. When RESET is asserted, the watchdog timer and
WDO are not affected.
There will be a startup delay if r76h[6:4] is set to a value
different than ‘000.’ If r76h[6:4] is set to ‘000,’ there will
not be a startup delay. See Table 17 for delay times.
In independent mode, if the Watchdog Reset Output
Enable bit r76h[7] is set to ‘1,’ when the watchdog timer
expires, WDO asserts then RESET asserts. WDO will
then deassert. WDO will be low for approximately 1Fs.
If the Watchdog Reset Output Enable bit (r76h[7]) is set
to ‘0,’ when the WDT expires, WDO asserts but RESET
is not affected.
A master device communicates to the MAX16070/
MAX16071 by transmitting the proper address followed
by a command and/or data words. The slave address
input, A0, is capable of detecting four different states,
allowing multiple identical devices to share the same
serial bus. The slave address is described further in
the Slave Address section. Each transmit sequence is
framed by a START (S) or REPEATED START (SR) con-
dition and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge pulse. SCL is a logic input, while SDA is
an open-drain input/output. SCL and SDA both require
external pullup resistors to generate the logic-high volt-
age. Use 4.7kI for most applications.
User-Defined Register
Register r8Ah provides storage space for a user-defined
configuration or firmware version number. Note that this
register controls the contents of the JTAG USERCODE
register bits 7:0. The user-defined register is stored at
r28Ah in the flash memory.
Memory Lock Bits
Register r8Ch contains the lock bits for the configuration
registers, configuration flash, user flash, and fault regis-
ter lock. See Table 18 for details.
Table 18. Memory Lock Bits
REGISTER
ADDRESS
FLASH ADDRESS
BIT RANGE
DESCRIPTION
Configuration register lock
1 = Locked
0
0 = Unlocked
Flash fault register lock
1 = Locked
0 = Unlocked
1
2
3
8Ch
28Ch
Flash configuration lock
1 = Locked
0 = Unlocked
User flash lock
1 = Locked
0 = Unlocked
30 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
SDA
SDA
SCL
S
P
SCL
CHANGE OF
DATA ALLOWED
START
CONDITION
STOP
CONDITION
DATA LINE STABLE,
DATA VALID
Figure 8. Bit Transfer
Figure 9. START and STOP Conditions
Bit Transfer
Acknowledge
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 8);
otherwise the MAX16070/MAX16071 register a START or
STOP condition (Figure 9) from the master. SDA and SCL
idle high when the bus is not busy.
The acknowledge bit (ACK) is the 9th bit attached to any
8-bit data word. The receiving device always generates
an ACK. The MAX16070/MAX16071 generate an ACK
when receiving an address or data by pulling SDA low
during the 9th clock period (Figure 10). When transmit-
ting data, such as when the master device reads data
back from the MAX16070/MAX16071, the device waits for
the master device to generate an ACK. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if the receiving device
is busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master can reattempt
communication at a later time. The MAX16070/MAX16071
generate a NACK after the command byte received dur-
ing a software reboot, while writing to the flash, or when
receiving an illegal memory address.
START and STOP Conditions
Both SCL and SDA idle high when the bus is not busy.
A master device signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. The master device issues a STOP
condition by transitioning SDA from low to high while
SCL is high. A STOP condition frees the bus for another
transmission. The bus remains active if a REPEATED
START condition is generated, such as in the block read
protocol (see Figure 1).
Early STOP Conditions
The MAX16070/MAX16071 recognize a STOP condition
at any point during transmission except if a STOP condi-
tion occurs in the same high pulse as a START condition.
This condition is not a legal SMBus format; at least one
clock pulse must separate any START and STOP condition.
Slave Address
Use the slave address input, A0, to allow multiple identi-
cal devices to share the same serial bus. Connect A0 to
GND, DBP (or an external supply voltage greater than
2V), SCL, or SDA to set the device address on the bus.
See Table 20 for a listing of all possible 7-bit addresses.
REPEATED START Conditions
A REPEATED START can be sent instead of a STOP
condition to maintain control of the bus during a read
operation. The START and REPEATED START conditions
are functionally identical.
The slave address can also be set to a custom value by
loading the address into register r8Bh[6:0]. See Table
19. If r8Bh[6:0] is loaded with 00h, the address is set by
input A0. Do not set the address to 09h or 7Fh to avoid
address conflicts. The slave address setting takes effect
immediately after writing to the register.
______________________________________________________________________________________ 31
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
CLOCK PULSE FOR ACKNOWLEDGE
2
1
8
9
SCL
SDA BY
TRANSMITTER
S
NACK
ACK
SDA BY
RECEIVER
Figure 10. Acknowledge
Table 19. SMBus Settings Register
REGISTER
FLASH ADDRESS
ADDRESS
BIT RANGE
DESCRIPTION
I2C Slave Address Register. Set to 00h to use A0 pin
address setting.
[6:0]
[7]
8Bh
28Bh
1 = Enable PEC (packet error check).
Table 20. Setting the SMBus Slave Address
SLAVE ADDRESSES
A0
0
SLAVE ADDRESS
1010 000R
1
1010 001R
SCL
SDA
1010 010R
1010 011R
R = Read/Write select bit
32 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Packet Error Checking (PEC)
The MAX16070/MAX16071 feature a PEC mode that is
useful for improving the reliability of the communication
bus by detecting bit errors. By enabling PEC, an extra
CRC-8 error check byte is added in the data string dur-
ing each read and/or write sequence. Enable PEC by
writing a ‘1’ to r8Bh[7].
Restrictions When Writing to Flash
Flash must be written to 8 bytes at a time. The initial
address must be aligned to 8-byte boundaries—the
three LSBs of the initial address must be ‘000.’ Write the
8 bytes using a single block-write command or using 8
successive Write Byte commands.
Send Byte
The send byte protocol allows the master device to send
one byte of data to the slave device (see Figure 11). The
send byte presets a register pointer address for a subse-
quent read or write. The slave sends a NACK instead of
an ACK if the master tries to send a memory address or
command code that is not allowed. If the master sends
A5h or A6h, the data is ACK, because this could be the
start of the write block or read block. If the master sends
a STOP condition before the slave asserts an ACK, the
internal address pointer does not change. If the master
sends A7h, this signifies a software reboot. The send
byte procedure is the following:
The CRC-8 byte is calculated using the polynomial
C = X8 + X2 + X + 1
The PEC calculation includes all bytes in the transmis-
sion, including address, command, and data. The PEC
calculation does not include ACK, NACK, START, STOP,
or REPEATED START.
Command Codes
The MAX16070/MAX16071 use eight command codes
for block read, block write, and other commands. See
Table 21 for a list of command codes.
To initiate a software reboot, send A7h using the send byte
format. A software-initiated reboot is functionally the same
as a hardware-initiated power-on reset. During boot-up,
flash configuration data in the range of 230h to 28Ch is
copied to r30h to r8Ch registers in the default page.
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a write
bit (low).
3) The addressed slave asserts an ACK on SDA.
Send command code A8h to trigger a fault store to flash.
Configure the Critical Fault Log Control register (r6Dh) to
store ADC conversion results and/or fault flags.
4) The master sends an 8-bit memory address or com-
mand code.
While in the flash page, send command code A9h to
access the flash page (addresses from 200h to 28Dh).
Once command code A9h has been sent, all addresses
are recognized as flash addresses only. Send command
code AAh to return to the default page (addresses from
000h to 08Dh). Send command code ABh to access
the user flash-page (addresses from 300h to 39Fh and
3B0h–3FFh), and send command code ACh to return to
the flash page.
5) The addressed slave asserts an ACK (or NACK) on SDA.
6) The master sends a STOP condition.
Table 21. Command Codes
COMMAND
CODE
ACTION
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
Block write
Block read
Reboot flash in register file
Trigger emergency save to flash
Flash page access ON
Flash page access OFF
User flash access ON (must be in flash page already)
User flash access OFF (return to flash page)
______________________________________________________________________________________ 33
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Send Byte Format
Receive Byte Format
S
ADDRESS R/W ACK COMMAND ACK
P
S
ADDRESS R/W ACK
DATA
8 bits
NACK
1
P
7 bits
0
0
8 bits
0
7 bits
1
0
Slave Address: Address
of the slave on the serial
interface bus.
Data Byte: Presets the internal
address pointer or represents
a command.
Slave Address: Address
of the slave on the serial
interface bus.
Data Byte: Data is read from
the location pointed to by the
internal address pointer.
Write Byte Format
ADDRESS R/W ACK COMMAND ACK
SMBALERT#
S
DATA
8 bits
ACK
0
P
S
ADDRESS R/W ACK
0001100 D.C.
DATA
8 bits
NACK
P
7 bits
0
0
8 bits
0
0
1
Slave Address: Address
of the slave on the serial
interface bus.
Command Byte:
Sets the internal
address pointer.
Data Byte: Data is written to
the locations set by the
internal address pointer.
Alert Response Address:
Only the device that
interrupted the master
responds to this address.
Slave Address: Slave places
its own address on the
serial bus.
Read Byte Format
SLAVE
S
SLAVE
ADDRESS
R/W ACK COMMAND ACK SR
R/W ACK DATA BYTE NACK
8 bits
P
ADDRESS
7 bits
0
0
8 bits
0
7 bits
1
0
1
Slave Address: Address
of the slave on the serial
interface bus.
Command Byte:
Sets the internal
address pointer.
Data Byte: Data is read from
the locations set by the
internal address pointer.
Block Write Format
BYTE
COUNT = N
Slave to master
Master to slave
S
ADDRESS
7 bits
ACK COMMAND ACK
ACK DATA BYTE 1 ACK DATA BYTE … ACK DATA BYTE N ACK
P
R/W
0
8 bits
8 bits
8 bits
8 bits
0
8 bits
0
0
0
0
0
Slave Address: Address
of the slave on the
Command Byte:
A5h
Data Byte: Data is written to the locations
set by the internal address pointer.
serial interface bus.
Block Read Format
BYTE
COUNT = N
S
ADDRESS
ACK COMMAND ACK SR
ADDRESS
7 bits
ACK
0
ACK DATA BYTE 1 ACK DATA BYTE … ACK DATA BYTE N NACK
P
R/W
R/W
0
0
7 bits
0
0
8 bits
1
8 bits
0
8 bits
0
8 bits
8 bits
1
Slave Address: Address
of the slave on the
Command Byte:
A6h
Slave Address: Address
of the slave on the
Data Byte: Data is read from the locations
set by the internal address pointer.
serial interface bus.
serial interface bus.
Write Byte Format with PEC
S
R/W
0
COMMAND
8 BITS
A
DATA
8 BITS
A
0
PEC
A
0
P
ADDRESS
7 BITS
A
0
0
8 BITS
Read Byte Format with PEC
S
ADDRESS
7 BITS
A
0
COMMAND
8 BITS
A
0
SR
ADDRESS
7 BITS
A
0
A
0
PEC
N
1
P
R/W
1
DATA
R/W
0
8 BITS
8 BITS
Block Write with PEC
DATA BYTE
8 BITS
S
ADDRESS R/W
COMMAND
8 BITS
A
0
BYTE COUNT N
8 BITS
A
0
DATA BYTE 1
8 BITS
A
0
A
0
DATA N
8 BITS
A
0
PEC
A
0
P
A
0
7 BITS
0
8 BITS
Block Read with PEC
DATA BYTE
8 BITS
BYTE COUNT N
8 BITS
A
0
ADDRESS R/W
A
0
COMMAND
8 BITS
SR
ADDRESS R/W
7 BITS
A
0
S
A
0
DATA BYTE 1
8 BITS
A
0
A
0
A
N
1
P
DATA BYTE N
8 BITS
PEC
7 BITS
0
1
0
8 BITS
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
D.C. = Don’t Care
ACK = Acknowledge, SDA pulled low during rising edge of SCL.
NACK = Not acknowledge, SDA left high during rising edge of SCL.
= SDA transitions from high to low during period of SCL.
= SDA transitions from low to high during period of SCL.
All data is clocked in/out of the device on rising edges of SCL.
Figure 11. SMBus Protocols
34 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Receive Byte
The receive byte protocol allows the master device to
read the register content of the MAX16070/MAX16071
(see Figure 11). The flash or register address must be
preset with a send byte or write word protocol first. Once
the read is complete, the internal pointer increases by
one. Repeating the receive byte protocol reads the con-
tents of the next address. The receive byte procedure
follows:
7) The slave asserts an ACK on the data line.
8) The master sends an 8-bit PEC byte.
9) The slave asserts an ACK on the data line (if PEC is
good, otherwise NACK).
10) The master generates a STOP condition.
Read Byte
The read byte protocol (see Figure 11) allows the master
device to read a single byte located in the default page,
extended page, or flash page depending on which page
is currently selected. The read byte procedure is the
following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a read
bit (high).
1) The master sends a START condition.
3) The addressed slave asserts an ACK on SDA.
4) The slave sends 8 data bits.
2) The master sends the 7-bit slave address and a
write bit (low).
5 The master asserts a NACK on SDA.
6) The master generates a STOP condition.
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends a REPEATED START condition.
Write Byte
The write byte protocol (see Figure 11) allows the master
device to write a single byte in the default page, extend-
ed page, or flash page, depending on which page is cur-
rently selected. The write byte procedure is the following:
7) The master sends the 7-bit slave address and a
read bit (high).
1) The master sends a START condition.
8) The addressed slave asserts an ACK on SDA.
9) The slave sends an 8-bit data byte.
10) The master asserts a NACK on SDA.
11) The master sends a STOP condition.
2) The master sends the 7-bit slave address and a write
bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
If the memory address is not valid, it is NACKed by the
slave at step 5 and the address pointer is not modified.
When PEC is enabled, the Read Byte protocol becomes:
1) The master sends a START condition.
7) The addressed slave asserts an ACK on SDA.
8) The master sends a STOP condition.
2) The master sends the 7-bit slave ID plus a write
bit (low).
To write a single byte, only the 8-bit memory address
and a single 8-bit data byte are sent. The data byte is
written to the addressed location if the memory address
is valid. The slave asserts a NACK at step 5 if the mem-
ory address is not valid.
3) The addressed slave asserts an ACK on the data line.
4) The master sends 8-bit memory address.
5) The active slave asserts an ACK on the data line.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave ID plus a read bit (high).
8) The addressed slave asserts an ACK on the data line.
9) The slave sends 8 data bits.
When PEC is enabled, the Write Byte protocol becomes:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write
bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends an 8-bit memory address.
5) The active slave asserts an ACK on the data line.
6) The master sends an 8-bit data byte.
10) The master asserts an ACK on the data line.
11) The slave sends an 8-bit PEC byte.
12) The master asserts a NACK on the data line.
13) The master generates a STOP condition.
______________________________________________________________________________________ 35
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Block Write
The block write protocol (see Figure 11) allows the mas-
ter device to write a block of data (1 byte to 16 bytes) to
memory. Preload the destination address by a previous
send byte command; otherwise the block write com-
mand begins to write at the current address pointer.
After the last byte is written, the address pointer remains
preset to the next valid address. If the number of bytes
to be written causes the address pointer to exceed 8Fh
for configuration registers or configuration flash or FFh
for user flash, the address pointer stays at 8Fh or FFh,
respectively, overwriting this memory address with the
remaining bytes of data. The slave generates a NACK at
step 5 if the command code is invalid or if the device is
busy, and the address pointer is not altered.
9) The slave asserts an ACK on the data line.
10) Repeat 8 and 9 n - 1 times.
11) The master sends an 8-bit PEC byte.
12) The slave asserts an ACK on the data line (if PEC is
good, otherwise NACK).
13) The master generates a STOP condition.
Block Read
The block read protocol (see Figure 11) allows the
master device to read a block of up to 16 bytes from
memory. Read fewer than 16 bytes of data by issuing
an early STOP condition from the master, or by generat-
ing a NACK with the master. The destination address
should be preloaded by a previous send byte command;
otherwise the block read command begins to read at
the current address pointer. If the number of bytes to
be read causes the address pointer to exceed 8Fh for
the configuration register or configuration flash or FFh
in user flash, the address pointer stays at 8Fh or FFh,
respectively. The block read procedure is the following:
The block write procedure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
1) The master sends a START condition.
4) The master sends the 8-bit command code for block
write (A5h).
2) The master sends the 7-bit slave address and a write
bit (low).
5) The addressed slave asserts an ACK on SDA.
3) The addressed slave asserts an ACK on SDA.
6) The master sends the 8-bit byte count (1 byte to 16
bytes), n.
4) The master sends 8 bits of the block read com-
mand (A6h).
7) The addressed slave asserts an ACK on SDA.
8) The master sends 8 bits of data.
5) The slave asserts an ACK on SDA, unless busy.
6) The master generates a REPEATED START condition.
9) The addressed slave asserts an ACK on SDA.
10) Repeat steps 8 and 9 n - 1 times.
7) The master sends the 7-bit slave address and a read
bit (high).
11) The
master
sends
a
STOP
condition.
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10) The master asserts an ACK on SDA.
11) The slave sends 8 bits of data.
When PEC is enabled, the Block Write protocol
becomes:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write
bit (low).
12) The master asserts an ACK on SDA.
13) Repeat steps 11 and 12 up to fifteen times.
14) The master asserts a NACK on SDA.
3) The addressed slave asserts an ACK on the data line.
4) The master sends 8 bits of the block write com-
mand code.
15) The master sends a STOP condition.When PEC is
enabled, the Block Read protocol becomes:
5) The slave asserts an ACK on the data line.
6) The master sends an 8-bit byte count (min 1, max
16), n.
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write
bit (low).
7) The slave asserts an ACK on the data line.
8) The master sends 8 bits of data.
3) The addressed slave asserts an ACK on the data line.
36 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 22. SMBus Alert Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
SMBus Alert Configuration
00 = Disabled
35h
235h
[1:0]
01 = Fault1 is SMBus ALERT
10 = Fault2 is SMBus ALERT
11 = ANY_FAULT is SMBus ALERT
4) The master sends 8 bits of the block read com-
mand code.
SMBALERT
The MAX16070/MAX16071 support the SMBus alert
protocol. To enable the SMBus alert output, set r35h[1:0]
according to Table 22, which configures a Fault1, Fault2,
or ANY_FAULT output to act as the SMBus alert. This
output is open-drain and uses the wired-OR configura-
tion with other devices on the SMBus. During a fault,
the MAX16070/MAX16071 assert ALERT low, signaling
the master that an interrupt has occurred. The master
responds by sending the ARA (Alert Response Address)
protocol on the SMBus. This protocol is a read byte with
09h as the slave address. The slave acknowledges the
ARA (09h) address and sends its own SMBus address to
the master. The slave then deasserts ALERT. The master
can then query the slave and determine the cause of the
fault. By checking r1Ch[6], the master can confirm that
the MAX16070/MAX16071 triggered the SMBus alert.
The master must send the ARA before clearing r1Ch[6].
Clear r1Ch[6] by writing a ‘1’.
5) The slave asserts an ACK on the data line unless busy.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave ID plus a read
bit (high).
8) The slave asserts an ACK on the data line.
9) The slave sends an 8-bit byte count (16).
10) The master asserts an ACK on the data line.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on the data line.
13) Repeat steps 11 and 12 up to 15 times.
14) The slave sends an 8-bit PEC byte.
15) The master asserts a NACK on the data line.
16) The master generates a STOP condition.
JTAG Serial Interface
The MAX16070/MAX16071 feature a JTAG port that
®
complies with a subset of the IEEE 1149.1 specifica-
tion. Either the SMBus or the JTAG interface can be used
to access internal memory; however, only one interface
is allowed to run at a time. The MAX16070/MAX16071
do not support IEEE 1149.1 boundary-scan functionality.
The MAX16070/MAX16071 contain extra JTAG instruc-
tions and registers not included in the JTAG specifica-
tion that provide access to internal memory. The extra
instructions include LOAD ADDRESS, WRITE DATA,
READ DATA, REBOOT, SAVE.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
______________________________________________________________________________________ 37
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
01100
REGISTERS
AND FLASH
01011
01010
01001
01000
00111
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
00110
MUX 1
MEMORY READ REGISTER
[LENGTH = 8 BITS]
00101
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
00100
00011
COMMAND
DECODER
USER CODE REGISTER
[LENGTH = 32 BITS]
01001
01010
01011
01100
01000
00111
SETFLSHADD
RSTFLSHADD
SETUSRFLSH
RSTUSRFLSH
SAVE
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
00000
11111
BYPASS REGISTER
[LENGTH = 1 BIT]
REBOOT
V
DB
INSTRUCTION REGISTER
[LENGTH = 5 BITS]
R
PU
TDI
MUX 2
TDO
TMS
TCK
TEST ACCESS PORT
(TAP) CONTROLLER
Figure 12. JTAG Block Diagram
Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
Test Access Port (TAP)
Controller State Machine
The TAP controller is a finite state machine that responds
to the logic level at TMS on the rising edge of TCK. See
Figure 13 for a diagram of the finite state machine. The
possible states are described in the following:
Select-DR-Scan: All test data registers retain their previ-
ous state. With TMS low, a rising edge of TCK moves the
controller into the capture-DR state and initiates a scan
sequence. TMS high during a rising edge on TCK moves
the controller to the select-IR-scan state.
Test-Logic-Reset: At power-up, the TAP controller
is in the test-logic-reset state. The instruction register
contains the IDCODE instruction. All system logic of the
device operates normally. This state can be reached
from any state by driving TMS high for five clock cycles.
Capture-DR: Data can be parallel-loaded into the test
data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected
test data register does not allow parallel loads, the test
38 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
TEST-LOGIC-RESET
1
0
1
1
1
SELECT-DR-SCAN
SELECT-IR-SCAN
RUN-TEST/IDLE
0
0
CAPTURE-DR
0
0
CAPTURE-IR
0
1
1
0
SHIFT-DR
0
SHIFT-IR
1
1
1
0
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
PAUSE-IR
0
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
0
Figure 13. Tap Controller State Diagram
data register remains at its current value. On the rising
edge of TCK, the controller goes to the shift-DR state if
TMS is low or it goes to the exit1-DR state if TMS is high.
the controller goes to the run-test/idle state if TMS is low
or goes to the select-DR-scan state if TMS is high.
Select-IR-Scan: All test data registers retain the previ-
ous states. The instruction register remains unchanged
during this state. With TMS low, a rising edge on TCK
moves the controller into the capture-IR state. TMS high
during a rising edge on TCK puts the controller back into
the test-logic-reset state.
Shift-DR: The test data register selected by the current
instruction connects between TDI and TDO and shifts
data one stage toward its serial output on each rising
edge of TCK while TMS is low. On the rising edge of TCK,
the controller goes to the exit1-DR state if TMS is high.
Exit1-DR: While in this state, a rising edge on TCK puts
the controller in the update-DR state. A rising edge on TCK
with TMS low puts the controller in the pause-DR state.
Capture-IR: Use the capture-IR state to load the shift
register in the instruction register with a fixed value. This
value is loaded on the rising edge of TCK. If TMS is high
on the rising edge of TCK, the controller enters the exit1-
IR state. If TMS is low on the rising edge of TCK, the
controller enters the shift-IR state.
Pause-DR: Shifting of the test data registers halts while
in this state. All test data registers retain their previous
state. The controller remains in this state while TMS is
low. A rising edge on TCK with TMS high puts the con-
troller in the exit2-DR state.
Shift-IR: In this state, the shift register in the instruction
register connects between TDI and TDO and shifts data
one stage for every rising edge of TCK toward the TDO
serial output while TMS is low. The parallel outputs of
the instruction register as well as all test data registers
remain at the previous states. A rising edge on TCK with
TMS high moves the controller to the exit1-IR state. A
rising edge on TCK with TMS low keeps the controller in
the shift-IR state while moving data one stage through
the instruction shift register.
Exit2-DR: A rising edge on TCK with TMS high while in
this state puts the controller in the update-DR state. A ris-
ing edge on TCK with TMS low enters the shift-DR state.
Update-DR: A falling edge on TCK while in the update-
DR state latches the data from the shift register path of
the test data registers into a set of output latches. This
prevents changes at the parallel output because of
changes in the shift register. On the rising edge of TCK,
______________________________________________________________________________________ 39
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the
rising edge of TCK, the controller enters the update-IR
state.
register connects between TDI and TDO. While in the
shift-IR state, a rising edge on TCK with TMS low shifts
the data one stage toward the serial output at TDO. A
rising edge on TCK in the exit1-IR state or the exit2-IR
state with TMS high moves the controller to the update-
IR state. The falling edge of that same TCK latches the
data in the instruction shift register to the instruction reg-
ister parallel output. Table 23 shows the instructions sup-
ported by the MAX16070/MAX16071 and the respective
operational binary codes.
Pause-IR: Shifting of the instruction shift register halts
temporarily. With TMS high, a rising edge on TCK puts
the controller in the exit2-IR state. The controller remains
in the pause-IR state if TMS is low during a rising edge
on TCK.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of TCK
in this state.
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through the
1-bit bypass test data register. This allows data to pass
from TDI to TDO without affecting the device’s operation.
Update-IR: The instruction code that has been shifted
into the instruction shift register latches to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the run-
test/idle state. With TMS high, the controller enters the
select-DR-scan state.
IDCODE: When the IDCODE instruction is latched into the
parallel instruction register, the identification data register
is selected. The device identification code is loaded into
the identification data register on the rising edge of TCK
following entry into the capture-DR state. Shift-DR can be
used to shift the identification code out serially through
TDO. During test-logic-reset, the IDCODE instruction
is forced into the instruction register. The identification
code always has a ‘1’ in the LSB position. The next 11 bits
identify the manufacturer’s JEDEC number and number
of continuation bytes followed by 16 bits for the device
and 4 bits for the version. See Table 24.
Instruction Register
The instruction register contains a shift register as well
as a latched 5-bit-wide parallel output. When the TAP
controller enters the shift-IR state, the instruction shift
Table 23. JTAG Instruction Set
INSTRUCTION
CODE
0x1F
0x00
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
NOTES
BYPASS
Mandatory instruction code
IDCODE
Load manufacturer ID code/part number
Load user code
USERCODE
LOAD ADDRESS
READ DATA
WRITE DATA
REBOOT
Load address register content
Read data pointed by current address
Write data pointed by current address
Reboot FLASH data content into register file
Trigger emergency save to flash
Flash page access ON
SAVE
SETFLSHADD
RSTFLSHADD
SETUSRFLSH
RSTUSRFLSH
Flash page access OFF
User flash access ON (must be in flash page already)
User flash access OFF (return to flash page)
Table 24. 32-Bit Identification Code
MSB
LSB
VERSION
REV
PART NUMBER (16 BITS)
MANUFACTURER (11 BITS)
00011001011
FIXED VALUE (1 BIT)
MAX16070
MAX16071
1000000000000011
1000000000000100
1
1
REV
00011001011
40 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 25. 32-Bit User-Code Data
MSB
LSB
Don’t Care
SMBus slave ID
See Table 20
User ID (r8Ah[7:0])
00000000000000000
USERCODE: When the USERCODE instruction latches
into the parallel instruction register, the user-code data
register is selected. The device user-code loads into the
user-code data register on the rising edge of TCK fol-
lowing entry into the capture-DR state. Shift-DR can be
used to shift the user-code out serially through TDO. See
Table 25. This instruction can be used to help identify
multiple MAX16070/MAX16071 devices connected in a
JTAG chain.
and GPIO_ input/output data. Use this page to access
registers 200h to 2FFh
RSTFLSHADD: This is an extension to the standard
IEEE 1149.1 instruction set. Use RSTFLSHADD to return
to the default page and disable access to the flash page.
SETUSRFLSH: This is an extension to the standard IEEE
1149.1 instruction set that allows access to the user flash
page. When on the configuration flash page, send the
SETUSRFLSH command, all addresses are recognized
as flash addresses only. Use this page to access regis-
ters 300h to 3FFh.
LOAD ADDRESS: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16070/MAX16071. When the LOAD
ADDRESS instruction latches into the instruction register,
TDI connects to TDO through the 8-bit memory address
test data register during the shift-DR state.
RSTUSRFLSH: This is an extension to the standard IEEE
1149.1 instruction set. Use RSTUSRFLSH to return to the
configuration flash page and disable access to the user
flash.
READ DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16070/MAX16071. When the READ DATA
instruction latches into the instruction register, TDI con-
nects to TDO through the 8-bit memory read test data
register during the shift-DR state.
Restrictions When Writing to Flash
Flash must be written to 8 bytes at a time. The initial
address must be aligned to 8-byte boundaries—the 3
LSBs of the initial address must be ‘000’. Write the 8
bytes using eight successive WRITE DATA commands.
WRITE DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16070/MAX16071. When the WRITE DATA
instruction latches into the instruction register, TDI con-
nects to TDO through the 8-bit memory write test data
register during the shift-DR state.
Applications Information
Device Behavior at Power-Up
is ramped from 0, the RESET output is high
When V
CC
impedance until V
reaches 1.4V, at which point RESET
CC
goes low. All other outputs are high impedance until V
CC
reaches 2.7V, when the flash contents are copied into
register memory. This takes 150Fs (max), after which the
outputs assume their programmed states.
REBOOT: This is an extension to the standard IEEE
1149.1 instruction set to initiate a software-controlled
reset to the MAX16070/MAX16071. When the REBOOT
instruction latches into the instruction register, the
MAX16070/MAX16071 reset and immediately begin the
boot-up sequence.
Maintaining Power
During a Fault Condition
Power to the MAX16070/MAX16071 must be maintained
for a specific period of time to ensure a successful flash
fault log operation during a fault that removes power to
the circuit. Table 26 shows the amount of time required
depends on the settings in the fault control register
(r6Dh[1:0]).
SAVE: This is an extension to the standard IEEE 1149.1
instruction set that triggers a fault log. The current ADC
conversion results along with fault information are saved
to flash depending on the configuration of the Critical
Fault Log Control register (r6Dh).
Maintain power for shutdown during fault conditions in
applications where the always-on power supply cannot
be relied upon by placing a diode and a large capacitor
SETFLSHADD: This is an extension to the standard IEEE
1149.1 instruction set that allows access to the flash
page. Flash registers include ADC conversion results
between the voltage source, V , and V
(Figure 14).
IN
CC
______________________________________________________________________________________ 41
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The capacitor value depends on V and the time delay
across the diode, and V
is 2.7V. For example, with
IN
UVLO
required, t
. Use the following formula to cal-
FAULT_SAVE
a V of 14V, a diode drop of 0.7V, and a t
IN FAULT_SAVE
culate the capacitor size:
of 153ms, the minimum required capacitance is 202FF.
C = (t x I
)/(V - V
- V
)
FAULT_SAVE
CC(MAX)
IN
DIODE
UVLO
where the capacitance is in Farads and t
is in
FAULT_SAVE
seconds, I
is 14mA, V
is the voltage drop
CC(MAX)
DIODE
V
V
CC
IN
C
Table 26. Maximum Write Time
MAX16070
MAX16071
MAXIMUM
WRITE TIME
(ms)
r6Dh[1:0]
DESCRIPTION
VALUE
Save flags and ADC
readings
00
153
GND
01
10
11
Save flags
102
153
—
Save ADC readings
Do not save anything
Figure 14. Power Circuit for Shutdown During Fault Conditions
Figure 15. Graphical User Interface Screenshot
42 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Configuring the Device
R
S
An evaluation kit and a graphical user interface (GUI) is
available to create a custom configuration for the device.
Refer to the MAX16070/MAX16071 evaluation kit for con-
figuration.
I
LOAD
POWER
SUPPLY
MON
MON
EVEN
ODD
Cascading Multiple MAX16070/MAX16071s
Multiple MAX16070/MAX16071s can be cascaded to
increase the number of monitored rails. There are many
ways to cascade the devices depending on the desired
behavior. In general, there are several techniques:
MAX16070
MAX16071
U Configure a GPIO_ on each device to be EXTFAULT
(open drain). Externally wire them together with a
single pullup resistor. Set register bits r72h[5] and
r6Dh[2] to ‘1’ so that all faults will propagate between
devices. If a critical fault occurs on one device,
EXTFAULT will assert, triggering the nonvolatile fault
logger in all cascaded devices and recording a snap-
shot of all system voltages.
Figure 16. Current Monitoring Connection
Figure 16 shows how to connect a current-sense resis-
tor to a pair of MON_ inputs for monitoring both current
and voltage.
U Connect open-drain RESET outputs together to obtain
a master system reset signal.
For best accuracy, set the voltage range on the even-
numbered MON_ to 1.4V. Since the ADC conversion
results are 10 bits, the monitoring precision is 1.4V/1024
= 1.4mV. For more accurate current measurements,
use larger current-sense resistors. The application
requirements should determine the balance between
accuracy and voltage drop across the current-sense
resistor.
U Connect all EN inputs together for a master enable
signal.
Monitoring Current Using
the Differential Inputs
The MAX16070/MAX16071 can monitor up to seven
currents using the dedicated current-sense amplifier as
well as up to six pairs of inputs configured in differential
mode. The accuracy of the differential pairs is limited by
the voltage range and the 10-bit conversions. Each input
pair uses an odd-numbered MON_ input in combination
with an even-numbered MON_ input to monitor both the
voltage from the odd-numbered MON_ to ground and
the voltage difference between the two MON_ inputs.
This way a single pair of inputs can monitor the voltage
and the current of a power-supply rail. The overvoltage
threshold on the even numbered MON_ input can be
used as an overcurrent flag.
Layout and Bypassing
Bypass DBP and ABP each with a 1FF ceramic capacitor
to GND. Bypass V
with a 10FF capacitor to ground.
CC
Avoid routing digital return currents through a sensitive
analog area, such as an analog supply input return path
or ABP’s bypass capacitor ground connection. Use
dedicated analog and digital ground planes. Connect
the capacitors as close as possible to the device.
______________________________________________________________________________________ 43
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
ADC VALUES, FAULT REGISTERS, GPIO_S AS INPUT PORTS–NOT IN FLASH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E
01F
020
021
R
R
MON1 ADC output, MSBs
MON1 ADC output, LSBs
MON2 ADC output, MSBs
MON2 ADC output, LSBs
MON3 ADC output, MSBs
MON3 ADC output, LSBs
MON4 ADC output, MSBs
MON4 ADC output, LSBs
MON5 ADC output, MSBs
MON5 ADC output, LSBs
MON6 ADC output, MSBs
MON6 ADC output, LSBs
MON7 ADC output, MSBs
MON7 ADC output, LSBs
MON8 ADC output, MSBs
MON8 ADC output, LSBs
MON9 ADC output, MSBs
MON9 ADC output, LSBs
MON10 ADC output, MSBs
MON10 ADC output, LSBs
MON11 ADC output, MSBs
MON11 ADC output, LSBs
MON12 ADC output, MSBs
MON12 ADC output, LSBs
Current-sense ADC output
CSP ADC output, MSBs
CSP ADC output, LSBs
Fault register--failed line flags
Fault register—failed line flags/overcurrent
Reserved
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R
R
GPIO data in (read only)
Reserved
R
R/W
R
Flash status/reset output monitor
Reserved
44 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map (continued)
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
GPIO AND OUTPUT DEPENDENCIES/CONFIGURATIONS
230
231
232
233
234
235
236
237
238
239
23A
23B
23C
23D
23E
23F
240
241
242
030
031
032
033
034
035
036
037
038
039
03A
03B
03C
03D
03E
03F
040
041
042
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
SMBALERT pin configuration
Fault1 dependencies
Fault1 dependencies
Fault2 dependencies
Fault2 dependencies
Fault1/Fault2 secondary overcurrent dependencies
RESET output configuration
RESET output dependencies
RESET output dependencies
GPIO data out
GPIO configuration
GPIO configuration
GPIO configuration
GPIO push-pull/open drain
ADC—CONVERSIONS
243
244
245
246
247
043
044
045
046
047
R/W
R/W
R/W
R/W
R/W
ADCs voltage ranges—MON_ monitoring
ADCs voltage ranges—MON_ monitoring
ADCs voltage ranges—MON_ monitoring
Differential pairs enables
Current-sense gain-setting (CSP, HV or LV)
INPUT THRESHOLDS
248
249
24A
24B
24C
24D
24E
24F
250
251
252
253
048
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MON1 secondary selectable UV/OV
MON1 primary OV
049
04A
04B
04C
04D
04E
04F
050
051
052
053
MON1 primary UV
MON2 secondary selectable UV/OV
MON2 primary OV
MON2 primary UV
MON3 secondary selectable UV/OV
MON3 primary OV
MON3 primary UV
MON4 secondary selectable UV/OV
MON4 primary OV
MON4 primary UV
______________________________________________________________________________________ 45
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map (continued)
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
MON5 secondary selectable UV/OV
254
255
054
055
056
057
058
059
05A
05B
05C
05D
05E
05F
060
061
062
063
064
065
066
067
068
069
06A
06B
06C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MON5 primary OV
256
MON5 primary UV
257
MON6 secondary selectable UV/OV
MON6 primary OV
258
259
MON6 primary UV
25A
MON7 secondary selectable UV/OV
MON7 primary OV
25B
25C
MON7 primary UV
25D
MON8 secondary selectable UV/OV
MON8 primary OV
25E
25F
MON8 primary UV
260
MON9 secondary selectable UV/OV
MON9 primary OV
261
262
MON9 primary UV
263
MON10 secondary selectable UV/OV
MON10 primary OV
264
265
MON10 primary UV
266
MON11 secondary selectable UV/OV
MON11 primary OV
267
268
MON11 primary UV
269
MON12 secondary selectable UV/OV
MON12 primary OV
26A
26B
MON12 primary UV
26C
Secondary overcurrent threshold
FAULT SETUP
26D
06D
06E
06F
070
071
072
R/W
R/W
R/W
R/W
R/W
R/W
Save after EXTFAULT fault control
Faults causing store in flash
Faults causing store in flash
Faults causing store in flash
Faults causing store in flash
Faults causing store in flash
26E
26F
270
271
272
TIMEOUTS
Overcurrent debounce, watchdog mode, secondary threshold type, software
enables
273
073
R/W
274
275
276
277
074
075
076
077
R/W
R/W
R/W
R/W
ADC fault deglitch configuration
WDI toggle
Watchdog reset output enable, watchdog timers
Boot-up delay
46 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map (continued)
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
278
279
27A
27B
27C
27D
078
079
07A
07B
07C
07D
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MISCELLANEOUS
27E
27F
280
281
282
283
284
285
286
287
288
289
28A
28B
28C
28D
07E
07F
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Customer use (version)
PEC enable/I2C address
Lock bits
Revision code
NONVOLATILE FAULT LOG
200
201
202
203
204
205
206
207
208
209
20A
20B
20C
20D
20E
20F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
FAULT flags, MON1–MON8
FAULT flags, MON9–MON12, EXTFAULT
MON1 ADC output
MON2 ADC output
MON3 ADC output
MON4 ADC output
MON5 ADC output
MON6 ADC output
MON7 ADC output
MON8 ADC output
MON9 ADC output
MON10 ADC output
MON11 ADC output
MON12 ADC output
Current-sense ADC output
______________________________________________________________________________________ 47
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map (continued)
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
USER FLASH
300
3A0
3B0
39F
3AF
3FF
R/W
—
User flash
Reserved
User flash
R/W
Typical Operating Circuits
V
SUPPLY
+3.3V
OUT
OUT
OUT
IN
DC-DC
GND
MON1
V
CC
µC
MAX16070
MAX16071
SCL
SDA
IN
MON2–MON11
DC-DC
GND
RESET
FAULT
WDI
RESET
INT
I/O
WDO
INT
IN
MON12
DC-DC
GND
AO
GND
48 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Typical Operating Circuits (continued)
V
SUPPLY
+3.3V
OUT
IN
DC-DC
GND
MON1
MON2
V
CC
µC
LOAD
MAX16070
MAX16071
SCL
SDA
OUT
MON
MON
IN
ODD
DC-DC
GND
RESET
FAULT
WDI
RESET
INT
EVEN
I/O
LOAD
WDO
INT
OUT
IN
MON11
MON12
DC-DC
GND
AO
GND
LOAD
NOTE: MON
= MON1, MON3, MON5, MON7, MON9, MON11
= MON2, MON4, MON6, MON8, MON10, MON12
ODD
MON
EVEN
______________________________________________________________________________________ 49
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Pin Configurations
TOP VIEW
30 29 28 27 26 25 24 23 22 21
20
31
32
33
GPIO2
V
CC
19 GPIO1
18 GPIO8
ABP
GND
17
16
GPIO7
GND
MON7 34
35
36
37
38
39
40
MON8
MON9
MAX16070
15 SCL
14
AO
13 SDA
12
MON10
MON11
MON12
MON1
EP
8
+
TDO
11 TCK
1
2
3
4
5
6
7
9
10
TQFN
30 29 28 27 26 25 24 23 22 21
20
31
32
33
GPIO4
DBP
DBP
19 GPIO3
18 GPIO2
17 GPIO1
V
CC
ABP 34
16
GND
15 SCL
14
35
36
37
38
39
40
GND
MON7
MON8
N.C.
MAX16071
AO
13 SDA
12
EP
+
TDO
11 TCK
N.C.
MON1
1
2
3
4
5
6
7
8
9
10
TQFN
50 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE LAND PATTERN
NO.
NO.
40 TQFN-EP
T4066+5
21-0141
90-0055
______________________________________________________________________________________ 51
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
10/09
Initial release
—
1–5, 8, 10, 12, 13,
14, 19, 23–26,
29–31, 33–37,
41–43, 48–51
Updated Absolute Maximum Ratings and various sections to match current
style
1
6/10
2
3
2/11
8/11
Made correction to Table 16
27
Revised Pin Description and Pin Configuration
9, 50
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
52
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
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