MAX16939ATERB/V+ [MAXIM]
Switching Regulator, Current-mode, 6.2A, 2200kHz Switching Freq-Max, BICMOS, TQFN-16;
| 型号： | MAX16939ATERB/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Regulator, Current-mode, 6.2A, 2200kHz Switching Freq-Max, BICMOS, TQFN-16 信息通信管理 开关 |
| 文件： | 总17页 (文件大小：1046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converters
with 28µA Quiescent Current
General Description
Benefits and Features
● Integration and High-Switching Frequency Saves
The MAX16935/MAX16939 are 3.5A current-mode step-
down converters with integrated high-side and low-
side MOSFETs designed to operate with an external
Schottky diode for better efficiency. The low-side MOSFET
enables fixed-frequency forced-PWM (FPWM) operation
under light-load applications. The devices operate with
input voltages from 3.5V to 36V, while using only 28FA
quiescent current at no load. The switching frequency is
resistor programmable from 220kHz to 2.2MHz and can
be synchronized to an external clock. The devices’ output
voltage is available as 3.3V/5V fixed or adjustable from
1V to 10V. The wide input voltage range along with its
ability to operate at 98% duty cycle during undervoltage
transients make the devices ideal for automotive and
industrial applications.
Space
• Integrated 3.5A High-Side Switch
• Low-BOM-Count Current-Mode Control
Architecture
• Fixed Output Voltage with ±2% Accuracy or
Externally Resistor Adjustable (1V to 10V)
• 220kHz to 2.2MHz Switching Frequency with
Three Operation Modes (Skip Mode, Forced
Fixed-Frequency Operation, and External
Frequency Synchronization)
• Automatic LX Slew-Rate Adjustment for Optimum
Efficiency Across Operating Frequency Range
● 180° Out-of-Phase Clock Output at SYNCOUT
Enables Cascaded Power Supplies for Increased
Power Output
Under light-load applications, the FSYNC logic input
allows the devices to either operate in skip mode for
reduced current consumption or fixed-frequency FPWM
mode to eliminate frequency variation to minimize
EMI. Fixed-frequency FPWM mode is extremely use-
ful for power supplies designed for RF transceivers
where tight emission control is necessary. Protection
features include cycle-by-cycle current limit and thermal
shutdown with automatic recovery. Additional features
include a power-good monitor to ease power-supply
sequencing and a 180N out-of-phase clock output relative
to the internal oscillator at SYNCOUT to create cascaded
power supplies with multiple devices.
● Spread-Spectrum Frequency Modulation Reduces
EMI Emissions
● Wide Input Voltage Range Supports Automotive
Applications
• 3.5V to 36V Input Voltage Range (42V Tolerant)
• Enable Input Compatible from 3.3V Logic Level
to 42V
● Robust Performance Supports Wide Range of
Automotive Applications
• -40°C to +125°C Automotive Temperature Range
• Thermal-Shutdown Protection
• AEC-Q100 Qualified
The MAX16935/MAX16939 operate over the -40NC
to +125NC automotive temperature range and are
available in 16-pin (5mm x 5mm) TQFN-EP and 16-pin
TSSOP-EP packages.
● Power-Good Output Allows Power-Supply
Sequencing
● Tight Overvoltage Protection Provides Smaller
Applications
● Point-of-Load Applications
Overshoot Voltages (MAX16939)
● Distributed DC Power Systems
● Navigation and Radio Head Units
Ordering Information/Selector Guide and Typical
Application Circuit appear at end of data sheet.
19-6868; Rev 17; 1/18
MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converters
with 28µA Quiescent Current
Absolute Maximum Ratings
SUP, SUPSW, EN to PGND...................................-0.3V to +42V
LX (Note 1) ............................................................-0.3V to +42V
SUP to SUPSW.....................................................-0.3V to +0.3V
BIAS to AGND.........................................................-0.3V to +6V
SYNCOUT, FOSC, COMP, FSYNC,
Output Short-Circuit Duration....................................Continuous
Continuous Power Dissipation (T = +70NC)*
A
TQFN (derate 28.6mW/NC above +70NC)...............2285.7mW
TSSOP (derate 26.1mW/NC above +70NC).............2088.8mW
Operating Temperature Range .................... -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
PGOOD, FB to AGND ........................-0.3V to (V
+ 0.3V)
BIAS
OUT to PGND........................................................-0.3V to +12V
BST to LX (Note 1) ..................................................-0.3V to +6V
AGND to PGND...................................................-0.3V to + 0.3V
LX Continuous RMS Current ................................................3.5A
*As per JEDEC51 standard (multilayer board).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 2)
TQFN
TSSOP
Junction-to-Ambient Thermal Resistance (B ) ..........35NC/W
Junction-to-Ambient Thermal Resistance (B ) .......38.3NC/W
JA
JA
Junction-to-Case Thermal Resistance (B )..............2.7NC/W
Junction-to-Case Thermal Resistance (B ).................3NC/W
JC
JC
Note 1: Self-protected against transient voltages exceeding these limits for ≤ 50ns under normal operation and loads up to the maxi-
mum rated output current.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= V
= 14V, V
= 14V, L1 = 2.2FH, C = 4.7FF, C
= 22FF, C
= 1FF, C
= 0.1FF, R = 12kI,
FOSC
SUP
SUPSW
EN
IN
OUT
BIAS
BST
T
= T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
36
UNITS
Supply Voltage
V
V
3.5
V
SUP, SUPSW
Load-Dump Event Supply
Voltage
V
t
< 1s
LD
42
V
SUP_LD
Standby mode, no
load, V = 5V,
MAX16935/39
MAX16935C
MAX16935/39
MAX16935C
28
32
22
40
45
35
OUT
V
= 0V
FSYNC
Supply Current
I
FA
SUP_STANDBY
Standby mode, no
load, V = 3.3V,
OUT
23
5
36
10
V
V
V
= 0V
FSYNC
Shutdown Supply Current
BIAS Regulator Voltage
BIAS Undervoltage Lockout
I
= 0V
FA
V
SHDN
EN
= V
= 6V to 42V,
SUPSW
SUP
V
4.7
5
5.4
3.40
650
BIAS
I
= 0 to 10mA
rising
BIAS
BIAS
V
V
2.95
3.15
450
+175
15
V
UVBIAS
BIAS Undervoltage-Lockout
Hysteresis
mV
NC
NC
Thermal-Shutdown Threshold
Thermal-Shutdown Threshold
Hysteresis
Maxim Integrated
│ 2
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MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converters
with 28µA Quiescent Current
Electrical Characteristics (continued)
(V
= V
= 14V, V
= 14V, L1 = 2.2FH, C = 4.7FF, C
= 22FF, C
= 1FF, C
= 0.1FF, R = 12kI,
FOSC
SUP
SUPSW
EN
IN
OUT
BIAS
BST
T
= T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT VOLTAGE (OUT)
V
4.9
5
5.1
V
= V
6V < V < 36V,
SUPSW
OUT_5V
FB
BIAS,
FPWM Mode Output Voltage
V
V
fixed-frequency mode (Notes 3, 4)
V
3.234
4.9
3.3
5
3.366
5.15
3.4
OUT_3.3V
V
No load, V = V
FB
5)
skip mode (Note
OUT_SKIP_5V
BIAS,
Skip Mode Output Voltage
V
3.234
3.3
0.5
OUT_SKIP_3.3V
Load Regulation
Line Regulation
V
V
= V
= V
, 300mA < I < 3.5A
LOAD
%
%/V
mA
FA
FB
BIAS
, 6V < V
< 36V
FB
BIAS
SUPSW
0.02
1.5
(Note 4)
I
High-side MOSFET on, V
- V = 5V
1
2
5
BST_ON
BST
BST
LX
BST Input Current
High-side MOSFET off, V
- V = 5V,
LX
I
BST_OFF
T
= +25°C
A
LX Current Limit
LX Rise Time
I
Peak inductor current
= 12kW
4.2
5.2
4
6.2
A
LX
R
ns
FOSC
MAX16935
MAX16939
150
200
300
400
400
500
Skip Mode Current Threshold
I
T
= +25°C
mA
SKIP_TH
A
Spread Spectrum
Spread spectrum enabled
f
Q6%
OSC
High-Side-Switch
On-Resistance
R
I
= 1A, V = 5V
100
1
220
3
mI
FA
I
ON_H
LX
BIAS
High-Side-Switch Leakage
Current
High-side MOSFET off, V
V
= 36V,
SUP
= 0V, T = +25NC
LX
A
Low-Side Switch
On-Resistance
R
I
= 0.2A, V = 5V
BIAS
1.5
3
ON_L
LX
Low-Side Switch
Leakage Current
V
= 36V, T = +25NC
1
FA
LX
A
TRANSCONDUCTANCE AMPLIFIER (COMP)
FB Input Current
I
20
1.0
100
nA
V
FB
FB connected to an external resistor
divider, 6V < V < 36V (Note 6)
FB Regulation Voltage
V
0.99
1.015
FB
SUPSW
FB Line Regulation
DV
6V < V
< 36V
0.02
700
%/V
FS
LINE
SUPSW
Transconductance
(from FB to COMP)
g
V
= 1V, V
= 5V
m
FB
BIAS
Minimum On-Time
t
(Note 5)
80
98
ns
%
ON_MIN
Maximum Duty Cycle
OSCILLATOR FREQUENCY
DC
MAX
R
R
= 73.2kI
= 12kI
340
2.0
400
2.2
460
2.4
kHz
FOSC
Oscillator Frequency
MHz
FOSC
Maxim Integrated
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MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converters
with 28µA Quiescent Current
Electrical Characteristics (continued)
(V
= V
= 14V, V
= 14V, L1 = 2.2FH, C = 4.7FF, C
= 22FF, C
= 1FF, C
= 0.1FF, R = 12kI,
FOSC
SUP
SUPSW
EN
IN
OUT
BIAS
BST
T
= T = -40NC to +125NC, unless otherwise noted. Typical values are at T = +25NC.)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL CLOCK INPUT (FSYNC)
External Input Clock
Acquisition time
t
1
Cycles
MHz
V
FSYNC
External Input Clock
Frequency
R
= 12kI (Note 7)
1.8
1.4
2.6
FOSC
External Input Clock High
Threshold
V
V
rising
falling
FSYNC_HI
FSYNC
FSYNC
External Input Clock Low
Threshold
V
V
0.4
12
V
FSYNC_LO
Soft-Start Time
t
5.6
2.4
8
ms
SS
ENABLE INPUT (EN)
Enable Input High Threshold
Enable Input Low Threshold
V
V
EN_HI
V
0.6
EN_LO
Enable Threshold Voltage
Hysteresis
V
0.2
0.1
V
EN_HYS
Enable Input Current
I
T
= +25NC
A
1
FA
EN
POWER GOOD (PGOOD)
V
V
V
rising, V
= high
93
4.5
90
95
97
%V
FB
TH_RISING
FB
PGOOD
falling, V
= low
= 5V)
FB
PGOOD
V
(MAX16935C, V
PGOOD Switching Level
OUT
PGOOD
PGOOD
V
TH_FALLING
V
V
falling, V
falling, V
= low
92
92.5
25
94
94.5
50
%V
%V
FB
FB
= low (MAX16935C)
90.5
10
FB
FB
PGOOD Debounce Time
PGOOD Assertion Delay
PGOOD Output Low Voltage
PGOOD Leakage Current
SYNCOUT Low Voltage
Fs
V
rising edge (MAX16935B)
= 5mA
200
300
Fs
V
OUT
I
0.4
1
SINK
V
in regulation, T = +25NC
FA
V
OUT
A
I
= 5mA
0.4
1
SINK
SYNCOUT Leakage Current
FSYNC Leakage Current
OVERVOLTAGE PROTECTION
T
T
= +25NC
FA
FA
A
A
= +25NC
1
MAX16935
MAX16939
MAX16935
MAX16939
107
105
105
102
V
rising (monitored
OUT
at FB pin)
Overvoltage-Protection
Threshold
%
V
falling (monitored
OUT
at FB pin)
Note 3: Device not in dropout condition.
Note 4: Filter circuit required, see the Typical Application Circuit.
Note 5: Guaranteed by design; not production tested.
Note 6: FB regulation voltage is 1%, 1.01V (max), for -40°C < T < +105°C.
A
Note 7: Contact the factory for SYNC frequency outside the specified range.
Maxim Integrated
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MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converter
with 28µA Quiescent Current
Typical Operating Characteristics
(V
= V
= 14V, V = 14V, V
= 5V, V
= 0V, R
= 12kI, T = +25NC, unless otherwise noted.)
SUP
SUPSW
EN
OUT
FYSNC
FOSC
A
VOUT LOAD REGULATION
EFFICIENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
toc03
toc01
toc02
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 5V, VIN = 14V
SKIP MODE
fSW = 2.2MHz, VIN = 14V
fSW = 400kHz, VIN = 14V
SKIP MODE
5V
SKIP MODE
5V
400kHz
3.3V
3.3V
5V
3.3V
3.3V
5V
PWM MODE
PWM MODE
2.2MHz
0.0000
0.0010
0.1000
10.0000
0.0000
0.0010
0.1000
10.0000
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
LOAD CURRENT (A)
LOAD CURRENT (A)
ILOAD (A)
VOUT LOAD REGULATION
fSW vs. LOAD CURRENT
fSW vs. LOAD CURRENT
toc04
toc05
toc06
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
2.30
2.28
2.26
2.24
2.22
2.20
2.18
2.16
2.14
2.12
2.10
445
443
441
439
437
435
433
431
429
427
425
VIN = 14V,
PWM MODE
VIN = 14V,
PWM MODE
VOUT = 5V, VIN = 14V
PWM MODE
400kHz
VOUT = 5V
VOUT = 5V
VOUT = 3.3V
2.2MHz
VOUT = 3.3V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
ILOAD (A)
2.0
2.5
3.0
3.5
ILOAD (A)
ILOAD (A)
SWITCHING FREQUENCY vs. R
f
vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
FOSC
SW
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
50
45
40
35
30
25
20
15
10
V
= 14V,
IN
2.28
2.24
2.20
2.16
2.12
2.08
2.04
2.00
PWM MODE
V
= 5V
OUT
5V/2.2MHz
SKIP MODE
12
42
72
(kΩ)
102
132
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
6
16
26
36
R
SUPPLY VOLTAGE (V)
FOSC
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MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converter
with 28µA Quiescent Current
Typical Operating Characteristics (continued)
(V
= V
= 14V, V = 14V, V
= 5V, V
= 0V, R
= 12kI, T = +25NC, unless otherwise noted.)
SUP
SUPSW
EN
OUT
FYSNC
FOSC A
V
vs. V
V
vs. TEMPERATURE
SHDN CURRENT vs. SUPPLY VOLTAGE
OUT
IN
BIAS
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
10
5.02
5V/2.2MHz
PWM MODE
I
= 0A
LOAD
5.01
5.00
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.92
4.91
4.90
9
8
7
6
5
4
3
2
1
0
I
= 0A
LOAD
5V/2.2MHz
SKIP MODE
V
= 14V,
PWM MODE
IN
6
12
18
24
30
36
42
6
12
18
24
30
36
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
V
(V)
SUPPLY VOLTAGE (V)
IN
SLOW VIN RAMP BEHAVIOR
FULL-LOAD STARTUP BEHAVIOR
V
vs. V
IN
OUT
toc15
toc14
5.05
5.03
5.01
4.99
4.97
4.95
5V/400kHz
PWM MODE
10V/div
0V
10V/div
0V
I
= 0A
LOAD
VIN
VIN
5V/div
0V
5V/div
0V
VOUT
1A/div
0V
VOUT
5V/div
0V
VPGOOD
2A/div
0V
ILOAD
5V/div
0V
ILOAD
VPGOOD
6
12
18
24
30
36
V
(V)
IN
SYNC FUNCTION
DIPS AND DROPS TEST
toc17
toc18
10V/div
V
IN
5V/2.2MHz
0V
V
5V/div
2V/div
LX
5V/div
V
OUT
0V
10V/div
V
LX
V
FSYNC
0V
5V/div
V
PGOOD
0V
200ns
10ms
Maxim Integrated
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MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converter
with 28µA Quiescent Current
Typical Operating Characteristics (continued)
(V
= V
= 14V, V = 14V, V
EN
= 5V, V
= 0V, R
= 12kI, T = +25NC, unless otherwise noted.)
SUP
SUPSW
OUT
FYSNC
FOSC
A
COLD CRANK
LOAD DUMP
toc19
toc20
V
IN
10V/div
V
IN
2V/div
2V/div
0V
V
OUT
V
OUT
5V/div
0V
V
PGOOD
2V/div
0V
400ms
100ms
LOAD TRANSIENT (PWM MODE)
SHORT CIRCUIT IN PWM MODE
toc21
toc22
2V/div
200mV/
div
VOUT
(AC_COUPLED)
V
OUT
0V
2A/div
0A
INDUCTOR
CURRENT
2A/
div
0A
LOAD
CURRENT
5V/div
0V
V
PGOOD
10ms
Maxim Integrated
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MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converters
with 28µA Quiescent Current
Pin Configurations
TOP VIEW
16 15 14 13 12 11 10
9
12
11
10
9
BST
8
7
6
5
LX 13
PGND 14
PGOOD 15
MAX16935
MAX16939
AGND
BIAS
MAX16935
MAX16939
EP
+
16
EP
4
COMP
SYNCOUT
+
1
2
3
4
5
6
7
8
1
2
3
TQFN
TSSOP
Pin Descriptions
PIN
NAME
FUNCTION
TQFN
TSSOP
Open-Drain Clock Output. SYNCOUT outputs 180N out-of-phase signal relative to the
internal oscillator. Connect to OUT with a resistor between 100I and 1kW for 2MHz
operation. For low frequency operation, use a resistor between 1kW and 10kW.
16
1
SYNCOUT
FSYNC
Synchronization Input. The device synchronizes to an external signal applied to
FSYNC. Connect FSYNC to AGND to enable skip mode operation. Connect to BIAS or
to an external clock to enable fixed-frequency forced PWM mode operation.
1
2
Resistor-Programmable Switching Frequency Setting Control Input. Connect a resistor
from FOSC to AGND to set the switching frequency.
2
3
4
5
3
4
5
6
FOSC
OUT
FB
Switching Regulator Output. OUT also provides power to the internal circuitry when
the output voltage of the converter is set between 3V to 5V during standby mode.
Feedback Input. Connect an external resistive divider from OUT to FB and AGND to
set the output voltage. Connect to BIAS to set the output voltage to 5V.
Error Amplifier Output. Connect an RC network from COMP to AGND for stable
operation. See the Compensation Network section for more information.
COMP
Linear Regulator Output. BIAS powers up the internal circuitry. Bypass with a 1FF
capacitor to ground.
6
7
8
7
8
9
BIAS
AGND
BST
Analog Ground
High-Side Driver Supply. Connect a 0.1FF capacitor between LX and BST for
proper operation.
SUP Voltage Compatible Enable Input. Drive EN low to disable the device. Drive EN
high to enable the device.
9
10
EN
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MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converters
with 28µA Quiescent Current
Pin Descriptions (continued)
PIN
NAME
FUNCTION
TSSOP
TQFN
Voltage Supply Input. SUP powers up the internal linear regulator. Bypass SUP to
PGND with a 4.7FF ceramic capacitor. It is recommended to add a placeholder for
an RC filter to reduce noise on the internal logic supply (see the Typical Application
Circuit)
10
11
SUP
Internal High-Side Switch Supply Input. SUPSW provides power to the internal switch.
Bypass SUPSW to PGND with 0.1FF and 4.7FF ceramic capacitors.
11
12
SUPSW
12, 13
14
13, 14
15
LX
Inductor Switching Node. Connect a Schottky diode between LX and AGND.
Power Ground
PGND
Open-Drain, Active-Low Power-Good Output. PGOOD asserts when V
is above
OUT
15
16
PGOOD
95% regulation point. PGOOD goes low when V
is below 92% regulation point.
OUT
Exposed Pad. Connect EP to a large-area contiguous copper ground plane for
effective power dissipation. Do not use as the only IC ground connection. EP must be
connected to PGND.
—
—
EP
Wide Input Voltage Range
Detailed Description
The devices include two separate supply inputs (SUP and
SUPSW) specified for a wide 3.5V to 36V input voltage
The MAX16935/MAX16939 are 3.5A current-mode step-
down converters with integrated high-side and low-side
MOSFETs designed to operate with an external Schottky
diode for better efficiency. The low-side MOSFET
enables fixed-frequency forced-PWM (FPWM) operation
under light-load applications. The devices operate with
input voltages from 3.5V to 36V, while using only 28FA
quiescent current at no load. The switching frequency
is resistor programmable from 220kHz to 2.2MHz and
can be synchronized to an external clock. The output
voltage is available as 3.3V/5V fixed or adjustable from
1V to 10V. The wide input voltage range along with its
ability to operate at 98% duty cycle during undervoltage
transients make the devices ideal for automotive and
industrial applications.
range. V
provides power to the device and V
SUP
SUPSW
provides power to the internal switch. When the device
is operating with a 3.5V input supply, conditions such as
cold crank can cause the voltage at SUP and SUPSW to
drop below the programmed output voltage. Under such
conditions, the device operate in a high duty-cycle mode
to facilitate minimum dropout from input to output.
In applications where the input voltage exceeds 25V,
output is ≤ 5V, operating frequency is ≥ 1.8MHz and the
IC is selected to be in FPWM mode by either forcing the
FSYNC pin high, or using an external clock, pulse skipping
is observed on the LX pin. This happens due to insufficient
minimum on time. Under certain load conditions (typically
< 1A), a filter circuit from LX to GND is required to maintain
the output voltage within the expected data sheet limits. A
Under light-load applications, the FSYNC logic input
allows the devices to either operate in skip mode for
reduced current consumption or fixed-frequency FPWM
mode to eliminate frequency variation to minimize EMI.
Fixed frequency FPWM mode is extremely useful for
power supplies designed for RF transceivers where
tight emission control is necessary. Protection
features include cycle-by-cycle current limit,
overvoltage protection, and thermal shutdown with auto-
matic recovery. Additional features include a power-
good monitor to ease power-supply sequencing
and a 180N out-of-phase clock output relative to the
internal oscillator at SYNCOUT to create cascaded power
supplies with multiple devices.
typical filter value of R
= 1I, C
= 220pF (see
FILTER
FILTER
the Typical Application Circuit) is sufficient to filter out the
noise and maintain the output voltage within data sheet
limits. This extra filter on the LX pin of the IC has no impact
on efficiency.
Linear Regulator Output (BIAS)
The devices include a 5V linear regulator (BIAS) that
provides power to the internal circuit blocks. Connect a
1FF ceramic capacitor from BIAS to AGND.
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OUT
COMP
PGOOD
EN
SUP
BIAS
FB
FBSW
FBOK
AON
HVLDO
SWITCH
OVER
BST
SUPSW
EAMP
PWM
LOGIC
HSD
REF
LX
CS
SOFT
START
BIAS
LSD
MAX16935
MAX16939
PGND
SLOPE
COMP
OSC
SYNCOUT
FSYNC FOSC
AGND
Figure 1. Internal Block Diagram
Power-Good Output (PGOOD)
reaching > 110% of the regulated voltage. If MAX16935C
output reaches overvoltage-protection thresholds it turns
on the active pulldown on the output (100Ω, typ) to
prevent the output from rising above 110% of regu-
lated voltage. This does not protect against a hard-short
across the HSFET of the IC.
The devices feature an open-drain power-good output,
PGOOD. PGOOD asserts when V rises above 95%
OUT
of its regulation voltage. PGOOD deasserts when V
OUT
drops below 92% of its regulation voltage. Connect
PGOOD to BIAS with a 10kI resistor.
Overvoltage Protection (OVP)
Synchronization Input (FSYNC)
If the output voltage reaches the OVP threshold, the
high-side switch is forced off and the low-side switch
is forced on until negative-current limit is reached. After
negative-current limit is reached, both the high-side and
low-side switches are turned off. The MAX16939 offers a
lower voltage threshold for applications requiring tighter
limits of protection.
FSYNC is a logic-level input useful for operating mode
selection and frequency control. Connecting FSYNC to
BIAS or to an external clock enables fixed-frequency
FPWM operation. Connecting FSYNC to AGND enables
skip mode operation.
The external clock frequency at FSYNC can be higher
or lower than the internal clock by 20%. Ensure the duty
cycle of the external clock used has a minimum pulse
width of 100ns. The devices synchronize to the external
The MAX16935C offers overvoltage protection in all
modes of operation and protects the output against
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Internal Oscillator (FOSC)
clock within one cycle. When the external clock signal
at FSYNC is absent for more than two clock cycles, the
devices revert back to the internal clock.
The switching frequency (f ) is set by a resistor (R
)
SW
FOSC
connected from FOSC to AGND. See Figure 3 to select
the correct R value for the desired switching fre-
FOSC
System Enable (EN)
quency. For example, a 400kHz switching frequency is set
with R = 73.2kI. Higher frequencies allow designs
An enable control input (EN) activates the device from its
low-power shutdown mode. EN is compatible with inputs
from automotive battery level down to 3.5V. The high
voltage compatibility allows EN to be connected to SUP,
KEY/KL30, or the inhibit pin (INH) of a CAN transceiver.
FOSC
with lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gate
charge currents, and switching losses increase.
EN turns on the internal regulator. Once V
is above
BIAS
Synchronizing Output (SYNCOUT)
SYNCOUT is an open-drain output that outputs a 180N
out-of-phase signal relative to the internal oscillator.
the internal lockout threshold, V
= 3.15V (typ), the
UVL
controller activates and the output voltage ramps up
within 8ms.
A logic-low at EN shuts down the device. During
shutdown, the internal linear regulator and gate drivers
turn off. Shutdown is the lowest power state and reduces
the quiescent current to 5FA (typ). Drive EN high to bring
the device out of shutdown.
Overtemperature Protection
Thermal-overload protection limits the total power
dissipation in the device. When the junction temperature
exceeds 175NC (typ), an internal thermal sensor shuts
down the internal bias regulator and the step-down
controller, allowing the device to cool. The thermal
sensor turns on the device again after the junction
temperature cools by 15NC.
Spread-Spectrum Option
The devices have an internal spread-spectrum option
to optimize EMI performance. This is factory set and the
S-version of the device should be ordered. For spread-
spectrum-enabled devices, the operating frequency is
varied 6% centered on the oscillator frequency (f
The modulation signal is a triangular wave with a period
).
OSC
of 110µs at 2.2MHz. Therefore, f will ramp down 6%
OSC
and back to 2.2MHz in 110µs and also ramp up 6% and
back to 2.2MHz in 110µs. The cycle repeats.
For operations at f
values other than 2.2MHz, the
OSC
modulation signal scales proportionally (e.g., at 400kHz,
the 110µs modulation period increases to 110µs x
2.2MHz/400kHz = 605µs).
The internal spread spectrum is disabled if the device is
synced to an external clock. However, the device does not
filter the input clock and passes any modulation (including
spread-spectrum) present on the driving external clock to
the SYNCOUT pin.
Automatic Slew-Rate Control on LX
The devices have automatic slew-rate adjustment that
optimizes the rise times on the internal HSFET gate drive
to minimize EMI. The device detects the internal clock
frequency and adjusts the slew rate accordingly. When
the user selects the external frequency setting resistor
V
OUT
R
R
FB1
FB2
MAX16935
MAX16939
FB
R
FOSC
such that the frequency is > 1.1MHz, the HSFET
is turned on in 4ns (typ). When the frequency is < 1.1MHz
the HSFET is turned on in 8ns (typ). This slew-rate control
optimizes the rise time on LX node externally to minimize
EMI while maintaining good efficiency.
Figure 2. Adjustable Output-Voltage Setting
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Applications Information
In skip mode of operation, the converter’s switching
frequency is load dependent. At higher load current, the
switching frequency does not change and the operating
mode is similar to the FPWM mode. Skip mode helps
improve efficiency in light-load applications by allowing
the converters to turn on the high-side switch only when
the output voltage falls below a set threshold. As such,
the converters do not switch MOSFETs on and off as
often as is the case in the FPWM mode. Consequently,
the gate charge and switching losses are much lower in
skip mode.
Setting the Output Voltage
Connect FB to BIAS for a fixed 5V output voltage. To
set the output to other voltages between 1V and 10V,
connect a resistive divider from output (OUT) to FB to
AGND (Figure 2). Use the following formula to determine
the R
of the resistive divider network:
FB2
R
FB2
= R x V /V
TOTAL FB OUT
where V = 1V, R
= selected total resistance of
FB
TOTAL
R , R
FB1 FB2
in ω, and V
is the desired output in volts.
OUT
Inductor Selection
Three key inductor parameters must be specified for
operation with the devices: inductance value (L), inductor
Calculate R
equation:
(OUT to FB resistor) with the following
FB1
V
OUT
R
= R
−1
saturation current (I
), and DC resistance (R
). To
DCR
FB2
FB1
SAT
V
FB
select inductance value, the ratio of inductor peak-to-
peak AC current to DC average current (LIR) must be
selected first. A good compromise between size and loss
is a 30% peak-to-peak ripple current to average current
ratio (LIR = 0.3). The switching frequency, input voltage,
output voltage, and selected LIR then determine the
inductor value as follows:
where V = 1V (see the Electrical Characteristics table).
FB
FPWM/Skip Modes
The devices offer a pin-selectable skip mode or fixed-
frequency PWM mode option. They have an internal LS
MOSFET that turns on when the FSYNC pin is connected
to V
or if there is a clock present on the FSYNC
BIAS
V
(V
− V
)
OUT SUP
OUT
LIR
pin. This enables the fixed-frequency-forced PWM mode
operation over the entire load range. This option allows the
user to maintain fixed frequency over the entire load range
in applications that require tight control on EMI. Even
though the device has an internal LS MOSFET for fixed-
frequency operation, an external Schottky diode is still
required to support the entire load range. If the FSYNC
pin is connected to GND, the skip mode is enabled on
the device.
L =
V
f
I
SUP SW OUT
where V
, V
, and I
are typical values (so that
OUT
SUP OUT
efficiency is optimum for typical conditions). The switch-
ing frequency is set by R
(see Figure 3).
FOSC
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor RMS current requirement (I
defined by the following equation:
) is
SWITCHING FREQUENCY vs. R
FOSC
RMS
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
V
(V
− V
)
OUT SUP
OUT
I
= I
RMS LOAD(MAX)
V
SUP
I
has a maximum value when the input voltage
RMS
equals twice the output voltage (V
I
= 2V
), so
SUP
OUT
= I
/2.
RMS(MAX)
LOAD(MAX)
Choose an input capacitor that exhibits less than +10NC
self-heating temperature rise at the RMS input current for
optimal long-term reliability.
The input voltage ripple is composed of DV (caused
Q
12
42
72
(kΩ)
102
132
by the capacitor discharge) and DV
(caused by the
ESR
R
FOSC
ESR of the capacitor). Use low-ESR ceramic capacitors
with high ripple current capability at the input. Assume
Figure 3. Switching Frequency vs. R
FOSC
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the contribution from the ESR and capacitor discharge
equal to 50%. Calculate the input capacitance and ESR
required for a specified input voltage ripple using the fol-
lowing equations:
V
OUT
R1
R2
COMP
∆V
ESR
g
m
ESR
=
IN
∆I
L
V
REF
R
C
I
+
OUT
2
C
F
where:
and:
C
C
(V
− V
)× V
SUP
V
OUT OUT
× f
∆I
=
L
×L
SUP
SW
Figure 4. Compensation Network
skip-mode operation. Connect this rectifier close to the
device, using short leads and short PCB traces. In FPWM
mode, the Schottky diode helps minimize efficiency
losses by diverting the inductor current that would other-
wise flow through the low-side MOSFET. Choose a rectifier
with a voltage rating greater than the maximum expected
I
×D(1− D)
V
OUT
V
SUPSW
OUT
C
=
and D =
IN
∆V × f
Q
SW
where I
is the maximum output current and D is the
OUT
duty cycle.
Output Capacitor
input voltage, V
. Use a low forward-voltage-drop
SUPSW
Schottky rectifier to limit the negative voltage at LX. Avoid
higher than necessary reverse-voltage Schottky rectifiers
that have higher forward-voltage drops.
The output filter capacitor must have low enough ESR
to meet output ripple and load transient requirements.
The output capacitance must be high enough to absorb
the inductor energy while transitioning from full-load
to no-load conditions without tripping the overvoltage
fault protection. When using high-capacitance, low-ESR
capacitors, the filter capacitor’s ESR dominates the
output voltage ripple. So the size of the output capaci-
tor depends on the maximum ESR required to meet the
Compensation Network
The devices use an internal transconductance error ampli-
fier with its inverting input and its output available to the
user for external frequency compensation. The output
capacitor and compensation network determine the loop
stability. The inductor and the output capacitor are chosen
based on performance, size, and cost. Additionally, the
compensation network optimizes the control-loop stability.
output voltage ripple (V ) specifications:
RIPPLE(P-P)
V
= ESR×I
×LIR
RIPPLE(P−P)
LOAD(MAX)
The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required
current through the external inductor. The device uses
the voltage drop across the high-side MOSFET to sense
inductor current. Current-mode control eliminates the
double pole in the feedback loop caused by the inductor
and output capacitor, resulting in a smaller phase shift
and requiring less elaborate error-amplifier compensation
than voltage-mode control. Only a simple single-series
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as
to the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value.
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by
the capacity needed to prevent voltage droop and
voltage rise from causing problems during load
transients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
rising load edge is no longer a problem. However, low
capacity filter capacitors typically have high ESR zeros
that can affect the overall stability.
resistor (R ) and capacitor (C ) are required to have a
C
C
stable, high-bandwidth loop in applications where ceramic
capacitors are used for output filtering (Figure 4). For other
types of capacitors, due to the higher capacitance and
ESR, the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output capacitor
Rectifier Selection
The devices require an external Schottky diode rectifier
as a freewheeling diode when they are configured for
loop, add another compensation capacitor (C ) from
F
COMP to GND to cancel this ESR zero.
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The basic regulator loop is modeled as a power
modulator, output feedback divider, and an error
amplifier. The power modulator has a DC gain set by
1
f
=
dpEA
2π × C ×(R
+ R )
C
C
OUT,EA
g
O R
, with a pole and zero pair set by R
,
1
m
LOAD
LOAD
f
=
=
zEA
the output capacitor (C
equations allow to approximate the value for the gain
of the power modulator (GAIN ), neglecting the
effect of the ramp stabilization. Ramp stabilization is
necessary when the duty cycle is above 50% and is
internally done for the device.
), and its ESR. The following
OUT
2π × C ×R
C
C
C
1
f
MOD(dc)
pEA
2π × C ×R
F
The loop-gain crossover frequency (f ) should be set
C
below 1/5th of the switching frequency and much higher
than the power-modulator pole (f
GAIN
= g ×R
m LOAD
):
MOD(dc)
/I
pMOD
where R
= V
in I and g = 3S.
m
f
LOAD
OUT LOUT(MAX)
SW
f
<< f ≤
C
pMOD
5
In a current-mode step-down converter, the output
capacitor, its ESR, and the load resistance introduce a
pole at the following frequency:
The total loop gain as the product of the modulator gain,
the feedback voltage-divider gain, and the error amplifier
gain at f should be equal to 1. So:
C
1
f
=
pMOD
2π × C
×R
LOAD
OUT
V
FB
GAIN
×
×GAIN
= 1
MOD(fC)
EA(fC)
C
V
The output capacitor and its ESR also introduce a zero at:
1
OUT
GAIN
= g
×R
EA(fC)
m, EA
f
=
zMOD
2π ×ESR× C
OUT
f
pMOD
GAIN
= GAIN
×
MOD(fC)
MOD(dc)
When C
is composed of “n” identical capacitors
OUT
f
C
in parallel, the resulting C
= n O C
, and
OUT
OUT(EACH)
Therefore:
GAIN
ESR = ESR
/n. Note that the capacitor zero for a
parallel combination of alike capacitors is the same as for
an individual capacitor.
(EACH)
V
FB
×
×g
×R = 1
m,EA C
MOD(fC)
V
OUT
The feedback voltage-divider has a gain of GAIN = V
/
FB
FB
Solving for R :
C
V
OUT
, where V is 1V (typ). The transconductance error
FB
amplifier has a DC gain of GAIN
= g
O R
,
V
,
EA(dc)
m EA
OUT,EA
OUT
R
=
C
where g
is the error amplifier transconductance,
m,EA
g
× V ×GAIN
FB MOD(fC)
m,EA
which is 700FS (typ), and R
resistance of the error amplifier 50MI.
is the output
OUT,EA
Set the error-amplifier compensation zero formed by R
C
a
and C (f
follows:
) at the f
zEA
. Calculate the value of C
pMOD
C
C
A dominant pole (f ) is set by the compensation
capacitor (C ) and the amplifier output resistance
) is set by the compensation
resistor (R ) and the compensation capacitor (C ).
dpEA
C
(R
OUT,EA
). A zero (f
1
zEA
C
=
C
C
C
2π × f
×R
C
pMOD
There is an optional pole (f
) set by C and R to
pEA
F C
If f
is less than 5 x f , add a second capacitor,
C
zMOD
cancel the output capacitor ESR zero if it occurs near
C , from COMP to GND and set the compensation pole
F
the crossover frequency (f ), where the loop gain equals
C
formed by R and C (f
) at the f
pEA
. Calculate the
C
F
zMOD
1 (0dB)). Thus:
value of C as follows:
F
1
C
=
F
2π × f
×R
zMOD
C
As the load current decreases, the modulator pole
also decreases; however, the modulator gain increases
accordingly and the crossover frequency remains the
same.
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PCB Layout Guidelines
4) Keep the power traces and load connections short. This
practice is essential for high efficiency. Use thick copper
PCBs (2oz vs. 1oz) to enhance full-load efficiency.
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. Use a multilayer board
whenever possible for better noise immunity and power
dissipation. Follow these guidelines for good PCB layout:
5) The analog signal lines should be routed away from
the high-frequency planes. Doing so ensures integrity
of sensitive signals feeding back into the IC.
1) Use a large contiguous copper plane under the IC
package. Ensure that all heat-dissipating compo-
nents have adequate cooling. The bottom pad of the
IC must be soldered down to this copper plane for
effective heat dissipation and for getting the full power
out of the IC. Use multiple vias or a single large via in
this plane for heat dissipation.
6) The ground connection for the analog and power
section should be close to the IC. This keeps the
ground current loops to a minimum. In cases where
only one ground is used, enough isolation between
analog return signals and high power signals must be
maintained.
2) Isolate the power components and high current path
from the sensitive analog circuitry. Doing so is essential
to prevent any noise coupling into the analog signals.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. The high-current path composed
of the input capacitor, high-side FET, inductor, and
the output capacitor should be as short as possible.
Typical Application Circuit
V
BAT
C
C
IN2
IN1
C
BST
SUP
SUPSW
BST
0.22µF
L1
2.2µH
V
OUT
EN
5V AT 3.5A
LX
OSC SYNC PULSE
FSYNC
V
D1
C
22µF
OUT
OUT
V
BIAS
MAX16935
MAX16939
R
SNUB*
OUT
FB
COMP
C
SNUB*
C
COMP1
R
FOSC
1000pF
C
COMP2
12pF
12kI
V
V
BIAS
OUT
R
COMP
FOSC
BIAS
20kI
R
R
PGOOD
SYNCOUT
100I
10kI
PGOOD
POWER-GOOD OUTPUT
C
BIAS
1µF
SYNCOUT
180° OUT-OF-PHASE OUTPUT
PGND AGND
*R
= 1Iand C
= 220pF required for the following
FILTER
FILTER
operating conditions:
ꢀ 25V, V
V
ꢁ 5V, f ꢀ 1.8MHz, FPWM mode enabled
SW
BAT
OUT
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Ordering Information/Selector Guide
V
OUT
SPREAD
SPECTRUM
PIN-
PACKAGE
ADJUSTABLE
(FB CONNECTED TO
RESISTIVE DIVIDER) (V)
FIXED
(FB CONNECTED
TO BIAS) (V)
PART
TEMP RANGE
MAX16935BAUER/V+
MAX16935BAUES/V+
MAX16935CAUER/V+
MAX16935CAUES/V+
MAX16935CAUERB/V+
MAX16935CAUESB/V+
MAX16935RATE/V+
MAX16935RATEB/V+
MAX16935RAUE/V+
MAX16935RAUEB/V+
MAX16935SATE/V+
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
1 to 10
5
5
Off
On
Off
On
Off
On
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off
On
On
On
On
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TQFN-EP*
-40°C to +125°C 16 TSSOP-EP*
-40°C to +125°C 16 TSSOP-EP*
5
5
3.3
3.3
5
3.3
5
3.3
5
MAX16935SATEB/V+
MAX16935SAUE/V+
MAX16935SAUEB/V+
MAX16939ATERA/V+
MAX16939ATERB/V+
MAX16939AUERA/V+**
MAX16939AUERB/V+**
MAX16939ATESA/V+
MAX16939ATESB/V+
MAX16939AUESA/V+**
MAX16939AUESB/V+**
3.3
5
3.3
5
3.3
5
3.3
5
3.3
5
3.3
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TQFN-EP
T1655+4
U16E+3
21-0140
21-0108
90-0121
90-0120
16 TSSOP-EP
Maxim Integrated
│ 16
www.maximintegrated.com
MAX16935/MAX16939
36V, 3.5A, 2.2MHz Step-Down Converters
with 28µA Quiescent Current
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
12/13
2/14
0
1
Initial release
—
Corrected typo for g value in Compensation Network section
13
m
Updated PGOOD pin description and updated Spread Spectrum, Automatic Slew-
Rate Control on LX, and Internal Oscillator (FOSC) sections
2
3/14
9, 11
Added TQFN options to General Description, Absolute Maximum Ratings, Package
Thermal Characteristics, Pin Configurations, Pin Description, Package Information,
and Ordering Information
3
1/15
1, 2, 8, 9, 18
4
5
2/15
3/15
Updated the Benefits and Features section
Corrected the first equation on the top left side of page
14
Added 3.3V output-voltage option; updated General Description, Absolute Maximum
Ratings, Package Thermal Characteristics, Electrical Characteristics, and Detailed
Description sections, deleted graph 16 and replaced graphs 01–06, 14, 15, 21 in
Typical Operating Characteristics; added four new /V OPNs to Ordering Information/
Selector Guide
6
5/15
1–7, 9, 16
7
8
5/15
6/15
6/15
4/16
Removed future product designations in Ordering Information
16
1–17
16
Added the MAX16939 to the data sheet as a future product
9
Corrected MAX16939 variants in Ordering Information/Selector Guide
Added bullet to Benefits and Features section, removed future product references
10
1, 16
Added PGOOD Assertion Delay in Electrical Characteristics, and added new
MAX16935 variants in Ordering Information/Selector Guide
11
12
8/16
4/17
4, 16
16
Removed future product status from MAX16935BAUES/V+/MAX16935BAUER/V+ in
Ordering Information/Selector Guide
Added Supply Current and PGOOD Switching Level for MAX16935C in Electrical
Characteristics, and added new MAX16935C future product variants in Ordering
Information/Selector Guide
13
14
15
5/17
6/17
2, 4, 16
4, 10, 16
16
Added new row in PGOOD Switching Level for MAX16935C in Electrical
Characteristics, updated Overvoltage Protection (OVP) section, and changed seven
variants in Ordering Information/Selector Guide from TSSOP-EP to TQFN-EP
Removed future product status from MAX16935CAUER/V+, MAX16935CAUES/
V+; added MAX16935CAUERB/V+, MAX16935CAUESB/V+ as future products in
Ordering Information/Selector Guide
7/17
Removed future product status from MAX16935CAUERB/V+, MAX16935CAUESB/
V+ in Ordering Information/Selector Guide
16
16.1
17
10/17
16
16
16
Added back future product status on MAX16935CAUERB/V+, MAX16935CAUESB/
V+ in Ordering Information/Selector Guide
Removed future product status from MAX16935CAUERB/V+, MAX16935CAUESB/
V+ in Ordering Information/Selector Guide
1/18
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2018 Maxim Integrated Products, Inc.
│ 17
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