MAX16993AGJD/VY+ [MAXIM]
Dual Switching Controller, Current-mode, 2100kHz Switching Freq-Max, QFND-32;
| 型号： | MAX16993AGJD/VY+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller, Current-mode, 2100kHz Switching Freq-Max, QFND-32 开关 |
| 文件： | 总24页 (文件大小：1088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
General Description
Benefits and Features
● High-Efficiency Voltage DC-DC Controller Saves
The MAX16993 power-management integrated circuit
(PMIC) is a 2.1MHz, multichannel, DC-DC convert-
er designed for automotive applications. The device
integrates three supplies in a small footprint. The device
includes one high-voltage step-down controller (OUT1)
designed to run directly from a car battery and two low-
voltage step-down converters (OUT2/OUT3) cascaded
from OUT1. Under no-load conditions, the MAX16993
consumes only 30µA of quiescent current, making it ideal
for automotive applications.
Power
• 3.5V to 36V Operating Supply Voltage
• Output Voltage: Pin Selectable, Fixed, or
Resistor-Divider Adjustable
• 350kHz to 2.1MHz Operation
• 30μAꢀQuiescentꢀCurrentꢀwithꢀDC-DCꢀ
Controller Enabled
● Dual 2.1MHz DC-DC Converters with Integrated
FETs Save Space
The high-voltage synchronous step-down DC-DC
controller (OUT1) operates from a voltage up to 36V
continuous and is protected from load-dump transients up
to 42V. There is a pin-selectable frequency option of either
2.1MHz or a factory-set frequency for 1.05MHz, 525kHz,
420kHz, or 350kHz. The low-voltage, synchronous step-
down DC-DC converters run directly from OUT1 and can
supply output currents up to 3A.
• OUT2 and OUT3 are Cascaded from OUT1,
Improving Efficiency
• 3A Integrated FETs
• 0.8V to 3.95V Output Voltage
• Fixed or Resistor-Divider-Adjustable Output Voltage
• 180° Out-of-Phase Operation
• Robust for the Automotive Environment
● Current-Mode Architecture with Forced-PWM and
Skip Modes of Operation
The device provides a spread-spectrum enable input
(SSEN) to provide quick improvement in electromagnetic
interference when needed. There is also a SYNC
input for providing an input to synchronize to
an external clock source (see the Selector Guide).
The device includes overtemperature shutdown and
overcurrent limiting. The device also includes indi-
vidual RESET_ outputs and individual enable inputs.
The individual RESET_ outputs provide voltage
monitoring for all output channels.
• Frequency Synchronization Input/Output Reduces
System Noise
• Individual Enable Inputs and RESET_ Outputs
• Overtemperature and Short-Circuit Protection
• AECQ-100ꢀQualified
• 32-Pin TQFN-EP (5mm x 5mm x 0.75mm) and
Side-Wettable QFND-EP (5mm x 5mm x 0.8mm)
• -40°C to +125°C Operating Temperature Range
The MAX16993 is available in a 32-pin TQFN/side-
wettable QFND-EP package and is specified for operation
over the -40°C to +125°C automotive temperature range.
Ordering Information and Selector Guide appear at end of
data sheet.
Applications
●ꢀ Automotive
●ꢀ Industrial
19-6684; Rev 14; 12/16
MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Absolute Maximum Ratings
V
, EN1 to GND ...............................................-0.3V to +45V
FB1, EN2, EN3 to GND........................................-0.3V to +6.0V
RESET_, ERR to GND.........................................-0.3V to +6.0V
CS1 to OUT1........................................................-0.3V to +0.3V
CSEL1, SSEN to GND.........................................-0.3V to +6.0V
COMP1 to GND.............................................-0.3V to PV + 0.3V
LX2, LX3 Output Short-Circuit Duration....................Continuous
SUP
PV_ to GND..........................................................-0.3V to +6.0V
PV_ to GND..........................................................-0.3V to +6.0V
PV2 to GND, PV2 to PGND2...............................-0.3V to +6.0V
PV3 to GND, PV3 to PGND3...............................-0.3V to +6.0V
PGND2–PGND3 to GND......................................-0.3V to +0.3V
LX1 to GND...............................................-6.0V to V
+ 6.0V
Continuous Power Dissipation (T = +70ºC)
SUP
A
BST1 to LX1 (Note 1)...........................................-0.3V to +6.0V
DH1 to LX1 (Note 1)..................................-0.3V to BST1 + 0.3V
BIAS to GND........................................................-0.3V to +6.0V
DL1 to GND (Note 1)...................................-0.3V to PV1 + 0.3V
LX2 to PGND2.............................................-0.3V to PV2 + 0.3V
LX3 to PGND3.............................................-0.3V to PV3 + 0.3V
OUT1, CS1, OUT2, OUT3 to GND ......................-0.3V to +6.0V
SYNC to GND .............................................-0.3V to PV_ + 0.3V
Side-Wettable QFND (derate 27mW/ºC above +70ºC)......2160mW
TQFN (derate 34.5mW/ºC above +70ºC)...............2758.6mW
Operating Temperature Range..........................-40ºC to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65ºC to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 2)
Package Thermal Characteristics
Side-Wettable QFND
Junction-to-AmbientꢀThermalꢀResistanceꢀ(θ ) ......... 37°C/W
TQFN
Junction-to-AmbientꢀThermalꢀResistanceꢀ(θ ) ......... 29°C/W
JA
JA
ꢀ
Junction-to-CaseꢀThermalꢀResistanceꢀꢀ(θ )............ 2.8°C/W
ꢀ Junction-to-CaseꢀThermalꢀResistanceꢀꢀ(θ )............ 1.7°C/W
JC
JC
Note 1:ꢀ Self-protectedꢀ againstꢀ transientꢀ voltagesꢀ exceedingꢀ theseꢀ limitsꢀ forꢀ ≤ꢀ 50nsꢀ underꢀ normalꢀ operationꢀ andꢀ loadsꢀ upꢀ toꢀ theꢀ
maximum rated output current.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 14V, V
= V
, V
= V
= V
; T = T = -40°C to +125°C, unless otherwise noted. Typical values are at
SUP
PV1
BIAS
PV2
PV3
OUT1 A J
T
= +25°C under normal conditions, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
4.25
3.5
TYP
MAX
UNITS
Supply Voltage Startup
Threshold
V
VSUP rising
Normal operation, after Buck 1 startup
4.5
4.75
V
V
SUP,STARTUP
Supply Voltage Range
V
36
15
40
2.2
SUP
SUP
V
V
= V
= V
= 0V
4
EN1
EN1
EN2
EN3
Supply Current
I
µA
= 5V, V
= V = 0V (no load)
EN3
20
2.1
EN2
Oscillator Frequency
f
2.0
1.7
MHz
MHz
SW
SYNC Input Frequency
Range
2.4
V
V
= V
= V
0
SSEN
SSEN
GND
Spread-Spectrum Range
BIAS Regulator Voltage
PV_ POR
%
V
+6
BIAS
V
6Vꢀ≤ꢀV
ꢀ≤ꢀ42V,ꢀnoꢀswitchover
4.6
2.5
5.0
2.7
0.45
5.4
2.9
BIAS
SUP
V
falling
BIAS
V
Hysteresis
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Electrical Characteristics (continued)
(V
= 14V, V
= V
, V
= V
= V
; T = T = -40°C to +125°C, unless otherwise noted. Typical values are at
SUP
PV1
BIAS
PV2
PV3
OUT1 A J
T
= +25°C under normal conditions, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT1: HIGH-VOLTAGE SYNCHRONOUS STEP-DOWN DC-DC CONTROLLER
V
V
= V
= V
2100
1050
CSEL1
CSEL1
GND
BIAS
(factory option)
V = V
CSEL1
Internally generated
(see the Selector
Guide)
BIAS
525
420
OUT1 Switching Frequency
f
(factory option)
kHz
SW1
V
= V
CSEL1
BIAS
(factory option)
V
= V
CSEL1
BIAS
350
3.3
5.0
(factory option)
V
= V
FB1
FB1
GND
BIAS
Fixed option
(see the Selector
Guide)
V
= V
Voltage
V
(factory option)
V
OUT1
V
= V
FB1
BIAS
3.15
1.0
(factory option)
FB1 Regulation Voltage
Adjustable option (see the Selector Guide)
0.985
300
1.019
1200
V
ErrorꢀAmplifierꢀ
Transconductance
g
700
µS
MEA
5.5Vꢀ≤ꢀV
ꢀ≤ꢀ18V,ꢀ0ꢀ<ꢀV
ꢀ<ꢀ75mV,ꢀ
SUP
LIM1
Voltage Accuracy
V
-2.0
+2.5
%
OUT1
PWM mode
PWM mode
PWM mode
DC Load Regulation
0.02
0.03
100
2
%/A
%/V
Ω
DC Line Regulation
OUT1 Discharge Resistance
V
V
V
V
V
= V
or V
SUP
200
4
EN1
DH1
DH1
DL1
DL1
GND
rising, I
= 100mA
= 100mA
High-Side Output Drive
Resistance
DH1
Ω
falling, I
1
4
DH1
rising, I
= 100mA
= 100mA
2.5
1.5
5
Low-Side Output Drive
Resistance
DL1
Ω
falling, I
3
DL1
Output Current-Limit
Threshold
V
CSI – OUT1
CS1 – OUT1, no load
100
10
120
150
60
mV
LIM1
Skip Current Threshold
Soft-Start Ramp Time
I
35
4
mV
ms
SKIP
LX_ Leakage Current
V
= V
0.01
µA
LX1
SUP
Duty-Cycle Range
Minimum On-Time
OUT1 OV Threshold
PWM mode
97.2
75
%
ns
%
60
107
110
113
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│ 3
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Electrical Characteristics (continued)
(V
= 14V, V
= V
, V
= V
= V
; T = T = -40°C to +125°C, unless otherwise noted. Typical values are at
SUP
PV1
BIAS
PV2
PV3
OUT1 A J
T
= +25°C under normal conditions, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT2 AND OUT3: LOW-VOLTAGE SYNCHRONOUS STEP-DOWN DC-DC CONVERTERS
Supply Voltage Range
Supply Current
V
2.7
5.5
5
V
µA
mA
%
SUP
I
V
= 5V, no load
0.1
PV_
EN_
Skip Mode Peak Current
Voltage Accuracy
0.2 x I
LMAX
V
0Aꢀ≤ꢀI
ꢀ≤ꢀI PWM mode
MAX,
-3.0
0.806
-1.5
+3.0
OUT
LOAD
Feedback-Voltage Accuracy
Adjustable mode, I
= 0mA
0.815
-1.0
0.824
V
OUT2
0Aꢀ≤ꢀI
0Aꢀ≤ꢀI
ꢀ≤ꢀI
ꢀ≤ꢀI
(PWM mode)
LOAD
MAX
Load Regulation
%
(PWM mode, low gain,
LOAD
MAX
-2.5
-1.7
see the Selector Guide)
LX_ On-Resistance High
LX_ On-Resistance Low
ILX_ = -800mA
70
50
110
90
mΩ
mΩ
ILX_ = 800mA
I
I
= 3.0A option (see the Selector Guide)
= 1.5A option (see the Selector Guide)
5.0
2.5
5.6
3.0
4
MAX
Current-Limit Threshold
I
A
LMAX
MAX
LX_ Rise/Fall Time
Soft-Start Ramp Time
LX_ Leakage Current
Duty-Cycle Range
LX_ Discharge Resistance
RESET_
PV2 = PV3 = 3.3V, I
= 2A
ns
ms
µA
%
OUT_
2.5
0.01
PWM mode
15
100
48
22
Ω
Rising (relative to nominal output voltage)
Falling (relative to nominal output voltage)
92
90
95
92
98
95
Reset Threshold
%
See the Selector Guide
(16,384 clocks)
7.8
3.9
1.9
0.1
7.8
3.9
1.9
0.1
See the Selector Guide
(8192 clocks)
OUT1 Active Timeout Period
ms
See the Selector Guide
(4096 clocks)
See the Selector Guide
(256 clocks)
See the Selector Guide
(16,384 clocks)
See the Selector Guide
(8192 clocks)
OUT2, OUT3 Active
Timeout Period
ms
See the Selector Guide
(4096 clocks)
See the Selector Guide
(256 clocks)
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Electrical Characteristics (continued)
(V
= 14V, V
= V
, V
= V
= V
; T = T = -40°C to +125°C, unless otherwise noted. Typical values are at
SUP
PV1
BIAS
PV2
PV3
OUT1 A J
T
= +25°C under normal conditions, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.1
10
MAX
0.2
20
UNITS
V
Output Low Level
I
= 3mA
SINK
OUT1, 5% below threshold
5
2
µs
Propagation Time
OUT2/OUT3, 5% below threshold
4
8
µs
ERR
Output Low Level
I
= 3mA
0.1
0.2
V
SINK
THERMAL OVERLOAD
Thermal-Warning
Temperature
+150
+170
15
°C
°C
°C
Thermal-Shutdown
Temperature
Thermal-Shutdown
Hysteresis
ENABLE INPUTS (EN_)
Input High
V
V
rising
= 5V
1.6
0.5
1.8
0.2
1.0
2.0
2.0
V
V
EN_
EN_
Hysteresis
EN Input Current
µA
SYNCHRONIZATION I/O (SYNC)
SYNC input option
(see the Selector Guide)
Input High
Input Low
1.8
V
V
SYNC input option
(see the Selector Guide)
0.8
80
SYNC input option (see the Selector
Input Current
50
µA
Guide); V
= 5V
SYNC
Pulldown Resistance
LOGIC INPUTS (CSEL1, SSEN)
Input High
100
kΩ
1.4
V
V
Input Low
0.5
2
Input Current
T
= +25°C
µA
A
Note 3: All units are 100% production tested at T = +25°C. All temperature limits are guaranteed by design.
A
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Typical Operating Characteristics
(V
= 14V, T = +25°C, unless otherwise noted)
SUP
A
BUCK 1 LOAD REGULATION (PWM)
BUCK 1 EFFICIENCY
BUCK 1 LOAD REGULATION (SKIP)
5.030
100
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
90
80
70
60
50
40
30
20
10
0
T
= +125ºC
5.025
5.020
5.015
A
T
A
= +125ºC
T
= +25ºC
A
T
= +25ºC
5.010
A
SKIP MODE
5.005
T
A
= -40ºC
PWM MODE
5.000
T
= -40ºC
3
A
4.995
4.990
0
1
2
4
5
6
1.00E-06
1.00E-04
1.00E-02
(A)
1.00E+00
0
1
2
3
4
5
6
I
(A)
OUT1
I
I
(A)
OUT1
OUT1
BUCK 1 LINE REGULATION (PWM MODE)
BUCK 1 LINE REGULATION (SKIP MODE)
BUCK 1 LINE REGULATION (SKIP MODE)
100.5
100.4
100.3
100.2
100.1
100.0
99.9
101.0
100.8
100.6
100.4
100.2
100.0
99.8
V
OUT1
= 5.0V
V
OUT1
= 5.0V
V
OUT1
= 3.3V
100.9
100.7
100.5
100.3
100.1
99.9
T
= +125ºC
A
T
= +25ºC
A
99.8
99.6
T
= -40ºC
A
99.7
99.4
99.7
99.6
99.2
99.5
99.0
99.5
0
5
10 15 20 25 30 35 40
(V)
0
5
10 15 20 25 30 35 40
(V)
0
5
10 15 20 25 30 35 40
(V)
V
SUP
V
V
SUP
SUP
BUCK 2 LOAD REGULATION (PWM MODE)
V
OUT1
vs. TEMPERATURE
BUCK 2 EFFICIENCY
3.19
3.18
3.17
3.16
3.15
3.14
3.13
3.12
3.11
3.10
3.09
3.08
5.030
5.025
5.020
5.015
5.010
5.005
5.000
4.995
4.990
4.985
4.980
100
90
80
70
60
50
40
30
20
10
0
I
= 3.75A
V
= 5.0V, I
MAX
= 1.5A, V
= 3.15V
OUT2
OUT1
PV2
SKIP MODE
T
= +125ºC
A
T
= +25ºC
A
PWM MODE
= 2.1MHz,
f
SW
T
A
= -40ºC
V
V
V
= 14V,
= 5.0V,
SUP
PV2
= 3.15V
OUT2
-50
0
50
100
150
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
(A)
1.00E-06
1.00E-04
1.00E-02
(A)
1.00E+00
TEMPERATURE (ºC)
I
OUT2
I
OUT3
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│ 6
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Typical Operating Characteristics (continued)
(V
= 14V, T = +25°C, unless otherwise noted)
SUP
A
BUCK 2 LOAD REGULATION (PWM MODE)
BUCK 2 LINE REGULATION (PWM MODE)
V
OUT2
vs. TEMPERATURE
3.345
3.340
3.335
3.330
3.325
3.320
3.315
3.310
101.0
3.150
3.145
3.140
3.135
3.130
3.125
3.120
3.115
3.110
3.105
3.100
V
= 5.0V
= 3A
V
= 3.15V
I
OUT2
= 1.125A
PV2
OUT2
100.8
100.6
100.4
100.2
100.0
99.8
I
MAX
T
= +125ºC
A
V
= 3.3V
OUT2
T
= +25ºC
A
99.6
99.4
T
= -40ºC
3.7
A
99.2
99.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
(A)
2.7
3.2
4.2
(V)
4.7
5.2
5.7
-50
0
50
100
150
I
OUT2
V
TEMPERATURE (ºC)
PV2
BUCK 3 LOAD REGULATION (PWM MODE)
BUCK 3 LOAD REGULATION (PWM MODE)
BUCK 3 EFFICIENCY
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.230
1.228
1.226
1.224
1.222
1.220
1.218
1.216
1.214
100
90
80
70
60
50
40
30
20
10
0
V
= 5.0V, I
= 1.5A, V
= 1.8V
OUT3
V
= 5.0V
= 3A
PV3
MAX
PV3
I
MAX
V
= 1.2V
OUT3
T
= +125ºC
A
SKIP MODE
T
= +25ºC
A
PWM MODE
= 2.1MHz,
f
SW
T
A
= -40ºC
V
V
V
= 14V,
= 5.0V,
SUP
PV3
= 1.8V
OUT3
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
(A)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
(A)
1.00E-06
1.00E-04
1.00E-02
(A)
1.00E+00
I
OUT3
I
OUT3
I
OUT3
V
vs. TEMPERATURE
OUT3
BUCK 3 LINE REGULATION (PWM MODE)
1.810
1.805
1.800
1.795
1.790
1.785
1.780
100.5
100.4
100.3
100.2
100.1
100.0
99.9
I
= 1.125A
OUT3
V
= 1.8V
OUT3
T
A
= +125ºC
T
= +25ºC
A
99.8
99.7
T
A
= -40ºC
99.6
99.5
3.3
3.8
4.3
4.8
5.3
-50
0
50
100
150
V
PV3
(V)
TEMPERATURE (ºC)
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Typical Operating Characteristics (continued)
(V
= 14V, T = +25°C, unless otherwise noted)
SUP
A
STARTUP SEQUENCE
(V
= V
= V )
OUT1
MAX16993 toc18
SUPPLY CURRENT vs. SUPPLY VOLTAGE
EN2
EN3
120
100
80
60
40
20
0
V
= V
GND
FB
SKIP MODE
ALL THREE BUCKS ENABLED
MEASURED AT VSUP
5V/div
V
EN1
5V/div
5V/div
T
= +125ºC
A
V
OUT1
V
V
RESET1
5V/div
5V/div
V
OUT2
RESET2
T
= +25ºC
A
5V/div
5V/div
V
OUT3
T
= -40ºC
A
V
RESET3
2ms/div
0
5
10 15 20 25 30 35 40
(V)
V
SUP
LOAD TRANSIENT RESPONSE (PWM MODE)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16993 toc21
70
60
50
40
30
20
10
0
V
= 5.0V, SKIP MODE
OUT1
ONLY BUCK CONTROLLER ENABLED
T
= +125ºC
A
V
100mV/div
OUT1
T
A
= +25ºC
I
1A/div
OUT1
T
A
= -40ºC
200µs/div
0
5
10 15 20 25 30 35 40
(V)
V
SUP
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
f
vs. TEMPERATURE
SPECTRAL ENERGY DENSITY
SW
10
9
8
7
6
5
4
3
2
1
0
103
102
101
100
99
60
50
40
30
20
10
0
V
= V
= V
= V
EN3 GND
EN1
EN2
f
= 2.1MHz
SW
MEASURED AT VSUP
SS DISABLED
SS ENABLED
T
= +125ºC
A
T
= -40ºC
A
98
T
= +25ºC
A
-10
97
1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30
FREQUENCY (MHz)
-50
0
50
100
150
0
5
10 15 20 25 30 35 40
(V)
TEMPERATURE (ºC)
V
SUP
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
16
15
OUT2 25
CSEL1 26
OUT3
EN3
14 EN2
27
28
29
30
31
32
SSEN
RESET1
GND
OUT1
CS1
13
12
MAX16993
11 FB1
COMP1
ERR
EP = GND
10
9
PV
+
BIAS
SYNC
1
2
3
4
5
6
7
8
TQFN/SIDE-WETTABLE QFND
Pin Description
PIN
NAME
FUNCTION
Supply Input for Buck 1 Low-Side Gate Drive. Connect a ceramic bypass capacitor of at least 0.1µF from PV1
to GND.
1
PV1
2
3
DL1
Low-Side Gate-Drive Output for Buck 1. DL1 output voltage swings from V
Power Ground for Buck 1
to V
.
GND
PV1
GND
Inductor Connection for Buck 1. Connect LX1 to the switched side of the inductor. LX1 serves as the lower
supply rail for the DH1 high-side gate drive.
4
5
LX1
DH1
High-Side Gate-Drive Output for Buck 1. DH1 output voltage swings from V
to V
.
LX1
BST1
Bootstrap Capacitor Connection for High-Side Gate Drive of Buck 1. Connect a high-voltage diode between
BIAS and BST1. Connect a ceramic capacitor between BST1 and LX1. See the High-Side Gate-Drive Supply
(BST1) section.
6
BST1
7
8
V
Supply Input. Bypass V
with a minimum 0.1µF capacitor as close as possible to the device.
SUP
SUP
EN1
High-Voltage Tolerant, Active-High Digital Enable Input for Buck 1. Driving EN1 high enables Buck 1.
5V Internal Linear Regulator Output. Bypass BIAS to GND with a low-ESR ceramic capacitor of
2.2µF minimum value. BIAS provides the power to the internal circuitry. See the Linear Regulator (BIAS)
section.
9
BIAS
AnalogꢀSupply.ꢀConnectꢀPVꢀtoꢀBIASꢀthroughꢀaꢀ10Ωꢀresistorꢀandꢀconnectꢀaꢀ1µFꢀceramicꢀcapacitorꢀfromꢀPVꢀtoꢀ
ground.
10
PV
FeedbackꢀInputꢀforꢀBuckꢀ1.ꢀForꢀtheꢀfixedꢀoutput-voltageꢀoption,ꢀconnectꢀFB1ꢀtoꢀBIASꢀforꢀtheꢀfactory-trimmedꢀ
(3.0Vꢀtoꢀ3.75Vꢀorꢀ4.6Vꢀtoꢀ5.35V)ꢀfixedꢀoutput.ꢀConnectꢀFB1ꢀtoꢀGNDꢀforꢀtheꢀ3.3Vꢀfixedꢀoutput.ꢀForꢀtheꢀresistor-
divider adjustable output-voltage option, connect FB1 to a resistive divider between OUT1 and GND to adjust
the output voltage between 3.0V and 5.5V. In adjustable mode, FB1 regulates to 1.0V (typ). See the OUT1
Adjustable Output-Voltage Option section.
11
FB1
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Pin Description (continued)
PIN
NAME
FUNCTION
Positive Current-Sense Input for Buck 1. Connect CS1 to the positive terminal of the current-sense resistor.
See the Current-Limit/Short-Circuit Protection and Current-Sense Measurement sections.
12
CS1
Output Sense and Negative Current-Sense Input for Buck 1. The buck uses OUT1 to sense the output
voltage. Connect OUT1 to the negative terminal of the current-sense resistor.
13
OUT1
See the Current-Limit/Short-Circuit Protection and Current-Sense Measurement sections.
14
15
EN2
EN3
Active-High Digital Enable Input for Buck 2. Driving EN2 high enables Buck 2.
Active-High Digital Enable Input for Buck 3. Driving EN3 high enables Buck 3.
Buck Converter 3 Voltage-Sense Input. Connect OUT3 to the output of Buck 3. Connect OUT3 to an external
feedback divider when setting DC-DC3 voltage externally. See the OUT2/OUT3 Adjustable Output-Voltage
Option section.
16
17
OUT3
Open-Drain Buck 3 Reset Output. RESET3ꢀremainsꢀlowꢀforꢀaꢀfixedꢀtimeꢀafterꢀtheꢀoutputꢀofꢀBuckꢀ3ꢀhasꢀ
reached its regulation level (see the Selector Guide). To obtain a logic signal, pull up RESET3 with an
external resistor connected to a positive voltage lower than 5V.
RESET3
18
19
20
21
22
23
PV3
LX3
Buck 3 Voltage Input. Connect a 2.2µF or larger ceramic capacitor from PV3 to PGND3. Connect PV3 to OUT1.
Buck 3 Switching Node. LX3 is high impedance when the device is off.
Power Ground for Buck 3
PGND3
PGND2
LX2
Power Ground for Buck 2
Buck 2 Switching Node. LX2 is high impedance when the device is off.
Buck 2 Voltage Input. Connect a 2.2µF or larger ceramic capacitor from PV2 to PGND2. Connect PV2 to OUT1.
PV2
Open-DrainꢀBuckꢀ2ꢀResetꢀOutput.ꢀThisꢀoutputꢀremainsꢀlowꢀforꢀaꢀfixedꢀtimeꢀafterꢀtheꢀoutputꢀofꢀBuckꢀ2ꢀhasꢀ
reached its regulation level (see the Selector Guide). To obtain a logic signal, pull up RESET2 with an
external resistor connected to a positive voltage lower than 5V.
24
25
RESET2
Buck Converter 2 Voltage-Sense Input. Connect OUT2 to the output of Buck 2. Connect OUT2 to an external
feedback divider when setting DC-DC2 voltage externally. See the OUT2/OUT3 Adjustable Output-Voltage
Option section.
OUT2
Buck 1 Clock Select. Connect CSEL1 to GND for 2.1MHz operation. Connect CSEL1 to BIAS for an OTP-
26
27
CSEL1
SSEN
programmable divide-down operation. See the Selector Guide for the f
divide ratio.
SW1
Spread-Spectrum Enable. Connect SSEN to GND for standard oscillator operation. Connect SSEN to BIAS to
enable the spread-spectrum oscillator.
Open-Drain Buck 1 Reset Output. RESET1ꢀremainsꢀlowꢀforꢀaꢀfixedꢀtimeꢀafterꢀtheꢀoutputꢀofꢀBuckꢀ1ꢀhasꢀ
reached its regulation level (see the Selector Guide). To obtain a logic signal, pull up RESET1 with an
external resistor connected to a positive voltage lower than 5V.
28
RESET1
29
30
GND
Analog Ground
COMP1
Compensation for Buck 1. See the Compensation Network section.
Open-Drain Error-Status Output. ERR signals a thermal-warning/shutdown condition. To obtain a logic signal,
pull up ERR with an external resistor connected to a positive voltage lower than 5V.
31
ERR
Synchronization Input. SYNC allows the device to synchronize to other supplies. Connect SYNC to GND or
leave unconnected to enable skip-mode operation under light loads. Connect SYNC to BIAS or an external
clockꢀtoꢀenableꢀfixed-frequencyꢀforced-PWM-modeꢀoperation.
32
SYNC
Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not remove
the requirement for proper ground connections to PGND2–PGND3 and GND. The exposed pad is attached
with epoxy to the substrate of the die, making it an excellent path to remove heat from the IC.
—
EP
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Typical Operating Circuit
BIAS
GND
LINEAR
REGULATOR
MAX16993
BIAS
PV1
PV
BST1
V
SUP
V
BATP
PV3
V
OUT1
DH1
LX1
N
N
P
N
V
OUT1
STEP-DOWN
PWM
LX3
V
OUT3
OUT3
DL1
GND
PGND3
OUT3
STEP-DOWN
CONTROLLER
OUT1
0.8V TO 3.95V
1.5A TO 3.0A
CS1
OUT1
FB1
PWM
EN
PWM
EN
COMP1
PV2
LX2
V
OUT1
RESET1
P
N
RESET2
RESET3
EN1
V
OUT2
STEP-DOWN
PWM
OUT2
PGND2
OUT2
POR
GENERATION
AND
EN2
0.8V TO 3.95V
1.5A TO 3.0A
EN3
CONTROL
ERR
PWM
EN
SSEN
CSEL1
SYNC
EP
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Enable Inputs (EN_)
Detailed Description
All three regulators have their own enable input. When
EN1 exceeds the EN1 high threshold, the internal
The MAX16993 power-management integrated circuit
(PMIC) is a 2.1MHz, multichannel, DC-DC converter
designed for automotive applications. The device includes
one high-voltage step-down controller (OUT1) designed
to run directly from a car battery and two low-voltage step-
down converters (OUT2/OUT3) cascaded from OUT1.
linear regulator is switched on. When V
exceeds the
SUP
V
threshold, Buck 1 is enabled and OUT1
SUP,STARTUP
starts to ramp up with a 4ms soft-start. Once the Buck 1
soft-start is complete, Buck 2 and Buck 3 can be enabled.
When either Buck 2 or Buck 3 is enabled, the correspond-
ing output ramps up with a 2.5ms soft-start. When an
enable input is pulled low, the converter is switched off
and the corresponding OUT_ and RESET_ are driven
low. If EN1 is low, all regulators are disabled.
The 2.1MHz, high-voltage buck controller operates with
a 3.5V to 36V input voltage range and is protected from
load-dump transients up to 42V. The high-frequency
operation eliminates AM band interference and reduces
the solution footprint. It can provide an output voltage
between 3.0V and 5.5V set at the factory or with external
resistors. Each device has two frequency options that
are pin selectable: 2.1MHz or a lower frequency based
on factory setting. Available factory-set frequencies are
1.05MHz, 525kHz, 420kHz, or 350kHz. Under no-load
conditions, the device consumes only 30µA of quiescent
current with OUT1 enabled.
Reset Outputs (RESET_)
The device features individual open-drain RESET_ out-
puts for each buck output that asserts when the buck
output voltage drops 6% below the regulated voltage.
RESET_ remains asserted for a fixed timeout period after
the buck output rises up to its regulated voltage. The
fixed timeout period is programmable between 0.1ms and
7.4ms (see the Selector Guide). To obtain a logic signal,
pull up RESET_ with an external resistor connected to a
positive voltage lower than 5V.
The dual buck converters can deliver 1.5A or 3.0A of
load current per output. They operate directly from OUT1
and provide 0.8V to 3.95V output voltage range. Factory
trimmed output voltages achieve ±3% output error over
load, line, and temperature without using expensive
±0.1% resistors. In addition, adjustable output-voltage
versions can be set to any desired values between 0.8V
and 3.6V using an external resistive divider. On-board
Linear Regulator (BIAS)
The device features a 5V internal linear regulator (BIAS).
Connect BIAS to PV, which acts as a supply for internal
circuitry. Also connect BIAS to PV1, which acts as a
supply for the low-side gate driver of Buck 1. Bypass BIAS
as close as possible to the device with a 2.2µF or larger
ceramic capacitor. BIAS can provide up to 100mA (max),
but is not designed to supply external loads. After OUT1
completes soft-start, BIAS LDO is turned off and the BIAS
pin is shorted to the OUT1 pin internally to power the
internal circuits (e.g., if OUT1 is set to 3.3V, BIAS transi-
tions from 5V to 3.3V after soft-start).
low R
switches help minimize efficiency losses
DS(ON)
at heavy loads and reduce critical/parasitic inductance,
making the layout a much simpler task with respect to
discrete solutions. Following a simple layout and footprint
ensures first-pass success in new designs (see the PCB
Layout Guidelines section).
ThedevicefeaturesaSYNCinput (seetheSynchronization
(SYNC) section and the Selector Guide). An optional
spread-spectrum frequency modulation minimizes radi-
ated electromagnetic emissions due to the switching
frequency, and a factory-programmable synchronization
I/O (SYNC) allows better noise immunity. Additional fea-
tures include a 4ms fixed soft-start for OUT1 and 2.5ms
for OUT2/OUT3, individual RESET_ outputs, overcurrent,
and overtemperature protections. See the Selector Guide
for the available options.
Internal Oscillator
Buck 1 Clock Select (CSEL1)
The device offers a Buck 1 clock-select input. Connect
CSEL1 to GND for 2.1MHz operation. Connect CSEL1 to
BIAS to divide down the Buck 1 clock frequency by 2, 4, 5,
or 6 (see the Selector Guide). Buck 2 and Buck 3 switch
at 2.1MHz (typ) and are not controlled by CSEL1.
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
f
SW + 6%
INTERNAL OSCILLATOR
FREQUENCY
f
SW
t
t + 250µs
t + 500µs
t + 750µs
TIME
Figure 1. Effect of Spread Spectrum on Internal Oscillator
should have a duty cycle of 50%. A logic-low at the SYNC
input enables the device to enter a low-power skip mode
under light-load conditions.
Spread-Spectrum Enable (SSEN)
The device features a spread-spectrum enable (SSEN)
input that can quickly enable spread-spectrum operation
to reduce radiated emissions. Connect SSEN to BIAS to
enable the spread-spectrum oscillator. Connect SSEN
to GND for standard oscillator operation. When spread
spectrum is enabled, the internal oscillator frequency
Common Protection Features
Undervoltage Lockout
The device offers an undervoltage-lockout feature.
Undervoltage detection is performed on the PV input. If
is varied between f
and (f
+ 6%). The change in
SW
SW
V
decreases to the point where Buck 1 is in drop-
frequency has a sawtooth shape and a frequency of 4kHz
(see Figure 1). This function does not apply to externally
applied oscillation frequency. See the Selector Guide for
available options.
SUP
out, PV begins to decrease. If PV falls below the UVLO
threshold (2.7V, typ), all three converters switch off and
the RESET_ outputs assert low. Once the device has
been switched off, V
threshold before Buck 1 turns back on.
must exceed the V
SUP
SUP,STARTUP
Synchronization (SYNC)
SYNC is factory-programmable I/O. See the Selector
Guide for available options. When SYNC is configured as
an input, a logic-high on SYNC enables fixed-frequency,
forced-PWM mode. Apply an external clock on the SYNC
input to synchronize the internal oscillator to an external
clock. The SYNC input accepts signal frequencies in the
Output Overvoltage Protection
The device features overvoltage protection on the buck
converter outputs. If the FB1 input exceeds the output
overvoltage threshold, a discharge current is switched on
at OUT1 and RESET1 asserts low.
rangeꢀofꢀ1.7MHzꢀ<ꢀf
ꢀ<ꢀ2.4MHz.ꢀTheꢀexternalꢀclockꢀ
SYNC
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
across the load. Under soft-overload conditions, when the
Soft-Start
peak inductor current exceeds the selected current limit
(see the Current-Limit/Short-Circuit Protection section),
the high-side MOSFET is turned off immediately and the
low-side MOSFET is turned on and remains on to let the
inductor current ramp down until the next clock cycle.
The device includes a 4ms fixed soft-start time on OUT1
and 2.5ms fixed soft-start time on OUT2/OUT3. Soft-start
time limits startup inrush current by forcing the output
voltage to ramp up towards its regulation point. If OUT1
is prebiased above 1.25V, all three buck converters do
not start up until the prebias has been removed. Once the
prebias has been removed, OUT1 self-discharges to GND
and then goes into soft-start.
PWM/Skip Modes
The device features a synchronization input that puts all
the buck regulators either in skip mode or forced-PWM
mode of operation (see the Synchronization (SYNC)
section). In the PWM mode of operation, the regulator
switches at a constant frequency with variable on-time.
In the skip mode of operation, the regulator’s switching
frequency is load dependent until the output load reaches
a certain threshold. At higher load current, the switch-
ing frequency does not change and the operating mode
is similar to the PWM mode. Skip mode helps improve
efficiency in light-load applications by allowing the regula-
tor to turn on the high-side switch only when the output
voltage falls below a set threshold. As such, the regulator
does not switch MOSFETs on and off as often as is the
case in the PWM mode. Consequently, the gate charge
and switching losses are much lower in skip mode.
Thermal Warning and Overtemperature
Protection
The device features an open-drain, thermal-warning
indicator (ERR). ERR asserts low when the junction
temperature exceeds +150°C (typ). The hysteresis on
the thermal warning is 15°C (typ). For a logic signal,
connect a pullup resistor from ERR to a supply less than
or equal to 5V. When the junction temperature exceeds
+170°C (typ), an internal thermal sensor shuts down the
buck converters, allowing the device to cool. The thermal
sensor turns the device on again after the junction
temperature cools by 15°C (typ).
Buck 1 (OUT1)
Buck controller 1 uses a PWM current-mode control
scheme. An internal transconductance amplifier estab-
lishes an integrated error voltage. The heart of the PWM
controller is an open-loop comparator that compares the
integrated voltage-feedback signal against the amplified
current-sense signal plus the slope-compensation ramp,
which are summed into the main PWM comparator to
preserve inner-loop stability and eliminate inductor stair-
casing. At each rising edge of the internal clock, the high-
side MOSFET turns on until the PWM comparator trips or
the maximum duty cycle is reached, or the peak current
limit is reached. During this on-time, current ramps up
through the inductor, storing energy in a magnetic field
and sourcing current to the output. The current-mode
feedback system regulates the peak inductor current as a
function of the output-voltage error signal. The circuit acts
as a switch-mode transconductance amplifier and pushes
the output LC filter pole normally found in a voltage-mode
PWM to a higher frequency.
Minimum On-Time and Duty Cycle
The high-side gate driver for Buck 1 has a minimum on-
time of 75ns (max). This helps ensure no skipped pulses
when operating the device in PWM mode at 2.1MHz with
supply voltage up to 18V and output voltage down to
3.3V. Pulse skipping can occur if the on-time falls below
the minimum allowed (see the Electrical Characteristics).
Current-Limit/Short-Circuit Protection
OUT1 offers a current-limit feature that protects Buck 1
against short-circuit and overload conditions on the buck
controller. Buck 1 offers a current-limit sense input (CS1).
Place a sense resistor in the path of the channel 1 current
flow. Connect CS1 to the high side of the sense resistor
and OUT1 to the low side of the sense resistor. Current-
limit protection activates once the voltage across the
sense resistor increases above the 120mV (typ) current-
limit threshold. In the event of a short-circuit or overload
condition, the high-side MOSFET remains on until the
inductor current reaches the current-limit threshold. The
converter then turns on the low-side MOSFET and the
inductor current ramps down. The converter allows the
high-side MOSFET to turn on only when the voltage
across the current-sense resistor ramps down to below
120mV (typ). This cycle repeats until the short or overload
condition is removed.
During the second half of the cycle, the high-side
MOSFET turns off and the low-side MOSFET turns on.
The inductor releases the stored energy as the current
ramps down, providing current to the output. The out-
put capacitor stores charge when the inductor current
exceeds the required load current and discharges when
the inductor current is lower, smoothing the voltage
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Current-Sense Measurement
V
SUP
For the best current-sense accuracy and overcurrent pro-
tection, use a 1% tolerance current-sense resistor between
the inductor and output, as shown in Figure 2. This con-
figuration constantly monitors the inductor current, allow-
ing accurate current-limit protection. Use low-inductance
current-sense resistors for accurate measurement.
MAX16993
C
IN
DH1
N
N
L1
R
CS
LX1
DL1
C
OUT
High-Side Gate-Drive Supply (BST1)
GND
The high-side MOSFET is turned on by closing an inter-
nal switch between BST1 and DH1 and transferring the
bootstrap capacitor’s (at BST1) charge to the gate of the
high-side MOSFET. This charge refreshes when the high-
side MOSFET turns off and the LX1 voltage drops down
to ground potential, taking the negative terminal of the
capacitor to the same potential. At this time, the bootstrap
diode recharges the positive terminal of the bootstrap
capacitor. The selected n-channel high-side MOSFET
determines the appropriate boost capacitance values
CS1
OUT1
OUTPUT SERIES RESISITOR SENSING
Figure 2. Current-Sense Configuration
(C
in the Typical Operating Circuit) according to the
BST1
Buck 2 and Buck 3 (OUT2 and OUT3)
following equation:
Buck converters 2 and 3 are high-efficiency, low-
voltage converters with integrated FETs. They use a
PWM current-mode control scheme that is operated at
2.1MHz to optimize component size and efficiency, while
eliminating AM band interference. The buck converters
can be configured to deliver 1.5A or 3.0A per channel.
They operate directly from OUT1 and have either fixed
or resistor-programmable (see the Selector Guide) output
voltages that range from 0.8V to 3.95V. Buck 2 and Buck 3
feature low on-resistance internal FETs that contribute to
high efficiency and smaller system cost and board space.
Integration of the p-channel high-side FET enables both
channels to operate with 100% duty cycle when the input
voltage falls to near the output voltage. They feature a
programmable active timeout period (see the Selector
Guide) that adds a fixed delay before the corresponding
RESET_ can go high.
Q
G
C
=
BST1
∆V
BST1
where Q is the total gate charge of the high-side
G
MOSFETꢀ andꢀ ΔV
is the voltage variation allowed
on the high-side MOSFET driver after turn-on. Choose
ΔV such that the available gate-drive voltage is not
BST1
BST1
significantlyꢀdegradedꢀ(e.g.,ꢀΔV
when determining C
= 100mV to 300mV)
BST1
. Use a Schottky diode when
BST1
efficiency is most important, as this maximizes the gate-
drive voltage. If the quiescent current at high temperature
is important, it may be necessary to use a low-leakage
switching diode.
The boost capacitor should be a low-ESR ceramic
capacitor. A minimum value of 100nF works in most
cases. A minimum value of 470nF is recommended when
using a Schottky diode.
FPWM/Skip Modes
Dropout
The MAX16993 features an input (SYNC) that puts the
converter either in skip mode or forced PWM (FPWM)
mode of operation. See the Internal Oscillator section.
In FPWM mode, the converter switches at a constant
frequency with variable on-time. In skip mode, the con-
verter’s switching frequency is load-dependent until the
output load reaches a certain threshold. At higher load
current, the switching frequency does not change and the
operating mode is similar to the FPWM mode.
When OUT1 input voltage is lower than the desired output
voltage, the converter is in dropout mode. Buck 1 continu-
ously draws current from the bootstrap capacitor when the
high-side switch is on. Therefore, the bootstrap capacitor
needs to be refreshed periodically. When in dropout, the
Buck 1 high-side gate drive shuts off every 8µs, at which
point the low-side gate drive turns on for 120ns.
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Skip mode helps improve efficiency in light-load appli-
cations by allowing the converters to turn on the high-
side switch only when the output voltage falls below a
set threshold. As such, the converter does not switch
MOSFETs on and off as often as is the case in the FPWM
mode. Consequently, the gate charge and switching
losses are much lower in skip mode.
V
OUT1
OUT1
C1
R1
MAX16993
FB1
Current-Limit/Short-Circuit Protection
R2
Buck converters 2 and 3 feature current limit that protects
the device against short-circuit and overload conditions at
their outputs. The current limit value is dependent on the
version selected, 1.5A or 3.0A maximum DC current. See
the Selector Guide for the current limit value of the chosen
option and the Electrical Characteristics table for the cor-
responding current limit. In the event of a short-circuit or
overload condition at an output, the high-side MOSFET
remains on until the inductor current reaches the high-
side MOSFET’s current-limit threshold. The converter
then turns on the low-side MOSFET and the inductor cur-
rent ramps down.
Figure 3. Adjustable OUT1 Voltage Configuration
OUT1 Current-Sense Resistor Selection
Choose the current-sense resistor based on the maximum
inductor current ripple (K ) and minimum current-limit
INDMAX
threshold across current-sense resistor (V
= 0.1V).
LIM1MIN
The formula for calculating the current-sense resistor is:
V
LIM1MIN
Rcs
=
MAX
The converter allows the low-side MOSFET to turn off
only when the inductor current ramps down to the low-
side MOSFET’s current threshold. This cycle repeats until
the short or overload condition is removed.
K
INDMAX
2
I
×(1+
)
OUTMAX
where I
is the maximum load current for Buck 1
OUTMAX
and K
is the maximum inductor current ripple.
INDMAX
Applications Information
The maximum inductor current ripple is a function of the
inductor chosen, as well as the operating conditions, and
is typically chosen between 0.3 and 0.4:
OUT1 Adjustable Output-Voltage Option
The device’s adjustable output-voltage version (see
the Selector Guide for details) allows the customer to
set OUT1 voltage between 3.0V and 5.5V. Connect a
resistive divider from OUT1 to FB1 to GND to set the
output voltage (Figure 3). Select R2 (FB1 to GND resistor)
( V
− V
)×D
OUT
SUP
K
=
INDMAX
I
× f
MHz ×L µH
SW 1
[
]
[
]
OUTMAX
lessꢀthanꢀorꢀequalꢀtoꢀ100kΩ.ꢀCalculateꢀR1ꢀ(V
resistor) with the following equation:
to FB1
where D is the duty cycle. Below is a numerical exam-
ple to calculate the current-sense resistor in Figure 2.
The maximum inductor current ripple is chosen at the
maximum supply voltage (36V) to be 0.4:
OUT1
V
OUT1
R
= R
−1
2
1
V
FB1
0.1
Rcs
=
MAX
K
where V
= 1.0V (see the Electrical Characteristics).
INDMAX
2
FB1
I
× 1+
OUTMAX
0.1
The external feedback resistive divider must be frequency
compensated for proper operation. Place a capacitor
across R1 in the resistive divider network. Use the follow-
ing equation to determine the value of the capacitor:
=
= 0.0166 Ω
0.4
2
5 × 1+
if R2/R1 > 1, C1 = C(R2/R1)
else, C1 = C, where C = 10pF.
OUT1 Inductor Selection
Three key inductor parameters must be specified for
operation with the device: inductance value (L), inductor
For fixed output options, connect FB1 to BIAS for the
factory-programmed, fixed output voltage. Connect FB1
to GND for a fixed 3.3V output voltage.
saturation current (I
), and DC resistance (R
SAT
). Use
DCR
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│ 16
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
the following formulas to determine the minimum inductor
value:
Use the following formula to determine the minimum out-
put capacitor for Buck 1:
I
OUT1(MAX)
C
≥
OUT
V
∆V
OUT 1
OUT1
2π × f
×
× V
OUT1
V
− V
×
(
)
CO
SUPMAX
OUT 1
1
V
V
OUT1
SUPMAX
L
[H] = 1.3 ×
MIN1
where f
is the crossover frequency set by R and C ,
C C
CO
×
andꢀΔV
is the allowable change in voltage during a
f
×I
×K
OUT1
SW 1 OUTMAX
INDMAX
load transient condition.
For proper functionality, ceramic capacitors must be
used. Make sure that the self-resonance of the ceramic
capacitors is above 1MHz to avoid instability.
where f
is the operating frequency and 1.3 is a
SW1
coefficient that accounts for inductance initial precision.
or:
V
Buck 1 MOSFET Selection
OUT1
L
[H] = 1.3 ×
×R
CS
MIN 2
Buck 1 drives two external logic-level n-channel MOSFETs
as the circuit switch elements. The key selection param-
eters to choose these MOSFETs are:
0.8 V
6
2.1×10
× A
×
V_CS
f
SW1
●ꢀ On-resistance (R
)
DS(ON)
●ꢀ Maximum drain-to-source voltage (V
)
DS(MAX)
where A
is current-sense amplifier gain (8V/V, typ).
V_CS
●ꢀ Minimum threshold voltage (V
)
TH(MIN)
For proper operation, the chosen inductor value must be
greater than or equal to L and L . The maximum
inductor value recommended is twice the chosen value
●ꢀ Total gate charge (Q )
MIN1
MIN2
G
●ꢀ Reverse transfer capacitance (C
●ꢀ Power dissipation
)
RSS
from the above formulas.
Table 1 lists some of the inductor values for 5A output
current and several switching frequencies and output
voltages.
Both n-channel MOSFETs must be logic-level types with
guaranteed on-resistance specifications at V
= 4.5V
GS
when V
is set to 5V or V
= 3V when V
is set
OUT1
GS
OUT1
Buck 1 Input Capacitor
The device is designed to operate with a single 0.1µF
to 3.3V. The conduction losses at minimum input voltage
should not exceed MOSFET package thermal limits or
violate the overall thermal budget. Also, ensure that the
conduction losses plus switching losses at the maximum
input voltage do not exceed package ratings or violate the
overall thermal budget. In particular, check that the dV/dt
caused by DH1 turning on does not pull up the DL1 gate
through its drain-to-gate capacitance. This is the most
frequent cause of cross-conduction problems.
capacitor on the V
input and a single 0.1µF capacitor on
SUP
the PV1 input. Place these capacitors as close as possible to
their corresponding inputs to ensure the best EMI and jitter
performance.
OUT1 Output Capacitor
The primary purpose of the OUT1 output capacitor is
to reduce the change in V
conditions. The minimum capacitor depends on the output
voltage, maximum current, and load regulation accuracy.
during load transient
OUT1
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. Therefore, the power dissipation
in the device due to drive losses must be checked. Both
MOSFETs must be selected so that their total gate charge
Table 1. Inductor Values vs. (V
V
)
SUPMAX, OUT1
V
to V
(V)
V
= 36V, V
0.525
5.6
= 5V
V
= 36V, V
0.525
4.7
= 3.3V
SUPMAX
OUT1
SUPMAX
OUT1
SUPMAX
1.05
OUT1
f
(MHz)
2.1
1.5
1.05
0.420
6.8
0.350
8.2
2.1
1.0
0.420
4.7
0.350
6.8
SW1
INDUCTOR (µH), I
= 5A
3.3
2.2
LOAD
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
is low enough; therefore, PV1/V
drivers without overheating the device:
can power both
In a current-mode step-down converter, the output capaci-
tor and the load resistance introduce a pole at the follow-
OUT1
ing frequency:
1
P
= V x (Q + Q
) x f
SW1
DRIVE
OUT1
GTOTH
GTOTL
f
=
pMOD
where Q
is the low-side MOSFET total gate charge
GTOTL
2 π × C
×R
LOAD
OUT
and Q
is the high-side MOSFET total gate charge.
GTOTH
Select MOSFETs with a Q total of less than 10nC. The
The unity-gain frequency of the power stage is set by
G_
selected MOSFET must have an input capacitance (C
)
C
and g
:
ISS
OUT
mc
less than 900pF (typ) to prevent possible damage to the
device.
g
mc
f
=
UGAINpMOD
2 π × C
OUT
The n-channel MOSFETs must deliver the average
current to the load and the peak current during switching.
Dual MOSFETs in a single package can be an economical
solution. To reduce switching noise for smaller MOSFETs,
use a series resistor in the DH1 path and additional gate
capacitance. Contact the factory for guidance using gate
resistors.
The output capacitor and its ESR also introduce a zero at:
1
f
=
zMOD
2 π ×ESR × C
OUT
When C
is composed of “n” identical capacitors in
OUT
parallel, the resulting C
= n x C
, and ESR
OUT
OUT(EACH)
Compensation Network
= ESR
/n. Note that the capacitor zero for a parallel
(EACH)
The device uses a current-mode-control scheme that
regulates the output voltage by forcing the required
current through the external inductor, so the controller
uses the voltage drop across the DC resistance of the
inductor or the alternate series current-sense resistor
to measure the inductor current. Current-mode control
eliminates the double pole in the feedback loop caused
by the inductor and output capacitor, resulting in a smaller
phase shift and requiring less elaborate error-amplifier
compensation than voltage-mode control. A single series
resistor (R ) and capacitor (C ) is all that is required
combination of like-value capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GAIN
=
FB
V
/V
, where V is 1V (typ).
FB OUT FB
The transconductance error amplifier has a DC gain
of GAIN = g x R , where g is
EA(DC)
m,EA
OUT,EA
m,EA
the error amplifier transconductance, which is 660µS
(typ), and R is the output resistance of the error
OUT,EA
amplifier,ꢀwhichꢀisꢀ30MΩꢀ(typ).
Adominant pole (f ) is set by the compensation capac-
C
C
dpEA
to have a stable, high-bandwidth loop in applications
where ceramic capacitors are used for output filtering
(see Figure 4). For other types of capacitors, due to the
higher capacitance and ESR, the frequency of the zero
created by the capacitance and ESR is lower than the
desired closed-loop crossover frequency. To stabilize a
nonceramic output capacitor loop, add another compen-
itor (C ) and the amplifier output resistance (R
). A
OUT,EA
C
zero (f
) is set by the compensation resistor (R ) and
ZEA
C
the compensation capacitor (C ). There is an optional
C
pole (f
) set by C and R to cancel the output
PEA
F
C
g
= 1/(A
x R
DC
)
VCS
mc
sation capacitor (C ) from COMP1 to GND to cancel this
F
CS_
ESR zero.
CURRENT-MODE
POWER MODULATION
OUT_
The basic regulator loop is modeled as a power modu-
lator, output feedback divider, and an error amplifier
(see Figure 4). The power modulator has a DC gain set by
g
= 660µS
MEA
R1
R2
R
ESR
FB_
g
mc
x R , with a pole and zero pair set by R , the
LOAD LOAD
COMP_
30MΩ
ERROR
AMP
output capacitor (C
), and its ESR. The loop response
OUT
C
OUT
V
REF
is set by the following equation:
GAIN = g x R
LOAD
R
C
C
F
MOD(dc)
mc
C
C
where R
1/(A
= V
x R ) in S. A
/I
ꢀ inꢀ Ωꢀ andꢀ g
is the voltage gain of the
=
LOAD
V_CS DC
OUT LOUT(MAX)
mc
V_CS
current-sense amplifier and is typically 8V/V. R
is the
DC
DC resistance of the inductor or the current-sense resistor
inꢀΩ.
Figure 4. Compensation Network
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
capacitor ESR zero if it occurs near the crossover
If f is less than 5 x f , add a second capacitor C
zMOD C F
frequency (f , where the loop gain equals 1 (0dB)).
from COMP1 to GND. The value of C is:
C
F
1
Thus:
C
=
F
1
2 π × f
×R
C
zMOD
f
=
dpEA
2 π × C ×(R
+ R
)
C
C
OUT,EA
As the load current decreases, the modulator pole also
decreases; however, the modulator gain increases accord-
ingly and the crossover frequency remains the same.
1
f
f
=
=
zEA
pEA
2 π × C ×R
C
1
C
C
Below is a numerical example to calculate the compensa-
tion network component values of Figure 4:
2 π × C ×R
F
A
R
= 8V/V
V_CS
The loop-gain crossover frequency (f ) should be set
C
below 1/5 of the switching frequency and much higher
ꢀ=ꢀ22mΩ
DCR
g
mc
= 1/(A
x R ) = 1/(8 x 0.022) = 5.68
DC
than the power-modulator pole (f ). Select a value
pMOD
V_CS
for f
in the range:
CO
V
= 5V
OUT
OUT(MAX)
f
SW
5
f
<< f
≤
CO
pMOD
I
= 5A
R
= V
I ꢀ=ꢀ5V/6Aꢀ=ꢀ0.833Ω
LOAD
OUT/ OUT(MAX)
At the crossover frequency, the total loop gain must be
equal to 1.
C
= 4 x 47µF = 188µF
OUT
ESRꢀ=ꢀ9mΩ/4ꢀ=ꢀ2.25mΩ
Thus:
f
= 0.420MHz
SW
V
FB
GAIN
= 5.68 x 0.833 = 4.73
1
GAIN
×
× GAIN
= 1
)
C
MOD(dc)
MOD( f
)
EA ( R
C
V
OUT
)
f
=
≈ 1kHz
pMOD
GAIN
= g
× f
m,EA
EA (f
C
f
×
2 π ×188µF× 0.833
C
f
pMOD
SW
f
<< f
≤
C
GAIN
= GAIN
pMOD
MOD ( f
)
MOD ( dc )
C
5
f
C
1kHz << f ≤ 80.6kHz, Select f = 20kHz
C
C
Therefore:
GAIN
1
V
FB
f
=
≈ 376kHz
zMOD
×
× g
×R = 1
m,EA C
MOD(f
)
π ×
Ω ×
2
2.25m
188µF
C
V
OUT
Solving for R :
Since f
> f :
zMOD C
C
R ꢀ≈ꢀ33kΩ
C
V
OUT
R
=
C
C ꢀ≈ꢀ4.7nF
C
g
× V
× GAIN
MOD(f
m,EA
FB
)
C
C ꢀ≈ꢀ12pF
F
OUT2/OUT3 Adjustable Output-Voltage Option
Set the error-amplifier compensation zero formed by
R
and C at the f
. Calculate the value of C as
C
The device’s adjustable output-voltage version (see the
Selector Guide for details) allows the customer to set
the outputs to any voltage between 0.8V and 3.95V.
Connect a resistive divider from the buck converter output
C
C
pMOD
follows:
1
C
=
C
2 π × f
×R
C
pMOD
(V
) to OUT_ to GND to set the output voltage
OUT_(BUCK)
(Figure 5). Select R4 (OUT_ to GND resistor) less than
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│ 19
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
orꢀequalꢀtoꢀ100kΩ.ꢀCalculateꢀR3ꢀ(V
to OUT_
OUT_(BUCK)
resistor) with the following equation:
R
CS
2 × m
L
= V
×
OUT
× 1.5
MIN2
V
OUT_( BUCK )
R 3 = R 4
−1
V
OUT_
To satisfy both L
and L
, L must be set to the
MIN2 MIN
MIN1
larger of the two.
where V
= 800mV (see the Electrical Characteristics).
OUT_
L
= max (L
, L
)
MIN
MIN1 MIN2
The external feedback resistive divider must be frequency
compensated for proper operation. Place a capacitor in
parallel to R3 in the resistive divider network. Use the fol-
lowing equation to determine the value of the capacitor:
The maximum inductor value recommended is 1.6 times
the chosen value from the above formula.
L
= 1.6 x L
MIN
MAX
if R4/R3 > 1, C2 = C(R4/R3)
else, C2 = C, where C = 10pF.
Select a nominal inductor value based on the following
formula:
For fixed output-voltage options, connect OUT_ to V
for the factory-programmed, fixed-output voltage between
0.8V and 3.95V.
OUT_
L
ꢀ<ꢀL
<ꢀL
MIN
NOM MAX
OUT2/OUT3 Input Capacitor
Place a single 4.7µF ceramic bypass capacitor on the
PV2 and PV3 inputs. Phase interleaving of the two low-
voltage buck converters contributes to a lower required
input capacitance by cancelling input ripple currents. Place
the bypass capacitors as close as possible to their cor-
responding PV_ input to ensure the best EMI and jitter
performance.
OUT2/OUT3 Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX16993: inductance value (L),
inductor saturation current (I
), and DC resistance
SAT
(R
). Use the following formulas to determine the mini-
DCR
mum inductor value.
OUT2/OUT3 Output Capacitor
V
− V
× V
)
(
IN
OUT_
OUT
The minimum capacitor required depends on output
voltage, maximum device current capability, and the
error-amplifier voltage gain. Use the following formula to
determine the required output capacitor value:
L
=
MIN1
V
× f
× I
× 35%
MAX
IN
SW
0.378Ωꢀforꢀ1.5Aꢀchannelꢀ
0.167Ωꢀforꢀ3.0Aꢀchannel
R
CS
V
×G
REF
× V
EAMP
×R
CS
C
=
OUT(MIN)
2π × f
CO
OUT
3.0A or 1.5A depending on part number. Use the
maximum output capability of the output channel
for the part number being used.
I
MAX
V
Reference voltage, V
= 0.8V.
REF
REF
Operating frequency. This value is 2.1MHz unless
externally synchronized to a different frequency.
f
SW
Internal current-sense resistance. See the Selector
Guideꢀforꢀtheꢀvalueꢀforꢀeachꢀspecificꢀpartꢀnumber.
R
CS
R
R
ꢀ=ꢀ0.378Ω;ꢀforꢀ1.5Aꢀoutputꢀchannels
ꢀ=ꢀ0.167Ω;ꢀforꢀ3.0Aꢀoutputꢀchannels
CS
CS
The next equation ensures that the inductor current down
slope is less than the internal slope compensation. For
this to be the case the following equation needs to be
satisfied:
f
Target crossover frequency, which is 210kHz.
CO
Error-amplifierꢀvoltageꢀgain.ꢀSeeꢀtheꢀSelectorꢀ
Guide for the setting for each channel.
44.7V/V = Normal gain setting
-mꢀ≥ꢀm2/2
G
EAMP
31.7V/V = Low gain setting
m2
-m
The inductor current downslope. [V
Slope Compensation [0.47 x V/µs]
/L x R
]
OUT
CS
The low gain setting trades off increased load-regulation
error for a smaller output capacitor requirement. This
allows optimization of system cost when system require-
ments allow for the increase in load regulation.
Solving for L and adding a 1.5 multiplier to account for
tolerances in the system:
Maxim Integrated
│ 20
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
is directly related to system-level variables and can be
modified to increase the maximum power dissipation. The
QFND package has an exposed thermal pad on its under-
side. This pad provides a low thermal-resistance path for
heat transfer into the PCB. This low thermally resistive
path carries a majority of the heat away from the IC. The
PCB is effectively a heatsink for the IC. The exposed pad
should be connected to a large ground plane for proper
thermal and electrical performance. The minimum size
of the ground plane is dependent upon many system
variables. To create an efficient path, the exposed pad
should be soldered to a thermal landing, which is con-
nected to the ground plane by thermal vias. The thermal
landing should be at least as large as the exposed pad
and can be made larger depending on the amount of free
space from the exposed pad to the other pin landings. A
sample layout is available on the MAX16993 Evaluation
V
OUT_(BUCK)
LX_
R3
C2
MAX16993
OUT_
R4
Figure 5. Adjustable OUT2/OUT3 Voltage Configuration
For proper functionality, ceramic capacitors must be
used. Make sure that the self-resonance of the ceramic
capacitors is above 1MHz to avoid instability.
Kit to speed designs.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. Use a multilayer board
whenever possible for better noise immunity and power
dissipation. Follow these guidelines for good PCB layout:
Thermal Considerations
How much power the package can dissipate strongly
depends on the mounting method of the IC to the PCB
and the copper area for cooling. Using the JEDEC test
standard, the maximum power dissipation allowed is
2160mW in the side-wettable QFND package. More
power dissipation can be handled by the package if great
attention is given during PCB layout. For example, using
the top and bottom copper as a heatsink and connect-
ing the thermal vias to one of the middle layers (GND)
transfers the heat from the package into the board more
efficiently, resulting in lower junction temperature at
high power dissipation in some MAX16993 applications.
Furthermore, the solder mask around the IC area on both
top and bottom layers can be removed to radiate the heat
directly into the air. The maximum allowable power dis-
sipation in the IC is as follows:
1) Use a large contiguous copper plane under the device
package. Ensure that all heat-dissipating components
have adequate cooling.
2) Isolate the power components and high-current path
from the sensitive analog circuitry. This is essential to
prevent any noise coupling into the analog signals.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. The high-current path comprising
of input capacitor, high-side FET, inductor, and the
output capacitor should be as short as possible.
4) Keep the power traces and load connections short. This
practice is essential for high efficiency. Use thick copper
PCBs (2oz vs. 1oz) to enhance full-load efficiency.
(T
− T )
A
J( MAX )
P
=
MAX
θ
+ θ
CA
5) The analog signal lines should be routed away from
the high-frequency planes. This ensures integrity of
sensitive signals feeding back into the device.
JC
where T
is the maximum junction temperature
J(MAX)
(+150°C), T ꢀisꢀtheꢀambientꢀairꢀtemperature,ꢀθ (2.8°C/W
A
JC
6) Use a single ground plane to reduce the chance of
ground-potential differences. With a single ground
plane, enough isolation between analog return signals
and high-power signals must be maintained.
for the side-wettable QFND) is the thermal resistance
fromꢀ theꢀ junctionꢀ toꢀ theꢀ case,ꢀ andꢀ θ is the thermal
resistance from the case to the surrounding air through
theꢀPCB,ꢀcopperꢀtraces,ꢀandꢀtheꢀpackageꢀmaterials.ꢀθ
CA
CA
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│ 21
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Typical Application Circuit
BIAS
D2
BIAS
BIAS
PV1
PV
2.2µF
1µF
0.1µF
VBATP
BST1
VSUP
10Ω
D1
FB1
0.1µF
0.1µF
0.1µF
220µF
0.1µF
1µF
V
OUT1
(5V, 5A)
V
OUT1
N1
N2
DH1
LX1
2.2µH
22mΩ
PV3
47µF
47µF
47µF
47µF
10µF
DL1
V
OUT3
GND
0.6µH
(1.2V, 3A)
LX3
47µF
47µF
PGND3
CS1
OUT1
BIAS
MAX16993
20pF
10kΩ
FB1
40kΩ
COMP1
OUT3
4.7nF
47pF
20kΩ
V
OUT1
V
OUT1
5.1kΩ
PV2
RESET1
RESET2
RESET3
RESET1
RESET2
RESET3
10µF
1µH
V
OUT2
VBATP
(3.3V, 3A)
100kΩ
LX2
EN1
47µF
47µF
PGND2
BIAS
V
OUT1
EN2
EN3
3.3pF
75kΩ
24kΩ
5.1kΩ
OUT2
GND
ERR
ERR
SYNC
CSEL1
SSEN
EP
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MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Selector Guide
BUCK 1
BUCK 2
BUCK 3
ACTIVE
TIMEOUT
PERIOD
f
SW1
FIXED
ACTIVE
TIMEOUT OUTPUT
FIXED
MAX
ACTIVE
FIXED
MAX
OUTPUT
DIVIDE
RATIO
FROM f
OPTION
SYNC
OUTPUT
VOLTAGE
(V)
OUTPUT TIMEOUT OUTPUT
PERIOD VOLTAGE CURRENT PERIOD VOLTAGE CURRENT (SAME AS
SW
(ms)
(V)
(A)
(ms)
(V)
(A)
BUCK 2)
(ms)
A
B
C
D
E
F
3.3/5.0
3.3/5.0
3.3/5.0
3.3/5.0
3.3/5.0
3.3/5.0
3.3/5.0
3.3/5.2
ADJ
÷5
÷5
÷5
÷5
÷5
÷5
÷5
÷5
÷5
÷4
÷5
÷5
3.9
3.9
1.9
3.9
3.9
3.9
3.9
3.9
1.9
3.9
3.9
3.9
ADJ
3.15
ADJ
1.05
3.30
3.3
3.0
1.5
1.5
3.0
1.5
1.5
1.5
3.0
1.5
3.0
3.0
1.5
3.9
3.9
1.9
3.9
3.9
3.9
3.9
3.9
1.9
3.9
3.9
3.9
ADJ
1.8 (L)
ADJ
3.3
3.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3.0
3.0
1.5
3.9
3.9
1.9
3.9
3.9
3.9
3.9
3.9
1.9
3.9
3.9
3.9
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
1.5
1.2
G
H
I
3.3
1.8
3.3
1.8
ADJ
ADJ
1.05
3.3
ADJ
ADJ
3.3
J*
K
L
3.3/5.0
3.3/5.0
3.3/4.9
1.25
(L) = Low gain setting.
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
MAX16993AGJ_/VY+
MAX16993ATJ_+
MAX16993ATJ_/V+
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
32 QFND-EP**
†
32 TQFN-EP
†
32 TQFN-EP
PACKAGE
TYPE
PACKAGE OUTLINE
LAND
PATTERN NO.
Note: Insert the desired suffix letter (from the Selector Guide)
into the blank to indicate buck switching frequency, active time-
out period, fixed or adjustable output voltages, and maximum
output current.
CODE
G3255Y+1
T3255+4
NO.
32 QFND-EP
32 TQFN-EP
21-0563
21-0140
90-0361
90-0012
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
**EP = Exposed pad/side-wettable flanked package.
†EP = Exposed pad.
Contact factory for options that are not included. Factory-
selectable features include:
• f
divide ratio with respect to master clock
SW1
• DC-DC output voltage
• Number of cycles in active timeout period
• Independent current limit for each channel up to 3A
Maxim Integrated
│ 23
www.maximintegrated.com
MAX16993
Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
5/13
Initial release
—
8/13
Corrected package type (from TQFN to QFND)
1, 2, 9, 22, 24
Added TQFN package, and updated SYNC pin function, limit/short-circuit information,
Package Thermal Characteristics, Typical Application Circuit, Selector Guide, Ordering
Information, and Package Information sections
1, 2, 9, 10,
16, 23, 24
2
10/13
Updated bypass capacitor on PV pin in Pin Description and added /V TQFN package
to Ordering Information
3
4
5
12/13
2/14
3/14
9, 24
11, 15, 21
20, 24
Removed lossless DCR sensing from data sheet, updated Typical Operating Circuit,
and updated G
values in OUT2/OUT3 Output Capacitor section
CS
Corrected the G
equation and -m equation in the OUT2/OUT3 Inductor Selection
CS
tables; updated the TQFN package code in the Package Information table
Removed references to SYNC output functionality: updated General Description,
Electrical Characteristics, Pin Description, General Description, Synchronization
(SYNC), OUT2/OUT3 Inductor Selection sections, and Typical Application Circuit and
Ordering Information
1, 5, 10, 12, 13,
20, 23, 24
6
6/14
Removed future product references from option F, G, H, and I variants in Selector
Guide
7
8
7/14
7/14
24
20
24
24
Corrected equation for slope compensation
Removed future product reference and updated Option D in Selector Guide, corrected
land pattern number for TQFN in Package Information
9
10/14
1/15
10
Added option J variant in Selector Guide
Updated Benefits and Features, added new Note 1 to Absolute Maximum Ratings
and renumbered remaining notes in Package Thermal Characteristics and Electrical
Characteristics, added missing units in Electrical Characteristics,ꢀclarifiedꢀequationsꢀ
in OUT1 Inductor Selection, Compensation Network, and OUT2/OUT3 Adjustable
Output-Voltage Option sections, updated OUT2/OUT3 Inductor Selection and OUT2/
OUT3 Output Capacitor section, deleted Table 2 and Table 3, and added future
product designation to option J variant in Selector Guide
1–5, 16, 19–21,
24
11
3/15
4, 14, 18, 20,
23
12
13
14
9/15
7/16
Miscellaneous updates
Updated Absolute Maximum Ratings and Linear Regulator (BIAS) sections; removed
future product reference from Option K and added Option L in Selector Guide
2, 12, 23
23
Removed future product reference from Option L in Selector Guideꢀandꢀchangedꢀfixedꢀ
output voltage from 3.3/5.0 to 3.3/4.9
12/16
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2016 Maxim Integrated Products, Inc.
│ 24
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