MAX17000AETG+C00_技术文档

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

General Description

Features

o SMPS Regulator (VDDQ)

The MAX17000A pulse-width modulation (PWM) con-

troller provides a complete power solution for notebook

DDR, DDR2, and DDR3 memory. It comprises a step-

down controller, a source-sink LDO regulator, and a ref-

erence buffer to generate the required VDDQ, VTT, and

VTTR rails.

Quick-PWM with 100ns Load-Step Response

Output Voltages—Preset 1.8V, 1.5V, or

Adjustable 1.0V to 2.5V

1% V

Accuracy Over Line and Load

OUT

26V Maximum Input Voltage Rating

Accurate Valley Current-Limit Protection

200kHz to 600kHz Switching Frequency

The VDDQ rail is supplied by a step-down converter

using Maxim’s proprietary Quick-PWM™ controller. The

high-efficiency, constant-on-time PWM controller han-

dles wide input/output voltage ratios (low duty-cycle

applications) with ease and provides 100ns response

to load transients while maintaining a relatively constant

switching frequency. The Quick-PWM architecture cir-

cumvents the poor load-transient timing problems of

fixed-frequency current-mode PWMs while also avoid-

ing the problems caused by widely varying switching

frequencies in conventional constant-on-time and con-

stant-off-time PWM schemes. The controller senses the

current to achieve an accurate valley current-limit pro-

tection. It is also built in with overvoltage, undervoltage,

and thermal protections. The MAX17000A can be set to

run in three different modes: power-efficient SKIP

mode, low-noise forced-PWM mode, and standby

mode to support memory in notebook computer stand-

by operation. The switching frequency is programma-

ble from 200kHz to 600kHz to allow small components

and high efficiency. The VDDQ output voltage can be

set to a preset 1.8V or 1.5V, or be adjusted from 1.0V to

2.5V by an external resistor-divider. This output has 1%

accuracy over line-and-load operating range.

o Source/Sink Linear Regulator (VTT)

±2A Peak Source/Sink

Low-Output Capacitance Requirement

Output Voltages-Preset VDDQ/2 or REFIN

Adjustable from 0.5V to 1.5V

o Soft-Start/Soft-Shutdown

o SMPS Power-Good Window Comparator

o VTT Power-Good Window Comparator

o Selectable Overvoltage Protection

o Undervoltage/Thermal Protections

o ±±mA Reference ꢀuffer (VTTR)

Ordering Information

PART

TEMP RANGE

PIN-PACKAGE

MAX17000AETG+

-40°C to +85°C

24 Thin QFN-EP*

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Pin Configuration

The MAX17000A includes a 2A source-sink LDO reg-

ulator for the memory termination VTT rail. This VTT reg-

ulator has a 5mV deadband that either sources or

sinks, ideal for the fast-changing load burst present in

memory termination applications. This feature also

reduces output capacitance requirements.

TOP VIEW

18

17

16

15

14

13

12

11

10

9

V

19

CSL

FB

DD

The VTTR reference buffer sources and sinks 3mA,

providing the reference voltage needed by the memory

controller and devices on the memory bus.

PGND1 20

AGND 21

SKIP 22

REFIN

MAX17000A

The MAX17000A is available in a 24-pin, 4mm x 4mm,

thin QFN package.

VTTI

V

8

VTT

23

24

CC

*EP

5

Applications

7

PGND2

SHDN

Notebook Computers

1

2

3

4

6

DDR, DDR2, and DDR3 Memory Supplies

SSTL Memory Supplies

THIN QFN

4mm x 4mm

*EXPOSED PAD

Quick-PWM is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

19-4307; Rev 3; 4/13

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

AꢀSOLUTE MAXIMUM RATINGS

TON to PGND1.......................................................-0.3V to +28V

VTTI to PGND2 .........................................................-0.3V to +6V

VTT to PGND2 ............................................-0.3V to (V + 0.3V)

V

to PGND1..........................................................-0.3V to +6V

DD

CC

TTI

to V ............................................................-0.3V to +0.3V

VTTS to AGND............................................-0.3V to (V

+ 0.3V)

DD

CC

OVP to AGND...........................................................-0.3V to +6V

SHDN, STDBY, SKIP to AGND.................................-0.3V to +6V

REFIN, FB, PGOOD1,

VTTR to AGND ..........................................-0.3V to (V

CSL

PGND1, PGND2 to AGND.....................................-0.3V to +0.3V

Continuous Power Dissipation (T = +70°C)

A

PGOOD2 to AGND ................................-0.3V to (V

CSH, CSL to AGND....................................-0.3V to (V

DL to PGND1..............................................-0.3V to (V

BST to PGND1...........................................................-1V to +34V

BST to LX..................................................................-0.3V to +6V

+ 0.3V)

24-Pin, 4mm x 4mm Thin QFN

CC

DD

(derated 27.8mW/°C above +70°C)..........................2222mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

DH to LX....................................................-0.3V to (V

+ 0.3V)

BST

BST to V .............................................................-0.3V to +28V

DD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V = 12V, V

= V

= 5V, V

= 1.8V, STDBY = SKIP = AGND, T = 0°C to +85°C, unless otherwise noted.

CSL A

IN

CC

DD

SHDN

REFIN

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PWM CONTROLLER

V

3

26

5.5

IN

Input Voltage Range

V

, V

CC DD

4.5

FB = AGND

FB = V

1.485

1.782

0.99

1

1.500

1.800

1.000

1.515

1.818

1.01

2.7

V

= 4.5V to 26V,

IN

Output-Voltage Accuracy

V

CSL

CC

SKIP = V

CC

FB = Adj

Output-Voltage Range

Load Regulation Error

Line Regulation Error

Soft-Start Ramp Time

Soft-Stop Ramp Time

Soft-Stop Threshold

V

CSL

V

CSH

- V

CSL

= 0 to 18mV, SKIP = V

CC

0.1

0.25

1.4

2.8

25

%

V

DD

= 4.5V to 5.5V, V = 4.5V to 26V

%

IN

t

Rising edge of SHDN

Falling edge of SHDN

2.1

ms

mV

SSTART

t

SSTOP

R

= 96.75kꢀ (600kHz),

TON

-15

-10

-15

+15

+10

+15

167ns nominal

V

= 12V,

= 1.2V

R

TON

= 200kꢀ (300kHz),

IN

On-Time Accuracy (Note 2)

t

%

ON

333ns nominal

CSL

R

TON

= 303.25kꢀ

(200kHz), 500ns nominal

2

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

ELECTRICAL CHARACTERISTICS (continued)

(V = 12V, V

IN

= V

= 5V, V

= 1.8V, STDBY = SKIP = AGND, T = 0°C to +85°C, unless otherwise noted.

CSL A

CC

DD

SHDN

REFIN

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

Minimum Off-Time

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

t

(Note 2)

FB forced above 1.0V, STDBY = AGND or

= +25°C

250

350

ns

OFF(MIN)

Quiescent Supply Current (V

)

I

0.01

2

1.00

4

μA

mA

μA

DD

CC

V

T

A

CC,

FB forced above 1.0V (PWM, VTT, and

VTTR blocks); STDBY = V

CC

Quiescent Supply Current (V

Shutdown Supply Current

)

CC

I

FB forced above 1.0V (PWM and VTTR

blocks); STDBY = AGND

900

0.01

1500

5

I

SHDN = AGND, T = +25°C

A

CC + DD

(V + V

)

CC

DD

SHDN = AGND, V = 26V, V = 0 or 5V,

IN

DD

TON Shutdown Current

I

1.00

TON

T

A

= +25°C

LINEAR REGULATOR (VTT)

VTTI Input Voltage Range

VTTI Supply Current

V

1.0

2.8

50

V

TTI

I

VTTI = 2.8V, REFIN = 1.4V, no load

SHDN = AGND, T = +25°C

10

μA

nA

V

VTTI

VTTI Shutdown Current

REFIN Input Bias Current

REFIN Range

10

A

VTTI = 2.8V, REFIN = 1.4V, T = +25°C

A

-50

0.5

+50

1.5

V

REFIN

V

0.3

-

CC

REFIN Disable Threshold

V

High-side on-resistance

0.12

0.18

0.25

0.36

+5

(source, I

= 0.1A)

VTT Internal MOSFET

ꢀ

VTT

Low-side on-resistance (sink, I

= 0.1A)

VTT

V

= 1V,

= +50μA

REFIN

-5

(V

- 5mV) or

/2 - 5mV) to

REFIN

I

VTT

VTT Output-Accuracy

Source Load

mV

CSL

V

= 0.5V to 1.5V,

= 1V,

REFIN

VTTS, VTT = VTTS

-5

I

= +300mA

VTT

V

REFIN

+5

17

(V

+ 5mV) or

/2 + 5mV) to

REFIN

I

= -50μA

VTT

VTT Output-Accuracy

Sink Load

CSL

V

= 0.5V to 1.5V,

= -300mA

REFIN

VTTS, VTT = VTTS

+5

I

VTT

VTT Load Regulation

VTT Line Regulation

-50μA to -1A ꢀ I

ꢀ +50μA to +1A

13

1

mV/A

mV

VTT

1.0V ꢀ V ꢀ 2.8V, I

= 100mA

TTI

VTT

Source

Sink

2

4

VTT Current Limit

A

-4

-2

VTT Current-Limit Soft-Start Time

VTT Discharge MOSFET

VTTS Input Current

With respect to internal VTT_EN signal

OVP = V

160

16

μs

ꢀ

CC

T

A

= +25°C

0.1

1.0

μA

Maxim Integrated

3

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

ELECTRICAL CHARACTERISTICS (continued)

(V = 12V, V

IN

= V

= 5V, V

= 1.8V, STDBY = SKIP = AGND, T = 0°C to +85°C, unless otherwise noted.

CSL A

CC

DD

SHDN

REFIN

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

REFERENCE BUFFER (VTTR)

I

=

1mA

3mA

1mA

3mA

-10

-20

-10

-20

+10

+20

+10

+20

VTT

VTTR Output Accuracy (Adj)

VTTR Output Accuracy (Preset)

REFIN to VTTR

mV

mA

V

CSL

/2 to VTTR

VTTR Maximum

Recommended Current

Source/sink

5

FAULT DETECTION (SMPS)

SMPS OVP and PGOOD1

Upper Trip Threshold

12

15

10

18

%

SMPS OVP and PGOOD1

Upper Trip Threshold

Fault-Propagation Delay

t

FB forced 25mV above trip threshold

Measured at FB, hysteresis = 25mV

μs

OVP

SMPS Output Undervoltage

Fault-Propagation Delay

t

200

-15

10

μs

%

UVP

SMPS PGOOD1 Lower Trip

Threshold

-12

-18

PGOOD1 Lower Trip Threshold

Propagation Delay

FB forced 50mV below PGOOD1 trip

threshold

t

I

μs

V

PGOOD1

PGOOD1 Output Low Voltage

I

= 3mA

0.4

1

SINK

FB = 1V (PGOOD1 high impedance),

PGOOD1 forced to 5V, T = +25°C

A

PGOOD1 Leakage Current

μA

Rising edge, PWM disabled below this level;

hysteresis = 200mV

TON POR Threshold

V

3.0

V

POR(IN)

PGOOD2

FAULT DETECTION (VTT)

PGOOD2 Upper Trip Threshold

PGOOD2 Lower Trip Threshold

Hysteresis = 25mV

8

10

13

-8

%

-13

-10

VTTS forced 50mV beyond PGOOD2

trip threshold

PGOOD2 Propagation Delay

t

I

10

5

μs

VTTS forced 50mV beyond PGOOD2

trip threshold

PGOOD2 Fault Latch Delay

PGOOD2 Output Low Voltage

PGOOD2 Leakage Current

ms

V

I

= 3mA

0.4

1

SINK

VTTS = V

(PGOOD2 high impedance),

REFIN

μA

PGOOD2 forced to 5V, T = +25°C

A

FAULT DETECTION

Thermal-Shutdown Threshold

T

Hysteresis = 15°C

160

4.1

16

°C

V

SHDN

V

CC

Undervoltage Lockout

Rising edge, IC disabled below this level

hysteresis = 200mV

V

3.8

4.4

UVLO(VCC)

Threshold

CSL Discharge MOSFET

OVP = V

ꢀ

CC

4

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

ELECTRICAL CHARACTERISTICS (continued)

(V = 12V, V

IN

= V

= 5V, V

= 1.8V, STDBY = SKIP = AGND, T = 0°C to +85°C, unless otherwise noted.

CSL A

CC

DD

SHDN

REFIN

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

CURRENT LIMIT

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Valley Current-Limit Threshold

V

- V

17

20

25

mV

LIMIT

CSH

CSL

Current-Limit Threshold

(Negative)

V

, SKIP = V

-23

NEG

CSH

CSL

CC

Current-Limit Threshold

(Zero Crossing)

V

- V

LX

1

mV

ZX

PGND1

SMPS GATE DRIVERS

DH Gate-Driver On-Resistance

R

BST - LX forced to 5V

DL high

1.5

0.6

5.0

3.0

ꢀ

DH

DL Gate-Driver On-Resistance

R

DL

DL low

DH Gate-Driver Source/

Sink Current

I

DH forced to 2.5V, BST - LX forced to 5V

1

A

DH

I

DL forced to 2.5V

1

3

DL Gate-Driver Source/

Sink Current

DL(SRC)

DL(SNK)

DL rising, T = +25°C

10

15

25

35

A

Dead Time

t

ns

ꢀ

DEAD

DL falling, T = +25°C

A

Internal BST Switch

On-Resistance

I

= 10mA,

BST

R

4.5

BST

V

DD

= 5V internal design target

V

= V = 26V, SHDN = AGND,

= +25°C

BST

LX

LX, BST Leakage Current

INPUTS AND OUTPUTS

Logic-Input Threshold

0.001

20

μA

T

A

SHDN, STDBY, SKIP, OVP, rising edge

hysteresis = 300mV/600mV (min/max)

1.30

1.65

55

2.00

+1

V

SHDN, STDBY, SKIP = 0 or V

,

CC

Logic-Input Current

-1

μA

T

A

= +25°C

Input Leakage Current

Input Bias Current

CSH = 0 or V , T = +25°C

+1

μA

CC

A

CSL = 0 or V

100

CC

Maxim Integrated

5

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

ELECTRICAL CHARACTERISTICS

(V = 12V, V = V = V

= V

= 5V, V

= 1.8V, STDBY = SKIP = AGND, T = -40°C to +85°C, unless otherwise noted.)

CSL A

IN

CC

DD

SHDN

REFIN

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

PWM CONTROLLER

V

3

26

IN

Input Voltage Range

V

, V

CC DD

4.5

5.5

FB = AGND

FB = V

1.485

1.782

0.990

1.520

1.820

1.020

V

= 4.5V to 26V,

IN

Output-Voltage Accuracy

V

CSL

CC

SKIP = V

CC

FB = Adj

= 96.75kꢀ

R

TON

(600kHz), 167ns

nominal

-15

-10

-15

+15

+10

+15

R

TON

= 200kꢀ

V

= 12V,

IN

On-Time Accuracy (Note 2)

t

%

(300kHz), 333ns

nominal

ON

= 1.2V

CSL

R

TON

= 303.25kꢀ

(200kHz), 500ns

nominal

Minimum Off-Time

t

(Note 2)

FB forced above 1.0V (PWM, VTT, and

VTTR blocks); STDBY = V

350

4

ns

OFF(MIN)

mA

CC

Quiescent Supply Current (V

)

CC

I

CC

FB forced above 1.0V (PWM and VTTR

blocks); STDBY = AGND

1500

μA

LINEAR REGULATOR (VTT)

VTTI Input Voltage Range

VTTI Supply Current

V

1.0

0.5

2.8

50

V

μA

V

VTTI

I

VTTI = 2.8V, REFIN = 1.4V, no load

VTTI

REFIN Range

V

1.5

REFIN

V

0.3

-

CC

REFIN Disable Threshold

V

High-side on-resistance (source, I

= 0.1A)

0.25

0.36

17

VTT

VTT Internal MOSFET

VTT Load Regulation

ꢀ

Low-side on-resistance (sink, I

= 0.1A)

VTT

-50μA to -1A ꢀ I

ꢀ +50μA to +1A

mV/A

VTT

6

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

ELECTRICAL CHARACTERISTICS (continued)

(V = 12V, V = V = V

= V

= 5V, V

= 1.8V, STDBY = SKIP = AGND, T = -40°C to +85°C, unless otherwise noted.)

CSL A

IN

CC

DD

SHDN

REFIN

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

REFERENCE BUFFER (VTTR)

I

=

1mA

3mA

1mA

3mA

-10

-20

-10

-20

+10

+20

+10

+20

VTT

VTTR Output Accuracy (Adj)

REFIN to VTTR

mV

VTTR Output Accuracy (Preset)

V

CSL

/2 to VTTR

FAULT DETECTION (SMPS)

PGOOD1 Output Low Voltage

FAULT DETECTION (VTT)

PGOOD2 Output Low Voltage

FAULT DETECTION

I

= 3mA

0.4

V

SINK

V

Undervoltage-Lockout

Rising edge, IC disabled below this level;

hysteresis = 200mV

CC

V

4.0

15

4.4

25

V

UVLO(VCC)

Threshold

CURRENT LIMIT

Valley Current-Limit Threshold

SMPS GATE DRIVERS

DH Gate-Driver On-Resistance

V

LIMIT

V

CSH

- V

CSL

mV

R

DH

BST - LX forced to 5V

DL high

5

3

ꢀ

DL Gate-Driver On-Resistance

R

DL

DL low

DL rising

10

15

Dead Time

t

ns

DEAD

DL falling

INPUTS AND OUTPUTS

Logic-Input Threshold

SHDN, STDBY, SKIP OVP, rising edge

hysteresis = 300mV/600mV (min/max)

1.3

2

V

Note 1: Limits are 100% production tested at T = +25°C. Maximum and minimum limits over temperature are guaranteed by design

A

and characterization.

Note 2: On-time and off-time specifications are measured from 50% point at the DH pin with LX = GND, V

= 5V, and a 250pF

BST

capacitor connected from DH to LX. Actual in-circuit times might differ due to MOSFET switching speeds.

Maxim Integrated

7

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Typical Operating Characteristics

(MAX17000A Circuit of Figure 1, V = 12V, V

IN

= V

= 5V, SKIP = GND, T = +25°C, unless otherwise noted.)

DD

CC

A

SMPS 1.5V EFFICIENCY

vs. LOAD CURRENT

SMPS 1.5V EFFICIENCY

vs. LOAD CURRENT

SMPS 1.5V EFFICIENCY

vs. LOAD CURRENT

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

SKIP MODE

STDBY = LOW

SKIP MODE

STDBY = LOW

SKIP MODE

STDBY = LOW

90

80

70

SKIP MODE

STDBY = HIGH

60

50

40

30

20

10

STDBY = HIGH

PWM MODE

STDBY = HIGH OR LOW

SKIP MODE

STDBY = HIGH

PWM MODE

STDBY = HIGH OR LOW

V

IN

= 7V

V

IN

= 12V

V = 20V

IN

0.01

0.1

1

10

0.01

0.1

1

10

0.01

0.1

1

10

LOAD CURRENT (A)

SMPS 1.5V OUTPUT VOLTAGE

vs. LOAD CURRENT

SMPS SWITCHING FREQUENCY

vs. LOAD CURRENT

SMPS VALLEY-CURRENT LIMIT

vs. INPUT VOLTAGE

1.51

1.50

1.49

350

300

250

10.50

10.25

10.00

PWM MODE

R

= 2mΩ

SENSE

SKIP MODE

PWM MODE

200

150

100

50

SKIP MODE

9.75

9.50

V

= 12V

IN

= 1.5V

V

IN

= 12V

OUT

0

0.001

0.01

0.1

1

10

0

2

4

6

8

10

4

8

12

16

20

24

28

LOAD CURRENT (A)

INPUT VOLTAGE (V)

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

PRESET 1.5V OUTPUT

VOLTAGE DISTRIBUTION

100

10

50

SAMPLE SIZE = 150

T

A

T

A

= +85°C

NO LOAD

= +25°C

PWM MODE, I + I

CC DD

40

30

20

10

PWM MODE, I

IN

STDBY = HIGH, SKIP MODE, I + I

CC DD

1

0.1

STDBY = LOW, SKIP MODE, I + I

CC DD

SKIP MODE, I

IN

0.01

0

4

8

12

16

20

24

28

1.490

1.495

1.500

1.505

1.510

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

8

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Typical Operating Characteristics (continued)

(MAX17000A Circuit of Figure 1, V = 12V, V

IN

= V

= 5V, SKIP = GND, T = +25°C, unless otherwise noted.)

DD

CC

A

STARTUP WAVEFORM

SHUTDOWN WAVEFORM

STANDBY TRANSITION WAVEFORM

(HEAVY LOAD)

(DISCHARGE MODE ENABLED)

MAX17000A toc11

MAX17000A toc09

MAX17000A toc10

I

= 50mA

VTT

STDBY

DL

SHDN

VDDQ

VTT

VDDQ

VTTR

TON

DL

VTT

PGOOD2

PGOOD1

VTT

VTTR

PGOOD1

LX

SHDN

I

LX

I

LX

I

LX

DL

100μs/div

200μs/div

PGOOD1: 2V/div

400μs/div

STDBY: 5V/div

VDDQ: 1V/div

VTT: 1V/div

TON: 1V/div

DL: 5V/div

LX: 10V/div

SHDN: 5V/div

R

= 0.25Ω

DL: 5V/div

PGOOD2: 5V/div

PGOOD1: 5V/div

SHDN: 10V/div

LOAD

VDDQ: 500mV/div

VTT: 500mV/div

VTTR: 500mV/div

I

: 5A/div

SKIP = GND

VDDQ: 2V/div

VTT: 1V/div

VTTR: 1V/div

LX

DL: 5V/div

I

: 2A/div

I

LX

: 2A/div

LX

SMPS LOAD-TRANSIENT RESPONSE

STANDBY TRANSITION WAVEFORM

(PWM MODE)

(SKIP MODE)

MAX17000A toc12

MAX17000A toc13

MAX17000A toc14

STDBY

VDDQ

LX

VDDQ

LX

VTT

TON

DL

LX

I

LOAD

I

LX

I

LX

I

LX

10μs/div

20μs/div

STDBY: 5V/div

VDDQ: 1V/div

VTT: 1V/div

DL: 5V/div

LX: 10V/div

VDDQ: 50mV/div

LX: 10V/div

I

: 5A/div

VDDQ: 50mV/div

LX: 10V/div

I : 5A/div

LOAD

LX

I

LX

: 5A/div

I : 2A/div

LX

TON: 1V/div

Maxim Integrated

9

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Typical Operating Characteristics (continued)

(MAX17000A Circuit of Figure 1, V = 12V, V

IN

= V

= 5V, SKIP = GND, T = +25°C, unless otherwise noted.)

DD

CC A

VTT VOLTAGE

vs. SOURCE/SINK LOAD CURRENT

VTT OFFSET VOLTAGE DISTRIBUTION

AT 300mA LOAD

OUTPUT OVERLOAD WAVEFORM

MAX17000A toc15

0.79

50

SAMPLE SIZE = 150

T

A

T

A

= +85°C

= +25°C

DL

0.78

0.77

0.76

0.75

40

30

20

10

VDDQ

VTT

VTTR

PGOOD2

PGOOD1

0.74

0.73

0.72

I

LX

V

= 1.5V

TTI

0

400μs/div

-2.0 -1.5 -1.0 -0.5

0

0.5 1.0 1.5 2.0

-15.0

-12.5

-10.0

-7.5

-5.0

DL: 5V/div

PGOOD2: 2V/div

PGOOD1: 2V/div

LOAD CURRENT (A)

OFFSET VOLTAGE (mV)

VDDQ: 1V/div

VTT: 1V/div

VTTR: 1V/div

I

LX

: 10A/div

VTT OVERLOAD FAULT WAVEFORMS

VTT SOURCE CURRENT LIMIT

VTT SINK CURRENT LIMIT

(5ms TIMER)

MAX17000A toc20

50

SAMPLE SIZE = 150

T

A

T

A

= +85°C

= +25°C

SAMPLE SIZE = 150

T

A

T

A

= +85°C

DL

= +25°C

40

30

20

10

40

30

20

10

I

LX

VDDQ

VTT

VTTR

PGOOD1

PGOOD2

0

2.0

2.5

3.0

3.5

4.0

-4.0

-3.5

-3.0

-2.5

-2.0

1ms/div

DL: 5V/div

: 2A/div

VDDQ: 2V/div

VTT: 1V/div

VTTR: 1V/div

PGOOD1: 2V/div

PGOOD2: 2V/div

CURRENT LIMIT (A)

I

LX

10

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Typical Operating Characteristics (continued)

(MAX17000A Circuit of Figure 1, V = 12V, V

= V

= 5V, SKIP = GND, T = +25°C, unless otherwise noted.)

IN

DD

CC

A

VTT LOAD-TRANSIENT RESPONSE (SOURCE)

BETWEEN 10mA AND 1.5A

VTT LOAD-TRANSIENT RESPONSE

I

(SINK)

VTT

MAX17000A toc21

MAX17000A toc22

I

VTT

I

VTT

VTT_ac

VDDQ = 1.5V

20μs/div

I

: 1A/div

I

: 1A/div

VTT

VTT: 20mV/div

VTT LOAD-TRANSIENT RESPONSE

(SOURCE-SINK)

VTTR OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX17000A toc23

0.79

0.78

0.77

0.76

I

VTT

0.75

0.74

0.73

VTT_ac

0.72

0.71

0.70

VDDQ = 1.5V

20μs/div

-6

-4

-2

0

2

4

6

I

: 1A/div

VTT

LOAD CURRENT (mA)

VTT: 50mV/div

Maxim Integrated

11

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Pin Description

NAME

FUNCTION

OVP Mode Control. This input selectively enables/disables the SMPS OV protection feature and

output discharge mode. When enabled, the SMPS OV protection feature is enabled. Connect OVP to

the following voltage levels for the desired function:

1

OVP

High (> 2.4V) = Enable SMPS OV protection, and SMPS and VTT discharge FETs.

Low (GND) = Disable SMPS OV protection, and SMPS and VTT discharge FETs.

Open-Drain Power-Good Output. PGOOD1 is low when the SMPS output voltage is more than 15%

(typ) beyond the normal regulation point, in standby, in shutdown, and during soft-start.

After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the SMPS output is

in regulation.

2

3

PGOOD1

PGOOD2

Open-Drain Power-Good Output. PGOOD2 is low when the VTT output voltage is more than 10% (typ)

beyond the normal regulation point, in standby, in shutdown, and during soft-start.

After the SMPS soft-start circuit has terminated, PGOOD2 becomes high impedance if the VTT output

is in regulation.

Standby Control Input. When SHDN is high and STDBY is low, the MAX17000A turns off the VTT output

(high-Z). When STDBY is high, normal SMPS operation resumes and the VTT output is enabled.

4

5

STDBY

Sense Pin for Termination Supply Output. Normally connected to the VTT pin to allow accurate

VTTS

regulation to V

/2 or the REFIN voltage.

CSL

Termination Reference Buffer Output. VTTR tracks V

/2 when REFIN is connected to V . VTTR

CC

CSL

6

VTTR

tracks V

when a voltage between 0.5V to 1.5V is set at REFIN. Decouple VTTR to AGND with a

REFIN

0.33μF ceramic capacitor.

7

8

PGND2

VTT

Power Ground for VTT. Connect PGND2 externally to the underside of the exposed pad.

Termination Power-Supply Output. Connect VTT to VTTS to regulate the VTT voltage to the VTTS

regulation setting.

Termination Power-Supply Input. VTTI is the input power supply to the VTT linear regulator. Normally

connected to the output of the SMPS regulator for DDR applications.

9

VTTI

External Reference Input. REFIN sets the feedback regulation voltage (VTTR = VTTS = V

MAX17000A.

) of the

REFIN

10

REFIN

Connect REFIN to V to use the internal V

/2 divider.

CC

CSL

Connect a 0.5V to 1.5V voltage input to set the adjustable output for VTT, VTTS, and VTTR.

Feedback Input for SMPS Output. Connect to V for a fixed +1.8V output or to AGND for a fixed

CC

+1.5V output. For an adjustable output (1.0V to 2.7V), connect FB to a resistive divider from the

output voltage. FB regulates to +1.0V.

11

12

13

FB

Negative Input of the PWM Output Current-Sense and Supply Input for VTTR. Connect CSL to the

negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of

the output inductor is utilized for current sensing.

CSL

CSH

CSL is also the path for the internal 16ꢀ discharge MOSFET when V UVLO occurs with OVP enabled.

CC

Positive Input of the PWM Output Current Sense. Connect CSH to the positive side of the output

current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is

utilized for current sensing.

12

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Pin Description (continued)

NAME

FUNCTION

Switching Frequency Setting Input. An external resistor between the input power source and this

pin sets the switching frequency per phase according to the following equation:

T

= C

TON

x (R

+ 6.5kꢀ)

SW

TON

14

TON

where C

= 16.26pF.

TON is high impedance in shutdown.

15

16

DH

LX

High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.

Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1.

Boost Flying Capacitor Connection. Connect to an external 0.1μF, 6V capacitor as shown in Figure

1. The MAX17000A contains an internal boost switch.

17

18

BST

DL

Synchronous-Rectifier Gate-Driver Output. DL swings from V

to PGND1.

DD

Supply Voltage Input for the DL Gate Driver and 3.3V Reference/Analog Supply. Connect to the

system supply voltage (+4.5V to +5.5V). Bypass V to power ground with a 1μF or greater

DD

19

V

DD

ceramic capacitor.

20

21

PGND1

AGND

Power Ground. Ground connection for the low-side MOSFET gate driver.

Analog Ground. Connect backside exposed pad to AGND.

Pulse-Skipping Control Input. This input determines the mode of operation under normal steady-

state conditions and dynamic output-voltage transitions:

High (> 2.4V) = Forced-PWM operation

22

23

SKIP

Low (AGND) = Pulse-skipping mode

Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass V to AGND with a 1μF or

CC

greater ceramic capacitor.

V

CC

Shutdown Control Input. Connect to V for normal operation. When SHDN is pulled low, the

CC

MAX17000A slowly ramps down the output voltage to ground. When the internal target voltage

reaches 25mV, the controller forces DL low, and enters the low current (1μA) shutdown state.

When discharge mode is enabled by OVP (OVP = high), the CSL and VTT internal 16ꢀ discharge

MOSFETs are enabled in shutdown. When discharge mode is disabled by OVP (OVP = low), LX,

VTT, and VTTR are high impedance in shutdown.

24

—

SHDN

A rising edge on SHDN clears the fault OV protection latch.

Exposed Pad. Connect backside exposed pad to AGND.

EP

Maxim Integrated

13

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

DDR2, or DDR3 in a notebook computer. See Table 1 for

component selections. Table 2 lists the component man-

ufacturers. Table 3 is the operating mode truth table.

Standard Application Circuits

The MAX17000A standard application circuit (Figure 1)

generates the VDDQ, VTT, and VTTR rails for DDR,

Table 1. Component Selection for Standard Applications

V

= 1.5V TO 1.8V AT 10A

V

= 1.5V TO 1.8V AT 6A

OUT

COMPONENT

V

= 7V TO 20V (±00kHz)

V

= 7V TO 16V (500kHz)

IN

(2x) 10μF, 25V

Taiyo Yuden TMK432BJ106KM

10μF, 25V

Taiyo Yuden TMK432BJ106KM

Input Capacitor

(2x) 330μF, 2.5V ,12mΩ (C2 case)

SANYO 2R5TPE330MCC2

(2x) 220μF, 2.5V, 21mΩ (B2 case)

SANYO 2R5TPE220MLB

Output Capacitor

Inductor

1.4μH, 12A, 3.4mΩ (typ)

Sumida CDEP105(L)NP-1R4

1.4μH, 12A, 3.4mΩ (typ)

Sumida CDEP105(L)NP-1R4

2mΩ, 0.5W (2010)

Vishay WSL20102L000FEA

3mΩ, 0.5W (2010)

Vishay WSL20103L000FEA

Current-Sensing Resistor

30V, 20A n-channel MOSFET (high side)

Fairchild FDMS8690;

30V, 40A n-channel MOSFET (low side)

Fairchild FDMS8660S

30V 20A n-channel MOSFET (high side)

Fairchild FDMS8690;

30V 40A n-channel MOSFET (low side)

Fairchild FDMS8660S

MOSFETs

Table 2. Component Suppliers

SUPPLIER

PHONE

WEꢀSITE

INDUCTORS

Dale (Vishay)

402-563-6866 (USA)

510-324-4110 (USA)

www.vishay,com

NEC/TOKIN America, Inc.

www.nec-tokinamerica.com

Panasonic Corp.

Sumida Corp.

65-231-3226 (Singapore), 408-749-9714 (USA)

408-982-9660 (USA)

www.panasonic.com

www.sumida.com

www.tokoam.com

TOKO America, Inc.

CAPACITORS

858-675-8013 (USA)

AVX Corp.

843-448-9411 (USA)

www.avxcorp.com

KEMET Corp.

408-986-0424 (USA)

www.kemet.com

Panasonic Corp.

SANYO Electric Co., Ltd.

Taiyo Yuden

65-231-3226 (Singapore), 408-749-9714 (USA)

81-72-870-6310 (Japan), 619-661-6835 (USA)

03-3667-3408 (Japan), 408-573-4150 (USA)

847-803-6100 (USA), 81-3-5201-7241 (Japan)

www.panasonic.com

www.sanyodevice.com

www.t-yuden.com

TDK Corp.

www.component.tdk.com

SENSING RESISTORS

Vishay

402-563-6866 (USA)

800-341-0392 (USA)

www.vishay,com

MOSFET

Fairchild Semiconductor

DIODES

www.fairchildsemi.com

Central Semiconductor Corp.

Nihon Inter Electronics Corp.

631-435-1110

www.centralsemi.com

www.niec.co.jp

81-3-3343-84-3411 (Japan)

14

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Table ±. Operating Mode Truth Table

SHDN STDBY SKIP

OPERATION

SMPS output ramps up in skip mode with a 1.4ms (typ) ramp time. PGOOD1 is held low until the

SMPS output is in regulation.

1

2

L ꢁ H L ꢁ H

X

VTT and VTTR ramp up to the final voltage based on V

VTT is in regulation.

/2 or V

. PGOOD2 is held low until

REFIN

CSL

SMPS output ramps up in skip mode with a 1.4ms ramp time. PGOOD1 is held low until the SMPS

output is in regulation.

VTT remains off throughout since STDBY is low. PGOOD2 stays low throughout.

L ꢁ H

L

VTTR ramps up to the final voltage based on V

/2 or V

.

REFIN

CSL

Standby mode is exited and the full current capability of the MAX17000A is available.

VTT ramps up after the internal SMPS block is ready. VTT ramps to the final voltage based on

3

4

5

6

7

H

L ꢁ H

X

H

L

V

CSL

/2 or V

.

REFIN

PGOOD2 goes high when VTT is in regulation.

SMPS is in forced-PWM mode.

VTT and VTTR are enabled.

PGOOD1 is high when the SMPS output is in regulation.

PGOOD2 is high when VTT is in regulation.

H

L

SMPS is in skip mode.

VTT and VTTR are enabled.

PGOOD1 is high when the SMPS output is in regulation.

PGOOD2 is high when VTT is in regulation.

SMPS is in forced-PWM mode.

VTT is off and is in high impedance.

PGOOD2 is forced low.

H

L

VTTR is active and regulates to V

/2 or V

.

CSL

REFIN

SMPS is in skip mode.

VTT is off and is high impedance.

PGOOD2 is forced low.

L

VTTR is active and regulates to V

/2 or V

.

CSL

REFIN

Skip mode is exited as the MAX17000A ramps the output down to zero.

VTTR tracks V /2 or V during shutdown. After the SMPS output reaches 25mV, DL goes low.

8

9

H ꢁ L

L

H

L

X

CSL

REFIN

Skip mode is exited as the MAX17000A ramps the output down to zero.

VTTR tracks V /2 or V during shutdown. After the SMPS output reaches 25mV, DL goes

CSL

REFIN

low. VTT is not enabled throughout soft-shutdown.

DL low. Internal16ꢀ discharge MOSFETs on CSL and VTT enabled if OVP is high, but disabled if

OVP is low.

10

X

Maxim Integrated

15

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

R

V

C

IN

R

=

R

DCR

CS

R

TON

7V TO 20V

R

+ R

C

14

EQ

1

TON

OVP

+5V

17

15

L1 ( 1 1 )

+

R

=

x

DCR

BST

DH

R3

100kΩ

R2

100kΩ

C

IN

C

EQ

R

EQ

C

N

H

2

3

C

PGOOD1

PGOOD2

BST

VDDQ

+1.8V OR 1.5V

0.1μF

L1

16

LX

R

EQ

C

18

20

N

L

19

C

OUT

DL

D1

+5V

V

DD

C

VDD

PGND1

1μF

PGND

R1

10Ω

13

12

C

EQ

CSH

CSL

23

21

V

5V V

CC

C

VCC

1μF

MAX17000A

R

FBA

FBB

FB OPTIONS:

AGND

11

1. CONNECT FB TO 5V FOR FIXED +1.8V.

2. CONNECT FB TO GND FOR FIXED +1.5V.

3. USE FB RESISTOR-DIVIDER FOR ADJUSTABLE

OUTPUT VOLTAGES.

FB

AGND

R

4

24

22

SLP_S3#

ON/OFF

STDBY

SHDN

SKIP

9

7

VTTI

+1V TO + 2.5V

C

VTTI

VTT

PGND2

C

10

V

CC

REFIN

8

5

6

VTT

VTTS

VTTR

VTT = VDDQ/2

VTTR = VDDQ/2

C

VTTR

0.33μF

EP

Figure 1. MAX17000A Standard Application Circuit

The MAX17000A includes a 2A source-sink LDO reg-

ulator for the memory termination rail. The source-sink

regulator features a dead band that either sources or

sinks, ideal for the fast-changing short-period loads

presenting in memory termination applications. This

feature also reduces the VTT output capacitance

requirement down to 1μF, though load-transient

response can still require higher capacitance values

between 10μF and 20μF.

Detailed Description

The MAX17000A complete DDR solution comprises a

step-down controller, a source-sink LDO regulator, and a

reference buffer. Maxim’s proprietary Quick-PWM pulse-

width modulator in the MAX17000A is specifically

designed for handling fast load steps while maintaining a

relatively constant operating frequency and inductor

operating point over a wide range of input voltages. The

Quick-PWM architecture circumvents the poor load-tran-

sient timing problems of fixed-frequency current-mode

PWMs, while also avoiding the problems caused by

widely varying switching frequencies in conventional con-

stant-on-time and constant-off-time PWM schemes.

Figure 1 is the MAX17000A standard application circuit

and Figure 2 is the MAX17000A functional diagram.

The reference buffer sources and sinks 3mA, generating

a reference rail for use in the memory controller and

memory devices.

16

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

TON

ON-TIME

t

OFF(MIN)

COMPUTE

CSL

Q

TRIG

BST

ONE-SHOT

TON

TRIG

ONE-SHOT

Q

DH

LX

S

R

Q

ERROR

AMP

V

DD

DL

S

R

Q

PGND1

SKIP

1.2V

SMPS FAULT

DETECTION

SMPS

FAULT

OVF

ZERO CROSSING

INT_FB

1mV

SMPS

FAULT

LATCH

OVP

CSL

CSH

VALLEY CURRENT LIMIT

VTT

FAULT

20mV

UVF

0.7V

10ms

TIMER

SMPS RUN

EA

SHDN

RUN

SOFT-START/

SOFT-STOP

1V REF

FB

DECODE

INT_FB

FB

POWER-GOOD1

PGOOD1

V

CC

OVF

1.15V

VTTR WINDOW

COMPARATOR

VTTR

INT_REF

VTT FAULT

MAX17000A

AGND

POWER-GOOD2

PGOOD2

VTT WINDOW

COMPARATOR

VTTS

VTTI

1.4ms

VTTI

VTT

VTT POS

CURRENT LIMIT

V

DD

5ms

TIMER

VTT

FAULT

VTT SS

CURRENT LIMIT

SMPS

FAULT

VTT

5mV

VTT_EN

VTT

VTT NEG

CURRENT LIMIT

STDBY

REFIN

DD

PGND2

V

- 0.3V

DD

PGND2

VTTR

VTT_EN

PGND2

CSL

R

CSL

VTT

CSL

V

CC

R

16Ω

UVLO

16Ω

RUN

OVP

PGND2

PGND1

Figure 2. MAX17000A Functional Diagram

Maxim Integrated

17

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

+5V Bias Supply (V , V

)

DD

CC

C

× (R

+ 6.5kΩ)× (V

+ 0.075V)

TON

CSL

The MAX17000A requires an external 5V bias supply in

addition to the battery. Typically, this 5V bias supply is

the notebook’s 95% efficient 5V system supply.

Keeping the bias supply external to the IC improves

efficiency and eliminates the cost associated with the

5V linear regulator that would otherwise be needed to

supply the PWM circuit and gate drivers. If stand-alone

capability is needed, the 5V supply can be generated

with an external linear regulator such as the MAX1615.

t

=

ON

V

IN

1

f

=

SW

C

× (R

+ 6.5kΩ)

TON

where C

= 16.26pF, and 0.075V is an approxima-

TON

tion to accommodate for the expected drop across the

low-side MOSFET switch. This algorithm results in a

nearly constant switching frequency despite the lack of

a fixed-frequency clock generator.

The 5V bias supply powers both the PWM controller

and internal gate-drive power, so the maximum current

drawn is:

For loads above the critical conduction point, where the

dead-time effect is no longer a factor, the actual switch-

ing frequency is:

I

= I + f

Q

= 2mA to 20mA (typ)

BIAS

Q

SW G(MOSFETs)

where I is the current for the PWM control circuit, f

Q

SW

is the switching frequency, and Q

total gate-charge specification limits at V

internal MOSFETs.

is the

G(MOSFETs)

V

+ V

DIS

OUT

f

=

= 5V for the

SW

GS

t

× (V − V

+ V

)

ON

IN

CHG

DIS

Free-Running Constant-On-Time PWM

Controller with Input Feed-Forward

where V

is the sum of the parasitic voltage drops in

DIS

the inductor discharge path, including synchronous

rectifier, inductor, and PCB resistances; V is the

The Quick-PWM control architecture is a pseudo-fixed-

frequency, constant on-time, current-mode regulator

with voltage feed-forward. This architecture utilizes the

output filter capacitor’s ESR to act as a current-sense

resistor, so the output ripple voltage can provide the

PWM ramp signal. In addition to the general Quick-

PWM, the MAX17000A also senses the inductor current

through DCR method or with a sensing resistor.

Therefore, it is less dependent on the output capacitor

ESR for stability. The control algorithm is simple: the

high-side switch on-time is determined solely by a one-

shot whose pulse width is inversely proportional to input

voltage and directly proportional to output voltage.

Another one-shot sets a minimum off-time (250ns typ).

The on-time one-shot is triggered if the error compara-

tor is low, the low-side switch current is below the valley

current-limit threshold, and the minimum off-time one-

shot has timed out.

CHG

sum of the parasitic voltage drops in the charging path,

including the high-side switch, inductor, and PCB resis-

tances; and t

MAX17000A.

is the on-time calculated by the

ON

Automatic Pulse-Skipping Mode

(SKIP = AGND)

In skip mode (SKIP = AGND), an inherent automatic

switchover to PFM takes place at light loads. This

switchover is affected by a comparator that truncates

the low-side switch on-time at the inductor current’s

zero crossing.

DC output-accuracy specifications refer to the thresh-

old of the error comparator. When the inductor is in

continuous conduction, the MAX17000A regulates the

valley of the output ripple, so the actual DC output volt-

age is higher than the trip level by 50% of the output

ripple voltage. In discontinuous conduction (SKIP =

On-Time One-Shot

The heart of the PWM core is the one-shot that sets the

high-side switch on-time. This fast, low-jitter, adjustable

one-shot includes circuitry that varies the on-time in

response to battery and output voltages. The high-side

switch on-time is inversely proportional to the battery

AGND and I

< I

), the output voltage has

LOAD(SKIP)

OUT

a DC regulation level higher than the error-comparator

threshold by approximately 1.5% due to slope compen-

sation. However, the internal integrator corrects for

most of it, resulting in very little load regulation.

The MAX17000A always uses skip mode during start-

up, regardless of the SKIP and STDBY setting. The

SKIP and STDBY controls take effect after soft-start is

done. See Figure 3.

voltage as measured by the V input, and proportional

IN

to the output voltage.

An external resistor between the input power source

and TON pin sets the switching frequency per phase

according to the following equation:

18

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

reverses at light loads while DH maintains a duty factor

of V /V . The benefit of forced-PWM mode is to keep

OUT IN

a fairly constant switching frequency. However, forced-

PWM operation comes at a cost: the no-load 5V bias

current remains between 2mA to 20mA, depending on

the switching frequency.

ΔI

Δt

V

- V

IN OUT

=

L

STDBY = AGND overrides the SKIP pin setting, forcing

the MAX17000A into standby.

I

PEAK

The MAX17000A switches to forced-PWM mode during

shutdown, regardless of the state of SKIP and STDBY

levels.

I

= I

/2

LOAD PEAK

Standby Mode (STDBY)

It should be noted that standby mode in the

MAX17000A corresponds to computer system standby

operation, and is not referring to the MAX17000A shut-

down status.

0

ON-TIME

TIME

Figure 3. Pulse-Skipping/Discontinuous Crossover Point

When standby mode is enabled (STDBY = AGND),

VTT is disabled (high impedance) but VTTR remains

active.

Forced-PWM Mode (SKIP = V

)

CC

The low-noise forced-PWM mode (SKIP = V ) disables

CC

When standby mode is disabled (STDBY = V ), the

CC

the zero-crossing comparator, which controls the low-

side switch on-time. This forces the low-side gate-drive

waveform to constantly be the complement of the high-

side gate-drive waveform, so the inductor current

VTT block is enabled and the VTT output capacitor is

charged. The VTT soft-start current limit increases lin-

early from zero to its maximum current limit in 160μs

(typ), keeping the input VTTI inrush low. See Figure 4.

STDBY

SMPS OUTPUT

VTTR OUTPUT

VTT HIGH-IMPEDANCE

VTT OUTPUT

VTT CURRENT LIMIT

160μs

PGOOD1

PGOOD2

STANDBY TIMING

Figure 4. MAX17000A Standby Mode Timing

Maxim Integrated

19

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

PGOOD2 is the open-drain output for a window com-

Valley Current-Limit Protection

The MAX17000A uses the same valley current-limit pro-

tection employed on all Maxim Quick-PWM controllers. If

the current exceeds the valley current-limit threshold,

the PWM controller is not allowed to initiate a new cycle.

The actual peak current is greater than the valley cur-

rent-limit threshold by an amount equal to the inductor

ripple current. Therefore, the exact current-limit charac-

teristic and maximum load capability are a function of

the inductor value and battery voltage. When combined

with the undervoltage-protection circuit, this current-limit

method is effective in almost every circumstance.

parator that continuously monitors the VTT output.

PGOOD2 is actively held low in standby, shutdown,

and during soft-start. PGOOD2 becomes high imped-

ance as long as the VTT output voltage is within 10%

of the regulation voltage. When the VTT output exceeds

the 10% threshold, the MAX17000A pulls PGOOD2

low. If PGOOD2 remains low for 5ms (typ), the

MAX17000A latches off with the soft-shutdown

sequence.

For logic-level output voltages, connect an external 100kΩ

pullup resistor from PGOOD1 and PGOOD2 to V

.

DD

In forced-PWM mode, the MAX17000A also implements

a negative current limit to prevent excessive reverse

POR, UVLO

rises above

Power-on reset (POR) occurs when V

CC

inductor currents when V

is sinking current. The

OUT

approximately 2V, resetting the fault latch and soft-start

circuit and preparing the controller for power-up. When

OVP protection is enabled, a rising edge on POR turns

on the 16Ω discharge MOSFET on CSL and VTT. When

OVP is disabled, the internal 16Ω discharge MOSFETs

on CSL and VTT also remain off.

negative current-limit threshold is set to approximately

115% of the positive current limit. See Figure 5.

I

PEAK

LOAD

V

undervoltage lockout (UVLO) circuitry inhibits

CC

switching until V

reaches 4.1V (typ). When V

rises

CC

above 4.1V, the controller activates the PWM controller

and initializes soft-start. When V drops below the

CC

UVLO threshold (falling edge), the controller stops, DL

is pulled low, and the internal 16Ω discharge

MOSFETs on the CSL and VTT outputs are enabled, if

OVP is enabled.

I

LIMIT

LIR

2

I

= I

1-

( )

LIM(VAL) LOAD(MAX)

Soft-Start and Soft-Shutdown

Soft-start and soft-shutdown for the MAX17000A PWM

block is voltage based. Soft-start begins when SHDN is

driven high. During soft-start, the PWM output is

ramped up from 0V to the final set voltage in 1.4ms.

This reduces inrush current and provides a predictable

ramp-up time for power sequencing. The MAX17000A

always uses skip mode during startup, regardless of

the SKIP and STDBY setting. The SKIP and STDBY con-

trols take effect after soft-start is done.

0

TIME

Figure 5. Valley Current-Limit Threshold Point

Power-Good Outputs

(PGOOD1 and PGOOD2)

The MAX17000A features two power-good outputs.

PGOOD1 is the open-drain output for a window com-

parator that continuously monitors the SMPS output.

PGOOD1 is actively held low in shutdown and during

soft-start and soft-shutdown. After the soft-start termi-

nates, PGOOD1 becomes high impedance as long as

the SMPS output voltage is between 115% (typ) and

85% (typ) of the regulation voltage. When the SMPS

output voltage exceeds the 115%/85% regulation win-

dow, the MAX17000A pulls PGOOD1 low. Any fault

condition on the SMPS output forces PGOOD1 and

PGOOD2 low and latches off until the fault latch is

The MAX17000A VTT LDO regulator uses a current-limit-

ed soft-start function. When the VTT block is enabled, the

internal source and sink current limits are linearly

increased from zero to the full-scale limit in 160μs. Full-

scale current limit is available when the VTT output is in

regulation, or after 160μs, whichever is earlier. The VTTR

reference buffer does not have any soft-start control.

cleared by toggling SHDN or cycling V

power below

CC

1V. Detection of an OVP event immediately pulls

PGOOD1 low, regardless of the OVP state (OVP

enabled or disabled).

20

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

SHDN

STDBY

INT_REF

REFOK

SMPS_RUNOK

1.4ms

2.8ms

25mV

SMPS OUTPUT

VTT OUTPUT

VTTR OUTPUT

VTT CURRENT LIMIT

160μs

PGOOD1

PGOOD2

SKIP

FPWM

DL

VTT 16Ω FET

CSL 16Ω FET

Figure 6. MAX17000A Startup/Shutdown Timing with OVP Enabled

When OVP is enabled (OVP = V ), the internal 16Ω

Soft-shutdown begins after SHDN goes low, an output

undervoltage fault occurs, or a thermal fault occurs. A

fault on the SMPS (UV fault for more than 200μs (typ)),

or fault on the VTT output that persists for more than

5ms (typ), triggers shutdown of the whole IC. During

soft-shutdown, the output is ramped down to 0V in

2.8ms, reducing negative inductor currents that can

cause negative voltages on the output. At the end of

soft-shutdown, DL is driven low.

CC

discharging MOSFETs on CSL and VTT are enabled

until startup is triggered again by a rising edge of

SHDN. When OVP is disabled (OVP = AGND), the CSL

and VTT internal 16Ω discharging MOSFETs are not

enabled in shutdown.

Output Fault Protection

The MAX17000A provides overvoltage/undervoltage

fault protections for the PWM output. Drive OVP to

enable and disable fault protection as shown in Table 4.

Maxim Integrated

21

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Table 4. Fault Protection and Shutdown Setting Truth Table

OVP

MODE

REACTION/DRIVER STATE

DL immediately pulled low.

VTTR tracks the SMPS output during soft-shutdown. CSL and VTT

COMMENT

Outputs high-

impedance in

shutdown.

Shutdown

(SHDN = low) are high impedance at the end of soft-shutdown (16ꢀ discharge

MOSFETs disabled).

DL immediately pulled low.

VTTR tracks the SMPS output during soft-shutdown. CSL and VTT

are high impedance at the end of soft-shutdown (16ꢀ discharge

SMPS latched fault

condition.

SMPS UVP

MOSFETs disabled).

OVP Disabled

Discharge Disabled

(OVP = Low)

SMPS OVP

(disabled)

Controller remains active (normal operation).

Note: An OVP detection still pulls PGOOD1 low.

Only PGOOD1 pulled

low; fault not latched.

PGOOD2 immediately pulled low.

Soft-shutdown initiated if fault persists for more than 5ms (typ). DH

VTT > +110% not used in soft-shutdown. DL low after soft-shutdown completed.

VTTR tracks the SMPS output soft-shutdown.

VTT latched fault

condition if fault

persists for more

than 5ms (typ).

VTT < -90% or

DL and DH immediately pulled low.

V

UVLO

PGOOD1 and PGOOD2 immediately forced low. VTT and VTTR

blocks immediately disabled (high impedance, no 16ꢀ discharge

on outputs).

CC

—

falling edge

Soft-shutdown initiated.

16ꢀ discharge

DL high after soft-shutdown completed.

(SHDN = low) VTTR tracks the SMPS output during soft-shutdown. Internal 16ꢀ

MOSFETs on CSL

and VTT enabled in

Shutdown

discharge MOSFETs on CSL and VTT enabled after soft-shutdown. shutdown.

Soft-shutdown initiated. DH not used in soft-shutdown. DL low

after soft-shutdown completed.

VTTR tracks the SMPS output during soft-shutdown. Internal 16ꢀ

discharge MOSFETs on CSL and VTT enabled after soft-shutdown.

SMPS latched fault

condition.

SMPS UVP

OVP Enabled

Discharge Enabled

(OVP = High)

DL immediately latched high, DH forced low.

PGOOD1 and PGOOD2 immediately forced low.

VTT and VTTR blocks immediately shut down. Internal 16ꢀ

discharge MOSFETs on CSL and VTT enabled.

SMPS OVP

(enabled)

SMPS latched fault

condition.

PGOOD2 immediately pulled low.

VTT latched fault

condition if fault

persists for more

than 5ms (typ).

Soft-shutdown initiated if fault persists for more than 5ms (typ). DH

not used in soft-shutdown. DL low after soft-shutdown completed.

VTTR tracks the SMPS output during soft-shutdown. Internal 16ꢀ

discharge MOSFETs on CSL and VTT enabled after soft-shutdown.

VTT < 90% or

VTT > 110%

DL and DH immediately pulled low.

PGOOD1 and PGOOD2 immediately forced low.

VTT and VTTR blocks immediately disabled.

Internal 16ꢀ discharge MOSFETs on CSL and VTT enabled

immediately.

OVP Enabled

Discharge Enabled

(OVP = High)

V

UVLO

CC

—

falling edge

22

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Table 4. Fault Protection and Shutdown Setting Truth Table (continued)

OVP

MODE

REACTION/DRIVER STATE

COMMENT

DL and DH immediately pulled low.

PGOOD1 and PGOOD2 immediately forced low.

VTT and VTTR blocks immediately disabled (high impedance, no

16ꢀ discharge on outputs).

Thermal fault

Active-fault condition.

Activate INT_REF once V rises above UVLO, and SHDN = high.

Once REFOK is valid (high), initiate the soft-start sequence.

DL remains low until switching/soft-start begins.

CC

General Shutdown

and Fault

Conditions

V

UVLO

CC

—

rising edge

V

POR

CC

DL forced low.

—

rising edge

V

CC

POR

DL = Don’t care. V less than 2VT is not sufficient to turn on the

CC

falling edge MOSFETs.

SMPS Overvoltage Protection (OVP)

completed, the MAX17000A forces DL and DH low, and

If the output voltage of the SMPS rises 115% above its

nominal regulation voltage while OVP is enabled (OVP =

enables the internal 16Ω discharge MOSFETs on CSL

and VTT. Cycle V

below 1V or toggle SHDN to clear

CC

V

CC

), the controller sets its overvoltage fault latch, pulls

the undervoltage fault latch and restart the controller.

PGOOD1 and PGOOD2 low, and forces DL high. The

VTT and VTTR block shut down immediately, and the

internal 16Ω discharge MOSFETs on CSL and VTT are

turned on. If the condition that caused the overvoltage

persists (such as a shorted high-side MOSFET), the bat-

Thermal-Fault Protection

The MAX17000A features a thermal-fault protection cir-

cuit. When the junction temperature rises above

+160°C, a thermal sensor activates the fault latch, pulls

PGOOD1 and PGOOD2 low, and shuts down using the

tery fuse blows. Cycle V

below 1V or toggle SHDN to

CC

shutdown sequence. Toggle SHDN or cycle V

power

CC

clear the overvoltage fault latch and restart the controller.

below V

POR to reactivate the controller after the

CC

OVP is disabled when OVP is connected to AGND

(Table 4). PGOOD1 upper threshold remains active at

115% of nominal regulation voltage even when OVP is

disabled and the 16Ω discharge MOSFETs on CSL

and VTT are not enabled in shutdown.

junction temperature cools by 15°C.

Design Procedure

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency and

inductor operating point (ripple-current ratio). The pri-

mary design trade-off lies in choosing a good switching

frequency and inductor operating point, and the follow-

ing four factors dictate the rest of the design:

SMPS Undervoltage Protection (UVP)

If the output voltage of the SMPS falls below 85% of its

regulation voltage for more than 200μs (typ), the controller

sets its undervoltage fault latch, pulls PGOOD1 and

PGOOD2 low, and begins soft-shutdown pulsing DL. DH

remains off during the soft-shutdown sequence initiated

by an undervoltage fault. After soft-shutdown has com-

pleted, the MAX17000A forces DL and DH low, and

enables the internal 16Ω discharge MOSFETs on CSL

•

Input Voltage Range: The maximum value

(V ) must accommodate the worst-case input

IN(MAX)

supply voltage allowed by the notebook’s AC

adapter voltage. The minimum value (V

)

IN(MIN)

must account for the lowest input voltage after

drops due to connectors, fuses, and battery selec-

tor switches. If there is a choice at all, lower input

voltages result in better efficiency.

and VTT. Cycle V

below 1V or toggle SHDN to clear

CC

the undervoltage fault latch and restart the controller.

VTT Overvoltage and Undervoltage Protection

If the output voltage of the VTT regulator exceeds

10% of its regulation voltage for more than 5ms (typ),

the controller sets its fault latch, pulls PGOOD1 and

PGOOD2 low, and begins soft-shutdown pulsing DL.

DH remains off during the soft-shutdown sequence initi-

ated by an undervoltage fault. After soft-shutdown has

•

Maximum Load Current: There are two values to

consider. The peak load current (I

) deter-

LOAD(MAX)

mines the instantaneous component stresses and

filtering requirements, and thus drives output

capacitor selection, inductor saturation rating, and

the design of the current-limit circuit. The continu-

ous load current (I

) determines the thermal

LOAD

Maxim Integrated

23

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

stresses and thus drives the selection of input

capacitors, MOSFETs, and other critical heat-con-

tributing components. Most notebook loads gener-

iron is inexpensive and can work well at 200kHz. The

core must be large enough not to saturate at the peak

inductor current (I

):

PEAK

ally exhibit I

= I

x 80%.

LOAD

LOAD(MAX)

LIR

2

⎛

⎝

⎞

I

= I

× 1+

⎜

LOAD(MAX)

⎟

⎠

PEAK

•

Switching Frequency: This choice determines the

basic trade-off between size and efficiency. The

optimal frequency is largely a function of maximum

input voltage, due to MOSFET switching losses that

Setting the Valley Current Limit

The minimum current-limit threshold must be high

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The val-

are proportional to frequency and V ². The opti-

IN

mum frequency is also a moving target, due to

rapid improvements in MOSFET technology that are

making higher frequencies more practical.

ley of the inductor current occurs at I

half the ripple current; therefore:

minus

LOAD(MAX)

Inductor Operating Point: This choice provides

trade-offs between size vs. efficiency and transient

response vs. output noise. Low inductor values pro-

vide better transient response and smaller physical

size, but also result in lower efficiency and higher

output noise due to increased ripple current. The

minimum practical inductor value is one that causes

the circuit to operate at the edge of critical conduc-

tion (where the inductor current just touches zero

with every cycle at maximum load). Inductor values

lower than this grant no further size-reduction bene-

fit. The optimum operating point is usually found

between 20% and 50% ripple current.

LIR

2

⎛

⎝

⎞

I

> I

× 1-

⎜

⎟

⎠

LIMIT(LOW) LOAD(MAX)

where I

equals the minimum current-limit

threshold voltage divided by the output sense element

(inductor DCR or sense resistor).

LIMIT(LOW)

The valley current limit is fixed at 17mV (min) across the

CSH to CSL differential input.

Special attention must be made to the tolerance and

thermal variation of the on-resistance in the case of DCR

sensing. Use the worst-case maximum value for R

from the inductor data sheet, and add some margin for

the rise in R with temperature. A good general rule

is to allow 0.5% additional resistance for each degree

Celsius of temperature rise, which must be included in

the design margin unless the design includes an NTC

thermistor in the DCR network to thermally compensate

the current-limit threshold.

DCR

Inductor Selection

DCR

The switching frequency and operating point (% ripple

current or LIR) determine the inductor value as follows:

⎛

⎞

⎛

⎝

⎞

⎠

V

- V

V

OUT

IN

OUT

L =

×

⎜

⎟

⎜

⎟

f

×I

× LIR

V

⎝

⎠

SW LOAD(MAX)

IN

The current-sense method (Figure 7) and magnitude

determine the achievable current-limit accuracy and

power loss. The sense resistor can be determined by:

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite

cores are often the best choice, although powdered

R

= V

/I

SENSE

LIMIT LIMIT

INPUT (V )

IN

C

N

H

IN

SENSE RESISTOR

DH

LX

R

L

ESL

SENSE

L

ESL

C

R

=

EQ EQ

R

SENSE

C

OUT

C

DL

EQ

MAX17000A

R

D

EQ

L

N

L

PGND1

CSH

CSL

A) OUTPUT SERIES RESISTOR SENSING

Figure 7a. Current-Sense Configurations (Sheet 1 of 2)

24

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

INPUT (V )

IN

C

IN

N

H

INDUCTOR

DH

LX

R

L

DCR

R2

R1 + R2

R

=

R

DCR

CS

C

OUT

R

2

1

MAX17000A

DL

D

L

N

L

1

R2

+

R

=

DCR

[_R1]

C

EQ

PGND1

C

EQ

CSH

CSL

FOR THERMAL COMPENSATION:

R2 SHOULD CONSIST OF AN NTC RESISTOR IN

SERIES WITH A STANDARD THIN-FILM RESISTOR.

B) LOSSLESS INDUCTOR SENSING

Figure 7b. Current-Sense Configurations (Sheet 2 of 2)

For the best current-sense accuracy and overcurrent

protection, use a 1% tolerance current-sense resistor

between the inductor and output as shown in Figure 7a.

This configuration constantly monitors the inductor cur-

rent, allowing accurate current-limit protection.

However, the parasitic inductance of the current-sense

resistor can cause current-limit inaccuracies, especially

when using low-value inductors and current-sense

MOSFET Gate Drivers (DH, DL)

The DH and DL drivers are optimized for driving moder-

ate-sized high-side, and larger low-side power MOSFETs.

This is consistent with the low duty factor seen in note-

book applications, where a large V - V

differential

IN

OUT

exists. The high-side gate driver (DH) sources and sinks

1.2A, and the low-side gate driver (DL) sources 1.0A and

sinks 2.4A. This ensures robust gate drive for high-cur-

rent applications. The DH floating high-side MOSFET dri-

ver is powered by an internal boost switch charge pump

at BST, while the DL synchronous-rectifier driver is pow-

resistors. This parasitic inductance (L

) can be can-

ESL

celled by adding an RC circuit across the sense resis-

tor with an equivalent time constant:

ered directly by the 5V bias supply (V ).

DD

L

ESL

C

× R

=

PWM Output Capacitor Selection

EQ

R

SENSE

The output filter capacitor must have low enough effec-

tive series resistance (ESR) to meet output ripple and

load-transient requirements, yet have high enough ESR

to satisfy stability requirements.

Alternatively, low-cost applications that do not require

highly accurate current-limit protection could reduce

the overall power dissipation by connecting a series RC

circuit across the inductor (Figure 7b) with an equiva-

lent time constant:

In core and chipset converters and other applications

where the output is subject to large-load transients, the

output capacitor’s size typically depends on how much

ESR is needed to prevent the output from dipping too

low under a load transient. Ignoring the sag due to finite

capacitance:

R2

R1+ R2

R

=

× R

DCR

CS

and:

V

STEP

LOAD(MAX)

R

(

+ R

≤

)

ESR

PCB

ΔI

L

1

⎡

⎤

R

=

×

+

DCR

⎢

⎣

⎥

⎦

C

R1 R2

In low-power applications, the output capacitor’s size

often depends on how much ESR is needed to maintain

an acceptable level of output ripple voltage. The output

ripple voltage of a step-down controller equals the total

inductor ripple current multiplied by the output capaci-

tor’s ESR.

EQ

where R

and R

is the required current-sense resistance,

is the inductor’s series DC resistance. Use

CS

DCR

the worst-case inductance and R

by the inductor manufacturer, adding some margin for

the inductance drop over temperature and load.

values provided

DCR

Maxim Integrated

25

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

The maximum ESR to meet ripple requirements is:

ceramic output capacitors can be compensated using

either a DC-compensation or AC-compensation

method. The DC-coupling requires fewer external com-

pensation capacitors, but this also creates an output

load line that depends on the inductor’s DCR (parasitic

resistance). Alternatively, the current-sense information

can be AC-coupled, allowing stability to be dependent

only on the inductance value and compensation com-

ponents and eliminating the DC load line.

⎡

⎢

⎤

⎥

V

× f

× L

× V

IN SW

R

≤

× V

RIPPLE

ESR

V

- V

)

(

⎢

⎣

⎥

⎦

IN

OUT

where f

is the switching frequency.

SW

With most chemistries (polymer, tantalum, aluminum,

electrolytic), the actual capacitance value required

relates to the physical size needed to achieve low ESR

and the chemistry limits of the selected capacitor tech-

nology. Ceramic capacitors provide low ESR, but the

capacitance and voltage rating (after derating) are

When only using ceramic output capacitors, output

overshoot (V

) typically determines the minimum

SOAR

output capacitance requirement. Their relatively low

capacitance value can allow significant output over-

shoot when stepping from full-load to no-load condi-

tions, unless a small inductor value and high switching

frequency are used to minimize the energy transferred

from inductor to capacitor during load-step recovery.

determined by the capacity needed to prevent V

SAG

and V

from causing problems during load tran-

SOAR

sients. Generally, once enough capacitance is added

to meet the overshoot requirement, undershoot at the

rising load edge is no longer a problem. Thus, the out-

put capacitor selection requires carefully balancing

capacitor chemistry limitations (capacitance vs. ESR

vs. voltage rating) and cost.

Unstable operation manifests itself in two related, but

distinctly different ways: double pulsing and feedback

loop instability. Double pulsing occurs due to noise on

the output or because the ESR is so low that there is not

enough voltage ramp in the output voltage signal. This

“fools” the error comparator into triggering a new cycle

immediately after the minimum off-time period has

expired. Double pulsing is more annoying than harmful,

resulting in nothing worse than increased output ripple.

However, it can indicate the possible presence of loop

instability due to insufficient ESR. Loop instability can

result in oscillations at the output after line or load

steps. Such perturbations are usually damped, but can

cause the output voltage to rise above or fall below the

tolerance limits.

PWM Output Capacitor

Stability Considerations

For Quick-PWM controllers, stability is determined by the

in-phase feedback ripple relative to the switching frequen-

cy, which is typically dominated by the output ESR. The

boundary of instability is given by the following equation:

f

1

SW

π

≥

2π × R

× C

EFF OUT

R

= R

+ A × R

EFF

ESR CS SENSE

where C

is the total output capacitance, R

is the

OUT

ESR

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully

observe the output voltage ripple envelope for over-

shoot and ringing. It can help to simultaneously monitor

the inductor current with an AC current probe. Do not

allow more than one cycle of ringing after the initial

step-response undervoltage/overshoot.

total equivalent series resistance of the output capaci-

tors, R

is the effective current-sense resistance

SENSE

(see Figure 7), and A is the current-sense gain of 2.

CS

For a standard 300kHz application, the effective zero

frequency must be well below 95kHz, preferably below

50kHz. With these frequency requirements, standard

tantalum and polymer capacitors already commonly

used have typical ESR zero frequencies below 50kHz,

allowing the stability requirements to be achieved with-

out any additional current-sense compensation. In the

standard application circuit (Figure 1), the ESR needed

Input Capacitor Selection

The input capacitor must meet the ripple current

requirement (I

RMS

lowing equation:

) imposed by the switching currents.

RMS

The I

requirements can be determined by the fol-

to support a 15mV

ripple is 15mV/(10A x 0.3) =

P-P

5mΩ. Two 330μF, 9mΩ polymer capacitors in parallel

provide 4.5mΩ (max) ESR and 1/(2π x 330μF x 9mΩ) =

53kHz ESR zero frequency.

⎛

⎝

⎞

⎠

I

LOAD

I

=

V

× V − V

(

)

RMS

OUT

IN

OUT

⎜

⎟

V

IN

Ceramic capacitors have a high-ESR zero frequency,

but applications with sufficient current-sense compen-

sation can still take advantage of the small size, low

ESR, and high reliability of the ceramic chemistry. By

the inductor current DCR sensing, applications with

The worst-case RMS current requirement occurs when

operating with V = 2V

IN

. At this point, the above

OUT

equation simplifies to:

I

= 0.5 x I

LOAD

RMS

26

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

For most applications, nontantalum chemistries (ceramic,

can be. Again, the optimum occurs when the switching

losses equal the conduction (R ) losses. High-

side switching losses do not usually become an issue

until the input is greater than approximately 15V.

aluminum, or OS-CON) are preferred due to their resis-

tance to inrush surge currents typical of systems with a

mechanical switch or connector in series with the input.

If the Quick-PWM controller is operated as the second

stage of a two-stage power-conversion system, tanta-

lum input capacitors are acceptable. In either configu-

ration, choose an input capacitor that exhibits less than

+10°C temperature rise at the RMS input current for

optimal circuit longevity.

DS(ON)

Calculating the power dissipation in high-side MOSFET

(N ) due to switching losses is difficult since it must

H

allow for difficult quantifying factors that influence the

turn-on and turn-off times. These factors include the

internal gate resistance, gate charge, threshold voltage,

source inductance, and PCB layout characteristics. The

following switching-loss calculation provides only a very

rough estimate and is no substitute for breadboard

evaluation, preferably including verification using a

MOSFET Selection

Most of the following MOSFET guidelines focus on the

challenge of obtaining high load-current capability

when using high-voltage (> 20V) AC adapters. Low-

current applications usually require less attention.

thermocouple mounted on N :

H

Q

⎛

⎞

G(SW)

PD (NH Switching) = V

×I

× f

IN(MAX) LOAD SW

⎜

⎟

The high-side MOSFET (N ) must be able to dissipate

H

the resistive losses plus the switching losses at both

I

⎝

⎠

GATE

2

C

× V × f

V

and V

. Calculate both these sums.

should be roughly equal to

OSS

IN

SW

IN(MIN)

Ideally, the losses at V

IN(MAX)

+

2

IN(MIN)

losses at V

at V

R

es at V

, with lower losses in between. If the

IN(MAX)

IN(MIN)

where C

G(SW)

is the N MOSFET’s output capacitance,

H

OSS

are significantly higher than the losses

Q

is the charge needed to turn on the N MOSFET,

H

, consider increasing the size of N (reducing

IN(MAX)

H

and I

is the peak gate-drive source/sink current

GATE

(2.2A typ).

but with higher C

). Conversely, if the loss-

GATE

DS(ON)

are significantly higher than the losses at

IN(MAX)

Switching losses in the high-side MOSFET can become

an insidious heat problem when maximum AC adapter

V

, consider reducing the size of N (increasing

IN(MIN)

R

H

to lower C

). If V does not vary over a

GATE IN

DS(ON)

voltages are applied, due to the squared term in the

wide range, the minimum power dissipation occurs

where the resistive losses equal the switching losses.

2

C x V

x f

switching-loss equation. If the high-side

SW

IN

MOSFET chosen for adequate R

voltages becomes extraordinarily hot when biased from

IN(MAX)

lower parasitic capacitance.

at low battery

DS(ON)

Choose a low-side MOSFET that has the lowest possi-

ble on-resistance (R ), comes in a moderate-sized

DS(ON)

V

, consider choosing another MOSFET with

package (i.e., one or two 8-pin SOs, DPAK, or D²PAK),

and is reasonably priced. Make sure that the DL gate

driver can supply sufficient current to support the gate

charge and the current injected into the parasitic gate-

to-drain capacitor caused by the high-side MOSFET

turning on; otherwise, cross-conduction problems can

occur (see the MOSFET Gate Drivers (DH, DL) section).

For the low-side MOSFET (N ), the worst-case power

L

dissipation always occurs at maximum input voltage:

⎡

⎤

⎛

⎞

V

2

OUT

PD (NL Resistive) =⎢1−

⎥ × I

× R

DS(ON)

(

)

⎜

⎟

LOAD

V

⎢

⎣

⎥

⎝

⎠

IN(MAX)

⎦

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor

The worst case for MOSFET power dissipation occurs

under heavy overloads that are greater than

LOAD(MAX)

the current limit and cause the fault latch to trip. To pro-

tect against this possibility, the circuit can be “over

designed” to tolerate:

extremes. For the high-side MOSFET (N ), the worst-

H

case power dissipation due to resistance occurs at the

minimum input voltage:

I

, but are not quite high enough to exceed

⎛

⎝

⎞

⎠

V

2

OUT

PD (NH Resistive) =

× I

(

× R

DS(ON)

)

LOAD

⎜

⎟

V

IN

ΔI

⎛

⎝

⎞

INDUCTOR

I

= I

+

LOAD ⎜ VALLEY(MAX)

⎟

⎠

2

Generally, a small high-side MOSFET is desired to

reduce switching losses at high input voltages.

required to stay within package

power dissipation often limits how small the MOSFET

I

× LIR

⎛

⎞

LOAD(MAX)

2

= I +

VALLEY(MAX)

However, the R

⎜

⎟

DS(ON)

⎝

⎠

Maxim Integrated

27

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

where I

is the maximum valley current

VTTI Input Capacitor

Stability Considerations

VALLEY(MAX)

allowed by the current-limit circuit, including threshold

tolerance and on-resistance variation. The MOSFETs

must have a good size heatsink to handle the overload

power dissipation.

The value of the VTTI bypass capacitor is chosen to

limit the amount of ripple/noise at VTTI, and the amount

of voltage dip during a load transient. Typically, VTTI is

connected to the output of the buck regulator, which

already has a large bulk capacitor. Nevertheless, a

ceramic capacitor of equivalent value to the VTT output

capacitor must be used and must be added and

placed as close as possible to the VTTI pin. This value

must be increased with larger load current, or if the

trace from the VTTI pin to the power source is long and

has significant impedance.

Choose a Schottky diode (DL) with a forward voltage

low enough to prevent the low-side MOSFET body

diode from turning on during the dead time. Select a

diode that can handle the load current during the dead

times. This diode is optional and can be removed if effi-

ciency is not critical.

Setting the PWM Output Voltage

Preset Output Voltages

The MAX17000A’s Dual Mode™ operation allows the

selection of common voltages without requiring external

components. Connect FB to AGND for a fixed 1.5V out-

Setting VTT Output Voltage

The VTT output stage is powered from the VTTI input.

The output voltage is set by the REFIN input. REFIN sets

the feedback regulation voltage (VTTR = VTTS =

put, to V

for a fixed 1.8V output, or connect FB

CC

V

) of the MAX17000A. Connect a 0.1V to 2.0V volt-

REFIN

directly to OUT for a fixed 1.0V output.

age input to set the adjustable output for VTT, VTTS, and

VTTR. If REFIN is tied to V , the internal CSL/2 divider

CC

Adjustable Output Voltage

is used to set VTT voltage; hence, VTT tracks the V

CSL

The output voltage can be adjusted from 1.0V to 2.7V

using a resistive voltage-divider (Figure 8). The

MAX17000A regulates FB to a fixed reference voltage

(1.0V). The adjusted output voltage is:

voltage and is set to V

/2. This feature makes the

CSL

MAX17000A ideal for memory applications in which the

termination supply must track the supply voltage.

VTT Output Capacitor Selection

A minimum value of 9μF is needed to stabilize a 300mA

VTT output. This value of capacitance limits the regula-

tor’s unity-gain bandwidth frequency to approximately

1.2MHz (typ) to allow adequate phase margin for stabil-

ity. To keep the capacitor acting as a capacitor within

the regulator’s bandwidth, it is important that ceramic

capacitors with low ESR and ESL be used.

⎛

⎝

⎞

⎠

R

FBA

V

= V × 1+

OUT

FB

⎜

⎟

R

FBB

where V is 1.0V.

FB

L1

V

OUT

LX

DL

N

L

C

OUT

D1

PGND1

CSH

CSL

MAX17000A

R

FBA

FB

FBB

Figure 8. Setting V

OUT

with a Resistive Voltage-Divider

Dual Mode is a trademark of Maxim Integrated Products, Inc.

28

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Since the gain bandwidth is also determined by the

PD(Total) = 2W

transconductance of the output FETs, which increases

with load current, the output capacitor might need to be

greater than 20μF if the load current exceeds 1.5A, but

can be smaller than 20μF if the maximum load current

is less than 1.5A. As a guideline, choose the minimum

capacitance and maximum ESR for the output capaci-

tor using the following:

The 2W total power dissipation is within the 24-pin

TQFN multilayer board power dissipation specification

of 2.22W. The typical application does not source or

sink continuous high currents. VTT current is typically

100mA to 200mA in the steady state. VTTR is down in

the microamp range, though the Intel specification

requires 3mA for DDR1 and 1mA for DDR2. True worst-

case power dissipation occurs on an output short-circuit

condition with worst-case current limit. The MAX17000A

does not employ any foldback current limiting, and

relies on the internal thermal shutdown for protection.

Both the VTT and VTTR output stages are powered from

the same VTTI input. Their output voltages are refer-

enced to the same REFIN input. The value of the VTTI

bypass capacitor is chosen to limit the amount of rip-

ple/noise at VTTI, or the amount of voltage dip during a

load transient. Typically, VTTI is connected to the output

of the buck regulator, which already has a large bulk

capacitor.

I

LOAD

C

= 20μF ×

OUT _MIN

1.5A

C

needs to be increased by a factor of 2 for

OUT_MIN

low-dropout operation:

1.5A

R

= 5mΩ ×

ESR_MAX

I

LOAD

R

value is measured at the unity-gain-band-

ESR_MAX

width frequency given by approximately:

I

36

LOAD

f

=

×

GBW

C

1.5A

OUT

Boost Capacitors

) must be selected large

The boost capacitors (C

BST

Once these conditions for stability are met, additional

capacitors, including those of electrolytic and tantalum

types, can be connected in parallel to the ceramic

capacitor (if desired) to further suppress noise or volt-

age ripple at the output.

enough to handle the gate-charging requirements of

the high-side MOSFETs. Typically, 0.1μF ceramic

capacitors work well for low-power applications driving

medium-sized MOSFETs. However, high-current appli-

cations driving large, high-side MOSFETs require boost

capacitors larger than 0.1μF. For these applications,

select the boost capacitors to avoid discharging the

capacitor more than 200mV while charging the high-

side MOSFETs’ gates:

VTTR Output Capacitor Selection

The VTTR buffer is a scaled-down version of the VTT

regulator, with much smaller output transconductance.

Its compensation capacitor can, therefore, be smaller

and its ESR larger than what is required for its larger

counterpart. For typical applications requiring load cur-

rent up to 4mA, a ceramic capacitor with a minimum

Q

GATE

C

=

BST

200mV

value of 0.33μF is recommended (R

Connect this capacitor between VTTR and the analog

ground plane.

< 0.3Ω).

ESR

where Q

is the total gate charge specified in the

GATE

high-side MOSFET’s data sheet. For example, assume

the FDS6612A n-channel MOSFET is used on the high

side. According to the manufacturer’s data sheet, a sin-

gle FDS6612A has a maximum gate charge of 13nC

Power Dissipation

Power loss in the MAX17000A is the sum of the losses

of the PWM block, the VTT LDO block, and the VTTR

reference buffer:

(V

= 5V). Using the above equation, the required

boost capacitance would be:

GS

PD(PWM) = I

× 5V = 40mA × 5V = 0.2W

BIAS

13nC

200mV

C

=

= 0.065μF

BST

PD(VTT) = 2A × 0.9V = 1.8W

Selecting the closest standard value, this example

requires a 0.1μF ceramic capacitor.

PD(VTTR) = 3mA × 0.9V = 2.7mW

Maxim Integrated

29

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Layout Procedure

1) Place the power components first, with ground ter-

minals adjacent (low-side MOSFET source, C

Applications Information

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

losses and clean, stable operation. The switching

power stage requires particular attention. If possible,

mount all the power components on the topside of the

board, with their ground terminals flush against one

another. Follow these guidelines for good PCB layout:

,

IN

C

, and anode of the low-side Schottky). If possi-

OUT

ble, make all these connections on the top layer

with wide, copper-filled areas.

2) Mount the controller IC adjacent to the low-side

MOSFET, preferably on the backside opposite the

MOSFETs to keep LX, GND, DH, and the DL gate-

drive lines short and wide. The DL and DH gate

traces must be short and wide (50 mils to 100 mils

wide if the MOSFET is 1in from the controller IC) to

keep the driver impedance low and for proper

adaptive dead-time sensing.

•

Keep the high-current paths short, especially at the

ground terminals. This practice is essential for sta-

ble, jitter-free operation.

•

Keep the power traces and load connections short.

This practice is essential for high efficiency. Using

thick copper PCBs (2oz vs. 1oz) can enhance full-

load efficiency by 1% or more. Correctly routing

PCB traces is a difficult task that must be

approached in terms of fractions of centimeters,

where a single milliohm of excess trace resistance

causes a measurable efficiency penalty.

3) Group the gate-drive components (BST diode and

capacitor, V

bypass capacitor) together near the

DD

controller IC.

4) Make the DC-DC controller ground connections as

shown in Figures 1 and 9. This diagram can be

viewed as having two separate ground planes:

power ground, where all the high-power compo-

nents go; and an analog ground plane for sensitive

analog components. The analog ground plane and

power ground plane must meet only at a single

point directly at the IC.

•

Minimize current-sensing errors by connecting CSH

and CSL directly across the current-sense resistor

(R

).

SENSE

When trade-offs in trace lengths must be made, it is

preferable to allow the inductor-charging path to be

made longer than the discharge path. For example,

it is better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-

side MOSFET or between the inductor and the out-

put filter capacitor.

5) Connect the output power planes directly to the out-

put filter capacitor positive and negative terminals

with multiple vias. Place the entire DC-to-DC con-

verter circuit as close as is practical to the load.

Table 5 lists the design differences between the

MAX17000 and MAX17000A.

•

Route high-speed switching nodes (BST, LX, DH,

and DL) away from sensitive analog areas (REFIN,

FB, CSH, and CSL).

Table 5. MAX17000 vs. MAX17000A Design Differences

MAX17000

MAX17000A

STDBY = Low turns off VTT and overrides the SKIP setting, forcing STDBY = Low only turns off VTT rail, and does not affect SMPS

the SMPS to enter a low-quiescent current ultra-skip mode. operation.

30

Maxim Integrated

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

KELVIN SENSE VIAS

UNDER THE INDUCTOR

(SEE EVALUATION KIT)

POWER STAGE LAYOUT (TOP SIDE OF PCB)

OUTPUT

INDUCTOR

L1

CSL

CSH

R

R2

R1

NTC

POWER

GROUND

C

EQ

KELVIN-SENSE VIAS TO

INDUCTOR PAD

INPUT

SMPS

INDUCTOR DCR SENSING

CONNECT AGND AND PGND1 TO

THE CONTROLLER AT THE

EXPOSED PAD

CONNECT THE

EXPOSED PAD TO

ANALOG GROUND

V

BYPASS

DD

CAPACITOR

VTTI BYPASS

CAPACITOR

VIA TO POWER GROUND

V

CC

BYPASS

CAPACITOR

VTT BYPASS

CAPACITOR

X-RAY VIEW.

IC MOUNTED

ON BOTTOM

SIDE OF PCB.

IC LAYOUT

Figure 9. PCB Layout Example

Package Information

Chip Information

For the latest package outline information and land patterns (foot-

prints), go to www.maximintegrated.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but the

drawing pertains to the package regardless of RoHS status.

TRANSISTOR COUNT: 7856

PROCESS: BiCMOS

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

24 TQFN

T2444-4

21-01±9

90-0022

Maxim Integrated

31

MAX17000A

Complete DDR2 and DDR3 Memory

Power-Management Solution

Revision History

REVISION

NUMBER

REVISION

DATE

PAGES

CHANGED

DESCRIPTION

0

1

2

3

10/08

12/08

11/10

4/13

Initial release

—

5, 11, 12, 13, 17, 23,

Modified STDBY pin function

Changed R

equation

29

2

ESR_MAX

Updated Absolute Maximum Ratings

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent

licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and

max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

32 ________________________________Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


型号：	MAX17000AETG+C00
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Power Supply Support Circuit, Adjustable, 2 Channel, BICMOS, TQFN-24 信息通信管理
文件：	总32页 (文件大小：750K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX17000AETG+C00 [MAXIM]

相关型号：

MAX17000AETG+CAJ

MAX17000AETG+TC00

MAX17000AETG+TCAJ

MAX17000AETG+TG40

MAX17000A_08

MAX17000A_10

MAX17000A_13

MAX17000ETG+

MAX17000ETG+G1D

MAX17000ETG+T

MAX17000ETG+TG1D

MAX17000_11