MAX17004ETJ+ [MAXIM]
High-Efficiency, Quad-Output, Main Power-Supply Controllers for Notebook Computers;
| 型号： | MAX17004ETJ+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Efficiency, Quad-Output, Main Power-Supply Controllers for Notebook Computers 信息通信管理 开关 |
| 文件： | 总36页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0765; Rev 0; 3/07
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
General Description
Features
The MAX17003/MAX17004 are dual step-down, switch-
mode, power-supply (SMPS) controllers with synchro-
nous rectification, intended for main 5V/3.3V power
generation in battery-powered systems. Fixed-frequen-
cy operation with optimal interleaving minimizes input
ripple current from the lowest input voltages up to the
26V maximum input. Optimal 40/60 interleaving allows
the input voltage to go down to 8.3V before duty-cycle
overlap occurs, compared to 180° out-of-phase regula-
tors where the duty-cycle overlap occurs when the
input drops below 10V.
o Fixed-Frequency, Current-Mode Control
o 40/60 Optimal Interleaving
o Internal BST Switches
o Internal 5V, 100mA Linear Regulator
o Auxiliary Linear-Regulator Driver (12V or
Adjustable Down to 1V)
o Dual Mode™ Feedback—3.3V/5V Fixed or
Adjustable Output Voltages
o 200kHz/300kHz/500kHz Switching Frequency
o Undervoltage and Thermal-Fault Protection
o Overvoltage-Fault Protection (MAX17003 Only)
o 6V to 26V Input Range
Output current sensing provides peak current-limit pro-
tection, using either an accurate sense resistor or using
lossless inductor DCR current sensing. A low-noise
mode maintains high light-load efficiency while keeping
the switching frequency out of the audible range.
o 2V 0.75ꢀ Reference Output
o Independent Enable Inputs and Power-Good
Outputs
An internal, fixed 5V, 100mA linear regulator powers up
the MAX17003/MAX17004 and their gate drivers, as well
as external keep-alive loads. When the main PWM regu-
lator is in regulation, an automatic bootstrap switch
bypasses the internal linear regulator, providing current
up to 200mA. An additional adjustable linear-regulator
driver with an external pnp transistor may be used with a
secondary winding to provide a 12V supply, or powered
directly from the main outputs to generate low-voltage
outputs as low as 1V.
o Soft-Start and Soft-Discharge (Voltage Ramp)
o 8µA (typ) Shutdown Current
Ordering Information
PIN-
PKG
PART
TEMP RANGE
PACKAGE
CODE
32 Thin QFN
(5mm x 5mm)
MAX17003ETJ+ -40°C to +85°C
T3255-4
T3255-4
Independent enable controls and power-good signals
allow flexible power sequencing. Voltage soft-start grad-
ually ramps up the output voltage and reduces inrush
current, while soft-discharge gradually decreases the
output voltage, preventing negative voltage dips. The
MAX17003/MAX17004 feature output undervoltage and
thermal-fault protection. The MAX17003 also includes
output overvoltage-fault protection.
32 Thin QFN
(5mm x 5mm)
MAX17004ETJ+ -40°C to +85°C
+Denotes lead-free package.
Pin Configuration
TOP VIEW
The MAX17003/MAX17004 are available in a 32-pin,
5mm x 5mm, thin QFN package. The exposed backside
pad improves thermal characteristics for demanding
linear keep-alive applications.
24 23 22 21 20 19 18 17
16
15
DH3 25
BST3 26
DH5
BST5
14 DSCHG5
27
28
29
30
31
32
DSCHG3
CSL3
CSH3
FB3
Applications
CSL5
CSH5
13
12
Main Power Supplies
MAX17003
MAX17004
2 to 4 Li+ Cell Battery-Powered Devices
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
11 FB5
10 SKIP
FBA
+
9
FSEL
OUTA
1
2
3
4
5
6
7
8
THIN QFN
5mm x 5mm
Dual Mode is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ABSOLUTE MAXIMUM RATINGS
BST3, BST5 LDO5.................................................-0.3V to +0.3V
LDO Short Circuit to GND ..........................................Momentary
REF Short Circuit to GND ...........................................Momentary
DRVA Current (Sinking) ......................................................30mA
OUTA Shunt Current ...........................................................30mA
IN, SHDN, DRVA, OUTA to GND............................-0.3V to +28V
LDO5, ON3, ON5, ONA to GND ..............................-0.3V to +6V
PGDALL, DSCHG3, DSCHG5 to GND.....................-0.3V to +6V
CSL3, CSH3, CSL5, CSH5 to GND ..........................-0.3V to +6V
REF, FB3, FB5, FBA to GND...................-0.3V to (V
SKIP, FSEL, ILIM to GND........................-0.3V to (V
DL3, DL5 to PGND..................................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
LDO5
LDO5
LDO5
Continuous Power Dissipation (T = +70°C)
A
Multilayer PCB
32-Pin, 5mm x 5mm TQFN
BST3, BST5 to PGND .............................................-0.3V to +34V
(derated 34.5mW/°C above +70°C) .........................2459mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
BST3 to LX3..............................................................-0.3V to +6V
DH3 to LX3 ..............................................-0.3V to (V
+ 0.3V)
BST3
BST5 to LX5..............................................................-0.3V to +6V
DH5 to LX5 ..............................................-0.3V to (V + 0.3V)
BST5
GND to PGND .......................................................-0.3V to +0.3V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
OUTA
IN
REF
LDO5
no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
3/MAX1704
PARAMETER
INPUT SUPPLIES (Note 1)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDO5 in regulation
IN = LDO5, V < 4.4V
5.4
4.5
26.0
5.5
V
V
Input Voltage Range
V
V
IN
IN
IN
CSL5
LDO5 switched over to CSL5, either
SMPS on
Operating Supply Current
I
20
36
µA
IN
V
= 6V to 26V, both SMPS off, includes
IN
V
V
Standby Supply Current
Shutdown Supply Current
I
65
8
120
20
µA
µA
IN
IN
IN(STBY)
I
SHDN
I
V
= 6V to 26V
IN
IN(SHDN)
Both SMPS on, FB3 = FB5 = LDO5,
SKIP = GND, V = 3.5V, V = 5.3V,
CSL3
CSL5
Quiescent Power Consumption
P
3.5
4.5
mW
Q
V
P
= 15V,
OUTA
+ P
+ P
+ P
IN
CSL3
CSL5 OUTA
MAIN SMPS CONTROLLERS
3.3V Output Voltage in Fixed
Mode
V
0 < V
= 6V to 26V, SKIP = FB3 = LDO5,
- V < 50mV (Note 2)
IN
V
V
3.265
4.94
3.315
5.015
2.010
2.010
3.365
5.09
V
V
OUT3
OUT5
CSH3
CSL3
V
0 < V
= 6V to 26V, SKIP = FB5 = LDO5,
IN
5V Output Voltage in Fixed Mode
- V
< 50mV (Note 2)
CSH5
CSL5
V
= 6V to 26V, FB3 or FB5
IN
1.980
1.990
2.040
2.030
duty factor = 20% to 80%
Feedback Voltage in Adjustable
Mode (Note 2)
V
V
FB_
V
= 6V to 26V, FB3 or FB5
IN
duty factor = 50%
2
_______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
OUTA
IN
REF
LDO5
no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Adjust Range
FB3, FB5 Dual-Mode Threshold
Feedback Input Leakage Current
Either SMPS
2.0
5.5
V
V
LOO5
- 1.0
V
LOO5
- 0.4
3.0
V
V
= V
= 2.1V
FB5
-0.1
+0.1
µA
FB3
Either SMPS, SKIP = LDO5,
0 < V - V < 50mV
DC Load Regulation
Line Regulation Error
-0.1
%
CSH_
CSL
Either SMPS, 6V < V < 26V
IN
0.03
200
300
500
99
%/V
FSEL = GND
FSEL = REF
FSEL = LDO5
(Note 1)
170
270
425
97.5
230
330
575
Operating Frequency (Note 1)
f
kHz
OSC
Maximum Duty Factor
Minimum On-Time
D
%
ns
MAX
t
100
40
ONMIN
%
SMPS3-to-SMPS5 Phase Shift
SMPS5 starts after SMPS3
144
Deg
CURRENT LIMIT
ILIM Adjustment Range
0.5
-1
V
V
REF
Current-Sense Input Leakage
Current
CSH3 = CSH5 = GND or LDO5
+1
µA
mV
mV
mV
%
Current-Limit Threshold (Fixed)
V
V
V
V
_ - V
CSH
_ - V
CSH
_, ILIM = LDO5
45
185
94
50
55
LIMIT
LIMIT
CSL
CSL
V
V
= 2.00V
= 1.00V
200
100
-60
215
106
-53
ILIM
ILIM
Current-Limit Threshold
(Adjustable)
_
V
V
_ - V
_ - V
_, SKIP = ILIM = LDO5
-67
CSH
CSL
CSL
Current-Limit Threshold
(Negative)
V
NEG
_, SKIP = LDO5, adjustable
CSH
-120
mode, percent of current limit
Current-Limit Threshold
(Zero Crossing)
V
CSH
ILIM = LDO5
_ - V _, SKIP = GND,
CSL
V
0
6
3
6
mV
mV
ZX
ILIM = LDO5
10
14
V
_ - V
_,
_,
CSH
CSL
With respect to
current-limit
Idle Mode™ Threshold
V
V
IDLE
SKIP = GND
20
5
%
mV
%
threshold (V
)
)
LIMIT
ILIM = LDO5
2.5
-1
7.5
+1
Idle Mode Threshold
(Low Audible-Noise Mode)
V
_ - V
CSH CSL
With respect to
current-limit
IDLE
SKIP = REF
10
threshold (V
LIMIT
ILIM Leakage Current
ILIM = GND or REF
µA
Idle Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
3
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
OUTA
IN
REF
LDO5
no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Measured from the rising edge of ON_ to
full scale
Soft-Start Ramp Time
Soft-Stop Ramp Time
t
2
4
ms
SSTART
Measured from the falling edge of ON_ to
full scale
t
ms
SSTOP
INTERNAL FIXED LINEAR REGULATORS
ON5 = GND, 6V < V < 26V,
IN
LDO5 Output Voltage
V
4.85
4.35
4.95
225
5.10
450
V
V
LDO5
0 < I
< 100mA
LDO5
LDO5 Undervoltage-Lockout Fault
Threshold
Rising edge, hysteresis = 1% (typ)
LDO5 Bootstrap Switch Threshold
LDO5 Bootstrap Switch Resistance
Short-Circuit Current
Rising edge of CSL5, hysteresis = 1% (typ)
4.55
1
4.70
5
V
Ω
LDO5 to CSL5, V
= 5V, I
= 50mA
CSL5
LDO5
LDO5 = GND, ON5 = GND
225
450
mA
Short-Circuit Current (Switched
over to CSL_)
LDO5 = GND, V
> 4.7V
200
0.5
425
mA
3/MAX1704
CSL5
AUXILIARY LINEAR REGULATOR
DRVA Voltage Range
V
26.0
0.4
V
DRVA
V
V
V
V
= 1.05V, V
= 5V
FBA
DRVA
DRVA Drive Current
mA
= 0.965V, V
= 5V
10
FBA
DRVA
FBA Regulation Threshold
FBA Load Regulation
OUTA Shunt Trip Level
FBA Leakage Current
V
= 5V, I = 1mA (sink)
DRVA
0.98
1.00
-1.2
26
1.02
-2.2
27
V
%
V
FBA
DRVA
= 5V, I
= 0.5mA to 5mA
DRA
DRVA
Rising edge
25
V
= 1.035V
0.1
+0.1
µA
FBA
Secondary Feedback Regulation
Threshold
V
- V
0
V
DRVA
OUTA
1/
DL5 Pulse Width
µs
3f
OSC
OUTA Leakage Current
REFERENCE (REF)
I
V
= V = 25V
OUTA
50
µA
OUTA
DRVA
Reference Voltage
V
LDO5 in regulation, I
= 0
1.985
-10
2.00
1.8
2.015
+10
V
mV
V
REF
REF
Reference Load-Regulation Error
REF Lockout Voltage
FAULT DETECTION
ΔV
REF
REF(UVLO)
I
= -5µA to +50µA
REF
V
Rising edge
Output Overvoltage Trip
Threshold (MAX17003 Only)
With respect to error-comparator
threshold
8
11
10
14
%
Output Overvoltage Fault
Propagation Delay (MAX17003 Only)
t
50mV overdrive
µs
OVP
4
_______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
IN
REF
LDO5
OUTA
no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Undervoltage Protection
Trip Threshold
With respect to error-comparator
threshold
65
70
10
75
%
Output Undevoltage Fault
Propagation Delay
t
50mV overdrive
µs
UVP
Output Undervoltage Protection
Blanking Time
From rising edge of ON_ with respect to
t
5000
-12
6144
-10
7000
-8
1/f
OSC
BLANK
f
SW
With respect to either SMPS error-
comparator threshold, hysteresis = 1% (typ)
PGDALL Lower Trip Threshold
PGDALL Propagation Delay
%
Falling edge, 50mV overdrive
Rising edge, 50mV overdrive
10
1
t
µs
PGDALL
PGDALL Output Low Voltage
PGDALL Leakage Current
Thermal-Shutdown Threshold
GATE DRIVERS
I
= 1mA
0.4
1
V
SINK
I
High state, PGDALL forced to 5.5V
Hysteresis = 15°C
µA
°C
PGDALL
t
+160
SHDN
DH_ Gate-Driver On-Resistance
R
BST_ – LX_ forced to 5V
DL_, high state
1.3
1.7
0.6
5
5
3
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
R
DL
DL_, low state
DH_ Gate-Driver Source/Sink
Current
DH_ forced to 2.5V, BST_ - LX_ forced to
5V
I
2
A
DH
DL_ Gate-Driver Source Current
DL_ Gate-Driver Sink Current
I
DL_ forced to 2.5V
DL_ forced to 2.5V
DH_low to DL_high
DL_low to DH_high
1.7
3.3
45
A
A
DL (SOURCE)
I
DL (SINK)
15
15
Dead Time
t
ns
DEAD
44
Internal BST_ Switch On-
Resistance
R
BST
I
= 10mA
_ = 26V
5
2
Ω
BST
BST_ Leakage Current
V
20
µA
BST
INPUTS AND OUTPUTS
Rising trip level
Falling trip level
1.1
0.96
2.4
1.6
1
2.2
SHDN Input Trip Level
V
V
1.04
High
Low
ONA Logic Input Voltage
Hysteresis = 600mV (typ)
0.8
0.8
2.1
SMPS off level/clear fault level
Delay start level
ON3, ON5 Input Voltage
V
1.9
2.4
5
SMPS on level
DSCHG_ On-Resistance
DSCHG_ Leakage Current
R
ON3 = ON5 = SH D N = 0; I
= 10mA
11
25
1
Ω
DSCHG_
DSCHG_
High state, DSCHG_ forced to 5.5V
µA
_______________________________________________________________________________________
5
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
IN
REF
LDO5
OUTA
no load, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
LDO5
- 0.4
High
Tri-Level Input Logic
Input Leakage Current
SKIP, FSEL
V
REF
1.65
2.35
0.5
+1
GND
SKIP, FSEL forced to GND or LDO5
SHDN forced to GND or 26V
-1
-1
µA
+1
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
OUTA
IN
REF
LDO5
no load, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
INPUT SUPPLIES (Note 1)
LDO5 in regulation
IN = LDO5, V < 4.4V
5.4
4.5
26.0
5.5
40
V
V
V
V
Input Voltage Range
V
V
3/MAX1704
IN
IN
IN
IN
IN
CSL5
Operating Supply Current
Standby Supply Current
Shutdown Supply Current
I
LDO5 switched over to CSL5, either SMPS on
μA
μA
μA
IN
IN(STBY)
V
= 6V to 26V, both SMPS off, includes
IN
I
120
20
I
SHDN
I
V
= 6V to 26V
IN
IN(SHDN)
Both SMPS on, FB3 = FB5 = LDO5; SKIP =
GND, V = 3.5V, V = 5.3V,
CSL3
CSL5
Quiescent Power Consumption
P
4.5
mW
Q
V
P
= 15V,
OUTA
IN
+ P
+ P
+ P
CSL3
CSL5 OUTA
MAIN SMPS CONTROLLERS
3.3V Output Voltage in Fixed
Mode
V
0 < V
= 6V to 26V, SKIP = FB3 = LDO5,
IN
V
V
3.255
4.925
3.375
5.105
V
V
OUT3
OUT5
- V
CSL3
< 50mV (Note 2)
CSH3
V
0 < V
= 6V to 26V, SKIP = FB5 = LDO5,
IN
5V Output Voltage in Fixed Mode
- V
CSL5
< 50mV (Note 2)
CSH5
Feedback Voltage in Adjustable
Mode
V
= 6V to 26V, FB3 or FB5
IN
V
FB_
1.974
2.0
2.046
5.5
V
V
V
duty factor = 20% to 80% (Note 2)
Output Voltage Adjust Range
Either SMPS
V
LDO5
0.4
-
FB3, FB5 Dual-Mode Threshold
3V
FSEL = GND
FSEL = REF
FSEL = LDO5
170
270
425
97
230
330
575
Operating Frequency (Note 1)
Maximum Duty Factor
f
kHz
%
OSC
D
MAX
6
_______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
OUTA
IN
REF
LDO5
no load, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
A
PARAMETER
CURRENT LIMIT
SYMBOL
CONDITIONS
MIN
MAX
UNITS
ILIM Adjustment Range
0.5
44
V
V
REF
Current-Limit Threshold (Fixed)
V
V
V
V
_ - V
_ - V
_, ILIM = LDO5
56
mV
LIMIT
CSH
CSL
V
V
= 2.00V
= 1.00V
185
93
215
107
Current-Limit Threshold
(Adjustable)
ILIM
ILIM
_
mV
LIMIT
CSH
CSL
INTERNAL FIXED LINEAR REGULATORS
ON5 = GND, 6V < V < 26V,
IN
LDO5 Output Voltage
V
LDO5
4.85
5.10
4.1
V
V
0 < I
< 100mA
LDO5
LDO5 Undervoltage-Lockout
Fault Threshold
Rising edge, hysteresis = 1% (typ)
3.7
LDO5 Bootstrap Switch
Short-Circuit Current
Rising edge of CSL5, hysteresis = 1% (typ)
LDO5 = GND, ON5 = GND
4.30
4.75
450
V
mA
Short-Circuit Current (Switched
over to CSL_)
LDO5 = GND, V
> 4.7V
200
0.5
mA
CSL5
AUXILIARY LINEAR REGULATOR
DRVA Voltage Range
V
26.0
0.4
V
DRVA
V
V
V
= 1.05V, V
DRVA
= 5V
FBA
DRVA Drive Current
mA
= 0.965V, V
= 5V
10
0.98
25
FBA
DRVA
FBA Regulation Threshold
OUTA Shunt Trip Level
REFERENCE (REF)
Reference Voltage
V
= 5V, I = 1mA (sink)
DRVA
1.02
27
V
V
FBA
DRVA
V
LDO5 in regulation, I
= 0
1.980
2.020
V
REF
REF
_______________________________________________________________________________________
7
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I
= I
= I
=
OUTA
IN
REF
LDO5
no load, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT DETECTION
Output Overvoltage Trip Threshold
(MAX17003 Only)
With respect to error-comparator threshold
With respect to error-comparator threshold
8
14
75
-8
%
%
%
V
Output Undervoltage Protection
65
-12
With respect to error-comparator threshold,
hysteresis = 1%
PGDALL Lower Trip Threshold
PGDALL Output Low Voltage
GATE DRIVERS
I
= 1mA
0.4
SINK
DH_ Gate-Driver On-Resistance
R
BST_ – LX_ forced to 5V
DL_, high state
5
5
3
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
INPUTS AND OUTPUTS
SHDN Input Trip Level
R
DL
DL_, low state
2.3
Rising trip level
Falling trip level
1.0
0.96
2.4
V
V
3/MAX1704
1.04
High
Low
ONA Logic Input Voltage
Hysteresis = 600mV (typ)
0.8
0.8
2.1
SMPS off level/clear fault level
Delay start level
ON3, ON5 Input Voltage
DSCHG_ On-Resistance
1.9
2.4
5
V
SMPS on level
R
ON3 = ON5 = SH D N = 0; I
= 10mA
High
25
1
Ω
DSCHG_
DSCHG_
V
LDO5
- 0.4
µA
Tri-Level Input Logic
SKIP, FSEL
REF
1.65
2.35
0.5
V
GND
Note 1: The MAX17003/MAX17004 cannot operate over all combinations of frequency, input voltage (V ), and output voltage. For
IN
large input-to-output differentials and high switching-frequency settings, the required on-time may be too short to maintain
the regulation specifications. Under these conditions, a lower operating frequency must be selected. The minimum on-time
must be greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are mea-
sured from 50% point to 50% point at the DH_ pin with LX_ = GND, V
= 5V, and a 250pF capacitor connected from
BST_
DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 2: When the inductor is in continuous conduction, the output voltage has a DC-regulation level lower than the error-comparator
threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regula-
tion level higher than the trip level by approximately 1% due to slope compensation.
Note 3: Specifications from -40°C to +85°C are guaranteed by design, not production tested.
8
_______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
Typical Operating Characteristics
(Circuit of Figure 1, V = 12V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
IN
A
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
5V OUTPUT VOLTAGE
vs. LOAD CURRENT
100
90
80
70
60
50
100
90
80
70
60
50
5.10
5.05
5.00
4.95
4.90
7V
SKIP MODE
SKIP MODE
LOW-NOISE MODE
12V
PWM MODE
PWM MODE
20V
LOW-NOISE
MODE
SKIP MODE
PWM MODE
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
0.0
1.0
2.0
3.0
4.0
5.0
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3.3V OUTPUT VOLTAGE
vs. LOAD CURRENT
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
100
90
80
70
60
50
100
90
80
70
60
50
3.39
3.36
3.33
3.30
3.27
3.24
SKIP MODE
7V
SKIP MODE
LOW-NOISE MODE
12V
20V
PWM MODE
PWM MODE
LOW-NOISE
MODE
SKIP MODE
PWM MODE
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
NO-LOAD INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
STANDBY AND SHUTDOWN INPUT CURRENT
vs. INPUT VOLTAGE
100
OUTPUT VOLTAGE DEVIATION
vs. INPUT VOLTAGE
100
10
1
3
2
STANDBY (ONx = GND)
PWM MODE
3.3V OUTPUT
5.0V OUTPUT
1
SHUTDOWN
(SHDN = GND)
10
0
-1
-2
-3
LOW-NOISE MODE
SKIP MODE
1
0
4
8
12
16
20
0
4
8
12
16
20
0
4
8
12
16
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
IN
A
3.3V SWITCHING FREQUENCY
vs. LOAD CURRENT
3.3V IDLE MODE CURRENT
vs. INPUT VOLTAGE
REFERENCE OFFSET VOLTAGE
DISTRIBUTION
3
2
1
0
1000
100
10
50
40
30
20
10
0
FORCED-PWM
+85°C
+25°C
SAMPLE SIZE = 125
SKIP MODE
SKIP = GND
LOW-NOISE SKIP
PULSE SKIPPING
LOW-NOISE MODE
SKIP = REF
1
0
4
8
12
16
20
0.001
0.01
0.1
1
10
-10
-6
-2
2
6
10
INPUT VOLTAGE (V)
LOAD CURRENT (A)
2V REF OFFSET VOLTAGE (mV)
3/MAX1704
LDO5 OUTPUT VOLTAGE
vs. LOAD CURRENT
OUTA OUTPUT VOLTAGE
vs. LOAD CURRENT
POWER-UP SEQUENCE
MAX17003/MAX17004 toc15
5.0
4.9
4.8
4.7
4.6
4.5
12.2
12.1
12.0
11.9
A
B
12V
0
0
C
0
5V
D
E
0
0
400μs/div
A. INPUT SUPPLY, 5V/div D. LDO5, 5V/div
0
20
40
60
80
100
0
50
100
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
B. REF, 1V/div
C. 5V OUTPUT (V
E. PGDALL, 5V/div
), 2V/div
OUT5
10 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
IN
A
SMPS DELAYED STARTUP SEQUENCE
SMPS DELAYED STARTUP SEQUENCE
(ON3 = REF)
(ON5 = REF)
SOFT-START WAVEFORM
MAX17003/MAX17004 toc17
MAX17003/MAX17004 toc16
MAX17003/MAX17004 toc18
3.3V
0
A
B
3.3V
0
A
A
5V
0
5V
0
B
C
D
E
B
0
0
0
0
2V
C
C
0
0
3.3V
0
3.3V
0
D
E
D
E
0
F
0
0
0
0
G
1ms/div
1ms/div
400μs/div
A. AUX LDO OUTPUT
(V ), 5V/div
A. ON5, 5V/div
B. 5V OUTPUT (V
C. PGOOD5, 5V/div
ON3 = REF
D. 3.3V OUTPUT (V
5V/div
E. PGOOD3, 5V/div
),
OUT3
A. ON3, 5V/div
B. 5V OUTPUT (V
C. PGOOD5, 5V/div
ON5 = REF
D. 3.3V OUTPUT (V ),
OUT3
D. PGDALL, 5V/div
ON3 = ON5, LDO5
), 2V/div E. REF, 2V/div
), 5V/div
OUT5
), 5V/div
5V/div
E. PGOOD3, 5V/div
OUT5
OUTA
B. 5V OUTPUT (V
OUT5
C. 3.3V OUTPUT (V
), 2V/div F. DL5, 5V/div
G. SHDN, 5V/div
OUT3
SMPS SHUTDOWN WAVEFORM
OUT5 LOAD TRANSIENT
OUT3 LOAD TRANSIENT
MAX17003/MAX17004 toc21
MAX17003/MAX17004 toc19
MAX17003/MAX17004 toc20
3A
5A
3.3V
5V
A
B
A
B
A
B
1A
5.1V
1A
3.35V
3.30V
3.25V
3.3V
5.0V
C
D
4.9V
5A
5V
3A
1A
0
0
C
D
1A
C
D
E
F
12V
0
0
5V
12V
0
0
20μs/div
= 1A TO 5A, 5A/div
4ms/div
20μs/div
= 1A TO 3A, 5A/div
A. I
B. V
C. INDUCTOR CURRENT,
5A/div
A. ON3, ON5, 5V/div
B. 5V OUTPUT (V
D. PGDALL, 5V/div
), 2V/div E. DL5, 5V/div
A. I
B. V
C. INDUCTOR CURRENT,
5A/div
OUT5
OUT3
, 50mV/div
, 50mV/div
OUT5
OUT5
OUT3
D. LX5, 10V/div
C. 3.3V OUTPUT (V
), 2V/div F. DL3, 5V/div
D. LX3, 10V/div
OUT3
______________________________________________________________________________________ 11
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, SKIP = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
IN
A
OUTPUT OVERVOLTAGE
OUTPUT UNDERVOLTAGE
FAULT PROTECTION (MAX17003 ONLY)
(SHORT-CIRCUIT) FAULT PROTECTION
SKIP TRANSITION
MAX17003/MAX17004 toc23
MAX17003/MAX17004 toc24
MAX17003/MAX17004 toc22
3.3V
5V
3.3V
A
B
0
3.3
A
B
A
3.35V
0
3.25V
0
B
5V
C
5V
2A
0
0
C
D
5V
5V
D
E
0
5V
0
5V
C
D
12V
0
0
0
40μs/div
100μs/div
4ms/div
A. SKIP, 5V/div
B. 3.3V OUTPUT (V
100mV/div
C. INDUCTOR CURRENT,
2A/div
D. LX3, 10V/div
A. 5V OUTPUT (V
B. 3.3V OUTPUT (V
C. DL3, 5V/div
), 2V/div D. DL5, 5V/div
), 2V/div E. PGDALL, 5V/div
A. 3.3V OUTPUT (V
B. 5V OUTPUT (V
), 2V/div C. PGDALL, 5V/div
), 2V/div D. DL3, 5V/div
OUT5
OUT3
OUT3
OUT5
),
OUT3
0.5A LOAD
R
= 5Ω
7
LOAD5
LDOA LOAD TRANSIENT
LD05 LOAD TRANSIENT
MAX17003/MAX17004 toc26
MAX17003/MAX17004 toc25
5V
0
A
B
5.00V
4.95V
A
B
15.0V
14.5V
100mA
0
12.0V
11.9V
C
20μs/div
A. LOAD FET GATE, 5V/div
B. AUX LDO INPUT, 0.5V/div
0 TO 150mA LOAD TRANSIENT
20μs/div
C. AUX LDO OUTPUT (V
0.1V/div
),
A. LDO5 OUTPUT, 50mV/div
B. LOAD CURRENT, 50mA/div
OUTA
12 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
Pin Description
PIN
NAME
FUNCTION
Auxiliary LDO Enable Input. When ONA is pulled low, OUTA is high impedance and the secondary feedback
control is disabled. When ONA is driven high, the controller enables the auxiliary LDO.
1
ONA
Auxiliary LDO Transistor Base Driver. Connect DRVA to the base of a pnp power transistor. Add a 680Ω
pullup resistor between the base and emitter.
2
3
DRVA
ILIM
Peak Current-Limit Threshold Adjustment. The current-limit threshold defaults to 50mV if ILIM is pulled up to
LDO5. In adjustable mode, the current-limit threshold across CSH_ and CSL_ is precisely 1/10th the voltage
seen at ILIM over a 0.5V to 2.0V range. The logic threshold for switchover to the 50mV default value is
approximately V
- 1V.
LDO5
Shutdown Control Input. The device enters its 8µA supply-current shutdown mode if V
is less than the
SHDN
SHDN input falling-edge trip level and does not restart until V
is greater than the SHDN input rising-
SHDN
4
SHDN
edge trip level. Connect SHDN to V for automatic startup. SHDN can be connected to V through a
IN
IN
resistive voltage-divider to implement a programmable undervoltage lockout.
3.3V SMPS Enable Input. Driving ON3 high enables the 3.3V SMPS, while pulling ON3 low disables the 3.3V
SMPS. If ON3 is connected to REF, the 3.3V SMPS starts after the 5V SMPS reaches regulation (delayed
start). Drive ON3 below the clear fault level to reset the fault latch.
5
6
ON3
ON5
5V SMPS Enable Input. Driving ON5 high enables the 5V SMPS, while pulling ON5 low disables the 5V
SMPS. If ON5 is connected to REF, the 5V SMPS starts after the 3.3V SMPS reaches regulation (delayed
start). Drive ON5 below the clear fault level to reset the fault latch.
2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater ceramic capacitor.
The reference sources up to 50µA for external loads. Loading REF degrades output-voltage accuracy
according to the REF load-regulation error. The reference shuts down when the system pulls SHDN low.
7
8
9
REF
GND
FSEL
Analog Ground. Connect the exposed backside pad to GND.
Frequency Select Input. This three-level logic input sets the controllers’ switching frequency. Connect to
LDO5, REF, or GND to select the following typical switching frequencies:
LDO5 = 500kHz, REF = 300kHz, GND = 200kHz.
Pulse-Skipping Control Input. Connect to LDO5 for low-noise, forced-PWM operation. Connect to REF for
automatic, low-noise, pulse-skipping operation at light loads. Connect to GND for automatic, high-efficiency,
pulse-skipping operation at light loads. Startup is always in the low-noise, pulse-skipping mode (i.e., same
as SKIP = REF setting), regardless of the SKIP setting. The SKIP setting takes effect once the respective
SMPS is in regulation.
10
SKIP
Feedback Input for the 5V SMPS. Connect to LDO5 for the preset 5V output. In adjustable mode, FB5
regulates to 2V.
11
12
FB5
Positive Current-Sense Input for the 5V SMPS. Connect to the positive terminal of the current-sense element.
Figure 7 describes two different current-sensing options—using accurate sense resistors or lossless inductor
DCR sensing.
CSH5
Output-Sense and Negative Current-Sense Input for the 5V SMPS. When using the internal preset 5V
feedback-divider (FB5 = LDO5), the controller uses CSL5 to sense the output voltage. Connect to the
negative terminal of the current-sense element. CSL5 also serves as the bootstrap input for LDO5. For the
MAX17003, place a Schottky diode from CSL5 to GND to prevent CSL5 from going below -7V.
13
14
CSL5
Open-Drain Discharge Input for the 5V SMPS. DSCHG5 is pulled low when ON5 is low, discharging the
SMPS5 output. DSCHG5 is also low under fault conditions.
Connect a resistor from DSCHG5 to the SMPS5 output. Limit the peak discharge current to less than 100mA:
DSCHG5
V
OUT5
R
DIS5
≥
−R
DSCHG5(MIN)
100mA
is 5Ω, taken from the Electrical Characteristics.
where R
DSCHG5(MIN)
______________________________________________________________________________________ 13
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Pin Description (continued)
PIN
15
NAME
BST5
DH5
FUNCTION
Boost Flying Capacitor Connection for the 5V SMPS. The MAX17003/MAX17004 include an internal boost
switch connected between LDO5 and BST5. Connect to an external capacitor as shown in Figure 1.
16
High-Side Gate-Driver Output for the 5V SMPS. DH5 swings from LX5 to BST5.
Inductor Connection for the 5V SMPS. Connect LX5 to the switched side of the inductor. LX5 serves as the
lower supply rail for the DH5 high-side gate driver.
17
LX5
18
19
DL5
Low-Side Gate-Driver Output for the 5V SMPS. DL5 swings from PGND to LDO5.
Power Ground
PGND
5V Internal Linear-Regulator Output. Bypass with 4.7µF minimum (1µF/25mA). Provides at least 100mA for
the DL_ low-side gate drivers, the DH_ high-side drivers through the BST switches, the PWM controller,
logic, reference, and external loads. If CSL5 is greater than 4.5V and soft-start is complete, the linear
regulator shuts down, and LDO5 connects to CSL5 through a 1Ω switch rated for loads up to 200mA.
20
LDO5
IN
Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to PGND with a 0.22µF or
greater ceramic capacitor close to the IC.
21
22
Open-Drain Power-Good Output for SMPS3 and SMPS5. PGDALL is pulled low if either SMPS3 or SMPS5
PGDALL output drops more than 10% (typ) below the normal regulation point, or if either ON3 or ON5 are low.
PGDALL becomes high impedance when both SMPS3 and SMPS5 are in regulation.
3/MAX1704
23
24
25
26
DL3
LX3
Low-Side Gate-Driver Output for the 3.3V SMPS. DL3 swings from PGND to LDO5.
Inductor Connection for the 3.3V SMPS. Connect LX3 to the switched side of the inductor. LX3 serves as the
lower supply rail for the DH3 high-side gate driver.
DH3
BST3
High-Side Gate-Driver Output for the 3.3V SMPS. DH3 swings from LX3 to BST3.
Boost Flying Capacitor Connection for the 3.3V SMPS. The MAX17003/MAX17004 include an internal boost
switch connected between LDO5 and BST3. Connect to an external capacitor as shown in Figure 1.
Open-Drain Discharge Output for the 3.3V SMPS. DSCHG3 is pulled low when ON3 is low, discharging the
SMPS3 output. DSCHG3 is also low under fault conditions.
Connect a resistor from DSCHG3 to the SMPS3 output. Limit the peak discharge current to less than 100mA:
27
28
DSCHG3
CSL3
V
OUT3
R
DIS3
≥
−R
DSCHG3(MIN)
100mA
is 5Ω, taken from the Electrical Characteristics.
where R
DSCHG3(MIN)
Output Sense and Negative Current Sense for the 3.3V SMPS. When using the internal preset 3.3V feedback
divider (FB3 = LDO5), the controller uses CSL3 to sense the output voltage. Connect to the negative
terminal of the current-sense element.
Positive Current-Sense Input for the 3.3V SMPS. Connect to the positive terminal of the current-sense
element. Figure 7 describes two different current-sensing options—using accurate sense resistors or
lossless inductor DCR sensing.
29
30
CSH3
FB3
Feedback Input for the 3.3V SMPS. Connect to LDO5 for fixed 3.3V output. In adjustable mode, FB3
regulates to 2V.
14 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
Pin Description (continued)
PIN
NAME
FUNCTION
Auxiliary LDO Feedback Input. Connect a resistive voltage-divider from OUTA to analog ground to adjust
the auxiliary linear-regulator output voltage. FBA regulates at 1V.
31
FBA
Adjustable Auxiliary Linear-Regulator Output. Bypass OUTA to GND with 1µF or greater capacitor
(1µF/25mA). When DRVA < OUTA, the secondary feedback control triggers the DL5 for 1µs forcing the
controller to recharge the auxiliary storage capacitor. When DRVA exceeds 25V, the MAX17003/MAX17004
enable a 10mA shunt on OUTA, preventing the storage capacitor from rising to unsafe levels due to the
transformer’s leakage inductance. Pulling ONA high enables the linear-regulator driver and the secondary
feedback control.
32
EP
OUTA
EP
Exposed Pad. Connect the exposed backside pad to analog ground.
Table 1. Component Selection for Standard Applications
300kHz
5V AT 5A
3.3V AT 5A
500kHz
5V AT 3A
3.3V AT 5A
COMPONENT
INPUT VOLTAGE
, Input Capacitor
V
= 7V TO 24V
V
= 7V TO 24V
IN
IN
(3) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(3) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
C
IN_
5V OUTPUT
, Output Capacitor
2x 100µF, 6V, 35mΩ
SANYO 6TPE100MAZB
2x 100µF, 6V, 35mΩ
SANYO 6TPE100MAZB
C
OUT5
6.8µH, 6.4A, 18mΩ (max) 1:2
Sumida 4749-T132
L5/T5 Inductor/Transformer
—
Fairchild Semiconductor
FDS6612A
International Rectifier
IRF7807V
Fairchild Semiconductor
FDS6612A
International Rectifier
IRF7807V
N
N
High-Side MOSFET
Low-Side MOSFET
H5
Fairchild Semiconductor
FDS6670S
International Rectifier
IRF7807VD1
Fairchild Semiconductor
FDS6670S
International Rectifier
IRF7807VD1
L5
3V OUTPUT
, Output Capacitor
2x 150µF, 4V, 35mΩ
SANYO 4TPE150MAZB
2x 100µF, 6V, 35mΩ
SANYO 6TPE100MAZB
C
OUT3
5.8µH, 8.6A, 16.2mΩ
Sumida CORH127/LD-5R8NC
3.9µH, 6.5A, 15mΩ
Sumida CDRH124-3R9NC
L3, Inductor
Fairchild Semiconductor
FDS6612A
International Rectifier
IRF7807V
Fairchild Semiconductor
FDS6612A
International Rectifier
IRF7807V
N
N
High-Side MOSFET
Low-Side MOSFET
H3
L3
Fairchild Semiconductor
FDS6670S
International Rectifier
IRF7807VD1
Fairchild Semiconductor
FDS6670S
International Rectifier
IRF7807VD1
______________________________________________________________________________________ 15
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
INPUT (V )
IN
C
IN
C
IN
21
IN
D1
SECONDARY
OUTPUT
N
N
H1
H2
25
26
16
15
DH3
DH5
C
AUX
4.7μF
T1
BST3
BST5
C
BST2
C
BST1
0.1μF
L1
0.1μF
24
23
17
18
5V PWM
OUTPUT
3.3V PWM
OUTPUT
LX3
DL3
LX5
DL5
C
OUT3
C
OUT5
D
R1
R3
10.5kΩ
L1
D
L2
N
L2
N
L1
6.96kΩ
19
8
PGND
GND
R4
R2
4.02kΩ
3.48kΩ
29
28
12
13
CSH3
CSL3
CSH5
CSL5
C1
0.22μF
C2
0.22μF
C3
1000pF
C4
1000pF
3
ILIM
FB5
3/MAX1704
REF
(300kHz)
9
7
11
30
20
FSEL
REF
FB3
C
REF
0.22μF
LDO5
5V LDO OUTPUT
C
LDO5
4.7μF
SECONDARY
OUTPUT
MAX17003
MAX17004
R10
680Ω
2
10
DRVA
SKIP
32
12V LDO
OUTPUT
OUTA
FBA
C
4.7μF
LDOA
R5
110kΩ
CONNECT
TO 5V OR 3.3V
31
R7
100kΩ
R6
10kΩ
22
27
14
PGDALL
DSCHG3
SMPS POWER-GOOD
3.3V PWM OUTPUT
5V PWM OUTPUT
R8
47Ω
4
5
6
1
SHDN
ON3
DSCHG5
ON OFF
R9
47Ω
ON5
ONA
POWER GROUND
ANALOG GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
Figure 1. Standard Application Circuit
16 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
The MAX17003/MAX17004 switch-mode power supplies
(SMPS) require a 5V bias supply in addition to the high-
power input supply (battery or AC adapter). This 5V bias
supply is generated by the controller’s internal 5V linear
regulator (LDO5). This bootstrapped LDO allows the
controller to power up independently. The gate-driver
input supply is connected to the fixed 5V linear-regulator
output (LDO5). Therefore, the 5V LDO supply must pro-
vide LDO5 (PWM controller) and the gate-drive power,
so the maximum supply current required is:
Table 2. Component Suppliers
SUPPLIER
WEBSITE
www.avx.com
Central Semiconductor www.centralsemi.com
AVX
Fairchild
International Rectifier
KEMET
www.fairchildsemi.com
www.irf.com
www.kemet.com
NEC/Tokin
Panasonic
Philips
www.nec-tokin.com
www.panasonic.com/industrial
www.philips.com
I
= I
+ f
(Q
+ Q
)
BIAS
CC
SW
G(LOW)
G(HIGH)
= 5mA to 50mA (typ)
where I
and Q
is 0.7mA (typ), f
is the switching frequency,
CC
SW
Pulse
www.pulseeng.com
www.renesas.com
www.edc.sanyo.com
www.sumida.com
and Q
are the MOSFET data
G(LOW)
G(HIGH)
Renesas
SANYO
sheet’s total gate-charge specification limits at V = 5V.
GS
SMPS to LDO Bootstrap Switchover
When the 5V main output voltage is above the LDO5
bootstrap-switchover threshold and has completed
soft-start, an internal 1Ω (typ) p-channel MOSFET
shorts CSL5 to LDO5, while simultaneously shutting
down the LDO5 linear regulator. This bootstraps the
device, powering the internal circuitry and external
loads from the 5V SMPS output (CSL5), rather than
through the linear regulator from the battery. Boot-
strapping reduces power dissipation due to gate
charge and quiescent losses by providing power from
a 90%-efficient switch-mode source, rather than from a
much-less-efficient linear regulator. The current capa-
bility increases from 100mA to 200mA when the LDO5
output is switched over to CSL5. When ON5 is pulled
low, the controller immediately disables the bootstrap
switch and reenables the 5V LDO.
Sumida
Taiyo Yuden
TDK
www.t-yuden.com
www.component.tdk.com
www.tokoam.com
TOKO
Vishay (Dale, Siliconix) www.vishay.com
Detailed Description
The MAX17003/MAX17004 standard application circuit
(Figure 1) generates the 5V/5A and 3.3V/5A typical of the
main supplies in a notebook computer. The input supply
range is 7V to 24V. See Table 1 for component selec-
tions, while Table 2 lists the component manufacturers.
The MAX17003/MAX17004 contain two interleaved,
fixed-frequency, step-down controllers designed for low-
voltage power supplies. The optimal interleaved archi-
tecture guarantees out-of-phase operation, reducing the
input capacitor ripple. One internal LDO generates the
keep-alive 5V power. The MAX17003/MAX17004 have
an auxiliary LDO with an adjustable output for generating
either the 3.3V keep-alive supply or regulating the low-
power 12V system supply.
Reference (REF)
The 2V reference is accurate to 1% over temperature
and load, making REF useful as a precision system re-
ference. Bypass REF to GND with a 0.1µF or greater
ceramic capacitor. The reference sources up to 50µA
and sinks 5µA to support external loads. If highly accu-
rate specifications are required for the main SMPS out-
put voltages, the reference should not be loaded.
Loading the reference reduces the LDO5, CSL5
(OUT5), CSL3 (OUT3), and OUTA output voltages
slightly because of the reference load-regulation error.
Fixed 5V Linear Regulator (LDO5)
An internal linear regulator produces a preset 5V low-
current output. LDO5 powers the gate drivers for the
external MOSFETs, and provides the bias supply
required for the SMPS analog controller, reference, and
logic blocks. LDO5 supplies at least 100mA for exter-
nal and internal loads, including the MOSFET gate
drive, which typically varies from 5mA to 50mA,
depending on the switching frequency and external
MOSFETs selected. Bypass LDO5 with a 4.7µF or
greater ceramic capacitor (1µF per 25mA of load) to
guarantee stability under the full-load conditions.
System Enable/Shutdown (SHDN)
Drive SHDN below the precise SHDN input falling-edge
trip level to place the MAX17003/MAX17004 in its low-
power shutdown state. The controller consumes only
8µA of quiescent current while in shutdown mode.
When shutdown mode activates, the reference turns off
after the controller completes the shutdown sequence
______________________________________________________________________________________ 17
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
IN
SHDN
LDO5
5V LINEAR
REGULATOR
OSC
FSEL
LDO BYPASS
CIRCUITRY
ILIM
SKIP
CSH5
CSL5
CSH3
CSL3
LDO5
PWM5
CONTROLLER
(FIGURE 3)
BST5
DH5
LX5
BST3
DH3
LX3
PWM3
CONTROLLER
(FIGURE 3)
3/MAX1704
LDO5
DL5
LDO5
DL3
PGND
ON5
FB5
FB
FB
DECODE
(FIGURE 5)
DECODE
(FIGURE 5)
INTERNAL
FB
FB3
ON3
REF
DSCHG5
DSCHG3
PGDALL
2.0V
REF
GND
R
R
POWER-GOOD AND FAULT
PROTECTION
(FIGURE 6)
DRVA
OUTA
FBA
AUXILIARY
LINEAR REGULATOR
ONA
MAX17003
MAX17004
Figure 2. Functional Diagram
18 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
Table 3. Operating Mode Truth Table
INPUTS*
ON5
X
OUTPUTS
5V SMPS
MODE
SHDN
Low
ON3
X
LDO5
3V SMPS
Shutdown Mode
Standby Mode
OFF
ON
ON
ON
OFF
OFF
High
High
High
Low
Low
High
High
OFF, DSCHG5 LOW
ON
OFF, DSCHG3 LOW
Normal Operation
3.3V SMPS Active
High
Low
ON
ON
OFF, DSCHG5 LOW
OFF
LDO5 to CSL5 bypass
switch enabled
5V SMPS Active
High
High
High
High
Ref
Low
High
Ref
ON
OFF, DSCHG3 LOW
ON
Normal Operation
(Delayed 5V SMPS
Startup)
OFF
ON
LDO5 to CSL5 bypass Power-up after 3.3V
switch enabled
SMPS is in regulation
Normal Operation
(Delayed 3.3V SMPS
Startup)
OFF
ON
LDO5 to CSL5 bypass
switch enabled
Power-up after 5V
SMPS is in regulation
High
ON
*SHDN is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3
and ON5 are tri-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the mid-
dle-logic level is between 1.7V and 2.3V (see the Electrical Characteristics table).
making the threshold to exit shutdown less accurate. To
guarantee startup, drive SHDN above 2V (SHDN input
rising-edge trip level). For automatic shutdown and
The internal soft-start gradually increases the feedback
voltage with a 1V/ms slew rate. Therefore, the outputs
reach their nominal regulation voltage 2ms after the
SMPS controllers are enabled (see the Soft-Start
Waveform in the Typical Operating Characteristics).
This gradual slew rate effectively reduces the input
surge current by minimizing the current required to
startup, connect SHDN to V . The accurate 1V falling-
IN
edge threshold on SHDN can be used to detect a spe-
cific input voltage level and shut the device down. Once
in shutdown, the 1.6V rising-edge threshold activates,
providing sufficient hysteresis for most applications.
charge the output capacitors (I
= I
+ C
x
OUT
OUT
LOAD
V
/t
).
OUT(NOM) SLEW
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when LDO5 rises above
approximately 1V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled
high until the SMPS controllers are activated. Figure 2
is the MAX17003/MAX17004 block diagram.
SMPS Enable Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs. Driving ON_ below 0.8V clears the
overvoltage, undervoltage, and thermal fault latches.
The LDO5 input undervoltage-lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (LDO5) is below
its 4V UVLO threshold. Once the 5V bias supply
(LDO5) rises above this input UVLO threshold and the
SMPS controllers are enabled (ON_ driven high), the
SMPS controllers start switching, and the output volt-
ages begin to ramp up using soft-start. If the LDO5
voltage drops below the UVLO threshold, the controller
stops switching and pulls the low-side gate drivers low
until the LDO5 voltage recovers or drops below the
POR threshold.
SMPS Power-Up Sequencing
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation
and starts after that output regulates. The second
SMPS remains on until the first SMPS turns off, the
device shuts down, a fault occurs, or LDO5 goes into
UVLO. Both supplies begin their power-down
sequence immediately when the first supply turns off.
______________________________________________________________________________________ 19
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Output Discharge (Soft-Discharge)
When the switching regulators are disabled—when ON_
or SHDN is pulled low, or when an output undervoltage
fault occurs—the internal soft-discharge gradually
decreases the output voltage by pulling DSCHG_ low
(see the SMPS Shutdown Waveform in the Typical
Operating Characteristics). This slowly discharges the
output capacitance, eliminating the negative output volt-
ages caused by quickly discharging the output through
the inductor and low-side MOSFET. Both SMPS con-
trollers contain separate soft-shutdown circuits.
Fixed-Frequency, Current-Mode
PWM Controller
The heart of each current-mode PWM controller is a
multi-input, open-loop comparator that sums two sig-
nals: the output-voltage error signal with respect to the
reference voltage and the slope-compensation ramp
(Figure 3). The MAX17003/MAX17004 use a direct-
summing configuration, approaching ideal cycle-to-
cycle control over the output voltage without a
traditional error amplifier and the phase shift associated
with it.
FROM FB
(SEE FIGURE 5)
REF
ON_
FSEL
SOFT-
START/STOP
SLOPE COMP
SKIP
OSC
GND
3/MAX1704
TRI-LEVEL
DECODE
R
S
DH DRIVER
Q
0.2 x V
LIMIT
0.1 x V
LIMIT
IDLE MODE
CURRENT
PEAK CURRENT
LIMIT
A = 1/10
ILIM
A = 1.2
NEG CURRENT
LIMIT
S
Q
R
CSH_
CSL_
DL DRIVER
ZERO
CROSSING
PGND
DRVA
OUTA
ONE-SHOT
5V SMPS ONLY
Figure 3. PWM Controller Functional Diagram
20 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
Idle Mode Current-Sense Threshold
Table 4. FSEL Configuration Table
When pulse-skipping mode is enabled, the on-time of the
FSEL
LDO5
REF
SWITCHING FREQUENCY (kHz)
step-down controller terminates when the output voltage
exceeds the feedback threshold and when the current-
sense voltage exceeds the idle-mode current-sense
threshold. Under light-load conditions, the on-time dura-
tion depends solely on the idle mode current-sense
threshold, which is 20% (SKIP = GND) of the full-load
current-limit threshold set by ILIM, or the low-noise cur-
rent-sense threshold, which is 10% (SKIP = REF) of the
full-load current-limit threshold set by ILIM. This forces
the controller to source a minimum amount of power with
each cycle. To avoid overcharging the output, another
on-time cannot begin until the output voltage drops
below the feedback threshold. Since the zero-crossing
comparator prevents the switching regulator from sinking
current, the controller must skip pulses. Therefore, the
controller regulates the valley of the output ripple under
light-load conditions.
500
300
200
GND
Frequency Selection (FSEL)
The FSEL input selects the PWM mode switching fre-
quency. Table 4 shows the switching frequency based
on FSEL connection. High-frequency (500kHz) operation
optimizes the application for the smallest component
size, trading off efficiency due to higher switching losses.
This may be acceptable in ultraportable devices where
the load currents are lower. Low-frequency (200kHz)
operation offers the best overall efficiency at the expense
of component size and board space.
Forced-PWM Mode
The low-noise forced-PWM mode (SKIP = LDO5) dis-
ables the zero-crossing comparator, which controls the
low-side switch on-time. This forces the low-side gate-
drive waveform to be constantly the complement of the
high-side gate-drive waveform, so the inductor current
reverses at light loads while DH_ maintains a duty factor
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads (Figure 4). This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The zero-crossing comparator senses the inductor cur-
of V /V . The benefit of forced-PWM mode is to keep
OUT IN
rent across CSH_ to CSL_. Once (V
_ - V
_)
CSL
the switching frequency fairly constant. However, forced-
PWM operation comes at a cost: the no-load 5V supply
current remains between 20mA to 50mA, depending on
the external MOSFETs and switching frequency.
CSH
drops below the 3mV zero-crossing, current-sense
threshold, the comparator forces DL_ low (Figure 3).
This mechanism causes the threshold between pulse-
skipping PFM and nonskipping PWM operation to coin-
cide with the boundary between continuous and
Forced-PWM mode is most useful for avoiding audio-
frequency noise and improving load-transient
response. Since forced-PWM operation disables the
zero-crossing comparator, the inductor current revers-
es under light loads.
Light-Load Operation Control (SKIP)
The MAX17003/MAX17004 include a light-load operat-
ing mode control input (SKIP) used to enable or dis-
able the zero-crossing comparator for both switching
regulators. When the zero-crossing comparator is
enabled, the regulator forces DL_ low when the cur-
rent-sense inputs detect zero inductor current. This
keeps the inductor from discharging the output capaci-
tors and forces the regulator to skip pulses under light-
load conditions to avoid overcharging the output. When
the zero-crossing comparator is disabled, the regulator
is forced to maintain PWM operation under light-load
conditions (forced-PWM).
V
OUT
t
=
ON(SKIP)
V f
IN OSC
I
I
PK
= I /2
LOAD PK
0
TIME
ON-TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
______________________________________________________________________________________ 21
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
discontinuous inductor-current operation (also known
TO ERROR
AMPLIFIER
as the “critical conduction” point). The load-current
level at which PFM/PWM crossover occurs, I
is given by:
,
LOAD(SKIP)
ADJUSTABLE
OUTPUT
FB
(V −V
)V
L
IN
OUT OUT
I
=
LDO5
LOAD(SKIP)
2V f
IN OSC
R
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output-voltage
ripple. Drawbacks of using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
9R
FIXED OUTPUT
FB = LDO5
OUT
Figure 5. Dual Mode Feedback Decoder
Connect FB3 and FB5 to LDO5 to enable the fixed
SMPS output voltages (3.3V and 5V, respectively), set
by a preset, internal resistive voltage-divider connected
between the output (CSL_) and analog ground.
Connect a resistive voltage-divider at FB_ between the
output (CSL_) and GND to adjust the respective output
3/MAX1704
Output Voltage
DC output accuracy specifications in the Electrical
Characteristics table refer to the error comparator’s
threshold. When the inductor continuously conducts,
the MAX17003/MAX17004 regulate the peak of the out-
put ripple, so the actual DC output voltage is lower than
the slope-compensated trip level by 50% of the output
ripple voltage. For PWM operation (continuous conduc-
tion), the output voltage is accurately defined by the fol-
lowing equation:
voltage between 2V and 5.5V (Figure 5). Choose R
FBLO
(resistance from FB to GND) to be approximately 10kΩ
and solve for R
(resistance from the output to FB)
FBHI
using the equation:
⎛
⎞
V
OUT_
R
= R
FBLO
−1
⎟
⎛
⎞
A
V
V
FBHI
⎛
⎞
⎜
SLOPE RIPPLE
RIPPLE
2
V
V
= V
1−
−
⎝
⎠
FB_
⎜
⎝
⎟
⎠
OUT(PWM)
NOM
⎜
⎟
V
⎝
⎠
IN
where V
= 2V nominal.
FB_
where V
is the nominal output voltage, A
SLOPE
NOM
When adjusting both output voltages, set the 3.3V
SMPS lower than the 5V SMPS. LDO5 connects to the
5V output (CSL5) through an internal switch only when
CSL5 is above the LDO5 bootstrap threshold (4.5V)
and the soft-start sequence for the CSL5 side has com-
pleted. Bootstrapping works most effectively when the
fixed output voltages are used. Once LDO5 is boot-
strapped from CSL5, the internal 5V linear regulator
turns off. This reduces the internal power dissipation
and improves efficiency at higher input voltages.
equals 1%, and V
is the output ripple voltage
RIPPLE
(V
= ESR x ΔI
, as described in the
RIPPLE
INDUCTOR
Output Capacitor Selection section).
In discontinuous conduction (I
< I
), the
LOAD(SKIP)
OUT
MAX17003/MAX17004 regulate the valley of the output
ripple, so the output voltage has a DC regulation level
higher than the error-comparator threshold. For PFM
operation (discontinuous conduction), the output volt-
age is approximately defined by the following equation:
⎛
⎜
⎞
1
2 f
f
SW
V
= V
+
I
ESR
Current-Limit Protection (ILIM)
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor cur-
rent. If the magnitude of the current-sense signal
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). The actual
OUT(PFM)
NOM
IDLE
⎟
⎝
⎠
OSC
where V
is the nominal output voltage, f
is the
NOM
OSC
maximum switching frequency set by the internal oscil-
lator, f is the actual switching frequency, and I is
SW
IDLE
the idle mode inductor current when pulse skipping.
22 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
maximum load current is less than the peak current-
limit threshold by an amount equal to half of the induc-
tor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
interprets the MOSFET gates as “off” while charge actu-
ally remains. Use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps prevent
DL_ from being pulled up due to capacitive coupling from
the drain to the gate of the low-side MOSFETs when the
(V
/V ).
OUT IN
In forced-PWM mode, the MAX17003/MAX17004 also
implement a negative current limit to prevent excessive
inductor node (LX_) quickly switches from ground to V .
IN
reverse inductor currents when V
is sinking current.
Applications with high input voltages and long inductive
driver traces may require additional gate-to-source
capacitance to ensure fast-rising LX_ edges do not pull
up the low-side MOSFETs gate, causing shoot-through
currents. The capacitive coupling between LX_ and DL_
created by the MOSFET’s gate-to-drain capacitance
OUT
The negative current-limit threshold is set to approxi-
mately 120% of the positive current limit and tracks the
positive current limit when ILIM is adjusted.
Connect ILIM to LDO5 for the 50mV default threshold,
or adjust the current-limit threshold with an external
resistor-divider at ILIM. Use a 2µA to 20µA divider cur-
rent for accuracy and noise immunity. The current-limit
threshold adjustment range is from 50mV to 200mV. In
the adjustable mode, the current-limit threshold voltage
equals precisely 1/10th the voltage seen at ILIM. The
logic threshold for switchover to the default value is
(C
= C
GD
), gate-to-source capacitance (C
= C
GD
RSS
GS ISS
- C ), and additional board parasitics should not
exceed the following minimum threshold:
⎛
⎞
C
C
RSS
V
>V
GS(TH) IN
⎜
⎟
⎝
⎠
ISS
approximately V
- 1V.
LDO5
Lot-to-lot variation of the threshold voltage may cause
problems in marginal designs.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the differential
current-sense signals seen by CSH_ and CSL_. Place
the IC close to the sense resistor with short, direct
traces, making a Kelvin-sense connection to the cur-
rent-sense resistor.
Power-Good Output (PGDALL)
PGDALL is the open-drain output of a comparator that
continuously monitors both SMPS output voltages for
undervoltage conditions. PGDALL is actively held low
in shutdown (SHDN = GND), during soft-start, and soft-
shutdown, and when either SMPS is disabled (either
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
FAULT
seen in notebook applications, where a large V
OUT
-
IN
POWER-GOOD
0.9 x INT REF_
PROTECTION
V
differential exists. The high-side gate drivers
0.7 x INT REF_ 1.11 x INT REF_
(DH_) source and sink 2A, and the low-side gate dri-
vers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
charge pumps at BST_ while the DL_ synchronous-rec-
tifier drivers are powered directly by the fixed 5V linear
regulator (LDO5).
INTERNAL FB
ENABLE OVP
ENABLE UVP
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead-time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; other-
wise, the sense circuitry in the MAX17003/MAX17004
6144
CLK
FAULT
LATCH
FAULT
POWER-GOOD
POR
Figure 6. Power-Good and Fault Protection
______________________________________________________________________________________ 23
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Table 5. Operating Modes Truth Table
MODE
CONDITION
COMMENT
Transitions to discharge mode after V POR and after REF
IN
becomes valid. LDO5, REF remain active. DL_ is low.
Power-Up
LDO5 < UVLO threshold
Run
SHDN = high, ON3 or ON5 enabled
Either output > 111% of nominal level
Normal operation.
Output Overvoltage
(OVP) Protection
(MAX17003)
Exited by POR or cycling SHDN, ON3, or ON5.
Exited by POR or cycling SHDN, ON3, or ON5.
Either output < 70% of nominal level,
UVP is enabled 6144 clock cycles
Output Undervoltage
Protection (UVP)
(1/f
) after the output is enabled
OSC
ON5 and ON3 < startup threshold,
SHDN = high
Standby
DL_ stays low. LDO5 active.
All circuitry off.
Shutdown
SHDN = low
Exited by POR or cycling SHDN, ON3, or ON5.
DL3 and DL5 go low before LDO5 turns off.
Thermal Shutdown
T > +160°C
J
3/MAX1704
Excessive current on LDO5 switchover
transistors
Switchover Fault
Exited by POR or cycling SHDN, ON3, or ON5.
ON3 or ON5 low). Once the soft-start sequence termi-
nates, PGDALL becomes high impedance as long as
both SMPS outputs are above 90% of the nominal regu-
lation voltage set by FB. PGDALL goes low once either
SMPS output drops 10% below its nominal regulation
point, an SMPS output overvoltage fault occurs, or ON_
or SHDN is low. For a logic-level PGDALL output volt-
age, connect an external pullup resistor between
PGDALL and LDO5. A 100kΩ pullup resistor works well
in most applications.
overvoltage persists (such as a shorted high-side MOS-
FET), the battery blows. The other output is shut down
using the soft-discharge feature with DL_ forced low.
Cycle LDO5 below 1V or toggle either ON3, ON5, or
SHDN to clear the fault latch and restart the SMPS con-
trollers.
Output Undervoltage Protection (UVP)
Each SMPS controller includes an output UVP protection
circuit that begins to monitor the output 6144 clock
cycles (1/f ) after that output is enabled (ON_ pulled
OSC
Fault Protection
Output Overvoltage Protection (OVP)—
MAX17003 Only
high). If either SMPS output voltage drops below 70% of
its nominal regulation voltage and the UVP protection is
enabled, the UVP circuit sets the fault latch, pulls
PGDALL low, and shuts down both controllers using the
soft-discharge feature with DL_ forced low. Cycle LDO5
below 1V or toggle either ON3, ON5, or SHDN to clear
the fault latch and restart the SMPS controllers.
If the output voltage of either SMPS rises above 111% of
its nominal regulation voltage and the OVP protection is
enabled, the controller sets the fault latch, pulls
PGDALL low, shuts down the SMPS controllers that
tripped the fault, and immediately pulls DH_ low and
forces DL_ high. This turns on the synchronous-rectifier
MOSFETs with 100% duty, rapidly discharging the out-
put capacitors and clamping both outputs to ground.
However, immediately latching DL_ high typically caus-
es slightly negative output voltages due to the energy
stored in the output LC at the instant the OVP occurs. If
the load cannot tolerate a negative voltage, place a
power Schottky diode across the output to act as a
reverse-polarity clamp. If the condition that caused the
Thermal-Fault Protection
The MAX17003/MAX17004 feature a thermal fault-pro-
tection circuit. When the junction temperature rises
above +160°C, a thermal sensor activates the fault
latch, pulls PGDALL low, and shuts down both SMPS
controllers using the soft-discharge feature with DL_
forced low. Toggle either ON3, ON5, or SHDN to clear
the fault latch and restart the controllers after the junc-
tion temperature cools by 15°C.
24 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
•
Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are
Auxiliary LDO Detailed Description
The MAX17003/MAX17004 include an auxiliary linear
regulator (OUTA) that can be configured for 12V, ideal for
PCMCIA power requirements, and for biasing the gates
of load switches in a portable device. OUTA can also be
configured for outputs from 1V to 23V. The auxiliary regu-
lator has an independent ON/OFF control, allowing it to
be shut down when not needed, reducing power con-
sumption when the system is in a low-power state.
proportional to frequency and V 2. The optimum fre-
IN
quency is also a moving target, due to rapid improve-
ments in MOSFET technology that are making higher
frequencies more practical.
•
Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher out-
put ripple due to increased ripple currents. The mini-
mum practical inductor value is one that causes the
circuit to operate at the edge of critical conduction
(where the inductor current just touches zero with
every cycle at maximum load). Inductor values lower
than this grant no further size-reduction benefit. The
optimum operating point is usually found between
20% and 50% ripple current. When pulse skipping
(SKIP low and light loads), the inductor value also
determines the load-current value at which
PFM/PWM switchover occurs.
A flyback-winding control loop regulates a secondary
winding output, improving cross-regulation when the pri-
mary output is lightly loaded or when there is a low input-
output differential voltage. If V
< V
, the
OUTA
DRVA
low-side switch is turned on for a time equal to 33% of
the switching period. This reverses the inductor (primary)
current, pulling current from the output filter capacitor
and causing the flyback transformer to operate in for-
ward mode. The low impedance presented by the trans-
former secondary in forward mode dumps current into
the secondary output, charging up the secondary
capacitor and bringing V
- V
back into regula-
INA
OUTA
tion. The secondary feedback loop does not improve
secondary output accuracy in normal flyback mode,
where the main (primary) output is heavily loaded. In this
condition, secondary output accuracy is determined by
the secondary rectifier drop, transformer turns ratio, and
accuracy of the main output voltage.
Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
SMPS Design Procedure
V
V
− V
(
)
OUT IN
OUT
L =
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
V f
I
LIR
IN OSCLOAD(MAX)
For example: I
= 5A, V = 12V, V
= 5V,
OUT
LOAD(MAX)
= 300kHz, 30% ripple current or LIR = 0.3:
IN
f
OSC
5V x 12V − 5V
12V x 300kHz x 5A x 0.3
(
)
•
Input Voltage Range. The maximum value
(V ) must accommodate the worst-case, high
L =
= 6.50μH
IN(MAX)
AC-adapter voltage. The minimum value (V
)
IN(MIN)
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Most induc-
tor manufacturers provide inductors in standard values,
such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also look for
non-standard values, which can provide a better compro-
mise in LIR across the input voltage range. If using a
swinging inductor (where the no-load inductance
decreases linearly with increasing current), evaluate the
LIR with properly scaled inductance values. For the
selected inductance value, the actual peak-to-peak
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
•
Maximum Load Current. There are two values to
consider. The peak load current (I
)
LOAD(MAX)
determines the instantaneous component stresses
and filtering requirements and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
inductor ripple current (ΔI
) is defined by:
INDUCTOR
ous load current (I
) determines the thermal
LOAD
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components.
V
(V − V
)
OUT IN
OUT
ΔI
=
INDUCTOR
V f
L
IN OSC
______________________________________________________________________________________ 25
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Ferrite cores are often the best choice, although pow-
dered iron is inexpensive and can work well at 200kHz.
The core must be large enough not to saturate at the
instead of ground in order to reduce the necessary turns
ratio. In this case, subtract V from the secondary
OUT5
voltage (V
- V
) in the transformer turns-ratio
SEC
OUT5
peak inductor current (I
):
equation above. The secondary diode in coupled-induc-
tor applications must withstand flyback voltages greater
than 60V. Common silicon rectifiers, such as the 1N4001,
are also prohibited because they are too slow. Fast sili-
con rectifiers such as the MURS120 are the only choice.
The flyback voltage across the rectifier is related to the
PEAK
ΔI
INDUCTOR
I
= I
+
PEAK LOAD(MAX)
2
Transformer Design (for
V
- V
difference, according to the transformer
OUT5
IN
MAX17003/MAX17004 Auxiliary Output)
A coupled inductor or transformer can be substituted
for the inductor in the 5V SMPS to create an auxiliary
output (Figure 1). The MAX17003/MAX17004 is particu-
larly well suited for such applications because the sec-
ondary feedback threshold automatically triggers DL5
even if the 5V output is lightly loaded.
turns ratio:
V
= V
+ (V – V
) x N
OUT5
FLYBACK
SEC
IN
where N is the transformer turns ratio (secondary wind-
ings/primary windings), and V is the maximum sec-
SEC
ondary DC output voltage. If the secondary winding is
returned to V instead of ground, subtract V
OUT5
OUT5
from V
in the equation above. The diode’s
FLYBACK
The power requirements of the auxiliary supply must be
considered in the design of the main output. The trans-
former must be designed to deliver the required current
in both the primary and the secondary outputs with the
proper turns ratio and inductance. The power ratings of
the synchronous-rectifier MOSFETs and the current limit
in the MAX17003/MAX17004 must also be adjusted
accordingly. Extremes of low input-output differentials,
widely different output loading levels, and high turns
ratios can further complicate the design due to parasitic
transformer parameters such as interwinding capaci-
tance, secondary resistance, and leakage inductance.
Power from the main and secondary outputs is com-
bined to get an equivalent current referred to the main
output. Use this total current to determine the current
limit (see the Setting the Current Limit section):
reverse breakdown voltage rating must also accommo-
date any ringing due to leakage inductance. The
diode’s current rating should be at least twice the DC
load current on the secondary output.
3/MAX1704
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low V - V
dif-
OUT
IN
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The total output voltage sag is the sum of the voltage
sag while the inductor is ramping up, and the voltage
sag before the next pulse can occur:
2
L ΔI
(
)
LOAD(MAX)
I
= P
/V
TOTAL
TOTAL OUT5
V
=
+
SAG
2C
V
x D
− V
where I
is the equivalent output current referred
OUT
(
IN
MAX
OUT
)
TOTAL
to the main output, and P
is the sum of the output
TOTAL
ΔI
T − ΔT
(
)
LOAD(MAX)
C
power from both the main output and the secondary
output:
OUT
V
+ V
FWD
SEC
where D
is maximum duty factor (see the Electrical
MAX
N =
Characteristics), T is the switching period (1/f
), and
V
+ V
+ V
OSC
OUT5
RECT SENSE
ΔT equals V
/V x T when in PWM mode, or L x 0.2 x
OUT IN
I
/(V - V
) when in skip mode. The amount of
MAX IN
OUT
where N is the transformer turns ratio, V
is the mini-
FWD
OUT5(MIN)
SEC
overshoot during a full-load to no-load transient due to
stored inductor energy can be calculated as:
mum required rectified secondary voltage, V
is the
forward drop across the secondary rectifier, V
2
is the minimum value of the main output voltage, and
is the on-state voltage drop across the synchro-
ΔI
L
(
)
LOAD(MAX)
V
RECT
V
≈
SOAR
2C
V
nous-rectifier MOSFET. The transformer secondary
return is often connected to the main output voltage
OUT OUT
26 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
INPUT (V )
IN
C
IN
MAX17003
MAX17004
SENSE RESISTOR
N
H
DH_
L
L
R
SENSE
ESL
L
R
SENSE
SENSE
LX_
DL_
C
R1 =
EQ
N
L
C
OUT
D
C
EQ
L
R1
PGND
CSH_
CSL_
A) OUTPUT SERIES RESISTOR SENSING
INPUT (V )
IN
C
IN
MAX17003
MAX17004
INDUCTOR
N
H
DH_
LX_
DL_
R2
R1 + R2
L
R
DCR
R
=
=
R
DCR
CS
)
(
L
N
L
1
1
C
OUT
R
+
DCR
]
[
C
R1 R2
D
EQ
L
R1
R2
PGND
C
EQ
CSH_
CSL_
B) LOSSLESS INDUCTOR SENSING
Figure 7. Current-Sense Configurations
______________________________________________________________________________________ 27
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Setting the Current Limit
L
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The
ESL
C R1=
EQ
R
SENSE
peak inductor current occurs at I
the ripple current; therefore:
plus half
LOAD(MAX)
Alternatively, high-power applications that do not
require highly accurate current-limit protection may
reduce the overall power dissipation by connecting a
series RC circuit across the inductor (Figure 7B) with
an equivalent time constant:
ΔI
⎛
⎞
INDUCTOR
I
> I
LIMIT LOAD(MAX) +
⎜
⎝
⎟
⎠
2
⎛
⎞
R2
R1+ R2
where I
equals the minimum current-limit thresh-
LIMIT_
R
=
R
DCR
CS
⎜
⎟
old voltage divided by the current-sense resistance
⎝
⎠
(R
). For the default setting, the minimum current-
SENSE_
limit threshold is 45mV.
and:
Connect ILIM to LDO5 for a default 50mV current-limit
threshold. In adjustable mode, the current-limit thresh-
old is precisely 1/10th the voltage seen at ILIM. For an
adjustable threshold, connect a resistive divider from
REF to analog ground (GND) with ILIM connected to
the center tap. The external 0.5V to 2V adjustment
range corresponds to a 50mV to 200mV current-limit
threshold. When adjusting the current limit, use 1% tol-
erance resistors and a divider current of approximately
10mA to prevent significant inaccuracy in the current-
limit tolerance.
L
1
1
⎡
⎤
R
=
+
DCR
⎢
⎣
⎥
⎦
C
R1 R2
EQ
where R
is the required current-sense resistance,
is the inductor’s series DC resistance. Use
the typical inductance and R
the inductor manufacturer.
CS
and R
DCR
3/MAX1704
values provided by
DCR
Output Capacitor Selection
The output filter capacitor must have low enough equiva-
lent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance
must be high enough to absorb the inductor energy while
transitioning from full-load to no-load conditions without
tripping the overvoltage fault protection. When using high
capacitance, low-ESR capacitors (see stability require-
ments), the filter capacitor’s ESR dominates the output
voltage ripple. So the output capacitor’s size depends on
the maximum ESR required to meet the output voltage
The current-sense method (Figure 7) and magnitude
determines the achievable current-limit accuracy and
power loss. Typically, higher current-sense limits pro-
vide tighter accuracy, but also dissipate more power.
Most applications employ a current-limit threshold
(V
) of 50mV to 100mV, so the sense resistor may
LIMIT
be determined by:
V
V
ILIM
LIMIT
R
=
=
CS
I
10 x I
LIMIT
LIMIT
ripple (V
) specifications:
RIPPLE(P-P)
V
= R
I
LIR
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure
7A. This configuration constantly monitors the inductor
current, allowing accurate current-limit protection.
However, the parasitic inductance of the current-sense
resistor can cause current-limit inaccuracies, especially
when using low-value inductors and current-sense
RIPPLE(P-P)
ESR LOAD(MAX)
In idle mode, the inductor current becomes discontinu-
ous, with peak currents set by the idle mode current-
sense threshold (V
no-load output ripple may be determined as follows:
= 0.2V
). In idle mode, the
LIMIT
IDLE
V
R
IDLE ESR
V
=
RIPPLE(P–P)
R
SENSE
resistors. This parasitic inductance (L
) can be can-
ESL
celed by adding an RC circuit across the sense resistor
with an equivalent time constant:
28 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
For low-input voltage applications where the duty cycle
exceeds 50% (V
should not be greater than twice the internal slope-
compensation voltage:
/V ≥ 50%), the output ripple voltage
OUT IN
V
≤ 0.02 x V
RIPPLE
OUT
where V
equals ΔI
x R
. The worst-
ESR
RIPPLE
INDUCTOR
case ESR limit occurs when V = 2 x V
, so the
OUT
IN
capacity needed to prevent V
and V
from
SOAR
SAG
above equation may be simplified to provide the follow-
ing boundary condition:
causing problems during load transients. Generally,
once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
R
ESR
≤ 0.04 x L x f
SW
is no longer a problem (see the V
and V
equa-
SOAR
SAG
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precau-
tions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
tions in the Transient Response section). However, low-
capacity filter capacitors typically have high ESR zeros
that may affect the overall stability (see the Output-
Capacitor Stability Considerations section).
Output-Capacitor Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The boundary of insta-
bility is given by the following equation:
Unstable operation manifests itself in two related but
distinctly different ways: short/long pulses and cycle
skipping resulting in lower frequency operation.
Instability occurs due to noise on the output or because
the ESR is so low that there is not enough voltage ramp
in the output voltage signal. This “fools” the error com-
parator into triggering too early or into skipping a cycle.
Cycle skipping is more annoying than harmful, resulting
in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
f
OSC
π
f
≤
ESR
where:
1
f
=
ESR
2πR
C
ESR OUT
For a typical 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero fre-
quencies of 25kHz. In the design example used for
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage-ripple envelope for over-
shoot and ringing. It may help to simultaneously moni-
tor the inductor current with an AC current probe. Do
not allow more than three cycles of ringing after the ini-
tial step-response under/overshoot.
inductor selection, the ESR needed to support 25mV
P-P
ripple is 25mV/1.5A = 16.7mΩ. One 220µF/4V Sanyo
polymer (TPE) capacitor provides 15mΩ (max) ESR.
This results in a zero at 48kHz, well within the bounds
of stability.
______________________________________________________________________________________ 29
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
INPUT-CAPACITOR RMS CURRENT
vs. INPUT VOLTAGE
5.0
4.5
4.0
IN PHASE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
50/50 INTERLEAVING
40/60 OPTIMAL
INTERLEAVING
6
8
10
12
V
14
(V)
16
18
20
IN
INPUT RMS CURRENT FOR INTERLEAVED OPERATION:
2
3/MAX1704
2
2
2
I
=
− I
D
) (
− D
+ I
(
−I
D
− D
+ I
(
+ I
− I
D
+ I
1 − D
(
− D
+ D
LX3 OL
(
)
) (
)
)
RMS
OUT5
IN
LX5
OL
V
OUT3
OUT3 IN
LX3
OL
OUT5
OUT3
IN
)
OL IN
LX5
V
OUT5
D
=
D
=
D
= DUTY − CYCLE OVERLAP FRACTION
LX5
LX3
OL
V
V
IN
IN
OUT3 OUT3
V
I
+ V
I
OUT5 OUT5
I
=
IN
V
IN
INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION:
⎛
⎞
V
V
− V
OUT
(
IN OUT
)
⎜
⎟
I
= I
LOAD
RMS
⎜
⎟
V
IN
⎜
⎝
⎟
⎠
Figure 8. Input RMS Current
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. Choose a capacitor that has less than
10°C temperature rise at the RMS input current for opti-
mal reliability and lifetime.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
RMS
For an out-of-phase regulator, the total RMS current in
the input capacitor is a function of the load currents,
the input currents, the duty cycles, and the amount of
overlap as defined in Figure 8.
The 40/60 optimal interleaved architecture of the
MAX17003/MAX17004 allows the input voltage to go as
low 8.3V before the duty cycles begin to overlap. This
offers improved efficiency over a regular 180° out-of-
phase architecture where the duty cycles begin to
overlap below 10V. Figure 8 shows the input-capacitor
RMS current vs. input voltage for an application that
requires 5V/5A and 3.3V/5A. This shows the improve-
ment of the 40/60 optimal interleaving over 50/50 inter-
leaving and in-phase operation.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
V
and V
. Ideally, the losses at V
IN(MAX) IN(MIN)
IN(MIN)
should be roughly equal to the losses at V
, with
IN(MAX)
30 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
lower losses in between. If the losses at V
are
H
where C
is the output capacitance of N , Q
G(SW)
is
IN(MIN)
OSS
H
significantly higher, consider increasing the size of N .
the charge needed to turn on the N MOSFET, and I
H
GATE
Conversely, if the losses at V
are significantly
is the peak gate-drive source/sink current (1A typ).
IN(MAX)
higher, consider reducing the size of N . If V does not
H
IN
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied, due to the squared term in the switching-
vary over a wide range, maximum efficiency is achieved
by selecting a high-side MOSFET (N ) that has conduc-
H
tion losses equal to the switching losses.
2
loss equation (C x V
x f ). If the high-side MOSFET
SW
at low battery voltages
DS(ON)
IN
Choose a low-side MOSFET (N ) that has the lowest pos-
chosen for adequate R
becomes extraordinarily hot when subjected to
, consider choosing another MOSFET with
L
sible on-resistance (R
), comes in a moderate-sized
DS(ON)
package (i.e., 8-pin SO, DPAK, or D2PAK), and is reason-
ably priced. Ensure that the MAX17003/MAX17004 DL_
gate driver can supply sufficient current to support the
gate charge and the current injected into the parasitic
drain-to-gate capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems may
occur. Switching losses are not an issue for the low-side
MOSFET since it is a zero-voltage switched device when
used in the step-down topology.
V
IN(MAX)
lower parasitic capacitance.
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at maximum battery voltage:
PD N Resistive =
(
)
L
⎡
⎤
⎛
⎜
⎞
⎟
V
2
OUT
1−
I
⎥
(
LOAD
⎥
⎦
R
DS(ON)
⎢
)
V
⎝ IN(MAX) ⎠
⎢
⎣
Power-MOSFET Dissipation
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at mini-
mum input voltage:
greater than I
but are not high enough to
LOAD(MAX)
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the cir-
cuit to tolerate:
⎛
⎞
V
V
2
OUT
PD N Resistive =
I
(
R
DS(ON)
(
)
)
H
LOAD
⎜
⎟
ΔI
⎛
⎞
⎝
⎠
IN
INDUCTOR
I
= I
−
⎜
⎝
⎟
⎠
LOAD LIMIT
2
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
required to stay within package power-dissipa-
tion limits often limits how small the MOSFET can be. The
optimum occurs when the switching losses equal the
) losses. High-side switching losses
do not become an issue until the input is greater than
approximately 15V.
where I
is the peak current allowed by the current-
LIMIT
R
DS(ON)
limit circuit, including threshold tolerance and sense-
resistance variation. The MOSFETs must have a
relatively large heatsink to handle the overload power
dissipation.
conduction (R
DS(ON)
Choose a Schottky diode (D ) with a forward-voltage
L
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3rd the load current. This diode is optional
and can be removed if efficiency is not critical.
Calculating the power dissipation in high-side MOSFETs
(N ) due to switching losses is difficult, since it must
H
allow for difficult-to-quantify factors that influence the turn-
on and turn-off times. These factors include the internal
gate resistance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The fol-
lowing switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard evalu-
ation, preferably including verification using a thermocou-
Boost Capacitors
) must be selected large
The boost capacitors (C
BST
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
ple mounted on N :
H
PD N Resistive =
(
)
H
I
Q
C
V
⎛
⎞
LOAD G(SW)
OSS IN(MAX)
+
V
f
IN(MAX) SW
⎜
⎟
I
2
⎝
⎠
GATE
______________________________________________________________________________________ 31
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
transistor’s base and emitter. Furthermore, the transis-
tor’s current gain increases the linear regulator’s DC
loop gain (see the LDOA Stability Requirements sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 100 at the
maximum output current can be difficult to stabilize and
are not recommended. The transistor’s input capaci-
tance and input resistance also create a second pole,
which could be low enough to make the output unsta-
ble when heavily loaded.
Q
200mV
GATE
C
=
BST
where Q
is the total gate charge specified in the
GATE
high-side MOSFET’s data sheet. For example, assume
the FDS6612A n-channel MOSFET is used on the high
side. According to the manufacturer’s data sheet, a sin-
gle FDS6612A has a maximum gate charge of 13nC
(V
= 5V). Using the above equation, the required
boost capacitance would be:
GS
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Alternatively, the package’s power dissipation could
limit the useable maximum input-to-output voltage dif-
ferential. The maximum power-dissipation capability of
the transistor’s package and mounting must exceed the
actual power dissipation in the device. The power dissi-
pation equals the maximum load current times the max-
imum input-to-output differential:
13nC
200mV
C
=
= 0.065μF
BST
Selecting the closest standard value, this example
requires a 0.1µF ceramic capacitor.
LDOA Design Procedure
Output Voltage Selection
Adjust the auxiliary linear regulator’s output voltage by
connecting a resistive divider between OUTA and ana-
log ground with the center tap connected to FBA
(Figure 1). Select R6 in the 10kΩ to 30kΩ range, and
calculate R5 with the following equation:
PWR = I
(V
- V
)
OUTA
3/MAX1704
LOAD(MAX) INA
PWR = I
V
LOAD(MAX) CE
LDOA Stability Requirements
The MAX17003/MAX17004 linear-regulator controller
uses an internal transconductance amplifier to drive an
external pnp pass transistor. The transconductance
amplifier, the pass transistor, the base-to-emitter resistor,
and the output capacitor determine the loop stability.
⎛
⎞
V
OUTA
R5 = R6
− 1
⎟
⎜
V
⎝
⎠
FBA
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
where V
= 1.0V.
FBA
Transistor Selection
The pass transistor must meet specifications for current
gain (β), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
⎛
⎞⎛
⎞
5.5V
V
T
I
h
BIAS FE
I
A
=
1+
V(LDO)
⎜
⎟⎜
⎟
⎝
⎠⎝
⎠
LOAD
where V is 26mV at room temperature, h is the pass
T
FE
⎛
⎞
V
transistor’s DC gain, and I
is the current through
BIAS
BE
I
= I
β
MIN
LOAD(MAX)
DRV −
⎜
⎟
the base-to-emitter resistor (R ). The 680Ω base-to-
BE
R
⎝
⎠
BE
emitter resistor used in Figure 1 was chosen to provide
a 1mA bias current (I
).
BIAS
where I
is the minimum guaranteed base drive cur-
DRV
rent, V is the base-to-emitter voltage of the transistor,
BE
and R
is the pullup resistor connected between the
BE
32 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal ampli-
fier delay, the pass transistor’s input capacitance, and the
stray capacitance at the feedback node create additional
poles in the system, and the output capacitor’s ESR gen-
erates a zero. For proper operation, use the following
steps to ensure the linear-regulator stability:
5) Next, calculate the zero caused by the output
capacitor’s ESR:
1
f
=
ZERO(ESR)
2πC
R
OUTA ESR
where R
OUTA
is the equivalent series resistance of
ESR
1) First, calculate the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
C
.
6) To ensure stability, choose C
large enough so
OUTA
that the crossover occurs well before the poles and
zero calculated in steps 2 through 5. The poles in
steps 3 and 4 generally occur at several MHz, and
using ceramic output capacitors ensures the ESR
zero occurs at several MHz as well. Placing the
crossover frequency below 500kHz is typically suf-
ficient to avoid the amplifier delay pole and gener-
ally works well, unless unusual component
selection or extra capacitance moves the other
poles or zero below 1MHz.
1
f
=
POLE(LDO)
2πC
R
OUTA LOAD
where C
is the output capacitance of the aux-
OUTA
iliary LDO and R
is the load resistance corre-
LOAD
sponding to the maximum load current. The unity-
gain crossover of the linear regulator is:
f
= A
f
CROSSOVER
V(LDO) POLE(LDO)
2) The pole caused by the internal amplifier delay is at
approximately 1MHz:
A capacitor connected between the linear regula-
tor’s output and the feedback node can improve
the transient response and reduce the noise cou-
pled into the feedback loop.
f
≈ 1MHz
POLE(AMP)
If a low-dropout solution is required, an external p-
channel MOSFET pass transistor could be used.
However, a pMOS-based linear regulator requires
higher output capacitance to stabilize the loop. The
high gate capacitance of the p-channel MOSFET
3) Next, calculate the pole set by the transistor’s input
capacitance, the transistor’s input resistance, and the
base-to-emitter pullup resistor. Since the transistor’s
input resistance (h /g ) is typically much greater
FE
m
than the base-to-emitter pullup resistance, the pole
lowers the f
and can cause instability. A
POLE(CIN)
can be determined from the simplified equation:
1
large output capacitance must be used to reduce
the unity-gain bandwidth and ensure that the pole
is well above the unity-gain crossover frequency.
f
≈
POLE(CIN)
2πC R
IN IN
g
2πf
m
C
IN
=
Applications Information
T
Duty-Cycle Limits
where g is the transconductance of the pass tran-
m
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). Keep in mind
that the transient performance gets worse as the step-
down regulators approach the dropout voltage, so bulk
output capacitance must be added (see the voltage sag
and soar equations in the Transient Response section of
the SMPS Design Procedure section). The absolute
point of dropout occurs when the inductor current ramps
sistor, and f is the transition frequency. Both para-
T
meters can be found in the transistor’s data sheet.
Therefore, the equation can be further reduced to:
f
T
f
≈
POLE(CIN)
h
FE
4) Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FBA and ground (approximately 5pF including
stray capacitance):
down during the off-time (ΔI
) as much as it ramps
DOWN
up during the on-time (ΔI ). This results in a minimum
UP
1
operating voltage defined by the following equation:
f
=
POLE(FBA)
2πC
(R5||R6)
FBA
______________________________________________________________________________________ 33
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
•
Minimize current-sensing errors by connecting
CSH_ and CSL_ directly across the current-sense
⎛
⎞
1
V
=V
+ V
+ h
−1 V
+ V
(
)
IN(MIN)
OUT
CHG
OUT DIS
⎜
⎟
resistor (R
).
SENSE_
D
⎝
⎠
MAX
•
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
where V
and V
are the parasitic voltage drops in
DIS
CHG
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
Maximum Input Voltage
The MAX17003/MAX17004 controllers include a mini-
mum on-time specification, which determines the maxi-
mum input operating voltage that maintains the
selected switching frequency (see the Electrical
Characteristics table). Operation above this maximum
input voltage results in pulse-skipping operation,
regardless of the operating mode selected by SKIP. At
the beginning of each cycle, if the output voltage is still
above the feedback threshold voltage, the controller
does not trigger an on-time pulse, effectively skipping a
cycle. This allows the controller to maintain regulation
above the maximum input voltage, but forces the con-
troller to effectively operate with a lower switching fre-
quency. This results in an input threshold voltage at
•
Route high-speed switching nodes (BST_, LX_,
DH_, and DL_) away from sensitive analog areas
(REF, FB_, CSH_, CSL_).
Layout Procedure
Place the power components first, with ground termi-
nals adjacent (N _ source, C , C
anode). If possible, make all these connections on the
top layer with wide, copper-filled areas.
_, and D _
L
L
IN
OUT
7
Mount the controller IC adjacent to the low-side MOSFET,
preferably on the back side opposite N and N in
order to keep LX_, GND, DH_, and the DL_ gate-drive
lines short and wide. The DL_ and DH_ gate traces must
be short and wide (50 mils to 100 mils wide if the MOSFET
is 1in from the controller IC) to keep the driver impedance
low and for proper adaptive dead-time sensing.
L_
H_
which the controller begins to skip pulses (V
):
IN(SKIP)
⎛
⎞
⎟
1
V
=V
OUT⎜
IN(SKIP)
f
t
⎝ OSC ON(MIN) ⎠
Group the gate-drive components (BST_ capacitor,
LDO5 bypass capacitor) together near the controller IC.
where f
is the switching frequency selected by FSEL.
OSC
Make the DC-DC controller ground connections as
shown in Figures 1 and 9. This diagram can be viewed
as having two separate ground planes: power ground,
where all the high-power components go, and an ana-
log ground plane for sensitive analog components. The
analog ground plane and power ground plane must
meet only at a single point directly at the IC.
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. The switching
power stage requires particular attention (Figure 9). If
possible, mount all the power components on the top
side of the board, with their ground terminals flush
against one another. Follow these guidelines for good
PCB layout:
Connect the output power planes directly to the output
filter capacitor positive and negative terminals with mul-
tiple vias. Place the entire DC-DC converter circuit as
close to the load as is practical.
•
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
•
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing
PCB traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
34 ______________________________________________________________________________________
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
3/MAX1704
MAX17003/MAX17004
CONNECT THE
EXPOSED PAD TO
ANALOG GND
VIA TO POWER
GROUND
CONNECT GND AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
REF BYPASS
CAPACITOR
DUAL
n-CHANNEL
MOSFET
KELVIN SENSE VIAS
UNDER THE SENSE
SINGLE
n-CHANNEL
MOSFETS
RESISTOR
(REFER TO THE EVALUATION KIT)
INDUCTOR
INDUCTOR
DH
LX
DL
C
IN
C
C
OUT
IN
INPUT
C
OUT
INPUT
C
OUT
GROUND
OUTPUT
GROUND
LOW-POWER LAYOUT
OUTPUT
HIGH-POWER LAYOUT
Figure 9. PCB Layout
Table 6. Functional Differences Between MAX8744/MAX8745 and MAX17003/MAX17004
FEATURE
MAX8744/MAX8745
MAX17003/MAX17004
Startup is always in low-noise pulse-skipping mode (i.e.,
same as SKIP = REF setting). This allows for startup into
prebiased outputs.
Startup operating mode depends on the SKIP setting.
(e.g., SKIP is low, then startup occurs in skip mode).
Startup
The SKIP setting takes effect once the SMPS is in regulation.
Soft discharge of the output using the DSCHG3 and
DSCHG5 pins.
Shutdown
Actively discharges the output down to zero.
DL3 and DL5 are high in shutdown.
DL3 and DL5 are latched high during an OV fault of
the respective output (MAX8744 only).
DL3 and DL5 are low in shutdown.
DL3 and DL5 are latched high during an OV fault of the
respective output (MAX17003 only).
DL3 and DL5
States
PGOOD3: Power-good indicator for SMPS3.
Power-Good PGOOD5: Power-good indicator for SMPS5.
PGOODA: Power-good indicator for the auxiliary LDO.
PGDALL: Power-good indicator for SMPS3 and SMPS5.
Auxiliary LDO does not have power-good indicator.
Chip Information
TRANSISTOR COUNT: 6897
PROCESS: BiCMOS
______________________________________________________________________________________ 35
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
3/MAX1704
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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