MAX17075 [MAXIM]
Boost Regulator with Integrated Charge Pumps, Switch Control, and High-Current Op Amp; 升压型稳压器，内置电荷泵，开关控制和大电流运算放大器
| 型号： | MAX17075 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Boost Regulator with Integrated Charge Pumps, Switch Control, and High-Current Op Amp |
| 文件： | 总23页 (文件大小：601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-ꢀ353; Rev 1; 5ꢁ12
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
General Description
Features
The MAX17075 includes a high-voltage boost regulator,
one high-current operational amplifier, two regulated
charge pumps, and one MLG block for gate-driver
supply modulation.
o 2.5V to 5.5V Input Operating Range
o Current Mode Step-Up Regulator
Fast-Transient Response
Built-In 20V, 3A, 0.16Ω n-Channel Power MOSFET
The step-up DC-DC converter is a 1.2MHz current-
mode boost regulator with a built-in power MOSFET. It
provides fast load-transient response to pulsed loads
while producing efficiencies over 85%. The built-in
160mΩ (typ) power MOSFET allows output voltages as
high as 18V boosted from inputs ranging from 2.5V to
5.5V. A built-in 7-bit digital soft-start function controls
startup inrush currents.
Cycle-by-Cycle Current Limit
87% Efficiency (5V Input to 13V Output)
1.2MHz Switching Frequency
1% Output Voltage Regulation Accuracy
o High-Current 18V VCOM Buffer
500mA Output Short-Circuit Current
45V/µs Slew Rate
20MHz -3dB Bandwidth
Rail-to-Rail Output
The gate-on and gate-off charge pumps provide regu-
lated TFT gate-on and gate-off supplies. Both output
voltages can be adjusted with external resistive
voltage-dividers.
o Regulated Charge Pump for TFT Gate-On Supply
o Regulated Charge Pump for TFT Gate-Off Supply
o Logic-Controlled High-Voltage Switches with
The operational amplifier, typically used to drive the
LCD backplane (VCOM), features high-output short-cir-
cuit current ( 500mA), fast slew-rate (ꢀ5Vꢁ/s), wide
bandwidth (20MHz), and rail-to-rail outputs.
Adjustable Delay
o Soft-Start and Timed Delay Fault Latch for All
Outputs
The MAX17075 is available in a 2ꢀ-pin thin QFN pack-
age with 0.5mm lead spacing. The package is a square
(ꢀmm x ꢀmm) with a maximum thickness of 0.8mm for
ultra-thin LCD design. It operates over the -ꢀ0°C to
+85°C temperature range.
o Overload and Thermal Protection
Simplified Operating Circuit
V
MAIN
V
IN
2.5V TO 5.5V
R1
10Ω
Applications
Notebook Computer Displays
VCC
OUT
LX
C5
1µF
FROM
SYSTEM
3.3V
PGND
LCD Monitor Panels
LCD TVs
FB
TO V
COM
COMP
V
IN
V
AVDD
MAX17075
Ordering Information
BGND
RST
RSTIN
NEG
POS
REF
PART
TEMP RANGE
PIN-PACKAGE
DRN
MAX17075ETG+
-40°C to +85°C
24 TQFN-EP*
*EP = Exposed paddle.
+Denotes a lead(Pb)-freeꢁRoHS-compliant package.
COM
SRC
V
GON
AGND
FBN
DRVP
V
GOFF
DRVN
BGND
FBP
DEL
SUP CTL EP
FROM
TCON
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
ABSOLUTE MAXIMUM RATINGS
VCC, CTL, RSTIN, RST to AGND ..........................-0.3V to +7.5V
DEL, REF, COMP, FB, FBN,
POS, NEG, OUT to AGND...........................-0.3V to (V
DRVN, DRVP RMS Current ...............................................200mA
LX, PGND RMS Current Rating.............................................2.ꢀA
+ 0.3)
SUP
FBP to AGND.......................................-0.3V to (V
+ 0.3V)
VCC
PGND, BGND to AGND.........................................-0.3V to +0.3V
LX to PGND ............................................................-0.3V to +20V
SUP to PGND .........................................................-0.3V to +20V
Continuous Power Dissipation (T = +70°C)
A
2ꢀ-Pin TQFN (derate 27.8mWꢁ°C above +70°C).......2222mW
Operating Temperature Range ...........................-ꢀ0°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DRVN, DRVP to PGND..............................-0.3V to (V
+ 0.3V)
SUP
SRC, COM, DRN to AGND.....................................-0.3V to +ꢀ0V
DRN to COM............................................................-30V to +30V
SRC to SUP ............................................................................23V
REF Short Circuit to AGND.........................................Continuous
MAX1075
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
VCC
= +5V, Circuit of Figure 1, V
= V
= +13V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
SUP A
AVDD
PARAMETER
CONDITIONS
MIN
2.5
TYP
MAX
5.5
2.45
200
1.5
5
UNITS
V
CC
V
CC
V
CC
Input Supply Range
V
V
Undervoltage-Lockout (UVLO) Threshold
Shutdown Current
V
rising, hysteresis (typ) = 50mV
= 2V
2.05
2.25
100
1
CC
V
CC
V
FB
V
FB
µA
= 1.3V, not switching
= 1.0V, switching
V
CC
Quiescent Current
mA
4
REFERENCE
REF Output Voltage
No external load
0n < I < 50µA
1.238
10
1.250
1
1.262
6
V
mV
µA
V
REF Load Regulation
LOAD
REF Sink Current
In regulation
REF Undervoltage-Lockout Threshold
OSCILLATOR AND TIMING
Frequency
Rising edge, hysteresis (typ) = 200mV
1.17
1000
87
1200
90
1400
93
kHz
%
Oscillator Maximum Duty Cycle
Duration to Trigger Fault Condition
DEL Capacitor Charge Current
DEL Turn-On Threshold
DEL Discharge Switch On-Resistance
STEP-UP REGULATOR
Output Voltage Range
FB Regulation Voltage
FB Fault Trip Level
FB or FBP or FBN below threshold
47
55
65
ms
µA
V
During startup, V
= 1.0V
4
5
6
DEL
1.19
1.25
20
1.31
ꢀ
V
18
V
V
VCC
FB = COMP, C
Falling edge
= 1nF
1.238
0.96
1.250
1
1.262
1.04
COMP
V
FB Load Regulation
0 < I
< full, transient only
-1
%
LOAD
FB Line Regulation
V
V
= 2.5V to 5.5V
= 1.25V
-0.2
50
0
+0.2
200
280
%/V
nA
µS
V/V
CC
FB
FB Input Bias Current
FB Transconductance
FB Voltage Gain
125
160
2600
ꢁI = 2.5µA at COMP, FB = COMP
75
FB to COMP
2
_______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
ELECTRICAL CHARACTERISTICS (continued)
(V
VCC
= +5V, Circuit of Figure 1, V
= V
= +13V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
SUP A
AVDD
PARAMETER
CONDITIONS
= 1.1V, duty cycle = 75%
MIN
TYP
3.0
0.16
10
MAX
3.5
UNITS
A
LX Current Limit
V
2.5
FB
LX On-Resistance
I
200mA
0.25
20
ꢀ
LX =
LX Leakage Current
Current-Sense Transresistance
Soft-Start Period
V
19V, T = +25°C
µA
LX =
A
0.1
0.2
14
0.3
V/A
ms
7-bit current ramp
POSITIVE CHARGE-PUMP REGULATOR
V
V
Input Supply Range
6
18
21
V
V
SUP
SUP
Overvoltage Threshold
V
= rising, hysteresis = 200mV
19
20
SUP
0.5 x
Operating Frequency
Hz
f
OSC
FBP Regulation Voltage
FBP Line Regulation Error
FBP Input Bias Current
DRVP Current Limit
-1.5%
-50
1.250 +1.5%
V
%/V
nA
mA
ꢀ
V
V
= 12V to 18V, V
= 30V
GON
0.2
+50
SUP
= 1.5V, T = +25°C
FBP
A
Not in dropout
400
DRVP PCH On-Resistance
DRVP NCH On-Resistance
FBP Fault Trip Level
4
1.5
1
6
3
ꢀ
Falling edge
0.96
1.04
V
7-bit voltage ramp with filtering to prevent
high peak currents
Positive Charge-Pump Soft-Start Period
3
5
ms
NEGATIVE CHARGE-PUMP REGULATOR
V
Input Supply Range
6
18
V
Hz
V
SUP
0.5 x
Operating Frequency
f
OSC
FBN Regulation Voltage (V
FBN Input Bias Current
- V
)
V
V
V
- V = 1V
FBN
-1.5%
-50
1
+1.5%
+50
REF
FBN
REF
FBN
SUP
= 0V, T = +25°C
nA
A
FBN Line Regulation Error
DRVN PCH On-Resistance
DRVN NCH On-Resistance
DRVN Current Limit
= 9V to 18V, V
= -7V
0.2
6
%/V
ꢀ
GOFF
4
1.5
3
ꢀ
Not in dropout
Rising edge
400
450
mA
mV
FBN Fault Trip level
7-bit voltage ramp with filtering to prevent
high peak currents
Negative Charge-Pump Soft-Start Period
3
5
ms
POSITIVE GATE DRIVER TIMING AND CONTROL SWITCHES
CTL Input Low Voltage
0.6
+1
V
V
CTL Input High Voltage
2
CTL Input Current
V
CTL
= 0V or V
, T = +25°C
A
-1
µA
ns
V
VCC
CTL-to-COM Rising Propagation Delay
SRC Input Voltage Range
C
LOAD
= 100pF
250
5
36
10
SRC-to-COM Switch On-Resistance
V
DEL
= 1.5V, CTL = VCC
ꢀ
_______________________________________________________________________________________
3
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
ELECTRICAL CHARACTERISTICS (continued)
(V
VCC
= +5V, Circuit of Figure 1, V
= V
= +13V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
SUP A
AVDD
PARAMETER
CONDITIONS
MIN
TYP
30
MAX
60
UNITS
ꢀ
DRN-to-COM Switch On-Resistance
COM-to-GND Pulldown
V
= 1.5V, CTL = AGND
= 0V
DEL
V
DEL
V
DEL
V
DEL
1.5
2.5
kꢀ
= 1.5V, CTL = VCC
= 1.5V, CTL = AGND
300
200
600
360
SRC Input Current
µA
OPERATIONAL AMPLIFIERS
SUP Supply Range
MAX1075
6
18
4.2
6.5
12
V
V
VSUP Undervoltage Threshold
SUP Supply Current
3.8
4
4
Buffer configuration, V
= V
/2, no load
SUP
mA
mV
µA
V
POS
Input Offset Voltage
V
, V
= V
= V
/2, T = +25°C
A
NEG POS
SUP
SUP
Input Bias Current
V
, V
/2, T = +25°C
-1
0
+1
NEG POS
A
Input Common-Mode Voltage Range
Input Common-Mode Rejection Ratio
V
SUP
80
dB
V
SUP
350
-
Output-Voltage-Swing High
I
I
50mA
mV
OUT =
OUT =
Output-Voltage-Swing Low
Large-Signal Voltage Gain
Slew Rate
-50mA
350
mV
dB
V
= 1V to (V
- 1)V
80
45
20
OUT
SUP
V/µs
MHz
-3dB Bandwidth
Sourcing
Sinking
500
500
Short-Circuit Current
XAO CONTROL
mA
Falling edge at V = 5V
1.225
1.213
-1
1.250
1.250
1.275
1.287
+1
CC
RSTIN Threshold
V
Falling edge at V = 1.8V
CC
RSTIN Input Current
RSTIN Hysteresis
RST Output Voltage
RST Blanking Time
XAO UVLO
T
A
= +25°C
µA
mV
V
50
I
= 1mA
0.4
280
1.7
SINK
Counting from V
crossing 2.25V
160
220
1.5
ms
V
VCC
V
rising with hysteresis of 50mV
VCC
4
_______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
ELECTRICAL CHARACTERISTICS
(V
= +5V, Circuit of Figure 1, V
= V
= +13V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
SUP A
CC
AVDD
PARAMETER
CONDITIONS
MIN
2.5
TYP
MAX
5.5
2.45
200
1.5
5
UNITS
V
CC
V
CC
V
CC
Input Supply Range
V
V
Undervoltage-Lockout Threshold
Shutdown Current
V
rising, hysteresis (typ) = 50mV
2.05
CC
µA
V
V
= 1.3V, not switching
= 1.0V, switching
FB
V
CC
Quiescent Current
mA
FB
REFERENCE
REF Output Voltage
No external load
0 < I < 50µA
1.230
10
1.267
6
V
mV
µA
V
REF Load Regulation
REF Sink Current
LOAD
In regulation
REF Undervoltage-Lockout Threshold
OSCILLATOR AND TIMING
Frequency
Rising edge, hysteresis (typ) = 200mV
1.15
1000
86
1400
94
kHz
%
Oscillator Maximum Duty Cycle
Duration to Trigger Fault Condition
DEL Capacitor Charge Current
DEL Turn-On Threshold
STEP-UP REGULATOR
Output Voltage Range
FB Regulation Voltage
FB Fault Trip Level
FB or FBP or FBN below threshold
47
65
ms
µA
V
During startup, V
= 1.0V
4
6
DEL
1.19
1.31
V
18
1.267
1.04
+0.25
200
V
V
IN
FB = COMP, C
Falling edge
= 1nF
1.230
0.96
-0.25
50
COMP
V
FB Line Regulation
V
CC
V
FB
= 2.5V to 5.5V
%/V
nA
µS
A
FB Input Bias Current
FB Transconductance
LX Current Limit
= 1.25V
ꢁI = 2.5µA at COMP, FB = COMP
75
280
V
FB
= 1.1V, duty cycle = 75%
2.5
3.5
LX On-Resistance
I
200mA
0.25
0.30
ꢀ
LX =
Current-Sense Transresistance
0.10
V/A
POSITIVE CHARGE-PUMP REGULATOR
V
V
Input Supply Range
6
18
21
V
V
SUP
SUP
Overvoltage Threshold
V
= rising, hysteresis = 200mV
19
SUP
FBP Regulation Voltage
FBP Line Regulation Error
FBP Input Bias Current
DRVP PCH On-Resistance
DRVP NCH On-Resistance
FBP Fault Trip Level
-2%
1.25
+2%
0.2
+50
6
V
%/V
nA
ꢀ
V
V
= 8V to 18V, V
= 30V
GON
SUP
= 1.5V, T = +25°C
-50
FBP
A
3
1.04
ꢀ
Falling edge
0.96
V
7-bit voltage ramp with filtering to prevent
high peak currents
Positive Charge-Pump Soft-Start Period
5
ms
_______________________________________________________________________________________
5
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, Circuit of Figure 1, V
= V
= +13V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
SUP A
CC
AVDD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NEGATIVE CHARGE-PUMP REGULATOR
Input Supply Range
V
6
18
+2%
+50
0.2
6
V
V
SUP
FBN Regulation Voltage (V
FBN Input Bias Current
- V
)
V
REF
V
FBN
V
SUP
- V = 1V
FBN
-2%
-50
1
REF
FBN
= 0V, T = +25°C
nA
%/V
ꢀ
A
FBN Line Regulation Error
DRVN PCH On-Resistance
DRVN NCH On-Resistance
= 9V to 18V, V
= -7V
GOFF
MAX1075
3
ꢀ
7-bit voltage ramp with filtering to prevent
high peak currents
Negative Charge-Pump Soft-Start Period
5
ms
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
CTL Input Low Voltage
0.6
V
V
CTL Input High Voltage
2
CTL Input Current
V
= 0V or V
, T = +25°C
-1
+1
36
µA
V
CTL
VCC
A
SRC Input Voltage Range
SRC-to-COM Switch On-Resistance
DRN-to-COM Switch On-Resistance
COM-to-GND Pulldown
V
DEL
= 1.5V, CTL = VCC
= 1.5V, CTL = AGND
= 0V
10
ꢀ
V
DEL
60
ꢀ
V
DEL
V
DEL
V
DEL
1.5
2.5
600
360
kꢀ
µA
µA
= 1.5V, CTL = VCC
= 1.5V, CTL = AGND
SRC Input Current
OPERATIONAL AMPLIFIERS
SUP Supply Range
6
18
4.2
6.5
8
V
V
V
Undervoltage Threshold
3.8
4
SUP
SUP Supply Current
Buffer configuration, V
V
/2, no load
mA
mV
µA
V
POS = SUP
Input Offset Voltage
V
V
, V
= V
= V
/2, T = +25°C
A
NEG POS
SUP
SUP
Input Bias Current
, V
/2, T = +25°C
-1
0
+1
NEG POS
A
Input Common-Mode Voltage Range
V
SUP
V
-
SUP
350
Output-Voltage-Swing High
I
I
50mA
mV
OUT =
OUT =
Output-Voltage-Swing Low
Short-Circuit Current
-50mA
350
mV
mA
Sourcing
Sinking
500
500
XAO CONTROL
RSTIN Threshold
RSTIN Input Current
RST Output Voltage
RST Blanking Time
XAO UVLO
Falling edge
1.22
-1
1.28
+1
V
µA
V
T
A
= +25°C
I
= 1mA
0.4
280
1.7
SINK
Counting from V
crossing 2.25V
160
ms
V
VCC
V
CC
rising with typical hysteresis of 50mV
Note 1: -ꢀ0°C specifcations are guaranteed by design, not production tested.
6
_______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
STEP-UP REGULATOR EFFICIENCY
STEP-UP REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT
STEP-UP REGULATOR LINE REGULATION
UNDER DIFFERENT LOADS
vs. LOAD CURRENT
100
0.6
0.4
0.20
0.15
V
= 5V
IN
90
80
70
60
50
40
30
20
10
0
0.2
0
0.10
0.05
0
300mA LOAD
NO
LOAD
V
= 3.3V
IN
-0.2
-0.4
-0.6
-0.8
-1.0
200mA LOAD
100mA LOAD
V
= 2.5V
IN
-0.05
-0.10
-0.15
-0.20
1
10
100
1000
0
100 200 300 400 500 600 700 800 900 1000
LOAD CURRENT (mA)
2.5
3.0
3.5
4.0
4.5
5.0
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
STEP-UP REGULATOR SWITCHING
FREQUENCY vs. INPUT VOLTAGE
STEP-UP REGULATOR STARTUP
WITH HEAVY LOAD (600mA)
MAX17075 toc05
1.24
1.23
150mA LOAD
V
IN
5V/div
V
AVDD
0V
0V
5V/div
1.22
1.21
1.20
1.19
1.18
1.17
1.16
I
L
1A/div
0A
0V
LX
10V/div
2.5
3.0
3.5
4.0
4.5
5.0
2ms/div
INPUT VOLTAGE (V)
STEP-UP REGULATOR LOAD-TRANSIENT
STEP-UP REGULATOR PULSED
RESPONSE (100mA TO 800mA)
LOAD-TRANSIENT RESPONSE (80mA TO 2.08mA)
MAX17075 toc06
MAX17075 toc07
V
AVDD
(AC-COUPLED)
500mV/div
0V
0A
V
0V
AVDD
(AC-COUPLED)
500mV/div
I
L
I
L
2A/div
2A/div
0A
0A
LOAD CURRENT
500mA/div
LOAD CURRENT
1A/div
0A
40µs/div
10µs/div
R
COMP
= 82kΩ
R
COMP
= 82kΩ
C
C
= 220pF
= 18pF
C
C
= 220pF
= 18pF
COMP1
COMP2
COMP1
COMP2
_______________________________________________________________________________________
7
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
IN SUPPLY QUIESCENT CURRENT
POWER-UP SEQUENCE OF
ALL SUPPLY OUTPUTS
vs. IN SUPPLY VOLTAGE
MAX17075 toc09
4.0
3.5
V
REF
IN
200mA LOAD
0V
AVDD
3.0
2.5
2.0
1.5
1.0
0.5
0
0V
0V
VCOM
SRC
MAX1075
0V
0V
NO SWITCHING
DEL
GOFF
GON
0V
2.5
3.0
3.5
4.0
4.5
5.0
4ms/div
V
: 5V/div
SRC : 20V/div
GOFF : 5V/div
GON : 20V/div
DEL : 2V/div
IN
SUPPLY VOLTAGE (V)
REF : 1V/div
AVDD : 10V/div
VCOM : 5V/div
POSITIVE CHARGE-PUMP REGULATOR
LINE REGULATION
POSITIVE CHARGE-PUMP REGULATOR
LOAD REGULATION
POSITIVE CHARGE-PUMP REGULATOR
LOAD-TRANSIENT RESPONSE (10mA TO 100mA)
MAX17075 toc12
0.05
0
0.4
VSRC
GON
(AC-COUPLED)
200mV/div
0V
0
-0.4
-0.8
-0.05
-0.10
-0.15
-0.20
GON
-1.2
-1.6
LOAD CURRENT
50mA/div
-0.25
-0.30
0A
-2.0
11
12
13
14
15
16
17
18
0
10 20 30 40 50 60 70 80
LOAD CURRENT (mA)
4µs/div
SUPPLY VOLTAGE (V)
NEGATIVE CHARGE-PUMP REGULATOR
LINE REGULATION
NEGATIVE CHARGE-PUMP REGULATOR
LOAD REGULATION
NEGATIVE CHARGE-PUMP REGULATOR
LOAD-TRANSIENT RESPONSE (10mA TO 100mA)
MAX17075 toc15
0.2
0.2
GOFF
(AC-COUPLED)
100mV/div
0V
0A
0
0
LOAD CURRENT
50mA/div
-0.2
-0.2
10.5 11.5 12.5 13.5 14.5 15.5 16.5 17.5
SUPPLY VOLTAGE (V)
0
20
40
60
80
100
120
4µs/div
LOAD CURRENT (mA)
8
_______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
OPERATION AMPLIFIER
FREQUENCY RESPONSE
OPERATIONAL AMPLIFIER RAIL-TO-RAIL
OPERATIONAL AMPLIFIER
INPUT/OUPUT WAVEFORMS
LOAD-TRANSIENT RESPONSE
MAX17075 toc17
MAX17075 toc18
2
100pF LOAD
1
0
V
VCOM
V
POS
(AC-COUPLED)
200mV/div
0V
0A
5V/div
-1
-2
-3
-4
-5
-6
-7
-8
0V
0V
NO LOAD
V
VCOM
5V/div
I
VCOM
50mV/div
100
1k
10k
100k
2µs/div
2µs/div
FREQUENCY (kHz)
OPERATIONAL AMPLIFIER
OPERATIONAL AMPLIFIER
LARGE-SIGNAL STEP RESPONSE
SMALL-SIGNAL STEP RESPONSE
MAX17075 toc19
MAX17075 toc20
V
POS
V
POS
5V/div
(AC-COUPLED)
100mV/div
0V
0V
0mV
0mV
V
V
VCOM
(AC-COUPLED)
100mV/div
VCOM
5V/div
40µs/div
40µs/div
HIGH-VOLTAGE SWITCH
CONTROL FUNCTION
SUP SUPPLY CURRENT
vs. SUP SUPPLY VOLTAGE
MAX17075 toc21
4.00
3.95
3.90
3.85
V
GON
10V/div
NO SWITCHING
3.80
3.75
0V
0V
3.70
3.65
3.60
V
CTL
5V/div
3.55
3.50
10µs/div
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
Pin Description
PIN
1
NAME
POS
FUNCTION
Operational Amplifier Noninverting Input
Operational Amplifier Inverting Input
Operational Amplifier Output
2
NEG
3
OUT
4
BGND
Analog Ground for Operational Amplifier and Charge Pump. Connect to AGND underneath the IC.
Operational Amplifier and Charge-Pump Supply Input. Connect this pin to the output of the boost
regulator (AVDD) and bypass to BGND with a minimum1µF capacitor.
5
SUP
MAX1075
6
7
DRVP
DRVN
Positive Charge-Pump Driver Output
Negative Charge-Pump Driver Output
High-Voltage Switch Control Input. When CTL is high, the switch between GON and SRC is on and the
switch between GON and DRN is off. When CTL is low, the switch between GON and DRN is on and the
switch between GON and SRC is off. CTL is inhibited by VCC UVLO and when DEL is less than 1.25V.
8
9
CTL
RST
FBP
Reset Output. RST is an open-drain output.
Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive voltage-
divider between the positive charge-pump regulator output and AGND to set the positive charge-pump
regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
10
Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltage-
divider between the negative output and REF to set the negative charge-pump regulator output voltage.
Place the resistive voltage-divider within 5mm of FBN.
11
FBN
Reference Output. Connect a 0.22µF capacitor from REF to AGND. All power outputs are disabled until
REF exceeds its UVLO threshold.
12
13
14
REF
VCC
Supplies the Internal Reference and Other Internal Circuitry. Connect VCC to the input supply voltage
and bypass VCC to AGND with a minimum 1µF ceramic capacitor.
Analog Ground for Step-Up Regulator and Linear Regulators. Connect to power ground (PGND)
underneath the IC.
AGND
15
16
RSTIN
COMP
Reset Input. Connect to the center of a resistor-divider from V .
IN
Compensation Pin for Error Amplifier. Connect a series RC from COMP to AGND.
Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between the
step-up regulator output and AGND to set the regulator’s output voltage. Place the resistive voltage-
divider within 5mm of FB.
17
FB
18, 19
20
PGND
LX
Power Ground
Step-Up Regulator Switching Node. Connect inductor and catch diode here and minimize trace area for
lowest EMI power ground.
21
22
DRN
COM
Switch Input. Drain of the internal high-voltage back-to-back p-channel FET connects to COM.
Internal High-Voltage MOSFET Switch Common Terminal
Switch Input. Source of the internal high-voltage pFET. Bypass SRC to PGND with a minimum 0.1µF
capacitor close to the pin.
23
SRC
24
—
DEL
EP
High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set delay.
Exposed Pad. Connect to AGND.
10 ______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
L1
3.0µH
D1
V
IN
V
AVDD
2.5V TO 5.5V
(4.5 TO 5.5V FOR FULL LOAD)
13V/500mA
C1
10µF
6.3V
C2
10µF
6.3V
C3
10µF
25V
C4
10µF
25V
R1
10Ω
R8
187kΩ
VCC
LX
C5
1µF
PGND
TO V
OUT
NEG
FB
COM
FROM SYSTEM
3.3V
R10
100kΩ
R9
MAX17075
V
AVDD
20kΩ
V
IN
COMP
C12
220pF
R13
10kΩ
R3
100kΩ
R11
RST
RSTIN
POS
REF
R14
C13
1kΩ
0.01µF
R12
V
20kΩ
DRN
COM
SRC
AVDD
V
C9
0.22µF
GON
30V/20mA
R6
AGND
FBN
13.7kΩ
C14
1µF
D2
C15
0.1µF
V
AVDD
C16
1µF
C17
0.1µF
DRVP
R7
100kΩ
D4
C11
DRVN
BGND
0.1µF
V
GOFF
-7V/20mA
C10
1µF
D3
R15
464kΩ
FBP
EP CTL DEL
SUP
R16
20kΩ
C8
0.033µF
C6
1µF
V
AVDD
FROM TCON
Figure 1. Typical Operating Circuit
a +13V source driver supply, a +30V positive gate-dri-
ver supply, and a -7V negative gate-driver supply from
a +2.5V to +5.5V input supply. Table 1 lists some
selected components, and Table 2 lists the contact
information for component suppliers.
Typical Operating Circuit
The typical operating circuit (Figure 1) of the
MAX17075 is a complete power-supply system for TFT
LCD panels in monitors and TVs. The circuit generates
______________________________________________________________________________________ 11
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
V
VCC
SUP
LX
V
AVDD
POS
NEG
BOOST
CONTROLLER
PGND
MAX1075
OUT
FB
BGND
COMP
SRC
DEL
CTL
V
VCC
COM
SWITCH
CONTROL
V
GON
MAX17075
FROM TCON
OSC
RSTIN
RST
DRN
VCC
V
VCC
SEQUENCE
REF
REF
V
AVDD
AGND
FBN
DRVP
FBP
NEGATIVE
CHARGE
PUMP
POSITIVE
CHARGE
PUMP
POUT
V
GOFF
DRVN
SUP
V
AVDD
Figure 2. Functional Diagram
high-performance operational amplifier designed to
drive the LCD backplane (VCOM). The amplifier fea-
tures high output current, fast slew rate (ꢀ5Vꢁ/s), wide
bandwidth (20MHz), and rail-to-rail outputs. In addition,
the MAX17075 features a high-voltage switch-control
block, a 1.25V reference output, well-defined power-up
and power-down sequences, and thermal-overload
protection. Figure 2 shows the MAX17075 functional
block diagram.
Detailed Description
The MAX17075 contains a step-up switching regulator
to generate the source driver supply, and two charge-
pump regulators to generate the gate-driver supplies.
Each regulator features adjustable output voltage, digi-
tal soft-start, and timer-delayed fault protection. The
step-up regulator uses fixed-frequency current-mode
control architecture. The MAX17075 also includes one
12 ______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
Table 1. Component List
DESIGNATION
DESCRIPTION
DESIGNATION
DESCRIPTION
10µF ±20%, 6.3V X5R ceramic capacitors
(0603)
Murata GRM188R60J106M
TDK C1608X5R0J106M
0.1µF ±10%, 50V X7R ceramic capacitors
(0603)
Murata GRM188R71H104K
TDK C1608X7R1H104K
C11, C15, C16,
C17
C1, C2
10µF ±20%, 25V X5R ceramic capacitors
(1206)
Murata GRM31CR61E106M
TDK C3216X5R1E106M
3A, 30V Schottky diode (M-Flat)
Toshiba CMS02 (TE12L,Q) (Top mark S2)
D1
D2, D3, D4
L1
C3, C4, C7
C10, C14
220mA, 100V dual diodes (SOT23)
Fairchild MMBD4148SE (Top mark D4)
1µF ±10%, 50V X7R ceramic capacitors
(1206)
Murata GRM31MR71H105KA
TDK C3216X7R1H105K
3.0µH, 3A
inductor
DC
Sumida CDRH6D28-3R0
Table 2. Component Suppliers
SUPPLIER
Fairchild Semiconductor
Sumida
PHONE
FAX
WEBSITE
408-822-2000
847-545-6700
847-803-6100
949-455-2000
408-822-2102
847-545-6720
847-390-4405
949-859-3963
www.fairchildsemi.com
www.sumida.com
TDK
www.component.tdk.com
www.toshiba.com/taec
Toshiba
Main Step-Up Regulator
The main step-up regulator employs a current-mode,
fixed-frequency PWM architecture to maximize loop
bandwidth and provide fast-transient response to
pulsed loads that are typical for TFT LCD panel source
drivers. The 1.2MHz switching frequency allows the use
of low-profile inductors and ceramic capacitors to mini-
mize the thickness of LCD panel design. The integrated
high-efficiency MOSFET and the built-in digital soft-start
function reduce the number of external components
required while controlling inrush currents. The output
CLOCK
LX
LOGIC
AND
DRIVER
PGND
CURRENT-LIMIT
COMPARATOR
SOFT-
START
I
LIMIT
SLOPE COMP
voltage can be set from V to 18V with an external
IN
resistive voltage-divider. The regulator controls the out-
put voltage and the power delivered to the output by
modulating the duty cycle (D) of the internal power
MOSFET in each switching cycle. The duty cycle of the
MOSFET is approximated by:
PWM
COMPARATOR
CURRENT
SENSE
∑
OSCILLATOR
ERROR AMP
V
− V
IN
AVDD
V
D ≈
TO FAULT LOGIC
FB
AVDD
1.0V
FAULT
COMPARATOR
1.25V
MAX17075
where V
is the output voltage of the step-up regulator.
AVDD
COMP
Figure 3 shows the functional diagram of the step-up
regulator. An error amplifier compares the signal at FB
to 1.25V and changes the COMP output. The voltage at
COMP sets the peak inductor current. As the load
varies, the error amplifier sources or sinks current to the
COMP output accordingly to produce the inductor peak
Figure 3. Step-Up Regulator Functional Diagram
current necessary to service the load. To maintain sta-
bility at high duty cycles, a slope-compensation signal
is summed with the current-sense signal.
______________________________________________________________________________________ 13
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
exceed the COMP voltage, the controller resets the
flip-flop and turns off the MOSFET. Since the inductor
current is continuous, a transverse potential develops
across the inductor that turns on the diode (D1). The
voltage across the inductor then becomes the differ-
ence between the output voltage and the input voltage.
This discharge condition forces the current through the
inductor to ramp back down, transferring the energy
stored in the magnetic field to the output capacitor and
the load. The MOSFET remains off for the rest of the
clock cycle.
The error amplifier compares the feedback signal (FBP)
with a 1.25V internal reference. If the feedback signal is
below the reference, the charge-pump regulator turns
on P1 and turns off N1 when the rising edge of the
oscillator clock arrives, level shifting C15 and C17 by
V
volts. If the voltage across C
plus a diode
POUT
SUP
drop (V
flying capacitor voltage (V
from C17 to C
if the voltage across C16 plus a diode drop (V
DIODE
voltage (V
+ V
) is smaller than the level-shifted
DIODE
POUT
+ V
), charge flows
SUP
C17
until diode D3-1 turns off. Similarly,
POUT
+
C16
MAX1075
V
) is smaller than the level-shifted flying capacitor
+ V
), charge flows from C15 to C16
SUP
C15
until diode D2-1 turns off. The falling edge of the oscil-
lator clock turns off P1 and turns on N1, allowing V
SUP
to charge up the flying capacitor C15 through D2-2 and
C16 to charge C17 through diode D3-2. If the feedback
signal is above the reference when the rising edge of
the oscillator comes, the regulator ignores this clock
edge and keeps N1 on and P1 off.
Positive Charge-Pump Regulator
The positive charge-pump regulator is typically used to
generate the positive supply rail for the TFT LCD gate-
driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to GND with the
midpoint connected to FBP. The number of charge-
pump stages and the setting of the feedback divider
determine the output voltage of the positive charge-
pump regulator. The charge pump includes a high-side
p-channel MOSFET (P1) and a low-side n-channel
MOSFET (N1) to control the power transfer as shown in
Figure ꢀ.
The MAX17075 also monitors the FBP voltage for
undervoltage conditions. If the V
is continuously
FBP
below 80% of the nominal regulation voltage for
approximately 50ms, the MAX17075 sets a fault latch,
shutting down all outputs except REF. Once the fault
condition is removed, cycle the input voltage (below the
UVLO falling threshold) to clear the fault latch and reac-
tivate the device.
INPUT
SUPPLY
SUP
MAX17075
C6
D2-2
OSC
P1
C15
C17
D2-1
D3-2
D3-1
ERROR
AMPLIFIER
DRVP
REF
1.25V
C16
C14
N1
POUT
POSITIVE CHARGE-PUMP REGULATOR
FBP
Figure ꢀ. Positive Charge-Pump Regulator Block Diagram
14 ______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
turns off. The falling edge of the oscillator clock turns
off N2 and turns on P2, allowing V to charge up fly-
ing capacitor C11 through diode Dꢀ-1. If the feedback
signal is below the reference when the rising edge of
the oscillator comes, the regulator ignores this clock
edge and keeps P2 on and N2 off.
Negative Charge-Pump Regulator
The negative charge-pump regulator is typically used to
generate the negative supply rail for the TFT LCD gate
driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to REF with the
midpoint connected to FBN. The number of charge-
pump stages and the setting of the feedback divider
determine the output of the negative charge-pump regu-
lator. The charge-pump controller includes a high-side p-
channel MOSFET (P2) and a low-side n-channel MOSFET
(N2) to control the power transfer as shown in Figure 5.
SUP
The MAX17075 also monitors the FBN voltage for
undervoltage conditions. If the V
is continuously
FBN
below 80% of the nominal regulation voltage (V
-
REF
V
) for approximately 50ms, the MAX17075 sets a
FBN
fault latch, shutting down all outputs except REF. Once
the fault condition is removed, cycle the input voltage
(below the UVLO falling threshold) to clear the fault
latch and reactivate the device.
The error amplifier compares the feedback signal (FBN)
with a 250mV internal reference. If the feedback signal
is above the reference, the charge-pump regulator
turns on N2 and turns off P2 when the rising edge of the
oscillator clock arrives, level shifting C11. This connects
C11 in parallel with reservoir capacitor C10. If the volt-
Operational Amplifiers
The MAX17075 has one operational amplifier. The oper-
ational amplifier is typically used to drive the LCD back-
plane (VCOM) or the gamma-correction divider string. It
features 500mA output short-circuit current, ꢀ5Vꢁ/s
slew rate, and 20MHz, 3dB bandwidth.
age across C10 minus a diode drop (V
- V
) is
C10
DIODE
higher than the level-shifted flying capacitor voltage
(-V
), charge flows from C10 to C11 until diode Dꢀ-2
C11
INPUT
SUPPLY
MAX17075
SUP
OSC
P2
D4-1
C11
DRVN
ERROR
AMPLIFIER
REF
0.25V
D4-2
GOFF
C10
N2
R7
R6
NEGATIVE CHARGE-PUMP REGULATOR
FBN
REF
Figure 5. Negative Charge-Pump Regulator Block Diagram
______________________________________________________________________________________ 15
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
Short-Circuit Current Limit and Input Clamp
The operational amplifier limits short-circuit current to
approximately 500mA if the output is directly shorted
to SUP or to BGND. If the short-circuit condition per-
sists, the junction temperature of the IC rises until it
reaches the thermal-shutdown threshold (+160°C typ).
Once the junction temperature reaches the thermal-
shutdown threshold, an internal thermal sensor immedi-
ately sets the thermal fault latch, shutting off all the IC’s
outputs. The device remains inactive until the input volt-
age is cycled. The operational amplifier has ꢀV input
clamp structures in series with a 500Ω resistance and a
diode (Figure 6).
reduces peaking, but also reduces the gain. An alterna-
tive method of reducing peaking is to place a series RC
network (snubber) in parallel with the capacitive load.
The RC network does not continuously load the output
or reduce the gain. Typical values of the resistor are
between 100Ω and 200Ω, and the typical value of the
capacitor is 10nF.
High-Voltage Switch Control
The MAX17075’s high-voltage switch control block
(Figure 7) consists of two high-voltage p-channel
MOSFETs: Q1, between SRC and COM; and Q2,
between COM and DRN. At power-up and only at
power up, before the switch control is enabled (a 1.5kΩ
pulldown is present on COM). At switch-off, COM is
high impedance.
MAX1075
Driving Pure Capacitive Load
The operational amplifier is typically used to drive the
LCD backplane (VCOM) or the gamma-correction
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation. As the operational amplifier’s capaci-
tive load increases, the amplifier’s bandwidth decreas-
es and gain peaking increases. A 5Ω to 50Ω small
resistor placed between OUT and the capacitive load
The switch control input (CTL) is not activated until all
four of the following conditions are satisfied: the input
voltage exceeds UVLO, the soft-start routine of all the
regulators is complete, there is no fault condition
detected, and V
exceeds its turn-on threshold.
DEL
Once activated and if CTL is logic-high, Q1 turns on
and Q2 turns off, connecting COM to SRC. When CTL
is logic-low, Q1 turns off and Q2 turns on, connecting
COM to DRN.
VCC
5µA
DEL
MAX17075
2.25V
SUP
FAULT
REF_OK
Q3
SRC
POS
V
REF
Q1
4V
COM
500Ω
MAX17075
NEG
SWITCH CONTROL
Q2
1.5kΩ
OUT
BGND
DRN
Q4
CTL
OP AMP INPUT CLAMP STRUCTURE
Figure 6. Op Amp Input Clamp Structure
Figure 7. Switch Control
16 ______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
When the input voltage falls below the UVLO falling
threshold, the controller turns off the main step-up regu-
lator and disables the switch-control block; the opera-
tional amplifier output is high impedance.
Reference Voltage (REF)
The reference voltage is nominally 1.25V, and can
source at least 50/A (see the Typical Operating
Characteristics). V
is the input of the internal refer-
CC
ence block. Bypass REF with a 0.22/F ceramic capaci-
tor connected between REF and AGND.
Fault Protection
During steady-state operation, if the output of the main
regulator or any of the linear-regulator outputs exceed
their respective fault-detection thresholds, the
MAX17075 activates an internal fault timer. If any condi-
tion or combination of conditions indicates a continuous
fault for the fault-timer duration (50ms typ), the
MAX17075 sets the fault latch to shut down all the out-
puts except the reference. Once the fault condition is
removed, cycle the input voltage (below the UVLO
falling threshold) to clear the fault latch and reactivate
the device. The fault-detection circuit is disabled during
the soft-start time.
Power-Up Sequence and Soft-Start
Once the voltage on V
exceeds the XAO UVLO
CC
threshold of approximately 1.5V, the reference turns on.
With a 0.22/F REF bypass capacitor, the reference
reaches its regulation voltage of 1.25V in approximately
1ms. When the reference voltage exceeds 1V and V
CC
exceeds its UVLO threshold of approximately 2.25V,
the IC enables the main step-up regulator, the gate-on
linear-regulator controller, and the gate-off linear-
regulator controller simultaneously.
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. Each output uses a 7-bit
soft-start DAC. For the step-up and the gate-on linear
regulator, the DAC output is stepped in 128 steps from
zero up to the reference voltage. For the gate-off linear
regulator, the DAC output steps from the reference
down to 250mV in 128 steps. The soft-start duration is
10ms (typ) for step-up regulator and 3ms (typ) for gate-
on and gate-off regulators.
V
V
V
VCC
REF
2.25V
1.5V
1V
AVDD
A capacitor (C
) from DEL to AGND determines the
DEL
switch-control-block startup delay. After the input volt-
age exceeds the UVLO threshold (2.25V typ) and the
soft-start routine for each regulator is complete and
there is no fault detected, a 5mA current source starts
SOFT-START
14ms
V
V
COM
charging C
. Once the capacitor voltage exceeds
DEL
1.25V (typ), the switch-control block is enabled as
shown in Figure 8. After the switch-control block is
enabled, COM can be connected to SRC or DRN
through the internal p-channel switches, depending
upon the state of CTL. Before startup and when V is
IN
less than UVLO, DEL is internally connected to AGND
3ms
SOFT-START
POUT
to discharge C
. Select C
to set the delay time
DEL
DEL
using the following equation:
5/A
1.25V
V
V
GOFF
DEL
C
= DELAY _ TIME ×
DEL
1.25V
Undervoltage Lockout (UVLO)
The UVLO circuit compares the input voltage at V
with the UVLO threshold (2.25V rising, 2.20V falling, typ)
to ensure the input voltage is high enough for reliable
operation. The 50mV (typ) hysteresis prevents supply
transients from causing a restart. Once the input voltage
exceeds the UVLO rising threshold, startup begins.
CC
V
GON
SOFT-START BEGINS
INPUT
VOLTAGE
OK
SWITCH
CONTROL
ENABLED
Figure 8. Power-Up Sequence
______________________________________________________________________________________ 17
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
peak current. Finding the best inductor involves choos-
ing the best compromise between circuit efficiency,
inductor size, and cost.
Thermal-Overload Protection
Thermal-overload protection prevents excessive power
dissipation from overheating the MAX17075. When the
junction temperature exceeds +160°C, a thermal sen-
sor immediately activates the fault protection, which
shuts down all outputs except the reference, allowing
the device to cool down. Once the device cools down
by approximately 15°C, cycle the input voltage (below
the UVLO falling threshold) to clear the fault latch and
reactivate the device.
The equations used here include a constant LIR, which
is the ratio of the inductor peak-to-peak ripple current to
the average DC inductor current at the full load current.
The best trade-off between inductor size and circuit
efficiency for step-up regulators generally has an LIR
between 0.3 and 0.6. However, depending on the AC
characteristics of the inductor core material and ratio of
inductor resistance to other power-path resistances, the
best LIR can shift up or down. If the inductor resistance
is relatively high, more ripple can be accepted to
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
decrease losses throughout the power path. If extreme-
ly thin high-resistance inductors are used, as is com-
mon for LCD-panel applications, the best LIR can
increase to between 0.5 and 1.0.
MAX1075
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous opera-
tion, do not exceed the absolute maximum junction
temperature rating of +150°C.
XAO Voltage Detector
Based upon the input at the RSTIN and VCC pins, the
XAO controller either pulls the reset pin RST low or sets
it to high impedance. RST is an open-drain output. Pull
it high to system 3.3V through a 10kΩ resistor. Connect
RSTIN to V through resistor-dividers R11 and R12
IN
(Figure 1) to set the proper XAO threshold.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
Once V
voltage exceeds approximately 2.25V, the
CC
controller initiates a 220ms blanking period during
which the drop on V is ignored and RST is set to
Calculate the approximate inductor value using the typ-
CC
ical input voltage (V ), the maximum output current
IN
high impedance. After this blanking period and if RSTIN
goes below approximately 1.25V, RST is pulled low
(I
)), and the expected efficiency (η
taken
MAIN(MAX
TYP)
from an appropriate curve in the Typical Operating
indicating low RSTIN input. RST stays low until V
falls
CC
Characteristics section, and an estimate of LIR based
below approximately 1V. Then RST cannot be held low
any more. The controller gives up and RST is pulled up
by the external resister. A 50mV hysteresis is imple-
mented for XAO threshold.
on the above discussion:
2
⎛
⎞
⎛
⎞
V
V
− V
× f
η
TYP
LIR
⎛
⎞
IN
AVDD
IN
L
=
⎜
⎝
⎟
AVDD
⎜
⎝
⎟
⎠
⎜
⎟
V
I
⎝
⎠
⎠
AVDD
AVDD(MAX) SW
Design Procedure
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
Step-Up Regulator
rent at the minimum input voltage (V ) using con-
IN(MIN)
Inductor Selection
The minimum inductance value, peak current rating,
and series resistance are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output load capability,
transient-response time, and output voltage ripple. Size
and cost are also important factors to consider.
servation of energy and the expected efficiency at that
operating point (η ) taken from the appropriate curve
MIN
in the Typical Operating Characteristics:
I
× V
AVDD(MAX)
AVDD
I
=
IN(DC,MAX)
V
× η
MIN
IN(MIN)
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the current
ripple, and therefore reduce the peak current, which
decreases core losses in the inductor and conduction
losses in the entire power path. However, large inductor
values also require more energy storage and more turns
of wire, which increase size and can increase conduc-
tion losses in the inductor. Low inductance values
decrease the size, but increase the current ripple and
V
× V
− V
(
)
IN(MIN)
AVDD IN(MIN)
I
=
AVDD_RIPPLE
L
× V
× f
AVDD
AVDD SW
I
AVDD_RIPPLE
2
I
= I
+
AVDD_PEAK IN(DC,MAX)
18 ______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
The inductor’s saturation current rating and the
MAX17075’s LX current limit should exceed I
Input-Capacitor Selection
_
,
The input capacitor (C ) reduces the current peaks
IN
AVDD PEAK
and the inductor’s DC current rating should exceed
drawn from the input supply and reduces noise injec-
tion into the IC. Two 10/F ceramic capacitors are used
in the typical operating circuit (Figure 1) because of the
high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
I
. For good efficiency, choose an inductor with
IN(DC,MAX)
less than 0.1Ω series resistance.
Considering the typical operating circuit, the maximum
load current (I
) is 500mA with a 13V output
AVDD(MAX)
and a typical input voltage of 5V. Choosing an LIR of 0.5
and estimating efficiency of 85% at this operating point:
Typically, C can be reduced below the values used in
IN
2
the typical operating circuit. Ensure a low-noise supply
5V
13V
13V − 5V
0.5A ×1.2MHz
0.85
0.5
⎛
⎞ ⎛
⎞ ⎛
⎞
L
=
≈ 3.35µH
⎜
⎝
⎟ ⎜
⎠ ⎝
⎟ ⎜
⎠ ⎝
⎟
⎠
AVDD
at V
by using adequate C . Alternately, greater volt-
CC
IN
age variation can be tolerated on C if VCC is decou-
IN
pled from C using an RC lowpass filter (see R1 and
IN
Using the circuit’s minimum input voltage (2.5V) and
estimating efficiency of 80% at that operating point:
C5 in Figure 1).
Rectifier Diode
The MAX17075’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 2A Schottky
diode complements the internal MOSFET well.
0.5A ×13V
2.5V × 0.8
I
=
≈ 3.25A
IN(DC,MAX)
The ripple current and the peak current are:
2.5V × 13V − 2.5V
(
)
≈ 0.51A
I
=
RIPPLE
3.3/H ×13V ×1.2MHz
Output Voltage Selection
The output voltage of the step-up regulator can be
adjusted by connecting a resistive voltage-divider from
0.51A
2
I
= 3.25A +
≈ 3.51A
PEAK
the output (V
) to ground with the center tap con-
AVDD
nected to FB (see Figure 1). Select R9 in the 10kΩ to
50kΩ range. Calculate R8 with the following equation:
Output Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohmic ripple due
to the capacitor’s equivalent series resistance (ESR):
⎛
⎝
⎞
⎠
V
AVDD
R8 = R9 ×
−1
⎜
⎟
V
FB
where V , the step-up regulator’s feedback set point,
FB
is 1.25V. Place R8 and R9 close to the IC.
V
= V
+ V
AVDD _RIPPLE
AVDD _RIPPLE(C) AVDD _RIPPLE(ESR)
Loop Compensation
⎛
⎞
I
C
V
V
− V
AVDD
AVDD IN
V
≈
,
Choose R
(R10 in Figure 1) to set the high-fre-
COMP
AVDD_RIPPLE(C)
⎜
⎟
f
⎝
⎠
AVDD
AVDD SW
quency integrator gain for fast-transient response.
Choose C
(C12 in Figure 1) to set the integrator
COMP
and
zero to maintain loop stability.
V
≈ I
R
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
AVDD _RIPPLE(ESR) PEAK ESR _ AVDD
where I
is the peak inductor current (see the
PEAK
Inductor Selection section). For ceramic capacitors, the
output voltage ripple is typically dominated by
AVDD RIPPLE(C)
312.5 × V × V
× C
IN
AVDD
AVDD
R
≈
COMP
L
×I
V
_
. The voltage rating and temperature
AVDD AVDD(MAX)
characteristics of the output capacitor must also be
considered.
V
× C
AVDD
AVDD
C
≈
COMP
10 ×I
R
COMP
AVDD(MAX)
______________________________________________________________________________________ 19
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
To further optimize transient response, vary R
in
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
COMP
20% steps and C
in 50% steps while observing
COMP
transient-response waveforms.
Charge-Pump Regulators
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement.
I
LOAD_CP
C
≥
OUT _CP
2f
V
OSC RIPPLE_CP
The number of positive charge-pump stages is given by:
MAX1075
where C
pump, I
_
is the output capacitor of the charge
OUT CP
V
+ V
− V
− 2 × V
D
GON
DROPOUT AVDD
η
=
POS
_
is the load current of the charge
LOAD CP
V
SUP
pump, and V
is the peak-to-peak value of the
is the switching frequency.
RIPPLE_CP
output ripple, and f
OSC
where n
is the number of positive charge-pump
is the output of the positive charge-pump
is the supply voltage of the charge-
pump regulators, V is the forward voltage drop of the
charge-pump diode, and V
margin for the regulator. Use V
POS
GON
regulator, V
stages, V
Output Voltage Selection
SUP
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from the
REG P output to GND with the center tap connected to
FBP (Figure 1). Select the lower resistor of divider R16
in the 10kΩ to 30kΩ range. Calculate the upper resistor
R15 with the following equation:
D
is the dropout
= 600mV.
DROPOUT
DROPOUT
The number of negative charge-pump stages is given by:
−V + V
GOFF
DROPOUT
η
=
NEG
⎛
⎝
⎞
⎠
V
V
GON
V
− 2 × V
SUP
D
R15 = R16 ×
−1
⎜
⎟
FBP
where n
is the number of negative charge-pump
NEG
stages and V
pump regulator.
where V
= 1.25V (typical).
is the output of the negative charge-
FBP
GOFF
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to V
negative charge pump is connected to ground.
V
to REF with the center tap connected to FBN
GOFF
(Figure 1). Select R6 in the 35kΩ to 68kΩ range.
and the first stage of the
AVDD
Calculate R7 with the following equation:
V
V
− V
GOFF
Flying Capacitors
Increasing the flying capacitor C (connected to DRVN
X
FBN
R7 = R6 ×
− V
REF
FBN
and DRVP) value lowers the effective source impedance
and increases the output current capability. Increasing
the capacitance indefinitely has a negligible effect on
output current capability because the internal switch
resistance and the diode impedance place a lower limit
on the source impedance. A 0.1/F ceramic capacitor
works well in most low-current applications. The flying
capacitor’s voltage rating must exceed the following:
where V
= 250mV, V
= 1.25V. Note that REF can
FBN
REF
only source up to 50/A, using a resistor less than 35kΩ
for R6 results in higher bias current than REF can supply.
Set the XAO Threshold Voltage
XAO threshold voltage can be adjusted by connecting
a resistive voltage-divider from input V to GND with
IN
the center tap connected to RSTIN (see Figure 1).
Select R12 in the 10kΩ to 50kΩ range. Calculate R11
with the following equation:
V
> n× V
SUP
CX
where n is the stage number in which the flying capaci-
tor appears.
⎛
⎞
V
INXAO
R11= R12 ×
−1
⎜
⎟
V
⎝
⎠
RSTIN
where V
INXAO
R11 and R12 close to the IC.
, the RSTIN threshold set point, is 1.25V.
RSTIN
V
is the desired XAO threshold voltage. Place
20 ______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
the operational amplifier divider ground connec-
PCB Layout and Grounding
tions, the COMP and DEL capacitor ground con-
Careful PCB layout is important for proper operation.
nections, and the device’s exposed backside
paddle. Connect the AGND and PGND islands by
connecting the PGND pin directly to the exposed
backside paddle. Make no other connections
between these separate ground planes.
Use the following guidelines for good PCB layout:
•
Minimize the area of high-current loops by placing
the inductor, the output diode, and the output
capacitors near the input capacitors and near the
LX and PGND pins. The high-current input loop
goes from the positive terminal of the input capaci-
tor to the inductor, to the IC’s LX pin, out of PGND,
and to the input capacitor’s negative terminal. The
high-current output loop is from the positive terminal
of the input capacitor to the inductor, to the output
diode (D1), and to the positive terminal of the output
capacitors, reconnecting between the output
capacitor and input capacitor ground terminals.
Connect these loop components with short, wide
connections.
•
•
Place all feedback voltage-divider resistors within
5mm of their respective feedback pins. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Take care to avoid running any feedback trace near
LX or the switching nodes in the charge pumps, or
provide a ground shield.
Place the VCC pin and REF pin bypass capacitors
as close as possible to the device. The ground con-
nection of the VCC bypass capacitor should be
connected directly to the AGND pin with a wide
trace.
•
•
Avoid using vias in the high-current paths. If vias
are unavoidable, use many vias in parallel to
reduce resistance and inductance.
•
•
Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
Create a power-ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all
these together with short, wide traces or a small
ground plane. Maximizing the width of the power
ground traces improves efficiency and reduces out-
put voltage ripple and noise spikes. Create an ana-
log ground plane (AGND) consisting of the AGND
pin, all the feedback-divider ground connections,
Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from feed-
back nodes (FB, FBP, and FBN) and analog
ground. Use DC traces to shield if necessary.
Refer to the MAX17075 evaluation kit for an example of
proper PCB layout.
______________________________________________________________________________________ 21
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
Pin Configuration
Chip Information
PROCESS: Sꢀ5UR
TOP VIEW
18
17
16
15
14
13
Package Information
12
11
10
9
PGND 19
REF
FBN
FBP
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
LX 20
DRN 21
COM 22
MAX1075
MAX17075
RST
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
21-0139
SRC
DEL
8
CTL
23
24
90-0022
2ꢀ TQFN
T2ꢀꢀꢀ+ꢀ
7
DRVN
1
2
3
4
5
6
TQFN
22 ______________________________________________________________________________________
Boost Regulator with Integrated Charge Pumps,
Switch Control, and High-Current Op Amp
MAX1075
Revision History
REVISION REVISION
PAGES
DESCRIPTION
NUMBER
DATE
CHANGED
0
11ꢁ08
Initial release
—
Updated Absolute Maximum Ratings
1
5ꢁ12
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
23 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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