MAX17230ETLR [MAXIM]
2Vâ36V, Synchronous Dual Buck Controller with Integrated Boost and 20μA Quiescent Current;
| 型号： | MAX17230ETLR |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2Vâ36V, Synchronous Dual Buck Controller with Integrated Boost and 20μA Quiescent Current |
| 文件： | 总29页 (文件大小：2022K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
General Description
Benefits and Features
● Eliminates External Components and Reduces Total Cost
• No Schottky-Synchronous Operation for High
EfficiencyꢀandꢀReducedꢀCost
The MAX17230/MAX17231 offers dual synchronous step-
down DC-DC controllers with integrated MOSFETs and a
step-up/boost controller. They operate over a 3.5V to 36V
input voltage range, and down to 2V with the boost controller
active. The devices can operate in dropout condition by
running at 95% duty cycle. The controllers can generate
fixed output voltages of 3.3V/5V, along with the capability
to program the output voltage between 1V to 10V.
• Simple External RC compensation for Stable
Operation at Any Output Voltage
• All-Ceramic Capacitor Solution: Ultra-Compact
Layout
• 180° Out-of-Phase Operation Reduces Output
Ripple and Enables Cascaded Power Supplies
These devices use current-mode-control architecture
and can be operated in the pulse-width modulation
(PWM) or pulse-frequency modulation (PFM) control
schemes. PWM operation provides constant frequency
operation at all loads and is useful in applications
sensitive to switching frequency. PFM operation disables
negative inductor current and additionally skips pulses at
light loads for high-efficiency. The low-resistance, on-chip
MOSFETs ensure high efficiency at full load and simplify
the layout.
● Reduces Number of DC-DC Controllers to Stock
• Fixed Output Voltage with ±1% Accuracy (5V/3.3V)
or Externally Resistor Adjustable (1V to 10V)
• 220kHz to 2.2MHz Adjustable Frequency with
External Synchronization
• Frequency Synchronization Input
● Reduces Power Dissipation
• 92%ꢀPeakꢀEfficiency
• 8μAꢀ(typ)ꢀinꢀShutdown
• 20μAꢀ(typ)ꢀQuiescentꢀCurrentꢀinꢀPFMꢀMode
The MAX17230/MAX17231 include a boost controller.
This boost circuitry turns on during low input voltage
conditions. It is designed to power step-down controller
channels with input voltages as low as 2V.
● Operates Reliably
• 42V Input Voltage Transient Protection
• Cycle-by-Cycle Current Limit, Thermal Shutdown
• Supply Overvoltage and Undervoltage Lockout
• Power-OK Monitor
• Reduced EMI Emission with Spread-Spectrum Control
• 50ns Minimum On-Time Guarantees PWM
Operation at Low Duty Cycle at 2.2MHz
These devices are available in a 40-pin TQFN package
with exposed pad, and are specified for operation over
-40°C to +85°C.
Applications
● Distributed Supply Regulation
● Wall Transformer Regulation
● General-Purpose Point-of-Load
Ordering Information and Selector Guide appear at end of
data sheet.
19-8313; Rev 0; 2/16
MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Typical Application Circuit
BIAS
OUT1
BIAS
BIAS
IN
EN2
OUT1
CS1
FB1
DH2
OUT2
LX2
PGOOD1
COMP1
PGOOD1
BST2
DL2
R
MAX17230/
MAX17231
IN
PGND2
N.C.
DH1
LX1
OUT1
BST1
DL1
BSTON
FSELBST
DL3
EN1
IN
V
IN
BAT
TERM
TERM
Maxim Integrated
│ 2
www.maximintegrated.com
MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Absolute Maximum Ratings
IN, INS, CS3P, CS3N, FB3, EN1, EN2,
LX_ to PGND_ (Note 1) .........................................-0.3V to +42V
EN3, TERM to PGND_.......................................-0.3V to +42V
CS1, CS2, OUT1, OUT2 to AGND ........................-0.3V to +11V
CS1 to OUT1 ........................................................-0.2V to +0.2V
CS2 to OUT2 ........................................................-0.2V to +0.2V
CS3P to CS3N......................................................-0.2V to +0.2V
BIAS, FSYNC, FOSC to AGND.............................-0.3V to +6.0V
COMP1, COMP2, BSTON to AGND.....................-0.3V to +6.0V
FB1, FB2, FSELBST, EXTVCC to AGND..............-0.3V to +6.0V
DL_ to PGND_ (Note 1)........................................-0.3V to +6.0V
BST_ to LX_ (Note 1)...........................................-0.3V to + 6.0V
DH_ to LX_ (Note 1) ............................................-0.3V to + 6.0V
PGND_ to AGND..................................................-0.3V to +0.3V
PGOOD1, PGOOD2 to AGND.......... ...................-0.3V to +6.0V
Continuous Power Dissipation (T = +70NC)
A
TQFN (derate 37mW/NC above +70NC).....................2963mW
QFND (derate 29.4mW/NC above +70NC).................2350mW
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature Range..........................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow)...................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 2)
TQFN
QFND
Junction-to-Ambient Thermal Resistance (q ) ..........34°C/W
Junction-to-Ambient Thermal Resistance (q ) ..........27°C/W
JA
JA
Junction-to-Case Thermal Resistance (q )..............3.9°C/W
Junction-to-Case Thermal Resistance (q ).................1°C/W
JC
JC
Note 1: Self-protected against transient voltages exceeding these limits for ≤ 50ns under normal operation and loads up to the
maximum rated output current.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V = 14V, V
= 5V, C
= 6.8μF, T = T = -40NC to +85NC, unless otherwise noted.) (Note 3)
IN
BIAS
BIAS
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
SYNCHRONOUS STEP-DOWN DC-DC CONVERTERS
Normal operation
t < 1s
3.5
36
42
Supply Voltage Range
V
V
IN
With preboost after initial startup condition
isꢀsatisfied
2.0
36
20
40
V
= V
= V = 0V
EN3
8
EN1
EN2
V
V
= 5V, V
= 5V, V
= V
EN3
= 0V,
= 0V,
EN1
OUT1
EN2
30
= 5V, no switching
EXTVCC
Supply Current
I
µA
V
V
V
= 5V, V
= 3.3V, V
= V
IN
EN2
OUT2
EN1 EN3
20
25
30
40
= 3.3V, no switching
EXTVCC
V
= V
= 5V, V
= 5V, V
= 3.3V,
EN1
EN2
OUT1
OUT2
V
V
V
V
V
= 0V, V
= 3.3V, no switching
EN3
FB1
FB1
FB2
FB2
EXTVCC
= V
= V
= V
= V
, PWM mode
, skip mode
, PWM mode
, skip mode
4.95
4.95
5
5.05
5.075
3.366
3.4
BIAS
BIAS
BIAS
BIAS
Buck 1 Fixed Output Voltage
V
V
OUT1
5
3.234
3.234
3.3
3.3
Buck 2 Fixed Output Voltage
V
V
OUT2
Output Voltage Adjustable Range
Buck 1, buck 2
1
10
Maxim Integrated
│ 3
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Electrical Characteristics (continued)
(V = 14V, V
= 5V, C
= 6.8μF, T = T = -40NC to +85NC, unless otherwise noted.) (Note 3)
IN
BIAS
BIAS
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
0.99
+10
+5
TYP
1.0
MAX
1.01
+20
+15
1
UNIT
Regulated Feedback Voltage
V
V
FB1,2
FB rising
FB falling (Note 4)
T = +25°C
+15
+10
0.01
0.00
Output Overvoltage Threshold
%
Feedback Leakage Current
I
µA
FB1,2
A
Feedback Line Regulation Error
V
= 3.5V to 36V, V = 1V
%/V
IN
FB
Transconductance
(from FB_ to COMP_)
g
V
= 1V, V = 5V (Note 5)
BIAS
1200
2400
µS
ns
m
FB
MAX17231, DL_ low to DH_ high
MAX17231, DH_ low to DL_ high
MAX17230, DL_ low to DH_ high
MAX17230, DH_ low to DL_ high
Buck 1, buck 2
35
60
Dead Time
60
100
Maximum Duty-Cycle
Minimum On-Time
95
%
t
Buck 1, buck 2
50
ns
ON(MIN)
Programmable, high frequency, MAX17231
1
2.2
1
PWM Switching Frequency
Range
MHz
MHz
Programmable, low frequency,
MAX17230
0.2
MAX17231, R
ꢀ=ꢀ13.7kΩ,
FOSC
1.98
360
2.2
2.42
440
V
= 5V
BIAS
Switching Frequency Accuracy
f
SW
MAX17230, R
= 5V
ꢀ=ꢀ80.6kΩ,
FOSC
400
±6
kHz
%
V
BIAS
Spread-Spectrum Range
Spread spectrum enabled
FSYNC INPUT
Minimum sync pulse of 100ns, MAX17231
Minimum sync pulse of 100ns, MAX17230
High threshold
1.2
240
1.5
2.4
MHz
kHz
FSYNC Frequency Range
1200
FSYNC Switching Thresholds
V
Low threshold
0.6
96
CS Current-Limit Voltage
Threshold
V
V
- V
V
= 5V, V ꢀ≥ꢀ2.5V
OUT
64
2
80
15
6
mV
mV
ms
LIMIT1,2
CS
OUT, BIAS
Skip Mode Threshold
Soft-Start Ramp Time
Current sense = 80mV
Buckꢀ1ꢀandꢀbuckꢀ2,ꢀfixedꢀsoft-startꢀtimeꢀ
regardless of frequency
10
Phase Shift Between Buck1 and
Buck 2
180
°
LX1, LX2 Leakage Current
DH1, DH2 Pullup Resistance
DH1, DH2 Pulldown Resistance
V
V
V
= 6V, V
= V , T = +25°C
0.01
10
2
1
20
4
µA
Ω
IN
LX_
IN
A
= 5V, I
= -100mA
= +100mA
BIAS
BIAS
DH_
DH_
= 5V, I
Ω
Maxim Integrated
│ 4
www.maximintegrated.com
MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Electrical Characteristics (continued)
(V = 14V, V
= 5V, C
= 6.8μF, T = T = -40NC to +85NC, unless otherwise noted.) (Note 3)
IN
BIAS
BIAS
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
4
MAX
8
UNIT
Ω
DL1, DL2 Pullup Resistance
V
V
= 5V, I
= 5V, I
= -100mA
= +100mA
BIAS
DL_
DL1, DL2 Pulldown Resistance
1.5
90
85
3
Ω
BIAS
DL_
P
% of V
% of V
, rising
, falling
85
80
95
90
GOOD_H
OUT_
PGOOD1, PGOOD2 Threshold
%
P
GOOD_F
OUT_
PGOOD1, PGOOD2 Leakage
Current
V
= 5V, T = +25°C
0.01
64
1
µA
Cycles
µs
PGOOD1,2
A
PGOOD1, PGOOD2 Startup
Delay Time
Buck 1 and buck 2 after soft-start
is complete
PGOOD1, PGOOD2 Debounce
Time
Fault detection
8
20
40
INTERNAL LDO: BIAS
Internal BIAS Voltage
V
V
V
> 6V
4.75
2.7
5
5.25
3.4
V
V
IN
rising
falling
3.1
2.9
0.2
BIAS
BIAS
BIAS UVLO Threshold
Hysteresis
V
V
External V
Threshold
V
EXTVCC rising, HYST = 110mV
3
3.2
CC
TH,EXTVCC
THERMAL OVERLOAD
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
EN LOGIC INPUT
High Threshold
(Note 5)
(Note 5)
170
20
°C
°C
1.8
V
V
Low Threshold
0.8
1
Input Current
EN1, EN2 logic inputs only, T = +25°C
0.01
µA
A
PREBOOST
Minimum On Time
TON
60
60
ns
ns
BST
Minimum Off Time
Switching Frequency
Current Limit
TOFF
BST
V
V
= 0V, R
=ꢀ13.7kΩ
1.98
0.4
2.2
0.44
120
2.42
0.48
132
FSELBST
FOSC
f
MHz
mV
BOOST
= V
, R
=ꢀ13.7kΩ
FSELBST
BIAS FOSC
I
CS3P - CS3N
One-time latch during startup; preboost
is disabled until the V rises above
108
LIMBST
INS
INS Unlock Threshold
V
1
1.05
1.1
V
INS,UV
this threshold (MAX17231ATLV/V+,
MAX17231ATLW/V+ (Note 6))
Maxim Integrated
│ 5
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Electrical Characteristics (continued)
(V = 14V, V
= 5V, C
= 6.8μF, T = T = -40NC to +85NC, unless otherwise noted.) (Note 3)
IN
BIAS
BIAS
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Battery rising and EN3 high, preboost
turns off if V
(MAX17231ATLV/V+, MAX17231ATLW/V+
is above this threshold
INS
INS Off Threshold
V
1.2
1.25
1.3
INS,OFF
(Note 6))
V
Battery falling and EN3 high, preboost
turns back on when V
this threshold (MAX17231ATLV/V+,
MAX17231ATLW/V+ (Note 6))
falls below
INS
INS On Threshold
V
1.1
1.15
0.35
0.3
1.2
INS,ON,SW
Battery rising and EN3 high
(MAX17231ATLV/V+, MAX17231ATLW/V+
(Note 6))
0.325
0.275
0.375
INS Threshold
Undervoltage Lockout
V
V
INS,UV
Battery falling and EN3 high, preboost
turns off when V
falls below this
INS
0.325
1
threshold (MAX17231ATLV/V+,
MAX17231ATLW/V+ (Note 6))
BSTON Leakage Current
BSTON Debounce Time
DL3 Pullup Resistance
DL3 Pulldown resistance
Feedback Voltage
V
= 5V, T = +25°C
0.01
10
4
µA
µs
Ω
BSTON
A
Fault detection
V
V
= 5V, I
= 5V, I
= -100mA
= +100mA
8
2
BIAS
DL3
1
Ω
BIAS
DL3
V
No load on boost output
0mV < V - V < 120mV,
1.1875
3.5
1.25
1.3125
V
FB3
CS3P
CS3N
Boost Load Regulation Error
EN3 Threshold
0.7
%/A
V
error proportional to input current
High threshold
Low threshold
2
14
150
1
EN3 Input Current
V
= 5.5V
7
µA
Ω
EN3
TERM Resistance
I
= 10mA
= 14V, V
70
TERM
TERM Leakage Current
INS and FB3 Leakage Current
V
= 0V, T = +25°C
0.01
0.01
µA
µA
TERM
EN3
A
T = +25°C
1
A
Note 3: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range and relevant supply volt-
A
age are guaranteed by design and characterization. Typical values are at T = +25°C.
A
Note 4: Overvoltage protection is detected at the FB1/FB2 pins. If the feedback voltage reaches overvoltage threshold of FB1/FB2
+ 15% (typ), the corresponding controllers stop switching. The controllers resume switching once the output drops below
FB1/FB2 + 10% (typ).
Note 5: Guaranteed by design; not production tested.
Note 6: INS pin functionality is disabled for the MAX17231ATLV/V+, MAX17231ATLW/V+. EN3 directly controls the turn-on and
turn-off of the boost controller.
Maxim Integrated
│ 6
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
NO-LOAD STARTUP SEQUENCE
(V = 0V)
FULL-LOAD STARTUP SEQUENCE
(V
= 0V)
FSYNC
FSYNC
toc01
toc02
V
V
BAT
5V/div
BAT
5V/div
V
OUT1
V
OUT1
2V/div
2V/div
I
OUT1
2A/div
V
OUT2
2V/div
V
PGOOD1
5V/div
V
PGOOD1
V
OUT2
5V/div
2V/div
I
OUT2
V
PGOOD2
2A/div
V
5V/div
PGOOD2
5V/div
2ms/div
4ms/div
QUIESCENT CURRENT
vs. TEMPERATURE
QUIESCENT CURRENT
vs. SUPPLY VOLTAGE
BUCK 1 EFFICIENCY
100
90
80
70
60
60
50
40
80
EXTVCC = V
= 2.2MHz
L = 2.2µH
OUT1
f
SW
V
V
= V
BAT
EN1
70
60
50
= 0V
EN2
V
V
= 14V
BAT
EXTVCC = V
OUT1
= 5V
OUT1
EXTVCC =
GND
SKIP MODE
EXTVCC =
GND
BUCK 1
50
40
30
20
10
30
20
10
40
30
EXTVCC = V
OUT2
EXTVCC =
V
OUT1
20
10
V
EN2
= 0V
BUCK 2
EN1
PWM MODE
V
= V
EXTVCC = V
BAT
OUT2
EXTVCC = V
OUT2
0
0
0
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
-60 -40 -20
0
20 40 60 80 100 120 140
0
5
10 15 20 25 30 35 40
SUPPLY VOLTAGE (V)
I
(A)
TEMPERATURE (°C)
OUT1
SWITCHING FREQUENCY
vs. LOAD CURRENT
SWITCHING FREQUENCY
vs. R (MAX17231)
BUCK 2 EFFICIENCY
FOSC
2.30
2.28
2.26
2.24
2.22
100
90
80
70
60
EXTVCC = V
= 2.2MHz
L = 2.2µH
OUT2
f
SW
2.4
2.2
BUCK 2
BUCK 1
V
V
= 14V
BAT
= 3.3V
OUT2
2.0
1.8
1.6
1.4
1.2
1.0
V
BIAS
= 5V
EXTVCC =
GND
SKIP MODE
2.20
2.18
2.16
2.14
2.12
50
40
30
20
10
EXTVCC =
GND
EXTVCC =
V
OUT2
V
BIAS
= 3.3V
PWM MODE
2.10
0
0
2
3
4
5
6
10
15
20
25
30
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
LOAD CURRENT (A)
R
(kΩ)
FOSC
I
(A)
OUT1
Maxim Integrated
│
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
SWITCHING FREQUENCY
SWITCHING FREQUENCY
vs. TEMPERATURE
vs. R
(MAX17230)
FOSC
1.1
2.40
2.35
2.30
R
= 13.7kΩ
FOSC
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
2.25
2.20
V
= 5V
BIAS
2.15
2.10
2.05
2.00
V
BIAS
= 3.3V
30 40 50 60 70 80 90 100 110 120 130 140 150 160 170
(kΩ)
-60 -40 -20
0
20 40 60 80 100 120 140
R
TEMPERATURE (ºC)
FOSC
LOAD TRANSIENT RESPONSE
EXTERNAL FSYNC TRANSITION
DIPS AND DROPS
toc11
toc12
toc13
V
V
BAT
LX1
10V/div
10V/div
V
OUT1
V
100mV/div
LX2
10V/div
V
PGOOD1
5V/div
I
OUT1
V
V
FSYNC
OUT1
1A/div
2V/div
5V/div
400µs/div
400ns/div
40ms/div
LOAD DUMP
SLOW V RAMP
IN
SHORT-CIRCUIT RESPONSE
toc14
toc15
toc16
V
BAT
5V/div
V
BAT
10V/div
I
OUT1
2A/div
V
OUT2
V
OUT1
1V/div
2V/div
V
PGOOD1
5V/div
V
OUT2
V
OUT1
V
PGOOD2
2V/div
1V/div
V
2V/div
5V/div
V
PGOOD2
5V/div
PGOOD1
LOAD DUMP, PWM
100ms/div
10s/div
200µs/div
Maxim Integrated
│ 8
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
OUTPUT OVERVOLTAGE RESPONSE
BUCK 1 LOAD REGULATION
toc17
4.998
4.997
4.996
4.995
4.994
4.993
4.992
4.991
4.990
4.989
V
= V
BIAS
FSYNC
V
OUT1
1V/div
V
2V/div
PGOOD1
1s/div
0
1
2
3
4
5
6
I
(A)
OUT_
BUCK 2 LOAD REGULATION
V
vs. TEMPERATURE
FB1 LINE REGULATION
OUT_
3.297
3.296
3.295
3.294
3.293
100.10
1.010
1.005
1.000
V
OUT2
V
= V
FSYNC
BIAS
EXTVCC = V
V
OUT1
=1.8V
GND
BIAS
V
= V
100.05
100.00
FSYNC
I
=0A
OUT_
V
OUT1
99.95
99.90
99.85
99.80
99.75
99.70
3.292
3.291
0.995
0.990
3.290
3.289
0
1
2
3
4
5
6
-60 -40 -20
0
20 40 60 80 100 120 140
0
5
10 15 20 25 30 35 40
I
(A)
TEMPERATURE (ºC)
V
(V)
OUT_
SUP
FB2 LINE REGULATION
MINIMUM ON-TIME (BUCK 1)
toc23
1.010
I
= 300mA
V
OUT1
= 1.8V
OUT1
1.005
1.000
V
BAT
5V/div
0.995
0.990
V
OUT1
1V/div
0
5
10 15 20 25 30 35 40
(V)
200ns/div
V
SUP
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
MINIMUM ON-TIME (BUCK 2)
BOOST CONTROLLER ON
BOOST ENABLE
toc24
toc25
toc26
I
= 300mA
OUT2
V
BAT
V
10V/div
V
5V/div
V
5V/div
V
5V/div
V
5V/div
V
5V/div
V
BAT
5V/div
IN
BSTON
V
BAT
5V/div
OUT1
V
IN
5V/div
PGOOD1
V
V
SNS
OUT1
OUT2
1V/div
1V/div
V
PGOOD2
BSTON
5V/div
5V/div
200ns/div
400ms/div
2s/div
LX WAVEFORMS
PREBOOST LOAD REGULATION
toc27
9.95
I
= I
= 1A
OUT1 OUT2
V
= 7V
BAT
9.90
9.85
9.80
9.75
9.70
V
LX1
5V/div
V
LX2
5V/div
9.65
9.60
9.55
9.50
V
LXBST
5V/div
200ns/div
0
1
2
3
4
5
6
I
(A)
OUT_
SPECTRAL ENERGY DENSITY
vs. FREQUENCY
SPECTRAL ENERGY DENSITY
vs. FREQUENCY
SPECTRAL ENERGY DENSITY
vs. FREQUENCY
50
40
30
20
40
35
30
25
20
15
MEASURED ON THE MAX17231ATLS/V+
MEASURED ON THE MAX17230ATLS/V+
MEASURED AT V
ON
THE MAX17231ATLU/V+
OUT2
35
30
25
20
15
10
5
10
5
10
0
0
0
-5
-5
-10
-10
-10
300 320 340 360 380 400 320 440 460 480 500
FREQUENCY (kHz)
800k
960k
1.0M
1.1M
1.2M
1.8
2.0
2.2
2.4
2.6
FREQUENCY (Hz)
FREQUENCY (MHz)
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Pin Configuration
TOP VIEW
30 29 28 27 26 25 24 23 22 21
DH2 31
20 PGOOD2
19 PGND3
18 DL3
BST2 32
FSELBST 33
BSTON 34
EN2 35
17 TERM
16 CS3N
15 CS3P
14 INS
MAX17230/
MAX17231
EN1 36
EN3 37
N.C. 38
13 FB3
BST1 39
DH1 40
12 PGOOD1
11 IN
+
1
2
3
4
5
6
7
8
9
10
TQFN/SIDE-WETTABLE QFND
Pin Description
PIN
NAME
FUNCTION
Inductor Connection for Buck 1. Connect LX1 to the switched side of the inductor. LX1 serves as the
lower supply rail for the DH1 high-side gate drive.
1
LX1
2
3
DL1
Low-Side Gate Drive Output for Buck 1. DL1 output voltage swings from V
Power Ground for Buck 1
to V
.
PGND1
BIAS
PGND1
Positive Current-Sense Input for Buck 1. Connect CS1 to the positive terminal of the current-sense
resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement
sections.
4
CS1
Output Sense and Negative Current-Sense Input for Buck 1. When using the internal preset 5V
feedback divider (FB1 = BIAS), the buck uses OUT1 to sense the output voltage. Connect OUT1 to
the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs
and Current-Sense Measurement sections.
5
OUT1
FeedbackꢀInputꢀforꢀBuckꢀ1.ꢀConnectꢀFB1ꢀtoꢀBIASꢀforꢀtheꢀ5Vꢀfixedꢀoutputꢀorꢀtoꢀaꢀresistiveꢀdividerꢀ
between OUT1 and GND to adjust the output voltage between 1V and 10V. In adjustable mode,
FB1 regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section.
6
7
8
FB1
COMP1
BIAS
Buckꢀ1ꢀError-AmplifierꢀOutput.ꢀConnectꢀanꢀRCꢀnetworkꢀtoꢀCOMP1ꢀtoꢀcompensateꢀbuckꢀ1.
5V Internal Linear Regulator Output. Bypass BIAS to GND with a low-ESR ceramic capacitor of 6.8µF
minimum value. BIAS provides the power to the internal circuitry and external loads. See the Fixed 5V
Linear Regulator (BIAS) section.
9
AGND
Signal Ground for IC
10
EXTVCC
3.1V to 5.2V Input to the Switchover Comparator
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Pin Description (continued)
PIN
NAME
FUNCTION
SupplyꢀInput.ꢀConnectꢀINꢀtoꢀtheꢀoutputꢀofꢀtheꢀpreboost.ꢀBypassꢀINꢀwithꢀsufficientꢀcapacitanceꢀtoꢀ
supply the two out-of-phase buck converters.
11
IN
Open-Drain Power-Good Output for Buck 1. PGOOD1 is low if OUT1 is more than 15% (typ) below
the normal regulation point. PGOOD1 asserts low during soft-start and in shutdown. PGOOD1
becomes high impedance when OUT1 is in regulation. To obtain a logic signal, pullup PGOOD1
withꢀanꢀexternalꢀresistorꢀconnectedꢀtoꢀaꢀpositiveꢀvoltageꢀlowerꢀthanꢀ5.5V.ꢀPlaceꢀaꢀminimumꢀofꢀ100Ωꢀ
12
13
14
PGOOD1
FB3
(R
) in series with PGOOD1. See the Voltage Monitoring (PGOOD_) section for details.
PGOOD1
Preboost Feedback Input. Connect FB3 to the center tap of a resistive-divider between the boost
regulator output and TERM to adjust the output voltage. FB3 regulates to 1.25V (typ). Ensure that the
parallelꢀcombinationꢀofꢀtheꢀresistor-dividerꢀnetworkꢀisꢀ>ꢀ500Ω.ꢀSeeꢀtheꢀSetting the Output Voltage in
Boost Converter section.
Input Voltage Sense for Preboost. The voltage at INS is compared to internal comparator reference.
Program the preboost threshold by using resistor-divider from BAT to INS to TERM pin. Ensure that
the parallel combination of the resistor-divider network is > 500W. For the MAX17231ATLV/V+ and
MAX17231ATLW/V+, the INS functionality is disabled; however, the INS pin should still be connected
INS
using the resistor-divider between V
and the TERM pin.
BAT
Positive Current-Sense Input for Preboost. Connect CS3P to the positive terminal of the current-
sense resistor. See the Current Limit in Boost Controller and Shunt Resistor Selection in Boost
Converter sections.
15
16
CS3P
CS3N
Negative Current-Sense Input for Preboost. Connect CS3N to the negative terminal of the current-
sense resistor. See the Current Limit in Boost Controller and Shunt Resistor Selection in Boost
Converter sections.
Ground Switch. TERM opens when the voltage at EN3 is logic-low. Use TERM to terminate the
preboost feedback and INS resistive divider.
17
18
19
TERM
DL3
Preboost nMOSFET Gate-Drive Output
Power Ground for Preboost. All the high-current paths for the preboost should terminate to this
ground.
PGND3
Open-Drain Power-Good Output for Buck 2. PGOOD2 is low if OUT2 is more than 90% (typ) below
the normal regulation point. PGOOD2 asserts low during soft-start and in shutdown. PGOOD2
becomes high impedance when OUT2 is in regulation. To obtain a logic signal, pullup PGOOD2 with
an external resistor connected to a positive voltage lower than 5.5V.
20
PGOOD2
21, 38
22
N.C.
No Connection
External Clock Synchronization Input. Synchronization to the controller operating frequency ratio is
FSYNC
1. Keep f
a minimum of 10% greater than the maximum internal switching frequency for stable
SYNC
operation. See the Switching Frequency/External Synchronization section.
Frequency Setting Input. Connect a resistor from FOSC to AGND to set the switching frequency of
the DC-DC converters.
23
24
FOSC
COMP2
Buckꢀ2ꢀErrorꢀAmplifierꢀOutput.ꢀConnectꢀanꢀRCꢀnetworkꢀtoꢀCOMP2ꢀtoꢀcompensateꢀbuckꢀ2.
FeedbackꢀInputꢀforꢀBuckꢀ2.ꢀConnectꢀFB2ꢀtoꢀBIASꢀforꢀtheꢀ3.3Vꢀfixedꢀoutputꢀorꢀtoꢀaꢀresistiveꢀdividerꢀ
between OUT2 and GND to adjust the output voltage between 1V and 10V. In adjustable mode, FB2
regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section.
25
FB2
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Pin Description (continued)
PIN
NAME
FUNCTION
Output Sense and Negative Current-Sense Input for Buck 2. When using the internal preset 3.3V
feedback-divider (FB2 = BIAS), the buck uses OUT2 to sense the output voltage. Connect OUT2 to
the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs
and Current-Sense Measurement sections.
26
OUT2
Positive Current-Sense Input for Buck 2. Connect CS2 to the positive terminal of the current-sense
resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement
sections.
27
CS2
28
29
PGND2
DL2
Power Ground for Buck 2
Low-Side Gate Drive Output for Buck 2. DL2 output voltage swings from V
to V
.
PGND2
BIAS
Inductor Connection for Buck 2. Connect LX2 to the switched side of the inductor. LX2 serves as the
lower supply rail for the DH2 high-side gate drive.
30
31
LX2
DH2
High-Side Gate Drive Output for Buck 2. DH2 output voltage swings from V
to V
.
LX2
BST2
Boost Capacitor Connection for High-Side Gate Voltage of Buck 2. Connect a high-voltage diode
between BIAS and BST2. Connect a ceramic capacitor between BST2 and LX2. See the High-Side
Gate-Driver Supply (BST_) section.
32
33
34
BST2
FSELBST
BSTON
Frequency Select Pin for the Preboost. When pulled low, the preboost will have the same switching
frequency as buck 1. When pulled high, the preboost will have a switching frequency that is 1/5th that
of buck 1. FSELBST is only active for the MAX17231. FSELBST should be connected to ground for
the MAX17230.
Preboost On-Indicator Output. To obtain a logic signal, pull up BSTON with an external resistor
connected to a positive voltage lower than 5.5V. BSTON goes high to indicate that the preboost
is on.
High-Voltage Tolerant, Active-High Digital Enable Input for Buck 2. Driving EN2 high enables
buck 2.
35
36
EN2
EN1
High-Voltage Tolerant, Active-High Digital Enable Input for Buck 1. Driving EN1 high enables
buck 1.
High-Voltage Tolerant, Active-High Digital Enable Input for Preboost. When EN3 is high, the external
37
EN3
preboost is enabled and begins switching if V
drops below V
and required conditions are
INS,OLV
INS
met (see the Preboost section).
Boost Capacitor Connection for High-Side Gate Voltage of Buck 1. Connect a high-voltage diode
between BIAS and BST1. Connect a ceramic capacitor between BST1 and LX1. See the High-Side
Gate-Driver Supply (BST_) section.
39
40
BST1
DH1
High-Side Gate-Drive Output for Buck 1. DH1 output voltage swings from V
to V
.
LX1
BST1
Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not
remove the requirement for proper ground connections to PGND1, PGND2, PGND3, and AGND. The
exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove
heat from the IC.
—
EP
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
EXTVCC Switchover
Detailed Description
The internal linear regulator can be bypassed by connecting
an external supply (3V to 5.2V) or the output of one of the
buck converters to EXTVCC. BIAS internally switches to
EXTVCC and the internal linear regulator turns off. This
configuration has several advantages:
The MAX17230/MAX17231 are automotive-rated triple-output
switching power supplies. These devices integrate two
synchronous step-down controllers and an non-synchronous
step-up controller and can provide up to three independently
controlled power rails as follows:
● It reduces the internal power dissipation of the
● A boost controller with adjustable output voltage.
MAX17230/MAX17231.
● A buck controller with a fixed 5V output voltage or an
● The low-load efficiency improves as the internal supply
adjustable 1V to 10V output voltage.
current gets scaled down proportionally to the duty cycle.
● A buck controller with a fixed 3.3V output voltage or
If V
drops below V
= 3.0V (min), the
an adjustable 1V to 10V output voltage.
EXTVCC
TH,EXTVCC
internal regulator enables and switches back to BIAS.
The buck controllers and the preboost can each provide up
to 10A output current and are independently controllable.
Undervoltage Lockout (UVLO)
Buck 1, buck 2, and the preboost are enabled and disabled
by the EN1, EN2, EN3 control inputs, respectively. These
are active-high inputs and can be connected directly to car
battery.
The BIAS input undervoltage-lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (BIAS) is below its
2.9V (typ) UVLO falling threshold. Once the 5V bias supply
(BIAS) rises above its UVLO rising threshold and EN1
and EN2 enable the buck controllers, the controllers start
switching and the output voltages begin to ramp up using
soft-start.
● EN1 and EN2 enable the respective buck controllers.
Connect EN1 and EN2 directly to V
supply sequencing logic.
or to power-
BAT
● EN3 controls the boost controller.
Buck Controllers
The devices provide two buck controllers with synchronous
rectification. The step-down controllers use a PWM, current-
mode control scheme. External logic-level MOSFETs allow
for optimized load-current design. Fixed-frequency operation
with optimal interleaving minimizes input ripple current from
the minimum to the maximum input voltages. Output-current
sensing provides an accurate current limit with a sense
resistor or power dissipation can be reduced using lossless
current sensing across the inductor.
In standby mode (only buck 2 is active), the total supply
current is reduced to 30µA (typ). When all three controllers
are disabled, the total current drawn is further reduced to
6.8µA.
Fixed 5V Linear Regulator (BIAS)
The internal circuitry of the devices require a 5V bias supply.
An internal 5V linear regulator (BIAS) generates this bias
supply. Bypass BIAS with a 6.8µF or greater ceramic
capacitor to guarantee stability under the full-load condition.
Soft-Start
The internal linear regulator can source up to 100mA
(150mA under EXTVCC switchover, see the EXTVCC
Switchover section). Use the following equation to estimate
the internal current requirements for the devices:
Once a buck converter is enabled by driving the
corresponding EN_ high, the soft-start circuitry gradually
ramps up the reference voltage during soft-start time
(t
= 6ms (typ)) to reduce the input surge currents
SSTART
I
= I
+ f (Q
+ Q
+ Q
+
BIAS
CC
SW G_DL3
G_DH1
G_DL1
during startup. Before the device can begin the soft-start,
the following conditions must be met:
Q
+ Q
) = 10mA to 50mA (typ)
G_DH2
G_DL2
where I
is the internal supply current, 5mA (typ), f
SW
CC
1) V
exceeds the 3.4V (max) undervoltage lockout
BIAS
is the switching frequency, and Q
total gate charge (specification limits at V
minimize the internal power dissipation, bypass BIAS to
an external 5V rail.
is the MOSFET’s
G_
threshold.
= 5V). To
GS
2) V is logic-high.
EN_
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Forced-PWM mode is useful for improving load-transient
response and eliminating unknown frequency harmonics
that can interfere with AM radio bands.
Switching Frequency/External Synchronization
The MAX17231 provides an internal oscillator adjustable
from 1MHz to 2.2MHz. The MAX17230 provides an
internal oscillator adjustable from 200kHz to 1MHz.
High-frequency operation optimizes the application for
the smallest component size, trading off efficiency to
higher switching losses. Low-frequency operation offers
the best overall efficiency at the expense of component
size and board space. To set the switching frequency,
Maximum Duty-Cycle Operation
The devices have a maximum duty cycle of 95%. The internal
logic of the IC looks for approximately 8 to 10 consecutive
high-side FET ON pulses and decides to turn ON the low-
sideꢀFETꢀforꢀ150nsꢀ(typ)ꢀeveryꢀ12μs.ꢀTheꢀinputꢀvoltageꢀatꢀ
which the devices enter dropout changes depending on the
input voltage, output voltage, switching frequency, load current,
and the efficiency of the design. The input voltage at which
the devices enter dropout can be approximated as:
connect a resistor R
from FOSC to AGND. See
FOSC
TOCs 8 and 9 in the Typical Operating Characteristics
section to determine the relationship between switching
frequency and R
.
FOSC
V
OUT
= [V
+ (I
x R )]/0.95
ON_H
OUT
OUT
Buck 1 and the boost converter are synchronized with
the internal clock-signal rising edge, while buck 2 is
synchronized with the clock-signal falling edge. The
preboost enables the low-side switch (DL3) with the
rising edge of the cycle while buck 1 turns on its high-side
nMOSFET (DH1).
Note: The above equation does not take into account the
efficiency and switching frequency, but is a good first-order
approximation. Use the R
sheet of the high-side MOSFET used.
max number from the data
ON_H
Spread Spectrum
The devices can be synchronized to an external clock by
connecting the external clock signal to FSYNC. A rising
edge on FSYNC resets the internal clock. Keep the FSYNC
frequency between 110% and 125% of the internal
frequency. The FSYNC signal should have a 50% duty cycle.
The MAX17231AGLS/MAX17231AGLU/MAX17230AGLS
feature enhanced EMI performance. They perform Q6%
dithering of the switching frequency to reduce peak emission
noise at the clock frequency and its harmonics, making it
easier to meet stringent emission limits. When using an
external clock source (i.e., driving the FSYNC input with
an external clock), spread spectrum is disabled.
Light-Load Efficiency Skip Mode (V
= 0V)
FSYNC
Drive FSYNC low to enable skip mode. In skip mode, the
devices stop switching until the FB voltage drops below
the reference voltage. Once the FB voltage has dropped
below the reference voltage, the devices begin switching
until the inductor current reaches 30% (skip threshold)
of the maximum current defined by the inductor DCR or
output shunt resistor.
MOSFET Gate Drivers (DH_ and DL_)
The DH_ high-side nMOSFET drivers are powered from
capacitors at BST_ while the low-side drivers (DL_) are
powered by the 5V linear regulator (BIAS). On each chan-
nel, a shoot-through protection circuit monitors the gate-
to-source voltage of the external MOSFETs to prevent a
MOSFET from turning on until the complementary switch
is fully off. There must be a low-resistance, low-inductance
path from the DL_ and DH_ drivers to the MOSFET gates
for the protection circuits to work properly. Follow the
instructions listed to provide the necessary low-resistance
and low-inductance path:
Forced-PWM Mode (V
)
FSYNC
Driving FSYNC high prevents the devices from entering
skip mode by disabling the zero-crossing detection of
the inductor current. This forces the low-side gate-driver
waveform to constantly be the complement of the high-
side gate-drive waveform, so the inductor current revers-
es at light loads and discharges the output capacitor. The
benefit of forced PWM mode is to keep the switching
frequency constant under all load conditions. However,
forced-frequency operation diverts a considerable amount
of the output current to PGND, reducing the efficiency
under light-load conditions.
● Use very short, wide traces (50 mils to 100 mils wide
if the MOSFET is 1in from the driver).
It may be necessary to decrease the slew rate for the
gate drivers to reduce switching noise or to compensate
for low-gate charge capacitors. For the low-side drivers,
use gate capacitors in the range of 1nF to 5nF from DL_
to GND. For the high-side drivers, connect a small 5I to
10I resistor between BST_ and the bootstrap capacitor.
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
can also be measured directly across the inductor. This
Note: Gate drivers must be protected during shutdown,
at the absence of the supply voltage (V = 0V) when
the gate is pulled high either capacitively or by the leakage
path on the PCB. Therefore, external gate pulldown resistors
are needed, especially at DL3 to prevent making a direct
method could cause up to 30% error over the entire
temperature range and requires a filter network in the
current-sensecircuit.SeetheCurrent-SenseMeasurement
section.
BIAS
path from V
to GND.
BAT
Voltage Monitoring (PGOOD_)
The MAX17230/MAX17231 include several power
monitoring signals to facilitate power-supply sequencing
and supervision. PGOOD_ can be used to enable circuits
that are supplied by the corresponding voltage rail, or to
turn on subsequent supplies.
High-Side Gate-Driver Supply (BST_)
The high-side MOSFET is turned on by closing an inter-
nal switch between BST_ and DH_ and transferring the
bootstrap capacitor’s (at BST_) charge to the gate of the
high-side MOSFET. This charge refreshes when the high-
side MOSFET turns off and the LX_ voltage drops down to
ground potential, taking the negative terminal of the capaci-
tor to the same potential. At this time the bootstrap diode
recharges the positive terminal of the bootstrap capacitor.
Each PGOOD_ goes high (high impedance) when the
corresponding regulator output voltage is in regulation.
Each PGOOD_ goes low when the corresponding
regulator output voltage drops below 15% (typ) or rises
above 15% (typ) of its nominal regulated voltage. Connect
a 10kI(typ) pullup resistor from PGOOD_ to the relevant
logic rail to level-shift the signal. PGOOD_ asserts low
during soft-start, soft-discharge, and when either buck
converter is disabled (either EN1 or EN2 is low). To
ensure latchup immunity on the PGOOD1 pin, a minimum
resistance of 100I should be placed between the
PGOOD1 pin and any other external components.
The selected n-channel high-side MOSFET determines the
appropriate boost capacitance values (C
in the Typical
Operating Circuit) according to the following equation:
BST_
V
× t
[s] × f [Hz]
SW
IN
ON,MIN
+ R
I
<
FAULT
R
+ R
SH
DCR
ON
where Q is the total gate charge of the high-side
G
MOSFET and DV
the high-side MOSFET driver after turn-on. Choose
is the voltage variation allowed on
BST_
Preboost
The MAX17230/MAX17231 include an non-synchronous
current-mode preboost with adjustable output. This
preboost can be used independently, but is ideally suited
for applications that need to stay fully functional during
input voltage dropouts typical in systems that have an the
input voltage that varies over a wide range and where the
input voltage can drop below the output voltage.
DV such that the available gate-drive voltage is not
BST_
significantly degraded (e.g., DV
= 100mV to 300mV)
BST_
. The boost capacitor should be
when determining C
BST_
a low-ESR ceramic capacitor. A minimum value of 100nF
works in most cases.
Current Limiting and Current-Sense Inputs
(OUT_ and CS_)
The current-limit circuit uses differential current-sense
inputs (OUT_ and CS_) to limit the peak inductor current.
If the magnitude of the current-sense signal exceeds the
The preboost is turned on by bringing EN3 high and
meeting the INS requirement.
EN3 can be used for power-supply sequencing and
implementing a boost timeout to prevent overheating the
components used for the boost converter.
current-limit threshold (V
= 80mV (typ)), the PWM
LIMIT1,2
controller turns off the high-side MOSFET. The actual
maximum load current is less than the peak current-limit
threshold by an amount equal to half of the inductor ripple
current. Therefore, the maximum load capability is a
function of the current-sense resistance, inductor value,
While the boost circuit is essential to maintain functionality
during undervoltage events, it reduces system efficiency.
During normal operation, the boost diode dissipates
power and the resistive dividers at INS and FB3 sink
significant amounts of quiescent current. To ensure latch-
up immunity on the INS and FB3 pins, ensure that the
parallel combination of this resistor-divider network used
onꢀtheseꢀpinsꢀisꢀ>ꢀ500ω.
switching frequency, and duty cycle (V /V ).
OUT_ IN
For the most accurate current sensing, use a current-
sense shunt resistor (R ) between the inductor and the
SH
output capacitor. Connect CS_ to the inductor side of R
SH
and OUT_ to the capacitor side. Dimension R
such that
SH
the maximum inductor current (I
= I +1/2
LOAD,MAX
L,MAX
I ) induces a voltage of V
RIPPLE,PP
across R
LIMIT1,2 SH
including all tolerances. For higher efficiency, the current
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Supply Monitoring (INS)
Current Limit in Boost Controller
The devices include a dedicated voltage sensor at INS to
quickly detect overvoltage and undervoltage for the boost
converter input power.
A current-sense resistor (R ), connected CS3P and
CS3N, sets the current limit of the boost converter. The
CS
CS input has a voltage trip level (V ) of 120mV (typ).
CS
The low 120mV current-limit threshold reduces the power
dissipation in the current-sense resistor. Use a current-
sense filter to reduce capacitive coupling during turn
on. See the Shunt Resistor Selection in Boost Converter
section.
The boost converter turns off when EN3 is low. When
EN3 is high AND:
● INS voltage rises above 0.35V or falls below 1.15V
(normal input range): Boost turns on
● INS voltage rises above 1.25V or falls below 0.3V
(OV or UV): Boost turns off
Thermal-Overload, Overcurrent, and
Overvoltage and Undervoltage Behavior
Connect INS to the center tap of a resistive divider from
the input voltage (battery) to TERM to set the proper turn-
on/turn-off of the preboost. If this setting is not sufficient,
optimize the divider for the most critical level. For the
MAX17231ATLV/V+ and MAX17231ATLW/V+, the INS
pin functionality is disabled; however, the INS pin should
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation
in the devices. When the junction temperature exceeds
+170NC, an internal thermal sensor shuts down the
devices, allowing them to cool. The thermal sensor turns
on the devices again after the junction temperature cools
by 20NC.
still be connected using the resistor-divider between V
and the TERM pin, as explained above.
BAT
Increasing the Efficiency of the Boost Circuit
(TERM)
The MAX17230/MAX17231 provide a feature to improve
the efficiency of the boost circuit when it is not active:
Overcurrent Protection
If the inductor current on the MAX17231 and MAX17230
exceed the maximum current limit programmed at
CS_ and OUT_, the respective driver turns off. In an
overcurrent mode, this results in shorter and shorter high-
side pulses.
● TERM provides a switch to GND for the INS and FB3
voltage-dividers. This switch opens during standby
mode and shutdown mode to reduce the quiescent
current by 240µA, assuming that resistors used in the
voltage-divider network are in the range of 100kI.
A hard short results in a minimum on-time pulse every
clock cycle.
Choose the components so they can withstand the short-
circuit current if required.
Preboost nMOSFET Driver (DL3)
DL3 drives the gate of an external nMOSFET. The driver
is powered by the 5V (typ) internal regulator (BIAS) or
the external bypass supply (EVTVCC). DL3 asserts low
during standby mode.
Overvoltage Protection
The devices limit the output voltage of the buck converters
by turning off the high-side gate driver at approximately
115% of the regulated output voltage. The output voltage
needs to come back in regulation before the high-side gate
driver starts switching again.
Switching Frequency in Boost Controller
The preboost switching frequency (f ) is derived
BOOST
from the buck controllers switching frequency (f ) by
SW
setting FOSC. See the Electrical Characteristics table.
On the MAX17231, f
can be set equal to f
by
BOOST
SW
connecting FBSTSEL to ground or to 1/5f
by connect-
SW
ing FBSTSEL to BIAS. The gate driver of the preboost
turns on simultaneously with the high-side driver of buck
1. FSELBST should be connected to ground on the
MAX17230.
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Design Procedure
DC output accuracy specifications in the Electrical
Characteristics table refer to the error comparator’s threshold,
Buck Converter Design Procedure
Effective Input Voltage Range in Buck Converters
Although the MAX17230/MAX17231 can operate from
input supplies up to 36V (42V transients) and regulate
V
FB_
= 1V (typ). When the inductor conducts continuously,
the devices regulate the peak of the output ripple, so the
actual DC output voltage is lower than the slope-compensated
trip level by 50% of the output ripple voltage.
down to 1V, the minimum voltage conversion ratio (V
/
OUT
In discontinuous conduction mode (skip or STDBY active
V ) might be limited by the minimum controllable on-
IN
and I
< I ), the devices regulate the valley of
OUT
LOAD(SKIP)
time. For proper fixed-frequency PWM operation and
optimal efficiency, buck 1 and buck 2 should operate in
continuous conduction during normal operating conditions.
For continuous conduction, set the voltage conversion ratio
as follows:
the output ripple, so the output voltage has a DC regulation
level higher than the error-comparator threshold.
Inductor Selection in Buck Converters
Three key inductor parameters must be specified for
operation with the MAX17230/MAX17231: inductance
V
OUT
> t
× f
SW
ON(MIN)
value (L), inductor saturation current (I ), and DC resistance
SAT
V
IN
(R
). To determine the optimum inductance, knowing
DCR
the typical duty cycle (D) is important.
where t
ON(MIN)
is 50ns (typ) and f
is the switching
SW
frequency in Hz. If the desired voltage conversion does not
meet the above condition, pulse skipping occurs to
decrease the effective duty cycle. Decrease the switching
frequency if constant switching frequency is required. The
same is true for the maximum voltage conversion ratio.
V
V
OUT
OUT
D =
OR D =
V
V
−I
(R
+ R
)
DCR
IN
IN OUT DS(ON)
if the R
of the inductor and R
of the MOSFET
DCR
DS(ON)
are available with V = (V
should be typical to optimize the design for normal operation.
- V
). All values
IN
BAT
DIODE
The maximum voltage conversion ratio is limited by the
maximum duty cycle (95%).
Inductance
V
OUT
The exact inductor value is not critical and can be
adjusted in order to make trade-offs among size, cost,
efficiency, and transient response requirements.
< 0.95
V
− V
DROP
IN
where V
= I
(R
+ R
) is the sum of the
DCR
DROP
OUT ON,HS
●
Lower inductor values increase LIR, which minimizes
size and cost and improves transient response at the
cost of reduced efficiency due to higher peak currents.
parasitic voltage drops in the high-side path and f
is
SW
the programmed switching frequency. During low drop
operation, the devices reduce f to 25% (max) of the
SW
programmed frequency. In practice, the above condition
should be met with adequate margin for good load-transient
response.
● Higher inductance values decrease LIR, which
increases efficiency by reducing the RMS current at
the cost of requiring larger output capacitors to meet
load-transient specifications.
Setting the Output Voltage in Buck Converters
Connect FB1 and FB2 to BIAS to enable the fixed buck
controller output voltages (5V and 3.3V) set by a preset
internal resistive voltage-divider connected between the
feedback (FB_) and AGND. To externally adjust the output
voltage between 1V and 10V, connect a resistive divider
from the output (OUT_) to FB_ to AGND (see the Typical
The ratio of the inductor peak-to-peak AC current to DC
average current (LIR) must be selected first. A good initial
value is a 30% peak-to-peak ripple current to average-
current ratio (LIR = 0.3). The switching frequency, input
voltage, output voltage, and selected LIR then determine
the inductor value as follows:
Operating Circuit. Calculate R
and R
with the
FB_1
FB_2
(V − V
IN OUT
)xD
xLIR
following equation:
L[µH] =
f
[MHz]xI
OUT
SW
V
OUT_
R
= R
−1
FB_1
FB_2
V
FB_
where V , V
, and I
are typical values (so that
IN
OUT
OUT
efficiency is optimum for typical conditions).
where V
table).
= 1V (typ) (see the Electrical Characteristics
FB_
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Current-Sense Measurement
Peak Inductor Current
For the best current-sense accuracy and overcurrent
protection, use a ±1% tolerance current-sense resistor
between the inductor and output as shown in Figure 1A.
This configuration constantly monitors the inductor current,
allowing accurate current-limit protection. Use low-inductance
current-sense resistors for accurate measurement.
Inductors are rated for maximum saturation current. The
maximum inductor current equals the maximum load current
in addition to half of the peak-to-peak ripple current:
∆I
INDUCTOR
I
= I
+
LOAD(MAX)
PEAK
2
Alternatively, high-power applications that do not require
highly accurate current-limit protection can reduce the
overall power dissipation by connecting a series RC
circuit across the inductor (Figure 1B) with an equivalent
time constant:
For the selected inductance value, the actual peak-to-peak
inductor ripple current (DI ) is calculated as:
INDUCTOR
V
(V − V
)
OUT IN
V
OUT
∆I
=
INDUCTOR
x f
xL
IN SW
is in mA, L is in µH, and f
R2
R1+ R2
where DI
is in kHz.
INDUCTOR
SW
R
=
R
DCR
CSHL
Once the peak current and the inductance are known, the
inductor can be selected. The saturation current should
and:
be larger than I
or at least in a range where the
PEAK
L
1
1
inductance does not degrade significantly. The MOSFETs
are required to handle the same range of current without
dissipating too much power.
R
=
+
DCR
C
R1 R2
EQ
where R
is the required current-sense resistor and
CSHL
MOSFET Selection in Buck Converters
R
DCR
is the inductor’s series DC resistor. Use the inductance
Each step-down controller drives two external logic-level
n-channel MOSFETs as the circuit switch elements. The
key selection parameters to choose these MOSFETs
include the items in the following sections.
and R
values provided by the inductor manufacturer.
DCR
Carefully observe the PCB layout guidelines to ensure the
noise and DC errors do no corrupt the differential current-
sense signals seen by CS_ and OUT_. Place the sense
resistor close to the devices with short, direct traces,
making a Kelvin-sense connection to the current-sense
resistor.
Threshold Voltage
All four n-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V = 4.5V. If
GS
the internal regulator is bypassed (for example: V
= 3.3V), then the nMOSFETs should be chosen to have
guaranteed on-resistance at that gate-to-source voltage.
EXTVCC
Input Capacitor in Buck Converters
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the input
capacitor must be carefully chosen to withstand the input
ripple current and keep the input voltage ripple within
design requirements. The 180° ripple phase operation
increases the frequency of the input capacitor ripple
current to twice the individual converter switching
frequency. When using ripple phasing, the worst-case
input capacitor ripple current is when the converter with
the highest output current is on.
Maximum Drain-to-Source Voltage (V
)
DS(MAX)
All MOSFETs must be chosen with an appropriate V
DS
rating to handle all V voltage conditions.
IN
Current Capability
The nMOSFETs must deliver the average current to the load
and the peak current during switching. Choose MOSFETs
with the appropriate average current at V
= 4.5V or V
GS
GS
= V
when the internal linear regulator is bypassed.
EXTVCC
The input voltage ripple is composed of DV (caused by
Q
For load currents below approximately 3A, dual MOSFETs in
a single package can be an economical solution. To reduce
switching noise for smaller MOSFETs, use a series resistor
in the BST_ path and additional gate capacitance. Contact
the factory for guidance using gate resistors.
the capacitor discharge) and DV
(caused by the ESR
ESR
of the input capacitor). The total voltage ripple is the sum
of DV and DV that peaks at the end of an on-cycle.
Q
ESR
Calculate the input capacitance and ESR required for a
specific ripple using the following equation:
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
∆V
ESR
ESR[W] =
The internal 5V linear regulator (BIAS) includes an output
UVLO with hysteresis to avoid unintentional chattering
during turn-on. Use additional bulk capacitance if the
input source impedance is high. At lower input voltage,
additional input capacitance helps avoid possible under-
shoot below the undervoltage lockout threshold during
transient loading.
∆I
P− P
I
+
LOAD(MAX)
2
V
OUT
V
I
x
LOAD(MAX)
IN
C
[µF] =
IN
∆V x f
(
)
Q
SW
Output Capacitor in Buck Converters
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. The capacitor
is usually selected by ESR and the voltage rating rather
than by capacitance value.
where:
V
− V
OUT
x V
(
)
IN
OUT
∆I
=
P−P
V
x f
xL
IN SW
I
is the maximum output current in A, DI
is
P-P
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
LOAD(MAX)
the peak-to-peak inductor current in A, f
ing frequency in MHz, and L is the inductor value in µH.
is the switch-
SW
capacity needed to prevent V
and V
from
SAG
SOAR
INPUT (V
IN
)
C
IN
MAX17230/
MAX17231
NH
NL
DH_
R
L
SENSE
LX_
DL_
C
OUT
GND
CS_
OUT_
A) OUTPUT SERIES RESISTOR SENSING
INPUT (V
IN
)
C
IN
MAX17230/
MAX17231
NH
INDUCTOR
DH_
L
DCR
LX_
C
OUT
R1
R2
NL
DL_
R2
C
EQ
R
=
R
DCR
CSHL
GND
(R1 + R2)
L
1
1
+
CS_
R
=
DCR
[ ]
C
R1 R2
EQ
OUT_
B) LOSSLESS INDUCTOR SENSING
Figure 1. Current-Sense Configurartions
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
causing problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the Transient Considerations
section). However, low-capacity filter capacitors typically
have high-ESR zeros that can affect the overall stability.
where D
is the maximum duty factor (approximately
MAX
95%), L is the inductor value in µH, C
capacitor value in µF, t is the switching period (1/f ) in
µs, and Dt equals (V
is the output
OUT
SW
/V ) x t.
OUT IN
The devices use a current-mode-control scheme that
regulates the output voltage by forcing the required current
through the external inductor, so the controller uses the
voltage drop across the DC resistance of the inductor or
the alternate series current-sense resistor to measure the
inductor current. Current-mode control eliminates the double
pole in the feedback loop caused by the inductor and output
capacitor resulting in a smaller phase shift and requiring less
elaborate error-amplifier compensation than voltage-mode
The total voltage sag (V
) can be calculated as follows:
SAG
2
L(∆I
)
LOAD(MAX)
V
=
SAG
2C
((V ×D
) − V
)
OUT
IN
MAX
OUT
∆I
(t − ∆t)
LOAD(MAX)
+
C
OUT
control. A single series resistor (R ) and capacitor (C ) is
C
C
The amount of overshoot (V ) during a full-load to
SOAR
all that is required to have a stable, high-bandwidth loop in
applications where ceramic capacitors are used for output
filtering (see Figure 2). For other types of capacitors, due to
the higher capacitance and ESR, the frequency of the zero
created by the capacitance and ESR is lower than the desired
closed-loop crossover frequency. To stabilize a nonceramic
output capacitor loop, add another compensation capacitor
no-load transient due to stored inductor energy can be
calculated as:
2
(∆I
) L
LOAD(MAX)
V
≈
SOAR
2C
V
OUT OUT
ESR Considerations
(C ) from COMP to AGND to cancel this ESR zero.
F
The output filter capacitor must have low enough
equivalent series resistance (ESR) to meet output
ripple and load-transient requirements, yet have high
enough ESR to satisfy stability requirements. When using
high-capacitance, low-ESR capacitors, the filter
capacitor’s ESR dominates the output-voltage ripple. So
the output capacitor’s size depends on the maximum ESR
The basic regulator loop is modeled as a power
modulator, output feedback divider, and an error
amplifier as shown in Figure 2. The power modulator has
a DC gain set by g x R
, with a pole and zero pair
LOAD
mc
set by R
, the output capacitor (C ), and its ESR.
OUT
LOAD
The loop response is set by the following equations:
required to meet the output-voltage ripple (V
specifications:
)
RIPPLE(P-P)
GAIN
= g
×R
LOAD
MOD(dc)
mc
where R
1/(A
= V
x R ) in S. A
/I
in I and g
is the voltage gain of the
=
mc
V
= ESR xI
xLIR
LOAD(MAX)
LOAD
V_CS DC
OUT LOUT(MAX)
RIPPLE(P−P)
V_CS
current-sense amplifier and is typically 11V/V. R
DC resistance of the inductor or the current-sense
resistor in I.
is the
DC
In standby mode, the inductor current becomes discontinuous,
with peak currents set by the idle-mode current-sense
threshold (V
= 26mV (typ)).
CS,SKIP
In a current-mode step-down converter, the output capacitor
and the load resistance introduce a pole at the following
frequency:
Transient Considerations
The output capacitor must be large enough to absorb
the inductor energy while transitioning from no-load to
full-load condition without tripping the overvoltage fault
protection. The total output-voltage sag is the sum of the
voltage sag while the inductor is ramping up and the voltage
sag before the next pulse can occur. Therefore:
1
f
=
pMOD
2π × C
×R
LOAD
OUT
The unity gain frequency of the power stage is set by C
OUT
and g
:
mc
2
L ∆I
(
)
LOAD(MAX)
gmc
2π × C
OUT
C
=
f
=
OUT
UGAINpMOD
2V
(V xD
− V
)
SAG IN
MAX
OUT
The output capacitor and its ESR also introduce a zero at:
∆I
t − ∆t
(
)
LOAD(MAX)
+
V
SAG
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
1
f
=
pEA
g
= 1/(A
VCS
x R )
DC
2π × C ×R
mc
F
C
CS_
CURRENT-MODE
POWER
MODULATION
The loop-gain crossover frequency (f ) should be set
C
below 1/5th of the switching frequency and much higher
OUT_
than the power-modulator pole (f
). Select a value for
pMOD
f
in the range:
R1
R2
C
g
= 1200µS
mea
R
ESR
FB_
f
SW
5
f
<< f
≤
pMOD
C
COMP_
ERROR
AMP
C
OUT
R
V
REF
C
30MI
At the crossover frequency, the total loop gain must be
equal to 1. So:
C
F
C
C
V
FB
GAIN
×
×GAIN
= 1
)
MOD(f
)
EA(f
C
C
V
OUT
GAIN
= g
×R
m,EA
Figure 2. Compensation Network
EA(f )
C
f
C
1
pMOD
f
=
GAIN
= GAIN
×
zMOD
MOD(f
)
MOD(dc)
C
2π ×ESR× C
f
OUT
C
When C
the resulting C
is composed of “n” identical capacitors in parallel,
OUT
Therefore:
GAIN
= n x C , and ESR =
OUT(EACH)
OUT
ESR
/n. Note that the capacitor zero for a parallel
V
(EACH)
FB
×
×g
×R = 1
m,EA C
MOD(f
)
combination of alike capacitors is the same as for an
individual capacitor.
C
V
OUT
Solving for R :
The feedback voltage-divider has a gain of GAIN
FB
=
C
V
/V
, where V is 1V (typ).
FB OUT
FB
V
OUT
The transconductance error amplifier has a DC gain of
GAIN = g x R , where g is the error
R
=
C
g
× V ×GAIN
FB MOD(f
m,EA
)
C
EA(DC) m,EA OUT,EA m,EA
amplifier transconductance, which is 1200µS (typ), and
is the output resistance of the error amplifier, which
Set the error-amplifier compensation zero formed by R
R
C
OUT,EA
is 30MI (typ) (see the Electrical Characteristics table.)
and C at the f
. Calculate the value of C as follows:
C
pMOD
C
1
A dominant pole (f ) is set by the compensation
dpEA
C
=
C
capacitor (C ) and the amplifier output resistance
C
2π × f
×R
pMOD
C
(R ). A zero (f ) is set by the compensation
OUT,EA ZEA
resistor (R ) and the compensation capacitor (C ). There
C
C
If f
is less than 5 x f , add a second capacitor C
C F
zMOD
is an optional pole (f
) set by C and R to cancel the
PEA
F C
from COMP to AGND. The value of C is:
F
output capacitor ESR zero if it occurs near the crossover
frequency (f ), where the loop gain equals 1 (0dB)). Thus:
1
C
C
=
F
1
2π × f
zMOD
×R
C
f
=
dpEA
2π × C ×(R
+ R )
C
C
OUT,EA
As the load current decreases, the modulator pole also
decreases; however, the modulator gain increases
accordingly and the crossover frequency remains the same.
1
f
=
zEA
2π × C ×R
C
C
Below is a numerical example to calculate the compensation
network component values of Figure 2:
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
A
V_CS
= 11V/V
Boost Converter Design Procedure
R
g
= 15mI
DCR
Setting the Output Voltage in Boost Converter
= 1/(A
x R ) = 1/(11 x 0.015) = 6.06
DC
Adjust the boost converter output voltage by connecting
a resistive divider from the output of the boost converter
mc
V_CS
V
OUT
= 5V
to FBBST to TERM (Figure 3) and R
(FB3 to TERM
B2
I
= 5.33A
OUT(MAX)
resistor). Calculate R (V
to FBBST resistor)
B1 OUT(BOOST)
R
C
= V
/I
= 5V/5.33A = 0.9375I
using the following equation:
LOAD
OUT OUT(MAX)
= 2x47µF = 94µF
V
OUT
)
OUT(BOOST
R
= R
−1
B2
B1
ESR = 9mI/2 = 4.5mI
= 26.4/65.5kI = 0.403MHz
V
FB3
f
SW
where V
= 1.2V (typ) (see the Electrical Characteristics table).
FB3
GAIN
= 6.06× 0.9375 = 5.68
MOD(dc)
Inductor Selection in Boost Converter
1
Duty cycle and frequency are important to calculate the
inductor size, as the inductor current ramps up during the
on-time of the switch and ramps down during its off-time.
A higher switching frequency generally improves transient
response and reduces component size.
f
=
≈ 1.8kHz
pMOD
2π × 94µF × 0.9375
f
SW
5
f
<< f
≤
pMOD
C
However, if the boost components are to be used as the
input filter components during nonboost operation, a low
frequency is advantageous.
1.8kHz << f ≤ 80.6kHz
C
select f = 40kHz
C
The boost frequency is selected as a multiple of the buck
frequency by setting the input voltage of FSELBST.
1
f
=
≈ 376kHz
zMOD
2π × 4.5mW × 94µF
•ꢀ If V
•ꢀ If V
=V
, then f
= f
FSELBST
GND
BOOST SW
= V
, then f
BIAS
= 1/5f
BOOST SW
since f
> f :
C
FSELBST
zMOD
R
C
≈ 16kI
≈ 5.6nF
C
C
C ≈ 27pF
F
V
OUT(BOOST)
R
R
B1
MAX17230/
MAX17231
FB3
B2
TERM
Figure 3. Boost Converter Adjustable Output Voltage
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
The duty-cycle range of the boost converter depends on
the effective input to output-voltage ratio. In the following
calculations, the duty cycle refers to the on-time of the
boost MOSFET:
If the boost converter response is too slow, increase the
ripple current. A smaller inductor and higher frequency
generally improves the preboost, especially for high input
to output ratios.
V
− V
MOSFET Selection in Boost Converter
The key selection parameters to choose the nMOSFET
used in the boost converter are as follows.
OUT(MAX)
BAT(MIN)
D
=
MAX
V
OUT(MAX)
or including the voltage drops across the inductor,
Threshold Voltage
MOSFET (V
), and the boost diode (V ):
ON,FET
D
The boost nMOSFETs must be a logic-level type
with guaranteed on-resistance specifications at
V
− V
+ V + (I
xR
)
DC
OUT(MAX)
BAT(MIN)
D
OUT
D
=
V
= 4.5V.
GS
MAX
V
OUT(MAX)
Maximum Drain-to-Source Voltage (V
DS(MAX)
The MOSFET must be chosen with an appropriate V
rating to handle all V voltage conditions.
)
In some applications, it may be beneficial to maintain
discontinuous conduction (DCM) in the boost converter
under all conditions. This formula defines the maximum
size of the inductor for DCM mode:
DS
IN
Current Capability
The nMOSFET must deliver the input current (I
):
IN(MAX)
L
< V
x D
/(2 x (I /1 - D ))
OUT(MAX) MAX
MAX
IN(MIN)
MAX
x f
SW(MIN)
D
MAX
I
= I
x
IN(MAX)
LOAD(MAX)
The ratio of the inductor peak-to-peak AC current to DC
average current (LIR) must be selected first. A good initial
value is a 30% peak-to-peak ripple current to average-
current ratio (LIR = 0.3). The switching frequency, input
voltage, output voltage, and selected LIR determine the
inductor value as follows:
1− D
MAX
Choose MOSFETs with the appropriate average current
at V = 4.5V.
GS
Diode Selection in Boost Converter
The diode must deliver the average output current (I
)
OUT
V
×D
IN
plus the peak inductor current (I
). The boost diode
L[µH] =
LPEAK
f
[MHz]×LIR
current can be higher during nonboost operation when it
supplies current to both buck converters under full-load
conditions.
SW
where:
D = (V
- V )/V
OUT
IN OUT
Use a boost diode with a power dissipation of P = I
x
OUT
V
V
= Typical input voltage
IN
V
or higher. To reduce the power dissipation, use a
DIODE
= Typical output voltage
OUT
Schottky diode.
LIR = 0.3 x I /1 - D
OUT
Input Capacitor Selection in Boost Converter
Select the inductor with a saturation current rating higher
than the peak switch current limit of the converter:
The input current for the boost converter is continuous
and the RMS ripple current at the input capacitor is low.
Calculate the minimum input capacitor value and maximum
ESR using the following equations:
∆I
L,RIP,MAX
2
I
> I
+
L,PEAK
L,MAX
∆I xD
L
C
=
BAT
Running a boost converter in continuous conduction mode
introduces a right-half plane zero into the transfer function,
which can only be compensated by reducing bandwidth in
the voltage feedback loop by adding a capacitor across the
low-side feedback resistor. This results in a system that is
slow to respond to load and line changes.
4 x f
x ∆V
SW
Q
∆V
ESR
ESR =
∆I
L
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
where:
DV is the portion of the ripple due to the capacitor
Q
discharge, and DV
of the capacitor. D
is the contribution due to the ESR
is the maximum duty cycle at the
ESR
MAX
(V
− V ) xD
DS
BAT
∆I
=
L
L x f
minimum input voltage. Use a combination of low-ESR
ceramic and high-value, low-cost aluminum capacitors for
lower output ripple and noise.
SW
V
DS
is the total voltage drop across the external MOSFET
plus the voltage drop across the inductor ESR. DI is
peak-to-peak inductor ripple current as calculated above.
L
Shunt Resistor Selection in Boost Converter
The current-sense resistor (R ), connected between the
CS
battery and the inductor, sets the current limit. The CS
DV is the portion of input ripple due to the capacitor
Q
discharge and DV
is the contribution due to ESR of
ESR
input has a voltage trip level (V ) of 120mV (typ).
CS
the capacitor. Assume the input capacitor ripple contribution
due to ESR (DV ) and capacitor discharge (DV ) are
Set the current-limit threshold high enough to
accommodate the component variations. Use the following
ESR
Q
equal when using a combination of ceramic and aluminum
capacitors. During the converter turn-on, a large current is
drawn from the input source especially at high output-to-
input differential.
equation to calculate the value of R
:
CS
V
CS
IN(MAX)
R
=
CS
I
Output Capacitor Selection in Boost Converter
In a boost converter, the output capacitor supplies the
load current when the boost MOSFET is on. The required
output capacitance is high, especially at higher duty
cycles. Also, the output capacitor ESR needs to be low
enough to minimize the voltage drop while supporting the
load current. Use the following equations to calculate the
output capacitor for a specified output ripple. All ripple
values are peak-to-peak.
where I
is the peak current that flows through the
IN(MAX)
MOSFET at full load and minimum V .
IN
I
= I
/(1 - D
)
MAX
IN(MAX)
LOAD(MAX)
When the voltage produced by this current (through the
current-sense resistor) exceeds the current-limit comparator
threshold, the MOSFET driver (DL3) quickly terminates
the on-cycle.
∆V
ESR
ESR =
I
OUT
I
xD
OUT
MAX
SW
C
=
OUT
∆V x f
Q
I
is the load current in A, f
is in MHz, C
is µF,
OUT
OUT
SW
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite NL_
and NH_ to keep LX_, GND, DH_, and the DL_ gate
Applications Information
Layout Recommendations
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention (Figure 4). If possible,
mount all the power components on the top side of the
board, with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
drive lines short and wide. The DL_ and DH_ gate
traces must be short and wide (50 mils to 100 mils
wide if the MOSFET is 1in from the controller IC) to
keep the driver impedance low and for proper adaptive
dead-time sensing.
3) Group the gate-drive components (BST_ diode and
capacitor and LDO bypass capacitor BIAS) together
near the controller IC. Be aware that gate currents of
up to 1A flow from the bootstrap capacitor to BST_,
from DH_ to the gate of the external HS switch and
from the LX_ pin to the inductor. Up to 100mA of
current flow from the BIAS capacitor through the
bootstrap diode to the bootstrap capacitor. Dimension
those traces accordingly.
● Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
● Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full
load efficiency by 1% or more.
● Minimize current-sensing errors by connecting CS_
4) Make the DC-DC controller ground connections as
shown in Figure 4. This diagram can be viewed as
having two separate ground planes: power ground,
where all the high-power components go; and an
analog ground plane for sensitive analog components.
The analog ground plane and power ground plane
must meet only at a single point directly under the IC.
and OUT_. Use kelvin sensing directly across the
current-sense resistor (R
).
SENSE_
● Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (FB_,
CS_, and OUT_).
Layout Procedure
1) Place the power components first, with ground
terminals adjacent (low-side FET, CIN, COUT_, and
Schottky). If possible, make all these connections on
the top layer with wide, copper-filled areas.
5) Connect the output power planes directly to the output
filter capacitor positive and negative terminals with
multiple vias. Place the entire DC-DC converter circuit
as close to the load as is practical.
KELVIN-SENSE VIAS
UNDER THE SENSE RESISTOR
(REFER TO THE EVALUATION KIT)
INDUCTOR
LOW-SIDE
n-CHANNEL
MOSFET (NH)
C
C
OUT
OUT
OUTPUT
GROUND
HIGH-SIDE
n-CHANNEL
MOSFET (NL)
INPUT
Figure 4. Layout Example
Maxim Integrated
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Block Diagram
PGOOD1 COMP1
DC-DC1
CONTROL LOGIC
PGOOD LOW LEVEL
PGOOD HIGH LEVEL
PGOOD
COMP
FB1
FEEDBACK
EAMP1
MAX17230
SELECT LOGIC
INTERNAL
SOFT START
EN1
BST1
DH1
LX1
REF = 1V
PWM1
CLK1
ZX1
OUT1
PWM1
80 mV(TYP) MAX
DIFFERENTIAL INPUT
STEP-DOWN DC-DC1
CSA1
GATE DRIVE
LOGIC
CS1
EN1
DL1
CL
ZERO
CROSS
COMP
SLOPE
COMP LOGIC
CURRENT LIMIT
THRESHOLD
PGND1
LX1
LX1
CLK1
FOSC
OSCILLATOR
VIN
SPREAD SPECTRUM
OPTION AVAILABLE WITH
INTERNAL CLOCK ONLY
EXTERNAL
CLOCK INPUT
BIAS
BIAS
INTERNAL LINEAR
REGULATOR
TIED HIGH (PWM MODE)
TIED LOW (SKIP MODE)
FSYNC
AGND
FSYNC
SELECT LOGIC
IF 3.1V <
< 5.2V
V
EXTVCC
EXTVCC
SWITCHOVER
CLK 180°
OUT OF PHASE
CLK2
EN2
PWM2
CLK2
ZX2
BST2
DH2
COMP2
FB2
OUT2
CS2
STEP-DOWN DC-DC2
LX2
DC-DC2 CONTROL LOGIC
SAME AS DC-DC1 ABOVE
GATE DRIVE
LOGIC
EN2
DL2
PGOOD2
LX2
PGND2
LX2
CLK1
TIED LOW
IF LOW, CLK3 = CLK1
FSELBST
INS
FSELBST
INPUT
TIED HIGH
IF HIGH, CLK3 = CLK1/5
BOOST
ENABLED
PGND3
DL3
BIAS
START-UP TURN
ON THRESHOLD
STEP-UP DC-DC3
VIN
PRE-BST SNS
THRESHOLD
COMPARATOR
BOOST ON-OFF
THRESHOLDS
GATE DRIVE
LOGIC
PWM3
CLK3
CLK3
UVLO THRESHOLD
IN
BOOST
ENABLED
EN3
EN GOES
HIGH
CHECK FOR INS
THRESHOLDS
BSTON
BOOST EN
FLAG
SLOPE COMP
LOGIC
CS3P
CS3N
50 mV(TYP) MAX
DIFFERENT INPUT
CSA3
CURRENT LIMIT
THRESHOLD
CL3
PWM3
FB3
EAMP3
REF3 = 1.25V
LOW GAIN EAMP, NO
COMP PIN REQUIRED
DC-DC3
CONTROL LOGIC
TERM
EN3
EP
Maxim Integrated
│ 27
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Selector Guide
BUCK 1 SWITCHING
FREQUENCY (f
BUCK 2 SWITCHING
FREQUENCY (f
SPREAD SPECTRUM
PART
INS ACTIVE
)
)
SW2
(%)
SW1
MAX17231ETLR+
MAX17231ETLS+
MAX17231ETLV+
MAX17231ETLW+
MAX17230ETLR+
MAX17230ETLS+
1MHz to 2.2MHz
1MHz to 2.2MHz
1MHz to 2.2MHz
1MHz to 2.2MHz
200kHz to 1MHz
200kHz to 1MHz
f
f
f
f
f
f
—
6
Active
Active
SW1
SW1
SW1
SW1
SW1
SW1
—
6
Inactive
Inactive
Active
—
6
Active
Ordering Information
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
MAX17231ETL_/T+
MAX17230ETL_/+T
-40°C to +85°C
-40°C to +85°C
40 TQFN-EP**
40 TQFN-EP**
Note: Insert the desired suffix letter (from Selector Guide) into
the blank to indicate buck 2 switching frequency and spread
spectrum.
+Denotes a lead(Pb)-free/RoHS-compliant package.
**Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
40 TQFN-EP
T4066+5
21-0141
90-0055
Chip Information
PROCESS: BiCMOS
Maxim Integrated
│ 28
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MAX17230/MAX17231
2V–36V, Synchronous Dual Buck Controller with
Integrated Boost and 20µA Quiescent Current
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
2/16
Initial release
—
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2016 Maxim Integrated Products, Inc.
│ 29
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