MAX17271ENE+ [MAXIM]
nanoPower Triple-Output, Single-Inductor, Multiple-Output (SIMO) Buck-Boost Regulator;
| 型号： | MAX17271ENE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | nanoPower Triple-Output, Single-Inductor, Multiple-Output (SIMO) Buck-Boost Regulator 开关 |
| 文件： | 总37页 (文件大小：1963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
General Description
Benefits and Features
● 3-Output, Single-Inductor, Multiple-Output (SIMO)
The MAX17270/MAX17271 are 3-output switching
regulators designed for applications requiring efficient
regulation of multiple supplies in a very small space, such
as wearable electronic devices.
Buck-Boost Regulator
● 2.7V to 5.5V Input Voltage Range
● Low-Power and Long Battery Life
• 1.3μA Operating Current (3 SIMO Channels)
• 330nA Shutdown Current
The parts use a buck-boost architecture that regulates
three outputs using a single, small 2.2µH inductor at
efficiencies up to 85%. This results in smaller board space
while delivering better total system efficiency than equivalent
power solutions using one buck and linear regulators.
• 85% Efficiency at 3.3V Output
● Flexible and Configurable
2
• I C-Compatible Interface (MAX17271)
The supply current is 0.85µA when only one output is
enabled, plus 0.2µA for each additional output enabled.
• Programmable Output Voltage: 0.8V to 5.175V
MAX17270/MAX17271
This SIMO (Single-Input Multiple-Output) regulator uti-
lizes the entire battery voltage range due to its ability to
create output voltages that are above, below, or equal to
the input voltage. Peak inductor current for each output is
programmable to optimize the balance between efficiency,
output ripple, EMI, PCB design, and load capability.
• Programmable Peak Current Limit
● Robust
• Soft-Start
• Overload Protection
• Thermal Protection
● Small Size
Two versions are available. The MAX17270 has 3 enable
inputs and 3 output voltage programming inputs. The
• 1.77mm x 1.77mm x 0.50mm, 16-Bump
0.4mm-Pitch WLP Package
• 3mm x 3mm x 0.75mm, 16-Pin TQFN Package
• Small Total Solution Size
2
MAX17271 includes an I C interface with interrupt, a
push-button turn on/off, and a power-good indication.
All versions are offered in either a 4 x 4, 0.4mm wafer-
level package (WLP) or a 16-pin TQFN package.
Applications
● Bluetooth Headsets
● Fitness Bands
● Watches
Ordering Information appears at end of data sheet.
● Hearables
● Wearables
● Internet of Things (IoT)
● Health Monitors
19-100234; Rev 5; 9/19
MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Simplified Application Circuit
L
C
BST
2.2µH
100nF
OUT3
IN
(3.3V/50mA)
(2.7V to 5.5V)
OUT2
C
IN
(1.8V/75mA)
10µF
OUT1
(1.2V/80mA)
MAX17270/1
C1
C2
C3
22µF
10µF
10µF
ENABLE INPUTS OR
2
I C INTERFACE
Maxim Integrated
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Absolute Maximum Ratings
V
, OUT1, OUT2, OUT3, V to GND...............-0.3V to +6V
EN1, EN2, EN3, IRQB, ON, RSTB, RSEL1, RSEL2,
RSEL3 to GND......................................-0.3V to V
PWR
IO
Continuous Power Dissipation (WLP)
+ 0.3V
+ 0.3V
SUP
(T = 70°C, derate 17.2mW/°C above 70°C.)...........1376mW
SCL, SDA to GND......................................-0.3V to V
A
VIO
Continuous Power Dissipation (TQFN)
V
to V
......................................................-0.3V to +0.3V
SUP
PWR
(T = 70°C, derate 20.8mW/°C above 70°C.)........1666.7mW
PGND to GND......................................................-0.3V to +0.3V
OUT1, OUT2, OUT3 Short-Circuit Duration..............Continuous
A
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -60°C to +150°C
Soldering Temperature (reflow).......................................+260°C
LXA Continuous Current (Note 1) .................................1.2A
LXB Continuous Current (Note 2).................................1.2A
RMS
RMS
BST to LXB................................................................-0.3V to 6V
BST to V .............................................................-0.3V to 6V
PWR
Lead Temperature (soldering, 10 seconds).......................300°C
Note 1: LXA has internal clamping diodes to PGND and V
. It is normal for these diodes to briefly conduct during switching
PWR
events. Avoid steady-state conduction of these diodes.
Note 2: Do not externally bias LXB. LXB has an internal low-side clamping diode to PGND, and an internal high-side clamping
diode that dynamically shifts to the selected SIMO output. It is normal for these internal clamping diodes to briefly conduct
during switching events. When the SIMO regulator is disabled, the LXB to PGND absolute maximum voltage is -0.3V to
OUT1 + 0.3V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
TQFN
PACKAGE CODE
T1633+5
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD:
Junction to Ambient (θ
21-0136
90-0032
)
48°C/W
10°C/W
JA
Junction to Case (θ
)
JC
WLP
PACKAGE CODE
N161A1+1
Outline Number
21-100190
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD:
Junction to Ambient (θ
)
57.93
N/A
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Package Information (continued)
(NE - 1)
X e
MARKING
E
E/2
D2/2
(ND - 1)
e
X e
D/2
AAAA
C
D2
D
L
k
b
0.10 M
C A B
C
L
E2/2
L
E2
C
L
C
L
0.10
C
0.08
C
A
A2
A1
L
L
e
e
maxim
integratedTM
PACKAGE OUTLINE,
8, 12, 16L THIN QFN, 3x3x0.75mm
1
21-0136
V
3
Maxim Integrated
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Package Information (continued)
COMMON DIMENSIONS
Pin 1
E
see Note 7
Indicator
Marking
A
MAX
0.03
0.50
0.19
1
A1
A2
A
0.28 REF
AAAA
D
A3
b
0.040 BASIC
0.27
0.03
0.025
0.025
BASIC
BASIC
D
1.768
1.768
E
TOP VIEW
SIDE VIEW
D1
E1
1.20
1.20
A3
A1
e
0.40 BASIC
0.20 BASIC
0.20 BASIC
S
SD
SE
A2
A
0.05
S
DEPOPULATED BUMPS:
NONE
FRONT VIEW
E1
SE
NOTES:
e
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
SD
D
C
B
B
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
D1
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
A
1
23 4
b
maxim
A
M
S
AB
0.05
TM
integrated
BOTTOM VIEW
TITLE
PACKAGE OUTLINE 16 BUMPS
THIN WLP PKG. 0.4 mm PITCH,N161A1+1
REV.
DOCUMENT CO2NT1RO-L1N0O.0190
B
APPROVAL
1
- DRAWING NOT TO SCALE -
1
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Electrical Characteristics (continued)
(V
= V
= 3.7V, T = -40°C to 85°C, Typical Application Circuits, typical values are at T = 25°C unless otherwise specified. Limits
SUP
PWR J J
over the specified operating temperature and supply voltage range are guaranteed by design and characterization, and production
tested at room temperature only. )
PARAMETER
SYMBOL
CONDITIONS
MIN
-15%
-15%
TYP
+0.6
+0.4
10
MAX
+15%
+15%
UNITS
ILIM[1:0] = 0b10
ILIM[1:0] = 0b11
LX Peak Current Limit
(MAX17271 Only)
I
At LXB, T = +25°C
A
LIM
A
LX Current Limit Delay
BST On Resistance
BST Leakage Current
ns
Ω
R
BST to V
36
77
BST
PWR
BST = 11V, LXB = 5.5V
0.01
1.0
μA
Required Select Resistor
Accuracy (MAX17270 Only)
Use the nearest ±1% resistor from
R
-1
+1
%
SEL_TOL
R
Selection table.
SEL
Select Resistor Detection Time
(MAX17270 Only)
t
V
= 2.7V, C
< 2pF
600
100
1.2
μs
RSEL
SUP
RSEL
st
EN rising edge to rising edge of 1 LXA
pulse, provided that RSEL
values have been determined (t
Soft-Start Enable Delay
(MAX17270 Only)
t
μs
DLY_SS
RSEL
has elapsed after applying V
)
SUP
Measured from 20% to 80% of OUT
ramp
Soft-Start Ramp Rate
dV
/dt
mV/μs
OUT SS
T Rising
165
150
J
Overtemperature Threshold
°C
T Falling
J
LOGIC INPUTS (EN1, EN2, EN3, ON)
T
= +25°C
0.001
0.01
1
Input voltage 0V
to 5.5V
A
Input Current
I
μA
LGC_IN
T = +85°C
A
0.7 x
EN Input Threshold, High
EN Input Threshold, Low
V
Voltage threshold, rising
Voltage threshold, falling
V
V
IH
V
SUP
0.3 x
V
IL
V
SUP
ON Input Threshold, High
ON Input Threshold, Low
ON Debounce Time
V
Voltage threshold, rising
1.4
V
V
IH
V
Voltage threshold, falling
0.4
IL
t
From ON high to sequencer on
From ON high to sequencer off
SWR bit set to 1, following reset
10
13
ms
s
ON_DB
ON Reset Time
t
ON_RST
ON Auto Power Enable
LOGIC OUTPUTS (IRQB, RSTB)
Output Voltage Low
102
ms
V
Asserted and sinking 1mA
0.1
1
V
OL
T
= +25°C
0.001
0.01
A
Leakage Current
I
μA
LKG
Deasserted, 5.5V
T = +85°C
A
Note 1: Typical values align with bench observations using the stated conditions. See the Typical Operating Characteristics.
Minimum and maximum values are tested in production with DC currents.
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Electrical Characteristics
(V
= V
= 3.7V, T = -40°C to 85°C, Typical Application Circuits, typical values are at T = 25°C unless otherwise specified. Limits
SUP
PWR J J
over the specified operating temperature and supply voltage range are guaranteed by design and characterization, and production
tested at room temperature only. )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
Input Voltage Range
V
2.7
V
IN
Rising
Falling
2.55
2.45
5.85
2.7
Outputs are
functional
V
V
Threshold
Threshold
V
V
V
IN UVLO
IN_UVLO
2.2
Rising
5.70
6.00
4.6
V
V
IN OVLO
IN_OVLO
OUT Voltage Range
(MAX17270 Only)
V
V
OUT1, OUT2, OUT3
0.8
0.8
OUT_RANGE
OUT Voltage Range
(MAX17271 Only)
OUT1, OUT2, OUT3
5.175
V
OUT_RANGE
All outputs disabled, BIAS OFF = 1
0.33
0.85
1.05
1.3
(MAX17271), T = +25°C
A
1 output enabled, RSTB, V , SCL,
IO
SDA, IRQB pins open
1.8
2.4
Input Supply Current
I
µA
CC
2 outputs enabled, RSTB, V , SCL,
IO
SDA, IRQB pins open
3 outputs enabled, RSTB, V , SCL,
IO
SDA, IRQB pins open
3.0
1.0
Outputs disabled, T = +25°C
A
0.01
0.1
μA
OUT Supply Current
I
OUT
Outputs enabled, no switching
µA
OUT Overregulation Threshold
(Ultra Low-Power Mode)
V
T = +25°C
A
2.5
5
%
%
OV
Falling switch threshold,
OUT Voltage Accuracy
-2
+2
2.7V < V
< 5.5V
SUP
OUT Load Regulation
OUT Line Regulation
Maximum On Time
Maximum Off Time
V
V
= 3.3V, I
= 0.1mA to 100mA
0.5
0.1
4.4
4.4
70
%
%
OUT
OUT
from 2.7V to 5.5V
IN
t
LXA switched high
LXB switched high
2.2
2.2
8.8
8.8
µs
µs
ON
t
OFF
V
V
V
V
V
V
V
V
= 3.7V
= 2.7V
= 3.7V
= 2.7V
= 3.7V
= 2.7V
= 3.7V
= 2.7V
140
IN
IN
IN
IN
IN
IN
IN
IN
R
High-side
Low-side
AH
90
180
LXA On Resistance
LXB On Resistance
mΩ
mΩ
50
100
R
AL
65
130
55
110
High-side, any
output
R
BH
75
150
55
110
R
Low-side
BL
LIM
LIM
90
180
At LXB, T = +25°C RSELx ≤ 56.2kΩ
-5%
-15%
-5%
+1.1
+0.6
+1.1
+0.8
+5%
+15%
+5%
+15%
LX Peak Current Limit
(MAX17270 Only)
A
I
I
A
A
At LXB, T = +25°C RSELx ≥ 66.5 kΩ
A
ILIM[1:0] = 0b00
LX Peak Current Limit
(MAX17271 Only)
At LXB, T = +25°C
A
ILIM[1:0] = 0b01
-15%
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
2
Electrical Characteristics - I C
(V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating temperature range
VPWR
VSUP IO J
(T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
V
Voltage Range
V
V
V
≤ V
SUP
1.7
-1
1.8
0
3.6
+1
+1
V
IO
IO
IH
IO
= 3.6V, V
= V
= V
= 0V or 3.6V,
= 0V or 1.7V
IO
SDA
SCL
T = +25°C
V
Bias Current
μA
A
IO
V
= 1.7V, V
0
IO
SDA
SCL
SDA AND SCL I/O STAGE
0.7 x
SCL, SDA Input High Voltage
V
V
V
= 1.7V to 3.6V
= 1.7V to 3.6V
V
V
IO
V
IO
0.3 x
SCL, SDA Input Low Voltage
SCL, SDA Input Hysteresis
V
IL
IO
V
IO
0.05 x
V
V
HYS
V
IO
SCL, SDA Input Leakage
Current
I
V
= 3.6V, V
= V
= 0V and 3.6V
-10
+10
0.4
μA
I
IO
SCL
SDA
SDA Output Low Voltage
V
Sinking 20mA
V
OL
SCL, SDA Pin Capacitance
C
10
pF
I
2
I C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST-MODE PLUS) (Note 2)
Clock Frequency
f
0
1000
kHz
SCL
Hold Time (REPEATED)
START Condition
t
0.26
μs
HD_STA
SCL Low Period
SCL High Period
t
0.5
μs
μs
LOW
t
0.26
HIGH
Setup Time (REPEATED)
START Condition
t
0.26
μs
SU_STA
HD_DAT
Data Hold Time
Data Setup Time
t
0
μs
t
50
ns
SU_DAT
Setup Time for STOP
Condition
t
0.26
0.5
μs
μs
ns
SU_STO
Bus Free Time between
STOP and START Condition
t
BUF
Pulse Width of Suppressed
Spikes
Maximum pulse width of spikes that must
be suppressed by the input filter
t
50
SP
Note 1: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through
A
correlation using statistical quality control methods.
Note 2: Design guidance only. Not production tested.
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Typical Operating Characteristics
(V = 2.7V , OUT1 = 1.2V , I 1 = 0.4A, OUT2 = 1.8V , I 2 = 0.8A, OUT3 = 3.3V , I 3 = 1.1A, L1 = 2.2μH (Coilcraft XFL4020-222ME),
IN
LIM
LIM
LIM
COUT1 = COUT2 = COUT3 = 22μF (TDK C1608X5R1A226M080AC))
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
SUPPLY CURRENT
vs. INPUT VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
toc03
toc01
toc02
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
900
800
700
600
500
400
300
200
100
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
BIAS OFF = 1
TA = 25°C
OUT1, OUT2, OUT3 ON
OUT1, OUT2 ON
OUT1 ON
TA = +85°C
TA = +25°C
TA = -40°C
OUT1, OUT2, OUT3 ON
OUT1, OUT2 ON
OUT1 ON
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
25
50
75
100
INPUT VOTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
LOAD REGULATION
LOAD REGULATION
LOAD REGULATION
(VOUT = 1.8V, ILIM = 0.8A)
(VOUT = 3.3V, ILIM = 1.1A)
(VOUT = 1.2V, ILIM = 0.4A)
toc05
toc06
toc04
1.860
1.850
1.840
1.830
1.820
1.810
1.800
1.790
1.780
3.380
3.360
3.340
3.320
3.300
3.280
1.228
1.224
1.220
1.216
1.212
1.208
1.204
1.200
5V INPUT
5V INPUT
5V INPUT
2.7V INPUT
2.7V INPUT
50
2.7V INPUT
0
50
100
150
200
250
0
100
150
200
250
300
0
10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
SWITCHING WAVEFORMS–
ULTRA-LOW-POWER MODE
SWITCHING WAVEFORMS–
LIGHT UTILIZATION
SWITCHING WAVEFORMS–
MEDIUM UTILIZATION
toc07
toc08
toc09
VOUT1
50mV/div
VOUT1
VOUT1
VOUT2
50mV/div
50mV/div
50mV/div
50mV/div
50mV/div
VOUT2
VOUT3
VOUT2
VOUT3
50mV/div
50mV/div
VOUT3
50mV/div
ILX
ILX
ILX
500mA/div
500mA/div
500mA/div
IOUT1 = IOUT2 = IOUT3 = 100µA
1ms/div
IOUT1 = 15mA, IOUT2 = IOUT3 = 30mA
5µs/div
IOUT1 = 5mA IOUT2 = IOUT3 = 10mA
10µs/div
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Typical Operating Characteristics (continued)
(V = 2.7V , OUT1 = 1.2V , I 1 = 0.4A, OUT2 = 1.8V , I 2 = 0.8A, OUT3 = 3.3V , I 3 = 1.1A, L1 = 2.2μH (Coilcraft XFL4020-222ME),
IN
LIM
LIM
LIM
COUT1 = COUT2 = COUT3 = 22μF (TDK C1608X5R1A226M080AC))
SWITCHING WAVEFORMS–
HEAVY UTILIZATION
POWER-UP
toc10
toc11
5.2V/div
ON
VOUT1
50mV/div
50mV/div
1.3V/div
1.9V/div
VOUT1
VOUT2
VOUT2
VOUT3
VOUT3
3.4V/div
50mV/div
IRQB
RSTB
ILX
500mA/div
IOUT1 = IOUT2= IOUT3 = 10mA
5ms/div
IOUT1 = 25mA, IOUT2 = IOUT3 = 55mA
2µs/div
LOAD TRANSIENT WAVEFORMS—OUT1
POWER-DOWN
toc13
toc12
5.2V/div
VOUT1
60mV/div
AC-COUPLED
ON
VOUT1
VOUT2
VOUT3
1.3V/div
1.9V/div
60mV/div
AC-COUPLED
VOUT2
60mV/div
AC-COUPLED
3.4V/div
VOUT3
1mA
IRQB
RSTB
25mA
IOUT1
30mA/div
IOUT1 = 1mA to 25mA, IOUT2 = IOUT3 = 10mA
1ms/div
IOUT1 = IOUT2 = IOUT3 = 10mA
2s/div
LOAD TRANSIENT WAVEFORMS—OUT2
LOAD TRANSIENT WAVEFORMS—OUT3
toc15
toc14
60mV/div
AC-COUPLED
VOUT1
VOUT2
VOUT3
60mV/div
AC-COUPLED
VOUT1
60mV/div
AC-COUPLED
60mV/div
AC-COUPLED
VOUT2
60mV/div
AC-COUPLED
VOUT3
60mV/div
AC-COUPLED
55mA
10mA
30mA/div
55mA
IOUT2
10mA
IOUT3
30mA/div
IOUT2 =10mA to 55mA, IOUT1 = IOUT3 = 10mA
1ms/div
IOUT3 =10mA to 55mA, IOUT1 = IOUT3 = 10mA
1ms/div
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Typical Operating Characteristics (continued)
(V = 2.7V , OUT1 = 1.2V , I 1 = 0.4A, OUT2 = 1.8V , I 2 = 0.8A, OUT3 = 3.3V , I 3 = 1.1A, L1 = 2.2μH (Coilcraft XFL4020-222ME),
IN
LIM
LIM
LIM
COUT1 = COUT2 = COUT3 = 22μF (TDK C1608X5R1A226M080AC))
LINE TRANSIENT RESPONSE
STARTUP WAVEFORMS
toc17
toc16
2V/div
2V/div
VIN
1V/div
EN1
EN2
EN3
2V/div
VOUT1
100mV/div
(AC-COUPLED)
1V/div
1V/div
1V/div
VOUT1
VOUT2
100mV/div
(AC-COUPLED)
VOUT2
100mV/div
(AC-COUPLED)
VOUT3
VOUT3
MAX17270
2ms/div
1.6ms/div
VIN = 2.7V, IOUT1 = IOUT2 = IOUT3 = 10mA
VOUT1 = 1.2V, VOUT2 = 1.8V, VOUT3 = 3.3V
EFFICIENCY vs. LOAD CURRENT
(VOUT1 = 1.2V, ILIM = 0.6A)
POWER-DOWN WAVEFORMS
toc18
toc19
95
85
75
65
55
45
35
25
MAX17270
VIN = 3.7V
4V/div
EN1
VIN = 2.7V
EN2
EN3
4V/div
4V/div
VIN = 5.0V
1V/div
2V/div
VOUT1
VOUT2
MAX17270ENE
3V/div
VOUT3
1.0E-6 10.0E-6 100.0E-6 1.0E-3 10.0E-3 100.0E-3
2ms/div
LOAD CURRENT (A)
V
IN = 2.7V, IOUT1 = IOUT2 = IOUT3 = 10mA
VOUT1 = 1.2V, VOUT2 = 1.8V, VOUT3 = 3.3V
EFFICIENCY vs. LOAD CURRENT
(VOUT1 = 1.8V, ILIM = 1.1A)
EFFICIENCY vs. LOAD CURRENT
(VOUT1 = 3.3V, ILIM = 1.1A)
toc21
toc20
90
85
80
75
70
65
60
55
50
45
40
95
90
VIN = 5.0V
VIN = 2.7V
85
80
75
70
65
60
55
50
VIN = 2.7V
VIN = 3.7V
MAX17270ENE
MAX17270ENE
VIN = 3.7V
VIN = 5.0V
1.0E-6 10.0E-6 100.0E-6 1.0E-3 10.0E-3 100.0E-3
1.0E-6 10.0E-6 100.0E-6 1.0E-3 10.0E-3 100.0E-3
LOAD CURRENT (A)
LOAD CURRENT (A)
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Typical Operating Characteristics (continued)
(V = 2.7V , OUT1 = 1.2V , I 1 = 0.4A, OUT2 = 1.8V , I 2 = 0.8A, OUT3 = 3.3V , I 3 = 1.1A, L1 = 2.2μH (Coilcraft XFL4020-222ME),
IN
LIM
LIM
LIM
COUT1 = COUT2 = COUT3 = 22μF (TDK C1608X5R1A226M080AC))
EFFICIENCY vs. LOAD CURRENT
(VOUT1 = 1.2V, ILIM = 0.4A)
EFFICIENCY vs. LOAD CURRENT
(VOUT1 = 1.8V, ILIM = 0.8A)
toc22
toc23
90
100
90
80
70
60
50
40
30
VIN = 3.7V
VIN = 2.7V
VIN = 2.7V
80
70
VIN = 5.0V
VIN = 3.7V
60
VIN = 5.0V
MAX17271ENE
MAX17271ENE
50
40
30
1.0E-6 10.0E-6 100.0E-6 1.0E-3 10.0E-3 100.0E-3
1.0E-6 10.0E-6 100.0E-6 1.0E-3 10.0E-3 100.0E-3
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
(VOUT1 = 3.3V, ILIM = 1.1A)
toc24
90
85
80
75
70
65
60
VIN = 5.0V
MAX17271ENE
VIN = 3.7V
VIN = 2.7V
1.0E-6 10.0E-6 100.0E-6 1.0E-3 10.0E-3 100.0E-3
LOAD CURRENT (A)
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Pin Configurations
TOP VIEW
TOP VIEW
MAX17270
MAX17271
1
2
3
4
1
2
3
4
+
+
A
A
OUT1
PGND
LXA
OUT2
LXB
OUT3
RSEL3
RSEL2
RSEL1
GND
EN3
EN2
EN1
OUT1
PGND
LXA
OUT2
LXB
OUT3
ON
GND
IRQB
SDA
SCL
B
C
D
B
C
D
BST
BST
RSTB
VIO
VPWR
VSUP
VPWR
VSUP
16-WLP
16-WLP
TOP VIEW
TOP VIEW
12
11
10
9
12
11
10
9
13
14
15
16
8
GND
EN1
RSEL1
VSUP
13
14
15
16
8
7
6
5
GND
SCL
VIO
7
6
5
OUT3
OUT2
OUT1
OUT3
OUT2
OUT1
MAX17270
MAX17271
VSUP
VPWR
+
VPWR
+
1
2
3
4
1
2
3
4
TQFN
3mm x 3mm
TQFN
3mm x 3mm
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Pin Description
PIN
NAME
FUNCTION
MAX17270 MAX17271 MAX17270 MAX17271
WLP
WLP
TQFN
TQFN
Regulator Output 1. Connect a 10μF (min) capacitor from
this pin to ground.
A1
A1
5
5
OUT1
PGND
LXA
Buck-Boost Power Ground. Connect to the ground plane
through a low impedance.
B1
C1
D1
A2
B2
B1
C1
D1
A2
B2
3
1
3
1
Buck-Boost Input-Side Inductor Connection. Connect a
2.2µH inductor between LXA and LXB.
Buck-Boost Input Power Supply Pin. Connect a 10µF(min)
capacitor from this pin to ground.
16
6
16
6
VPWR
OUT2
LXB
Regulator Output 2. Connect a 10µF(min) capacitor from
this pin to ground.
Buck-Boost Output-Side Inductor Connection. Connect a
2.2µH inductor between LXA and LXB.
4
4
Bootstrap pin for high-side output FET drivers. Connect a
3.3nF capacitor between BST and LXB.
C2
D2
A3
C2
D2
A3
2
15
7
2
15
7
BST
VSUP
OUT3
Analog Input Supply. Connect to VPWR.
Regulator Output 3. Connect a 10µF (min) capacitor from
this pin to ground.
Select Resistor Pin 3. Connect a resistor from this pin to
GND, using the values from Table 1 to configure the output
voltage of OUT3.
B3
—
—
9
—
9
RSEL3
ON
Push-Button Controller Input. Connect a 100kΩ resistor
from ON to GND and momentary switch between ON and
TTL Level Supply. Used to initiate power-up and power-
down sequencing.
B3
—
Select Resistor Pin 2. Connect a resistor from this pin to
GND, using the values from Table 1 to configure the output
voltage of OUT2.
C3
—
—
C3
—
12
—
14
—
12
—
RSEL2
RSTB
Open-Drain Output to Indicate All Outputs are Active. Con-
nect a pullup resistor between this pin and an external sup-
ply. Goes to logic-high only when all outputs are active.
Select Resistor Pin 1. Connect a resistor from this pin to
GND, using the values from Table 1 to configure the output
voltage of OUT1.
D3
RSEL1
2
Supply Voltage for the I C Inputs. Determines the SDA and
—
A4
B4
D3
A4
—
—
8
14
8
VIO
GND
EN3
2
SCL thresholds. Connect to I C supply rail.
Analog Ground.
Enable Input for OUT3. Hold high to enable output regula-
tion. Hold low to disable the output.
10
—
2
I C Interrupt Output. Connect a pullup resistor between this
pin and an external supply.
—
B4
—
10
IRQB
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Pin Description (continued)
PIN
NAME
FUNCTION
MAX17270 MAX17271 MAX17270 MAX17271
WLP
WLP
TQFN
TQFN
Enable Input for OUT2. Hold high to enable output regulation.
Hold low to disable the output.
C4
—
11
—
EN2
SDA
EN1
SCL
2
I C Data Input. Used to communicate with the part through
—
D4
—
C4
—
—
13
—
11
—
13
2
the I C interface.
Enable Input for OUT1. Hold high to enable output regulation.
Hold low to disable the output.
2
I C Clock Input. Used to communicate with the part through
D4
2
the I C interface.
Functional Diagram
100nF
2.2µH
LXA
LXB
BST
SYNCHRONOUS
RECTIFIER
M3_1
REVERSE
BLOCKING
MAIN POWER
STAGE
M1
VPWR
OUT1
OUT2
OUT3
10µF
10µF
10µF
10uF
M2
M4
SYNCHRONOUS
RECTIFIER
PGND
M3_2
REVERSE
BLOCKING
ENx
MAX17270
RSELx
SYNCHRONOUS
RECTIFIER
SIMO
CONTROLLER
M3_3
REVERSE
BLOCKING
I2C
ON
MAX17271
RSTB
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Output Voltage Configuration
Detailed Description
Each of the outputs are independently configu-
rable. In the MAX17270 to set the output voltages at
The MAX17270/MAX17271 are nanopower, single-induc-
tor, multiple-output (SIMO) buck-boost, DC-to-DC con-
verters designed for applications that require ultra-low
supply current and small solution size. A single inductor
is used to regulate three separate outputs, saving board
space while delivering higher total system efficiency than
equivalent power solutions using multiple buck and/or
linear regulators.
OUT1/2/3 and the inductor peak current limits (I ),
LIM
connect the appropriate resistors from RSEL1/2/3,
respectively, to GND, as shown in Table 1. RSEL1/2/3
resistors should have 1% (or better) tolerance. In the
2
MAX17271 to set the output voltages, use the I C
interface to load the configuration registers TVSIMOx[7:0].
TVSIMOx[7] is used to enable (TVSIMOx[7] = 1) or
disable (TVSIMOx[7] = 0) a 1.2V offset. TVSIMOx[6:0]
bits are used to set the output voltage as
The SIMO configuration utilizes the entire battery voltage
range due to its ability to create output voltages that are
above, below, or equal to the input voltage. Peak
inductor current for each output is programmable to
optimize the balance between efficiency, output ripple,
EMI, PCB design, and load capability.
OUT = 0.8V + 25mV × TVSIMO 6 : 0 decimal
](
[
)
.
This has been shown in Table 2.
Table 1. MAX17270 Output Voltage and Current Limit Setting
OUTPUT
VOLTAGE (V)
CURRENT
LIMIT(A)
OUTPUT
VOLTAGE (V)
CURRENT
LIMIT(A)
RSEL (KΩ)
RSEL (KΩ)
56.2
47.5
40.2
34
0.800
0.900
1.000
1.100
1.200
1.350
1.500
1.800
2.200
2.500
3.000
3.300
3.600
4.100
4.600
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
OPEN
909
768
634
536
452
383
324
267
226
191
162
133
113
0.800
0.900
1.000
1.100
1.200
1.350
1.500
1.800
2.200
2.500
2.800
3.000
3.300
3.600
4.100
4.600
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
28
23.7
20
16.9
14
11.8
10
8.45
7.15
4.99
SHORT
80.6
66.5
Table 2. MAX17271 Output Voltage Setting
TVSIMOX[6:0] OUTPUT VOLTAGE (V)OUTPUT VOLTAGE (V)
TVSIMOX[6:0] OUTPUT VOLTAGE (V)OUTPUT VOLTAGE (V)
(DECIMAL)
WITH TVSIMO[7] = 0 WITH TVSIMO[7] = 1
(DECIMAL)
6 to 122
123
WITH TVSIMO[7] = 0 WITH TVSIMO[7] = 1
0
1
2
3
4
5
0.8
0.825
0.85
0.875
0.9
2
0.95 to 3.85
3.875
3.9
2.15 to 5.05
5.075
5.1
2.025
2.05
2.075
2.1
124
125
3.925
3.95
5.125
5.15
126
0.925
2.125
127
3.975
5.175
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
limiting the slew rate of the output voltage during startup
SIMO Control Scheme
(dV
/dt ).
OUT SS
The SIMO buck-boost is designed to service multiple
outputs simultaneously. A proprietary controller ensures
that all outputs get serviced in a timely manner, even
while multiple outputs are contending for the energy
stored in the inductor. When no regulator needs service,
the state machine rests in a low-power rest state.
More output capacitance results in higher input current
surges during startup. The following set of equations and
example describes the input current surge phenomenon
during startup.
The current into the output capacitor (I
start is:
) during soft-
COUT
When the controller determines that a regulator requires
service, it charges the inductor (M1 + M4) until the
peak current limit is reached. The inductor energy then
discharges (M2 + M3_x) into the output until the
dV
OUT
I
= C
×
OUT
COUT
dt
SS
(Equation 1)
where:
● C
current reaches zero (I ). In the event that multiple
ZX
output channels need servicing at the same time, the
controller ensures that no output utilizes all of the switching
cycles. Instead, cycles interleave between all the outputs
that are demanding service, while outputs that do not
need service are skipped.
is the capacitance on the output of the regulator
OUT
● dV
/dt is the rate of change of the output voltage
OUT SS
The input current (I ) during soft-start is:
IN
V
OUT
(I
+ I
) ×
COUT LOAD
When the load current for any output is very light, that
output automatically switches to an ultra-low-power mode
(ULPM) to reduce the quiescent current consumption.
Figure 1 shows typical waveforms during the ULPM and
normal modes. While operating in ULPM, the output
voltage is biased 2.5% higher than normal mode by
design so that future large load transients can be handled
without excessive undershoot.
V
IN
I
=
IN
(Equation 2)
η
where:
● I
is calculated from Equation 1
COUT
● I
is current consumed from the external load
is the output voltage
LOAD
● V
OUT
● V is the input voltage
IN
SIMO Soft-Start
The soft-start feature of the SIMO limits inrush current
during startup. The soft-start feature is achieved by
● η is the efficiency of the regulator
VOUT
ULTRA LOW POWER MODE (UPLM): LIGHT LOADS
VOUT TARGET + 2.5%
MEDIUM , HEAVY LOADS
VOUT TARGET
24us
7.5us
LOAD DEPENDENT
TIME
Figure 1. ULPM and Normal Mode Waveforms
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
For example:
the active discharge feature helps ensure a complete
and timely power-down of all system peripherals. If the
active-discharge resistor is enabled by default, then the
● V is 3.5V
IN
● V
is 3.3V
= 10µF
OUT2
OUT2
active-discharge resistor is on whenever V is below
IN
● C
V
and above the power-on reset threshold which is
UVLO
typically 1.35V .
● dV
/dt = 1mV/µs
OUT SS
These resistors discharge the output when ADE = 1, and
their respective SIMO channel is off.
● R
= 330Ω (I
= 3.3V/330Ω = 10mA)
LOAD2
LOAD2
● η is 80%
Note that when V is less than 1.35V, the NMOS transistors
IN
that control the active discharge resistors lose their gate
drive and become open.
Calculation:
● I
= 10µF x 1mV/µs (from Equation 1)
COUT
● I
= 10mA
3.3V
COUT
On Pin Control and Power Sequencer
(MAX17271)
The ON pin available on the MAX17271 is a TTL
(10mA +10mA)×
●
(from Equation 2)
3.5V
I
=
IN
0.8
level input used to start and stop
a power-up
● I = 23.57mA for OUT2
IN
sequence defined through each SIMO configuration
register ENCTL[4:0] . A 10ms debounce delay is applied
to each edge of the ON signal for those applications
using a push-button switch to control the pin. When the
ON pin is toggled high for greater than 1µs and less
than 13 seconds, the start sequence will be latched to
commence following the 10ms debounce delay. Once
a start sequence has been initiated, the ON pin can be
taken low through a pulldown resistor connected to GND.
Any following toggles on the ON pin less than 13 seconds
will be ignored. A power-down will initiate after a start
sequence if the ON pin is held high longer than 13 sec-
onds. If, for some reason, the ON pin is stuck high, the
start sequencer will remain off until a falling edge on the
ON pin can be detected. The customer is also provided
a software configuration bit (SWR) which will enable the
SIMO to auto-restart following a power down and after the
100ms delay. This can be used for diagnostic purposes.
SIMO Registers (MAX17271)
In MAX17271, each SIMO buck-boost channel has a
dedicated register to program its target output voltage
(TVSIMOx[7:0]) and its peak current limit (ILIM[1:0]).
Additional controls are available for enabling/disabling the
active discharge resistors (ADE), as well as configuring the
power up and power down sequence of the SIMO buck-
boost channels (ENCTL[4:0]). For a full description of bits,
registers, default values, and reset conditions, refer to the
Register Map.
SIMO Active Discharge Resistance
(MAX17271)
In MAX17271, each SIMO buck-boost channel has an
internal 100Ω active-discharge resistor (R
) that
AD_SBBx
is automatically enabled/disabled based on an ADE bit
and the status of the SIMO regulator. The active dis-
charge feature may be enabled (ADE = 1) or disabled
(ADE = 0) independently for each SIMO channel. Enabling
Figure 2 shows an example of a power-up and power-
down controlled by the ON pin.
t
t
ON_DB
ON_RST
t
t
= 10ms (ON Debounce time)
ON_DB
ON
= 13s (ON Reset time)
ON_RST
OUT1
OUT2
slot , slot , slot : Available time slots during power up
A
B
C
slot , slot , slot : Available time slots during power down
X
Y
Z
Slot positions are set using the ENCTL[4:2] bits in the
CNFG_BBx_B register for each output.
OUT3
IRQB
IRQB is asserted when rising edge on ON is detected.
slot
slot
slot
slot
slot
slot
Z
A
B
C
X
Y
Figure 2. ON Pin Control and Power Sequencer for MAX17271.
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
The timing slots, with which the MAX17271 outputs pow-
er-up and power-down, can be set using the ENCTL[4:1]
bits in the CNFG_BBx_B I C registers.
If ENCTL[1] = 0, the outputs will not ramp up or ramp
down based on the ON pin signal regardless of the
ENCTL[4:2] bit settings.
2
For a given output, bits ENCTL[4:3] are used to set up the
delay between the detection of the ON rising edge (after
the debounce delay) and the start of the output voltage
ramp up.
If ENCTL[0] = 1, the output is forced ON, and does not
follow the power sequencer. If ENCTL[0] = 0, refer to
ENCTL[4:1] for operation of the output.
Fault Response and Reporting
(MAX17271)
Table 5 describes how the MAX17271 responds to differ-
ent types of fault events.
The four possible values for the power-up delay are given
in the Table 3.
The ENCTL[2] bit can be used to set the power-down
delay, as shown in Table 4. The power-down delay is the
delay between detection of the ON pin being high for 13s
and the start of the outputs being disabled.
2
When the I C Interrupt Register (GLBL_INT) is read back
following a fault event, it gets cleared (all bits reset to
zero) even if the fault condition persists.
To enable the power sequencer, bit ENCTL[1] should be
set to 1.
Bits in the GLBL_INT register can be set again only if the
fault condition goes away and then comes back (edge-
triggered event).
Table 3. Power-Up Delay Settings
Table 4. Power-Down Delay Settings
ENCTL[4:3] (BINARY)
POWER-UP DELAY (MS)
POWER-DOWN DELAY
ENCTL[2] (BINARY)
(MS)
00
01
10
11
0
0
1
0
10
20
30
30 - (Power-Up Delay)
Table 5. Fault Response and Reporting (MAX17271)
2
SIMO SWITCHING
STATE
I C INTERRUPT BIT
LATCHING
BEHAVIOR
EVENT
IRQB PIN
RSTB PIN
(GLBL_INT REGISTER)
Temperature >
Overtemperature
Threshold
ON pin needs to go
high again to restart
switching
All outputs turned
THI = 0 to 1
OVLO = 0 to 1
VOKB = 0 to 1
POKB = 0 to 1
IRQB = 1 to 0
RSTB = 1 to 0
off
RSTB goes from 1 to
0 only if OUT < V
Enabled outputs
remain on
No latching
behavior
V
V
> OVLO
< UVLO
IRQB = 1 to 0
IRQB = 1 to 0
IRQB = 1 to 0
IN
OUT
Target for 14µs or more
ON pin needs to go
high again to restart
switching
All outputs turned
RSTB = 1 to 0
IN
off
OUT < V
OUT
Enabled outputs
remain on
No latching
behavior
Target for 14µs
RSTB = 1 to 0
or more
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
2
● 0Hz to 100kHz (Standard Mode)
● 0Hz to 400kHz (Fast Mode)
● 0Hz to 1MHz (Fast Mode Plus)
Detailed Description–I C
General Description
2
The MAX17271 feature a revision 3.0 I C-compatible,
2-wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). The
MAX17271 act as slave-only devices where they rely on
the master to generate a clock signal. SCL clock rates
● 0Hz to 3.4MHz (High-Speed Mode)
2
● Does not utilize I C Clock Stretching
2
I C System Configuration
2
from 0Hz to 3.4MHz are supported.I C is an open-drain
2
The I C bus is a multimaster bus. The maximum number
bus and therefore SDA and SCL require pullups. Optional
resistors (24Ω) in series with SDA and SCL protect the
device inputs from high-voltage spikes on the bus lines.
Series resistors also minimize crosstalk and undershoot
on bus signals. Figure 3 below shows the functional dia-
of devices that can attach to the bus is only limited by bus
capacitance.
2
A device on the I C bus that sends data to the bus in
called a transmitter. A device that receives data from
the bus is called a receiver. The device that initiates
a data transfer and generates the SCL clock signals
to control the data transfer is a master. Any device
that is being addressed by the master is considered a
2
gram for the I C based communications controller. For
2
2
additional information on I C, refer the I C bus specifica-
tion and user manual that is available from NXP (docu-
ment title: UM10204)
2
slave. The MAX17271 I C compatible interface operates
2
as a slave on the I C bus with transmit and receive
Features
capabilities.
2
● I C Revision 3 Compatible Serial Communications
Channel
COMMUNICATIONS CONTROLLER
VIO
SCL
SDA
INTERFACE
DECODERS
SHIFT REGISTERS
BUFFERS
GND
PERIPHERAL
0
PERIPHERAL
1
PERIPHERAL
2
PERIPHERAL
N-1
PERIPHERAL
N
2
Figure 3. I C Simplified Block Diagram
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
2
Figure 4. I C System Configuration
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
2
transition on SDA with SCL high. A STOP condition is a low-
to-high transition on SDA, while SCL is high. See Figure 5.
I C Interface Power
2
The MAX17231’s I C interface derives its power from
V
. Typically a power input such as V would require
A START condition from the master signals the
beginning of a transmission to the MAX17271. The
master terminates transmission by issuing a not-acknowl-
edge followed by a STOP condition (see I2C Acknowledge
Bit for information on not-acknowledge). The STOP
condition frees the bus. To issue a series of commands
to the slave, the master can issue repeated start (Sr)
commands instead of a STOP command to maintain
control of the bus. In general a repeated start command is
functionally equivalent to a regular start command.
IO
IO
a local 0.1μF ceramic bypass capacitor to ground.
However, in highly integrated power distribution systems,
a dedicated capacitor might not be necessary. If the
impedance between V and the next closest capacitor
(≥ 0.1μF) is less than 100mΩ in series with 10nH, then a
IO
local capacitor is not needed. Otherwise, bypass V to
GND with a 0.1µF ceramic capacitor.
IO
V
IO
accepts voltages from 1.7V to 3.6V (V ). Cycling V
IO
IO
2
does not reset the I C registers. When V is less than
IN
V
, SDA and SCL are high impedance.
When a STOP condition or incorrect address is detected,
the MAX17271 internally disconnect SCL from the serial
interface until the next START condition, minimizing digital
noise and feedthrough.
UVLO
2
I C Data Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
2
I C Acknowledge Bit
2
2
is high are control signals. See the I C Start and Stop
Both the I C bus master and the MAX17271 (slave)
Conditions section. Each transmit sequence is framed by
a START (S) condition and a STOP (P) condition. Each
data packet is nine bits long: eight bits of data followed by
the acknowledge bit. Data is transferred with the MSB first.
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each nine bit data packet.
To generate an acknowledge (A), the receiving device
must pull SDA low before the rising edge of the acknowl-
edge-related clock pulse (ninth pulse) and keep it low
during the high period of the clock pulse. See Figure 6.
To generate a not-acknowledge (nA), the receiving device
allows SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high during
the high period of the clock pulse.
2
I C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
S
Sr
P
SDA
SCL
tSU;STA
tSU;STO
The MAX17271 issues an ACK for all register
addresses in the possible address space even if the
particular register does not exist.
tHD;STA
tHD;STA
2
Figure 5. I C Start and Stop Conditions
NOT ACKNOWLEDGE (NA)
ACKNOWLEDGE (A)
S
SDA
TSU;DAT
THD;DAT
1
2
8
9
SCL
Figure 6. Acknowledge Bit
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
2
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
I C Slave Address
2
The I C controller implements 7-bit slave addressing. An
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
pullup resistors. Higher time constants created by the
bus capacitance and pullup resistance (C x R) slow the
bus operation. Therefore, when increasing bus speeds,
the pullup resistance must be decreased to maintain a
reasonable time constant. Refer to the Pullup Resistor
2
I C bus master initiates communication with the slave by
issuing a START condition followed by the slave address.
See Figure 7. See Table 6. In addition to the address
listed in Table 6, 7-bit slave addresses 0x25 and 0x50 are
also acknowledged but serve no additional communica-
tion functions. Care must be taken that these addresses
2
do not conflict with existing I C addresses on the system.
2
Sizing section of the I C revision 3.0 specification
2
I C Clock Stretching
(UM10204) for detailed guidance on the pullup resistor
selection. In general for bus capacitances of 200pF, a
100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus
needs about a 1.5kΩ pullup resistors, and a 1MHz bus
needs 680Ω pullup resistors. Note that when the open-
drain bus is low, the pullup resistor is dissipating power,
2
In general, the clock signal generation for the I C bus is
the responsibility of the master device. The I C specification
2
allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX17271 does not use any form of clock
stretching to hold down the clock line.
2
lower value pullup resistors dissipate more power (V /R).
Operating in high-speed mode requires some special
considerations. For a full list of considerations, see the
2
I C General Call Address
2
I C Specification section. The major considerations with
2
The MAX17271 does not implement the I C specifica-
respect to the MAX17271:
tions general call address. If the MAX17271 sees the
general call address (0b0000_0000), it does not issue an
acknowledge.
2
● The I C bus master use current source pullups to
shorten the signal rise
2
● The I C slave must use a different set of input filters
2
I C Device ID
on its SDA and SCL lines to accommodate for the
higher bus
2
The MAX17271 does not support the I C Device ID feature.
● The communication protocols need to utilize the high-
speed master code.
2
I C Communication Speed
The MAX17271 is compatible with all 4 communication
speed ranges as defined by the Revision 3 I C specification:
At power-up and after each stop condition, the MAX17271
inputs filters are set for standard mode, fast mode, or fast
mode plus (i.e., 0Hz to 1MHz). To switch the input filters
for high-speed mode, use the high-speed master code
2
● 0Hz to 100kHz (Standard Mode)
● 0Hz to 400kHz (Fast Mode)
● 0Hz to 1MHz (Fast Mode)
2
protocols that are described in the I C Communication
Protocols section.
● 0Hz to 3.4MHz (High-Speed Mode)
S
1
1
0
2
0
3
1
4
0
5
0
6
0
7
R/W
A
9
SDA
SCL
ACKNOWLEDGE
8
Figure 7. Slave Address Example
2
Table 6. I C Slave Address Options
ADDRESS
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
Main Address
(ADDR = 1)
0x48, 0b 100 1000
0x90, 0b 1001 0000
0x91, 0b 1001 0001
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nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
2
● The master sends a stop condition (P) or a repeated
I C Communication Protocols
start condition (Sr). Issuing a P ensures that the bus
The MAX17271 supports both writing and reading from
its registers.
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their
current state.
Writing to a Single Register
2
Figure 8 shows the protocol for the I C master device to
write one byte of data to the MAX17271. This protocol is
the same as the SMBus specification’s write byte protocol.
Writing Multiple Bytes to Sequential Registers
Figure 9 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte
protocol above, except the master continues to write after
it receives the first byte of data. When the master is done
writing it issues a stop or repeated start.
The write byte protocol is as follows:
● The master sends a start command (S).
● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
The writing to sequential registers protocol is as follows:
● The addressed slave asserts an acknowledge (A) by
● The master sends a start command (S).
pulling SDA low.
● The master sends the 7-bit slave address followed by
● The master sends an 8-bit register pointer.
● The slave acknowledges the register pointer.
● The master sends a data byte.
a write bit (R/W = 0).
● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
● The master sends an 8-bit register pointer.
● The slave acknowledges the register pointer.
● The master sends a data byte.
● The slave updates with the new data
● The slave acknowledges or not acknowledges the
data byte. The next rising edge on SDA will load the
data byte into its target register and the data will
become active.
● The slave acknowledges the data byte. The next
rising edge on SDA load the data byte into its target
register and the data will become active.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A OR NA P OR SR*
R/nW
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
ACKNOWLEDGE
8
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR <=1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
Figure 8. Writing to a Single Register with the Write Byte Protocol
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nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
● Steps 6 to 7 are repeated as many times as the
● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their
current state.
master requires.
● During the last acknowledge related clock pulse,
the master can issue an acknowledge or a not
acknowledge.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X
A
DATA X
A
Α
Α
R/NW
NUMBER
OF BITS
8
1
8
1
DATA X+1
A
DATA X+2
A
Α
Α
REGISTER POINTER = X + 2
REGISTER POINTER = X + 1
8
NUMBER
OF BITS
1
8
1
1
A OR
NA
P OR
SR*
DATA N-1
A
DATA N
Β
REGISTER POINTER = X + (N-2)
REGISTER POINTER = X + (N-1)
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
B9
1
ACKNOWLEDGE
8
DETAIL: Α
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
*P FORCES THE BUS
FILTERS TO SWITCH
TO THEIR <=1MHZ
MODE. SR LEAVES
THE BUS FILTERS IN
THEIR CURRENT
STATE.
ACKNOWLEDGE
8
DETAIL: Β
Figure 9. Writing to Sequential Registers X to N
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
● The addressed slave places 8-bits of data on the bus
Reading from a Single Register
from the location specified by the register pointer.
2
Figure 10 shows the protocol for the I C master device to
read one byte of data to the MAX17271. This protocol is
the same as the SMBus specification’s read byte protocol.
The read byte protocol is as follows:
● The master issues a not acknowledge (nA).
● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their
current state.
● The master sends a start command (S).
● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
Note that, when the the MAX17271 receives a stop, it
does not modify its register pointer.
● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
Reading from Sequential Registers
● The master sends an 8-bit register pointer.
● The slave acknowledges the register pointer.
● The master sends a repeated start command (Sr).
Figure 11 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an acknowledge to signal the
slave that it wants more data: when the master has all the
data it requires it issues a not acknowledge (nA) and a
stop (P) to end the transmission.
● The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
● The addressed slave asserts an acknowledge by
pulling SDA low.
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR <=1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
8
NUMBER
OF BITS
1
7
1
0
1
1
1
7
1
1
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A Sr SLAVE ADDRESS
R/nW
A
DATA X
nA P or Sr*
R/nW
Figure 10. Reading from a Single Register with the Read Byte Protocol
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR <=1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
8
NUMBER
OF BITS
1
7
1
0
1
1
1
7
1
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A SR SLAVE ADDRESS
1
A
DATA X
A
R/NW
R/nW
NUMBER
OF BITS
8
1
8
1
8
1
DATA X+1
A
DATA X+2
A
DATA X+3
A
REGISTER POINTER = X + 1 REGISTER POINTER = X + 2 REGISTER POINTER = X + 3
NUMBER
OF BITS
8
1
8
1
8
1
1
P OR
SR*
DATA N-2
A
DATA N-1
A
DATA N
NA
REGISTER POINTER =
X + (N-3)
REGISTER POINTER =
X + (N-2)
REGISTER POINTER =
X + (N-1)
Figure 11. Reading Continuously from Sequential Registers X to N
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
The continuous read from sequential registers protocol is
as follows:
● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a stop (P) ensures that
the bus input filters are set for 1MHz or slower
operation. Issuing an Sr leaves the bus input filters in
their current state.
● The master sends a start command (S).
● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
Engaging HS-mode for operation up to 3.4MHz
● The addressed slave asserts an acknowledge (A) by
Figure 12 shows the protocol for engaging HS-mode
operation. HS-mode operation allows for a bus operating
speed up to 3.4MHz.
pulling SDA low.
● The master sends an 8-bit register pointer.
● The slave acknowledges the register pointer.
● The master sends a repeated start command (Sr).
The engaging HS mode protocol is as follows:
● Begin the protocol while operating at a bus speed of
● The master sends the 7-bit slave address followed
by a read bit (R/W = 1). When reading the RTC time-
keeping registers, secondary buffers are loaded with
the timekeeping register data during this operation.
1MHz or lower
● The master sends a start command (S).
● The master sends the 8-bit master code of 0b0000
1XXX where XXX are don’t care bits.
● The addressed slave asserts an acknowledge by
● The addressed slave issues a not acknowledge (nA).
pulling SDA low.
● The master may now increase its bus speed up to
● The addressed slave places 8-bits of data on the bus
3.4MHz and issue any read/write operation.
from the location specified by the register pointer.
The master may continue to issue high-speed read/write
operations until a stop (P) is issued. To continue operations
in high speed mode, use repeated start (Sr).
● The master issues an acknowledge (A) signaling the
slave that it wishes to receive more data.
● Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a not acknowledge (nA) to signal
that it wishes to stop receiving data.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
8
1
1
ANY R/W PROTOCOL
FOLLOWED BY SR
ANY R/W PROTOCOL
FOLLOWED BY SR
ANY READ/WRITE
PROTOCOL
S
HS-MASTER CODE
nA SR
SR
SR
P
FAST-MODE
HS-MODE
FAST-MODE
Figure 12. Engaging HS Mode
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nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Register Map
ADDRESS
NAME
MSB
LSB
REGISTER MAP
0x09
0x10
0x11
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
GLBL_CNFG[7:0]
GLBL_INT[7:0]
–
–
–
–
SWR
OVLO
DRV[1:0]
TIDL[1:0]
POKB2 POKB1
POKB3M POKB2M POKB1M
BIAS OFF
THI
ON
VOKB
VOKM
POKB3
GLBL_INTM[7:0]
CNFG_BB1_A[7:0]
CNFG_BB1_B[7:0]
CNFG_BB2_A[7:0]
CNFG_BB2_B[7:0]
CNFG_BB3_A[7:0]
CNFG_BB3_B[7:0]
ONM
OVLOM
THIM
TVSIMO1[7:0]
ILIM[1:0]
ADE
ADE
ADE
ENCTL[4:0]
ENCTL[4:0]
ENCTL[4:0]
TVSIMO2[7:0]
ILIM[1:0]
ILIM[1:0]
TVSIMO3[7:0]
Register Details
GLBL_CNFG (0x09)
BIT
Field
7
–
–
–
6
–
–
–
5
4
3
2
1
0
SWR
OTP
DRV[1:0]
TIDL[1:0]
OTP
BIAS OFF
OTP
Reset
OTP
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Disable Auto-Restart (default)
0x1: Enable Auto-Restart
SWR
5
Software Auto-Restart Enable
SIMO Drive Strength Setting
0x0: Slowest transition time (best for EMI)
0x1: A little faster than 0x0
0x2: A little faster than 0x1
DRV
4:3
0x3: Fastest transition time (best for efficiency)
(default)
0x0: 24µs (default)
0x1: 49µs
0x2: 70µs
Maximum Idle Time Between Pulses When
< V
TIDL
2:1
0
V
.
OV
OUT
0x3: 98µs
0x0: Turn on internal BIAS (default)
0x1: Turn off internal BIAS
BIAS OFF
Internal BIAS Disable
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
GLBL_INT (0x10)
BIT
Field
Reset
7
6
–
–
–
5
4
3
2
1
0
ON
0b0
OVLO
0b0
VOKB
0b0
POKB3
0b0
POKB2
0b0
POKB1
0b0
THI
0b0
Access Type Write, Read
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
ON
BITS
DESCRIPTION
ON Pin Rising Edge Interrupt
DECODE
0x0: No rising edge on on pin detected
0x1: Rising edge on on pin detected
7
0x0: No V
Overvoltage Interrupt
Overvoltage Interrupt Detected
SUP
OVLO
VOKB
POKB3
POKB2
POKB1
THI
5
4
3
2
1
0
V
V
Supply OVLO Interrupt
Undervoltage Interrupt
SUP
SUP
0x1: V
SUP
0x0: No V
Undervoltage Interrupt
Undervoltage Interrupt Detected
SUP
0x1: V
SUP
0x0: No OUT3 Power Regulation Interrupt
0x1: OUT3 Power Regulation Interrupt Detected
OUT3 Power Regulation Interrupt
OUT2 Power Regulation Interrupt
OUT1 Power Regulation Interrupt
Overtemperature Threshold Interrupt
0x0: No OUT2 Power Regulation Interrupt
0x1: OUT2 Power Regulation Interrupt Detected
0x0: No OUT1 Power Regulation Interrupt
0x1: OUT1 Power Regulation Interrupt Detected
0x0: No Overtemperature Interrupt
0x1: Overtemperature Interrupt Detected
GLBL_INTM (0x11)
BIT
Field
Reset
7
6
–
–
–
5
4
3
2
1
0
ONM
0b0
OVLOM
0b0
VOKM
0b0
POKB3M
0b0
POKB2M
0b0
POKB1M
0b0
THIM
0b0
Access Type Write, Read
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
ONM
BITS
DESCRIPTION
Mask ON pin rising edge Interrupt
DECODE
0x0: Do not mask ON pin rising edge Interrupt (default)
0x1: Mask ON pin rising edge Interrupt
7
0x0: Do not mask V
Overvoltage Interrupt (default)
SUP
OVLOM
VOKM
5
4
Mask V
Overvoltage Interrupt
Undervoltage Interrupt
SUP
SUP
0x1: Mask V
Overvoltage Interrupt
SUP
0x0: Do not mask V
Undervoltage Interrupt (default)
SUP
Mask V
0x1: Mask V
Undervoltage Interrupt
SUP
0x0: Do not mask OUT3 Power Regulation Interrupt
(default)
0x1: Mask OUT3 Power Regulation Interrupt
POKB3M
POKB2M
3
2
Mask OUT3 Power Regulation Interrupt
Mask OUT2 Power Regulation Interrupt
0x0: Do not mask OUT2 Power Regulation Interrupt
(default)
0x1: Mask OUT2 Power Regulation Interrupt
0x0: Do not mask OUT1 Power Regulation Fault (default)
0x1: Mask OUT1 Power Regulation Interrupt
POKB1M
THIM
1
0
Mask OUT1 Power Regulation Interrupt
Mask Overtemperature Threshold Interrupt
0x0: Do not mask Over-Temperature Interrupt (default)
0x1: Mask Over-Temperature Interrupt
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
CNFG_BB1_A (0x29)
BIT
Field
7
6
5
4
3
2
1
0
TVSIMO1[7:0]
Reset
OTP
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
TVSIMO1[7] = 0b0: 1.2V Offset Disabled
TVSIMO1[7] = 0b1: 1.2V Offset Enabled
OUT1 = 0.8V + 25mV x TVSIMO1[6:0](decimal)
Default Value of OUT1 = 1.2V
TVSIMO1
7:0
Set Voltage for OUT1
CNFG_BB1_B (0x2A)
BIT
Field
7
6
5
ADE
4
3
2
1
0
ILIM[1:0]
OTP
ENCTL[4:0]
OTP
Reset
OTP
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: ILIM1 = 1.1A
0x1: ILIM1 = 0.8A
0x2: ILIM1 = 0.6A
ILIM
7:6
LX Peak Current Limit for OUT1
0x3: ILIM1 = 0.4A (default)
0x0: Disable discharge resistor (default)
0x1: Enable discharge resistor
ADE
5
Enable Active Discharge Resistor for OUT1
ENCTL[4:3]:
0b00 = 0ms (default)
0b01 = 10ms
0b10 = 20ms
0b11 = 30ms
Enable Control for OUT1
Power-Up Delay for OUT1
Power-Down Delay for OUT1
Enable Power Sequencer for OUT1
ENCTL[1]
ENCTL[4:0]
ENCTL[4:3]
ENCTL[2]
ENCTL[2]:
0b0 = (Power-Down Delay = 0ms)
0b1 = (Power-Down Delay = 30ms–Power-Up
Delay) (default)
ENCTL
4:0
Output Force ON ENCTL[0]
ENCTL[1]:
0b0 = Disable Power Sequence for OUT1
0b1 = Enable Power Sequence for OUT1 (default)
ENCTL[0]:
0b00000 = OUT1 No Force On
0bXXXX1 = OUT1 Force On
Maxim Integrated
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
CNFG_BB2_A (0x2B)
BIT
Field
7
6
5
4
3
2
1
0
TVSIMO2[7:0]
Reset
OTP
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
TVSIMO2[7] = 0b0: 1.2V Offset Disabled
TVSIMO2[7] = 0b1: 1.2V Offset Enabled
OUT2 = 0.8V + 25mV x TVSIMO2[6:0](decimal)
Default Value of OUT2 = 1.8V
TVSIMO2
7:0
Set Voltage for OUT2
CNFG_BB2_B (0x2C)
BIT
Field
7
6
5
ADE
4
3
2
1
0
ILIM[1:0]
OTP
ENCTL[4:0]
OTP
Reset
OTP
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: ILIM2 = 1.1A
0x1: ILIM2 = 0.8A (default)
0x2: ILIM2 = 0.6A
ILIM
7:6
LX Peak Current Limit for OUT2
0x3: ILIM2 = 0.4A
0x0: Disable discharge resistor (default)
0x1: Enable discharge resistor
ADE
5
Enable Active Discharge Resistor for OUT2
ENCTL[4:3]:
0b00 = 0ms (default)
0b01 = 10ms
0b10 = 20ms
0b11 = 30ms
ENCTL[2]:
0b0 = (Power-Down Delay = 0ms)
0b1 = (Power-Down Delay = 30ms–Power-Up
Delay) (default)
Enable Control for OUT2
Power-Up Delay for OUT2
Power-Down Delay for OUT2
Enable Power Sequencer for OUT2
ENCTL[1]
ENCTL[4:0]
ENCTL[4:3]
ENCTL[2]
ENCTL
4:0
ENCTL[1]:
0b0 = Disable Power Sequence for OUT2
0b1 = Enable Power Sequence for OUT2 (default)
ENCTL[0]:
0b00000 = OUT2 No Force On
0bXXXX1 = OUT2 Force Onult)
Maxim Integrated
│ 30
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
CNFG_BB3_A (0x2D)
BIT
Field
7
6
5
4
3
2
1
0
TVSIMO3[7:0]
Reset
0x64
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
TVSIMO3[7] = 0b0: 1.2V Offset Disabled
TVSIMO3[7] = 0b1: 1.2V Offset Enabled
OUT3 = 0.8V + 25mV x TVSIMO3[6:0](decimal)
Default Value of OUT3 = 3.3V
TVSIMO3
7:0
Set Voltage for OUT3
CNFG_BB3_B (0x2E)
BIT
Field
7
6
5
ADE
4
3
2
1
0
ILIM[1:0]
OTP
ENCTL[4:0]
OTP
Reset
OTP
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: ILIM3 = 1.1A (default)
0x1: ILIM3 = 0.8A
0x2: ILIM3 = 0.6A
ILIM
7:6
LX Peak Current Limit for OUT3
0x3: ILIM3 = 0.4A
0x0: Disable discharge resistor (default)
0x1: Enable discharge resistor
ADE
5
Enable Active Discharge resistor for OUT3
ENCTL[4:3]:
0b00 = 0ms (default)
0b01 = 10ms
0b10 = 20ms
0b11 = 30ms
ENCTL[2]:
0b0 = (Power-Down Delay = 0ms)
0b1 = (Power-Down Delay = 30ms–Power-Up
Delay) (default)
Enable Control for OUT3
Power-Up Delay for OUT3
Power-Down Delay for OUT3
Enable Power Sequencer for OUT3
ENCTL[1]
ENCTL[4:0]
ENCTL[4:3]
ENCTL[2]
ENCTL
4:0
ENCTL[1]:
0b0 = Disable Power Sequence for OUT3
0b1 = Enable Power Sequence for OUT3 (default)
ENCTL[0]:
0b00000 = OUT3 No Force On
0bXXXX1 = OUT3 Force On
Maxim Integrated
│ 31
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
We calculate the maximum output currents, assuming
reasonable efficiencies
Applications Information
Maximum Output Power
I
I
I
= (1/2) x 79%/(1 + 1.2/2.7) = 272mA
= (1/2) x 83%/(1 + 1.8/2.7) = 249mA
= (1/2) x 87%/(1 + 3.3/2.7) = 196mA
MAX1
MAX2
MAX3
Because the SIMO shares one inductor between three
outputs, the maximum power available at any one output
is a function of the power being used by the other two outputs.
In order to determine if a set of output voltages and loads
can be supported, it is necessary to calculate the duty for
each output, and to guarantee that the total is less than
100%. The sum of the duties is called Utilization (U).
Utilized capacity (U) is calculated as :
I
I
I
I
I
I
OUT1
OUT2
OUT3
U
=
+
+
MAX1
MAX2
MAX3
U = Duty
+ Duty
+ Duty
(Equation 3)
OUT1
OUT2
OUT3
U should be less than 100% , otherwise the outputs will
be under regulated.
The duty for one output is simply the percentage of
switching time required to maintain that output at a given
load. The duty is a function of the maximum load,
U = (80/272) + (75/249) + (50/196)
= 29.4% + 30.1% + 25.5%
Duty = I
/I
(Equation 4)
(n)
LOAD(n) MAX(n)
= 85.0%
where the maximum load is determined by the peak induc-
tor current limit, I , the input and output voltages,
Since U < 100% , this combination of loads can be supported.
LIM(n)
V
and V
and the converter efficiency, Eff
.
IN
OUT(n),
= (I
(n)
SIMO Available Output Current
I
/2) x Eff /(1 + V
/V )
OUT(n) IN
The available output current on a given SIMO channel is
a function of the input voltage, output voltage, the peak
current limit setting, and the output current of the other
SIMO channels.
MAX(n)
LIM(n)
(n)
(Equation 5)
The peak inductor current can be set differently for each
output in order to trade max output current for efficiency,
explaining why a “(n)” is added to the variable names.
Table 7 shows typical output currents for common appli-
cations where the utilized capacity has been calculated
based on Equation 3.
Example: We might like to determine if the following set
of loads can be supported, assuming a 2.7V minimum
input and a 1A peak inductor current for all outputs
ESR_C
= 5mΩ, L = 2.2μH, DCR = 100mΩ
OUT
V
OUT1
V
OUT2
V
OUT3
= 1.2V, I
= 1.8V, I
= 3.3V, I
= 80mA
= 75mA
= 50mA
OUT1
OUT2
OUT3
Table 7. SIMO Available Output Current for Common Applications
PARAMETERS
EXAMPLE 1
2.7V
EXAMPLE 2
3.2V
EXAMPLE 3
3.4V
V
IN_MIN
OUT1
OUT2
OUT3
1V at 75mA
1.2V at 50mA
1.8V at 25mA
0.6A
1V at 50mA
1.2V at 75mA
5V at 25mA
0.6A
1V at 50mA
1.2V at 150mA
1.5V at 100mA
0.6A
I
I
I
LIM1
LIM2
LIM3
0.6A
0.6A
0.8A
1.1A
1.1A
1.1A
Utilized Capacity
91.6%
92.9%
88.4%
Maxim Integrated
│ 32
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
C
IN
reduces the current peaks drawn from the battery or
Inductor Selection
input power source during SIMO regulator operation and
reduces switching noise in the system. The ESR/ESL of the
input capacitor should be very low (i.e., ≤ 5mΩ + ≤ 500pH)
for frequencies up to 2MHz. Ceramic capacitors with X5R
or X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
Choose a 2.2μH inductor with a saturation current that is
greater than the the maximum peak current limit setting that
is used for all of the SIMO buck-boost channels (I ).
LIM
For example, if the 3-channel SIMO buck-boost has
programmed peak current limit settings of 0.6A, 0.8A, and
1.1A, then choose the saturation current to be greater
than 1.1A.
To fully utilize the available input voltage range of the
SIMO (5.5V max), use a 6.3V capacitor voltage rating.
Choose the RMS current rating of the inductor (typically
the current at which the temperature rises appreciably)
based on the expected load currents for the system. For
systems where the expected load currents are not well
known, you can choose the RMS current to be at least
60% of the max value associated with the maximum
peak current limit setting for all of the SIMO buck-boost
V
is a critical discontinuous current path that requires
PWR
careful bypassing. When the SIMO detects that an output
is below its regulation threshold, a switching cycle begins
and the V
current ramps up as a function of the input
PWR
voltage and inductor (di/dt = V /L) until it reaches the
IN
peak current limit (I ). Once I
is reached, the V
LIM
LIM
PWR
channels (I ). 60% of the max value is a safe choice
current falls to zero rapidly (~5ns). This rapid current
LIM
because the SIMO buck-boost regulator implements a
discontinuous conduction mode (DCM) control scheme,
which returns the inductor current to zero each cycle.
decrease makes the parasitic inductance in the PGND to
input capacitor to V
path critical. In the PCB layout,
PWR
place C as close as possible to the power pins (V
IN
PWR
and PGND) to minimize parasitic inductance. If making
connections to the input capacitor through vias, ensure
that the vias are rated for the expected input current so
they do not contribute excess inductance and resistance
between the bypass capacitor and the power pins.
Consider the DC-resistance (DCR), AC-resistance (ACR)
and solution size of the inductor. Typically, smaller
sized inductors have larger DCR and ACR that reduces
efficiency and the available output current. Note that many
inductor manufacturers have inductor families which
contain different versions of core material in order to balance
trade offs between DCR and ACR (i.e., core losses).
Boost Capacitor Selection
Choose the boost capacitance (C ) to be 100nF.
BST
See Table 8 for a list of recommended inductors. Inductor
technology may have advanced since the date on which
this table was generated, so it may no longer represent
the best market offerings.
Smaller values of C
(< 50nF) result in insufficient
BST
gate drive for the output FETs M3_x. Larger values of
(> 10nF) have the potential to degrade the startup
C
BST
performance. Ceramic capacitors with 0201 or 0402
case size are recommended. The voltage rating for C
should be greater than or equal to 6.3V.
BST
Input Capacitor Selection
Choose the input bypass capacitance (C ) to be 10µF.
IN
Larger values of C improve the decoupling for the SIMO
IN
regulator.
Table 8. Recommended Inductors
L
(μH)
I
I
MAX DCR
X
(mm)
Y
(mm)
Z
SAT
(A)
RMS
(A)
MANUFACTURER
PART NUMBER
(mΩ)
(mm)
MURATA
MURATA
MURATA
WURTH
DFM18PAN2R2MG0L
DFE201208S-2R2M
DFE201612E-2R2M
74479299222
2.2
2.2
2.2
2.2
2.2
2.2
1.4
1.8
2.4
3.5
3.7
7
0.9
1.4
1.8
2.1
8
390
204
116
106
23.5
26
1.6
2
0.8
1.2
1.6
3.2
4
1
0.8
1.2
1.2
2.1
3.1
2
2.5
4
COILCRAFT
WURTH
XFL4020-222ME
74438357022
5.2
4.1
4.1
Maxim Integrated
│ 33
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
slowly. This rapid current increase makes the parasitic
inductance in the OUTx to output capacitor to PGND path
Output Capacitor Selection
Choose each output bypass capacitance (C
) based
OUTx
critical. In the PCB layout, place C
as close as possi-
OUTx
on the desired output voltage ripple. Larger values of
improve the output voltage ripple, but also increase
ble to OUTx and PGND to minimize parasitic inductance.
If making connections to the output capacitor through
vias, ensure that the vias are rated for the expected out-
put current so they do not contribute excess inductance
and resistance.
C
OUTx
the input surge currents during soft-start and output voltage
changes. The peak-to-peak output voltage ripple (∆V) is
a function of the inductor value (L), the output voltage
(V ), and the peak current limit setting (I ). The output
OUT
LIM
capacitor value can be calculated based on Equation 6.
Unused Outputs
2
LxI
Do not leave unused outputs unconnected. If an output
left floating is accidentally enabled, inductor current will
dump into an open pin, and the output voltage will soar
above the absolute maximum rating, potentially causing
damage to the device. If the unused output is guaranteed
to be always disabled, connect that output to ground. If an
unusedoutputcanbeenabledatanypointduringoperation
(such as startup or accidental software access), then
implement one of the following:
LIM
C
=
(Equation 6)
OUT
2·V
· ∆ V
OUT
For example, for a an output voltage of 3.3V, using a
2.2μH inductor, peak current limit of 1A, if 1% peak to
peak output voltage ripple is desired, then the required
effective output capacitance is :
2
2.2μH x1A
= 10.1μF
C
=
2 x 3.3V x 33mV
OUT
1) Bypass the unused output with a 1uF ceramic capacitor
to ground.
So a 22μF rated output capacitor can be used which would
derate to no less than 10.1μF as a function of dc bias.
2) Connect the unused output to the power input
(V
). This connection is beneficial because it does
PWR
C
is required to keep the output voltage ripple small.
OUTx
not require an external component for the unused
output. The power input and its capacitance receives
the energy packets when the regulator is enabled and
The impedance of the output capacitor (ESR, ESL) should
be very low (i.e., ≤ 5mΩ + ≤ 500pH) for frequencies up to
2MHz. Ceramic capacitors with X5R or X7R dielectric are
highly recommended due to their small size, low ESR,
and small temperature coefficients.
V
IN
is below the target output voltage of the unused
output. Circulating the energy back to the power input
ensures that the unused output voltage does not fly
high.
A capacitor's effective capacitance decreases with
increased DC bias voltage. This effect is more pro-
nounced as capacitor case sizes decrease. Due to this
characteristic, it is possible for an 0603 case size capaci-
tor to perform well, while an 0402 case size capacitor of
the same value performs poorly. The SIMO regulator is
stable with low output capacitance (1μF) but the output
voltage ripple would be large; consider the effective out-
put capacitance value after initial tolerance, bias voltage,
aging, and temperature derating.
• Note that the active discharge resistor of the unused
output should be disabled (ADE = 0).
3) Connect the unused output to another power output
that is above the target voltage of the unused output.
In the same way as the option listed above, this
connection is beneficial because it does not require
an external component for the unused output. Unlike
the option above, this connection is preferred in cases
where the unused output voltage bias level is always
above the unused output voltage target because no
energy packages are provided to the unused output.
OUTx is a critical discontinuous current path that requires
careful bypassing. When the SIMO detects that an output
is below its target, it charges the inductor to a peak cur-
• Note that the active discharge resistor of the unused
output should be disabled (ADE = 0).
rent limit (I ) and then discharges that inductor into the
LIM
output. At the moment the charge is applied to the output,
the current increases rapidly and then decays relatively
Maxim Integrated
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Typical Application Circuits
IN
IN
(2.7V to 3.3V)
(2.7V TO 3.3V)
VSUP
GND
VPWR
PGND
VSUP
GND
VPWR
PGND
LXA
C6
10µF
C5
1µF
C6
10µF
C5
1µF
MAX17270
MAX17271
VIO
1.7V to 3.6V
LXA
LXB
VIO
L1
2.2µH
R2
2.2kΩ
R1
2.2kΩ
EN3
EN2
EN1
L1
2.2µH
ENABLE LOGIC
INPUTS
SCL
LXB
2
I C
SDA
IRQB
C4
100nF
C4
100nF
INTERFACE
BST
OUT3
OUT2
OUT1
IN
BST
OUT3
OUT2
OUT1
OUT3
(3.3V/50mA)
OUT2
(1.8V/75mA)
OUT1
(1.2V/50mA)
OUT3
(3.3V/50mA)
OUT2
(1.8V/75mA)
OUT1
(1.2V/50mA)
R3
10kΩ
RSEL3
RSEL2
RSEL1
R3
8.45kΩ
RSTB
ON
RESET
R2
16.9kΩ
IN
R4
100kΩ
C1
22µF
C2
10µF
C3
10µF
C1
22µF
C2
10µF
C3
10µF
R1
536kΩ
Maxim Integrated
│ 35
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Ordering Information
TEMPERATURE NUMBER OF
PART NUMBER
MAX17270ETE+
MAX17271ETE+
MAX17270ENE+
MAX17270AENE+
PIN-PACKAGE
FEATURES
RANGE
OUTPUTS
2
-40°C to +85°C
3
16 pin, 3 x 3mm TQFN
Enable Inputs, Resistor Configurable
2
I C Configurable, Pushbutton Input,
2
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
3
3
3
16 pin, 3 x 3mm TQFN
RSTB Output
4 x 4 bump, 0.4mm Pitch WLP Enable Inputs, Resistor Configurable
Enable Inputs, Resistor Configurable,
4 x 4 bump, 0.4mm Pitch WLP
Active Discharge Enabled
2
I C Configurable, Pushbutton Input,
MAX17271ENE+
-40°C to +85°C
3
4 x 4 bump, 0.4mm Pitch WLP
RSTB Output
+Denotes a lead(Pb)-free/RoHS-compliant package.
Maxim Integrated
│ 36
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MAX17270/MAX17271
nanoPower Triple-Output, Single-Inductor,
Multiple-Output (SIMO) Buck-Boost Regulator
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1/18
Initial release
—
Updated Electrical Characteristics table, Typical Operating Characteristics section,
Table 1, Table 7, and Inductor Selection section
4, 5, 7, 8, 12,
25, 26, 29
1
2/18
2
3
5/18
8/18
Updated Typical Operating Characteristics
Updated Typical Operating Characteristics and Ordering Information
9, 33
Removed references to MAX17272 and MAX17273, updated Applications section,
removed TOCs 4 through 6, updated Pin Description and Register Details tables,
updated Ordering Information table
1, 2, 4, 5, 7-14,
17-21, 23-25,
27-34
4
5
7/19
9/19
2
Added PODs to Package Information section, updated I C Slave Address section,
4, 5, 22, 36
updated Ordering Information table
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 37
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