MAX17526A [MAXIM]
5.5V to 60V, 6A Current-Limiter with OV, UV, Reverse Protection, and Power Limit;
| 型号： | MAX17526A |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 5.5V to 60V, 6A Current-Limiter with OV, UV, Reverse Protection, and Power Limit |
| 文件： | 总27页 (文件大小：772K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
General Description
Benefits and Features
● Robust Protection Reduces System Downtime
The Olympus series of ICs are the industry's smallest
and robust integrated system protection solutions. The
MAX17526A adjustable power limiter offers a unique
feature to limit power drawn from supplies or delivered to
loads, amongst a host of protection features. These pro-
tection features include adjustable input overvoltage and
undervoltage protection, positive and negative input volt-
age protection, overcurrent protection, reverse-current
protection and overtemperature protection. The device
• Wide Input-Supply Range: +5.5V to +60V
• Active Power Limit to Protect Supply or Load
(MAX17526A)
• Programmable Input Overvoltage Setting up to 40V
• Negative Input Fault Tolerant (with External NFET)
• Reverse Current Protection (with External NFET)
• Low R
Internal NFET (30mΩ typ)
ON
features a built-in low R
integrated gate drive for an optional external NFET.
(30mΩ typ) NFET, and an
● Dual-Stage Current Limiting
ON
• 1.0x Startup Current (MAX17526A)
• 1.5x Startup Current (MAX17526B)
• 2.0x Startup Current (MAX17526C)
● Fast Startup and Brownout Recovery
The device highlights a power limit feature that allows
programmed reduction in current limit, as an inverse func-
tion of an external voltage. Input or output power limit is
achieved by limiting the current through the device as a
function of input or output voltages.
• Continuous Current-Limit During Startup
• Thermal Foldback Current-Limit
● Flexible Design to Maximize Reuse and Minimize
Requalification
Input undervoltage protection level is adjustable between
5.5V and 24V, and input overvoltage protection level is
adjustable between 6V and 40V. The input undervolt-
age lockout (UVLO) threshold and overvoltage lockout
(OVLO) threshold are adjusted using external resistors.
The device offers a factory preset internal UVLO and
OVLO thresholds at 12.4V (typ) and 36.2V (typ) respec-
tively. The factory preset levels can be invoked by con-
necting the UVLO and/or the OVLO pins to GND.
• Adjustable UVLO and OVLO Thresholds
• ±8.5% Accurate Programmable Current Limit from
0.6A to 6.0A Over Full Temperature Range
• Programmable Overcurrent Response: Continu-
ous, Autoretry, and Latch-Off Modes
• Logic Level and High-Voltage Enable Inputs
(EN and HVEN)
The device features programmable current limit protec-
tion up to 6A. Current limit threshold is programmed by
connecting a resistor from the SETI pin to GND. When
the device current reaches the programmed threshold,
the controller inside the device prevents further increase
in current by modulating the internal NFET resistance.
The device offers three different behavioral modes under
current limited operation: Continuous mode, Autoretry
mode, and Latch-off mode. The continuous current limit
feature offers control of inrush current at startup while
charging high capacitances at the output side. Two addi-
tional part options that feature a dual-stage current-limit
mode, in which the current is continuously limited to 1.5x
(MAX17526B) and 2.0x (MAX17526C), the programmed
limits, are available upon request. The power limit feature
is disabled in the MAX17526B/C part options. The voltage
appearing on the SETI pin is proportional to the instan-
taneous current flowing through the device, and can be
read by the supervisory system.
• Protected External NFET Gate Drive
● Reduced Solution Footprint
• 20-Pin 5mm x 5mm TQFN-EP Package
• Integrated NFET for Common-Use Protection
Requirements
Applications
● Industrial Power Distribution Systems
● Control and Automation
● Motion Control Drives
● Human Machine Interfaces
Ordering Information appears at end of data sheet.
MAX17526A also offers reverse-current protection and
input reverse voltage polarity protection when deployed
with an external NFET, and built-in overtemperature
protection. It is available in a 20-pin 5mm x 5mm TQFN-
EP package. The device operates over -40°C to +125°C
extended temperature range.
19-100358; Rev 1; 11/18
MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Typical Operating Circuit
V
IN
NFET
GN
V
SYS
C
IN_IC
C
IN
IN IN IN IN IN
SN
V
IN
SYSTEM
CONTROLLER
UVLO
OUT
R1*
R3*
OUT
OUT
OUT
OUT
R2*
R4*
V
OUT
V
SYS
ADC
MAX17526A
C
OVLO
OUT
V
IN
220kΩ
R
SETI
SETI
FLAG
EN
HVEN
FAULT
EN
PLIM
GND
(EP)
CLMODE
V
OUT
R5
220kΩ
R6
R1 = R3 ≥ 10k
*R1, R2, R3, AND R4 ARE ONLY REQURED FOR ADJUSTABLE UVLO/OVLO FUNCTIONALITY.
OTHERWISE, TIE THE PIN TO GND TO USE THE INTERNAL, PRE-PROGRAMMED THRESHOLD.
R5, R6 REQUIRED FOR ADJUSTABLE PLIM ONLY. OTHERWISE, TIE THE PIN TO GND TO
DISABLE THIS FUNCTION.
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Absolute Maximum Ratings
IN to GND (Note 1)................................................-0.3V to +64V
IN Current (DC) ..................................................................6.51A
OUT to GND.................................................-0.3V to V + 0.3V
Continuous Power Dissipation (T = +70°C, TQFN derate
IN
A
HVEN to GND (Note 1) ................................-0.3V to V + 0.3V
34.5mW/°C above +70°C.)....................................... 2758mW
Operating Temperature Range......................... -40°C to +125°C
Junction Temperature....................................... -40°C to +150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature ( soldering, 10s) ................................+300°C
Soldering Temperature (reflow).......................................+260°C
IN
SN to GND .............................................................-62V to +64V
GN to GND...........................................(SN - 0.3V) to (SN + 6V)
UVLO, OVLO, PLIM, FLAG to GND ..........-0.3V to (V + 0.3V)
IN
EN, CLMODE to GND...............................................-0.3V to 6V
SETI to GND .................................-0.3V to min (V + 0.3V, 6V)
IN
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note 1: An external NFET or diode is required to achieve negative input protection.
Package Information
PACKAGE TYPE: 20-PIN TQFN
Package Code
T2055+6C
Outline Number
21-0140
Land Pattern Number
90-0010
THERMAL RESISTANCE, FOUR-LAYER BOARD:
Junction to Ambient (θ
)
29°C/W
2°C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Electrical Characteristics
(V = 5.5V to 60V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 24V, T = +25°C) (Note 2)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
IN Voltage Range
V
5.5
60.0
28
V
IN
16
V
V
= 0V, V
= 0V, V
= 0V, V
= 5V, V = V
= 40V
= 24V
=
EN
HVEN
HVEN
HVEN
IN
SN
Shutdown Input Current
Shutdown Output Current
I
μA
SHDN
9.9
17.0
= 5V, V = V
EN
IN
SN
V
V
= 5V, V
= V
EN
OUT
SN IN
I
80
170
μA
OFF
= 40V
Supply Current
I
1.26
1.90
mA
V
= V = V
= 24V, V
= 0V
IN
SN
IN
OUT
HVEN
UVLO, OVLO
V
V
rising, UVLO connected to GND
falling, UVLO connected to GND
11.9
11.5
12.4
12.0
3
13.0
12.5
Internal Undervoltage-Trip
Level
IN
V
V
V
%
V
UVLO
OVLO
IN
UVLO Threshold Hysteresis
Internal Overvoltage-Trip Level
OVLO Threshold Hysteresis
V
V
rising, OVLO connected to GND
falling, OVLO connected to GND
34.7
32.2
36.2
34.1
6
37.6
35.8
SN
SN
%
V
V
V
rising
12.2
11.9
1.20
1.18
0.15
12.8
12.4
1.26
1.22
0.38
13.4
12.9
1.33
1.27
0.50
Undervoltage-Trip Level on
Output
OUT
V
UVLO_OUT
falling, UVLO trip point
OUT
UVLO rising
UVLO falling
External UVLO Set Voltage
V
V
V
SET_UVLO
External UVLO Select Voltage
V
UVLO_SEL
External UVLO Leakage
Current
I
-250
+250
nA
UVLO_LEAK
OVLO rising
OVLO falling
1.18
1.09
0.15
1.22
1.15
0.38
1.27
1.20
0.50
External OVLO Set Voltage
V
V
V
SET_OVLO
External OVLO Select Voltage
V
OVLO_SEL
External OVLO Leakage
Current
I
-250
5.5
6
+250
24.0
40
nA
OVLO_LEAK
External UVLO Adjustment
Range
(Note 3)
(Note 3)
V
V
External OVLO Adjustment
Range
GN, SN
V
< 8V, V
= 5V, no reverse
IN
EN
3.9
4.98
9
4.2
5.25
18
5.5
5.60
28
External NFET Gate Drive
Voltage
condition
V
V
GN-SN
V
= 5V, no reverse condition
EN
EN
V
= 5V, V
= V
, no reverse
GN
SN
Gate Active Pullup Current
μA
condition
Gate Active Pulldown
Resistance
V
= 5V, reverse condition
140
mΩ
EN
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Electrical Characteristics (continued)
(V = 5.5V to 60V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 24V, T = +25°C) (Note 2)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.7
MAX
6.1
UNITS
kΩ
V
V
= 0V, V
= 0V, V
= 5V, V
= 5V, V
- V = 1.5V
SN
Shutdown Gate Pulldown
Resistance
EN
HVEN
GN
3.9
8.0
MΩ
- V = 0.5V
EN
HVEN
GN
SN
INTERNAL FETs
Internal FETs On-Resistance
R
I
= 100mA, V ≥ 10V, T = +25ºC
30
42
mΩ
ON
LOAD
IN
A
Current-Limit Adjustment
Range
I
0.6
6.0
A
LIM
0.6A ≤ I
≤ 6A (T = +25°C), V
<
LIM
A
PLIM
-6
+6
V
Current-Limit Accuracy
I
PLIM_TH
%
LIM_ACC
0.6A ≤ I
≤ 6A, V
< V
-8.5
+8.5
LIM
PLIM
PLIM_TH
Increase in (V - V
) drop until
FLAG Assertion Drop-Voltage
IN
OUT
V
490
-5.4
17
mV
mV
μs
FA
FLAG asserts, V = 24V
Threshold
IN
Slow Reverse-Current-Blocking
Threshold
V
V
- V
OUT
, falling
-0.5
-78
-10.5
30
RIB_SLOW
IN
Slow Reverse-Current-Blocking
Response Time
t
(Note 4)
- V
RIB_SLOW
Fast Reverse-Current-Blocking
Threshold
V
V
, falling
-98
108
-118
135
mV
ns
RIB_FAST
IN
OUT
Fast Reverse-Current-Blocking
Response Time
t
(Note 5, Note 8), C
= 10nF
RIB_FAST
GS
Reverse-Current-Blocking
Rising Threshold
V
V
V
- V , rising
OUT
65
100
135
mV
mA
RIB_RISING
SN
Reverse Output Current
PLIM
I
= 0V, V
= 24V, IN floating
3.20
5.11
OUT_REV
SN
OUT
PLIM Limit Threshold Voltage
V
0.867
1.009
1.151
3 x
V
PLIM_TH
V
PLIM_
PLIM Limit Operation Range
V
PLIM_
TH
TH
SETI
R
x I
V
V
< V
PLIM_TH
1.5
V
SETI
LIM
RI
PLIM
Current-Mirror Output Ratio
C
25000
A/A
IRATIO
LOGIC INPUT (HVEN, CLMODE, EN)
1.05
1.0
2.00
1.9
5
3.30
2.8
HVEN rising
HVEN falling
V
V
HVEN Threshold Voltage
HVEN _TH
%
HVEN Threshold Hysteresis
51
72
μA
V
I
V
= 60V
HVEN
HVEN Input Leakage Current
EN Input-Logic High
HVEN_LEAK
V
1.4
-1
IH
EN Input-Logic Low
V
0.4
V
IL
EN_LEAK
EN Input Leakage Current
I
V
= 0V, 5V
+1
μA
EN
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Electrical Characteristics (continued)
(V = 5.5V to 60V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 24V, T = +25°C) (Note 2)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CLMODE_
CLMODE Input-Logic High
3.59
4.00
4.52
V
IH
CLMODE Input-Logic Low
CLMODE Pullup Current
V
0.49
5.3
0.78
10.0
1.01
14.6
V
CLMODE_IL
μA
LOGIC OUTPUT (FLAG)
Logic-Low Voltage
I
= 1mA
0.4
1
V
SINK
Input Leakage Current
μA
mA
V
= 5.5V, FLAG open drain off
IN
4
FLAG Protection Current
FLAG open drain on
TIMING CHARACTERISTICS (NOTE 6)
V
= 24V, switch OFF to ON, R =
LOAD
IN
Switch Turn-On Time
t
240Ω, I
from 20% to 80% of V
= 1A, C
= 4.7μF, V
68
μs
μs
ON
LIM
OUT
OUT
IN
Fault Recovery nFET Turn-On
Time
t
Turn-on delay after fault timers expired
V > V , turn-on delay of
OUT
200
500
ON_NFET
Fault Recovery External NFET
Turn-On Time
UVLO_OUT
t
1.09
1.20
3
1.32
ms
μs
μs
ON_EXNFET
external NFET after fault timers expired
OVP Switch Response Time
t
OVP_RES
Overcurrent Protection
Response time
I
= 5A, I
step from 3A to 30A.
LIM
OUT
t
3
OCP_RES
Time to turn the switch off.
Initial start current-limit foldback timeout
(Figure 5)
Startup Timeout
t
1090
21.8
1.09
1200
24.0
1.20
1320
26.4
1.32
ms
ms
ms
STO
Startup Initial Time
IN Debounce Time
t
(Figure 5)
STI
Additional turn-on delay if V
<
OUT
t
DEB
V
, see Figures 5–8
UVLO_OUT
Blanking Time
t
Figures 7 and 8
Figure 7 (Note 7)
21.8
654
24.0
720
26.4
792
ms
ms
BLANK
t
RETRY
Autoretry Time
THERMAL PROTECTION
Thermal Foldback
T
150
165
10
°C
°C
°C
J(FB)
Thermal Shutdown
Thermal Shutdown Hysteresis
T
J
T
J(HYS)
Note 2: All devices are 100% production-tested at T = +25°C. Limits over the operating-temperature range are guaranteed by
A
design; not production tested.
Note 3: Not production-tested, user-adjustable. See the Overvoltage Lockout (OVLO) and Undervoltage Lockout (UVLO) sections.
Note 4: Time from V - V
voltage transition from 200mV to -50mV until GN pin voltage falls to V
voltage transition from 200mV to -250mV until GN pin voltage falls to V
+ 1V (Figure 1).
IN
OUT
OUT
SN
Note 5: Time from V - V
+ 1V (Figure 2).
IN
SN
Note 6: All timing is measured using 20% and 80% levels, unless otherwise specified.
Note 7: The autoretry time-to-blanking time ratio is fixed and is equal to 30.
Note 8: Guaranteed by design, not production tested.
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
200mV
V
> V
< V
IN
OUT
0mV
RIB_SLOW
V
V
IN
OUT
-50mV
t
RIB_SLOW
V
GN
1.0V
0.0V
NOTE: V = V
IN
SN
Figure 1. Slow Reverse-Current-Blocking Response Time
200mV
0mV
V
> V
IN
OUT
OUT
V
RIB_FAST
V < V
IN
-250mV
t
RIB_FAST
V
GN
1.0V
0.0V
NOTE: V = V
IN
SN
Figure 2. Fast Reverse-Current-Blocking Response Time
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Typical Operating Characteristics
(V = 24V, C = 1μF, C
= 1μF, T = +25°C, unless otherwise noted.)
A
IN
IN
OUT
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
QUIESCENT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
toc03
toc01
toc02
50
45
40
35
30
25
20
15
10
5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.4
1.3
1.3
1.2
1.2
1.1
1.1
1.0
EN = LOW
OUT = GND
HVEN = HIGH
TA = +125°C
VSN = 36V
TA = +25°C
TA = -40°C
VSN = 60V
VSN = 24V
VSN = 36V
VSN = 12V
VSN = 24V
VSN = 12V
VSN = 5.5V
0
-50 -25
0
25
50
75 100 125 150
5
10 15 20 25 30 35 40 45 50 55 60
SUPPLY VOLTAGE (V)
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
NORMALIZED UVLO THRESHOLD
NORMALIZED OVLO THRESHOLD
vs. TEMPERATURE
NORMALIZED INTERNAL FET
ON-RESISTANCE vs. SUPPLY VOLTAGE
vs. TEMPERATURE
toc04
toc05
toc06
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.10
1.05
1.00
0.95
0.90
NORMALIZED TO
TA = +25°C
NORMALIZED TO
VSN = 24V
NORMALIZED TO
TA = +25°C
-50 -25
0
25
50
75 100 125 150
5
10 15 20 25 30 35 40 45 50 55 60
SUPPLY VOLTAGE (V)
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
NORMALIZED INTERNAL FET
ON-RESISTANCE vs. OUTPUT CURRENT
HVEN INPUT CURRENT
NORMALIZED INTERNAL FET
ON-RESISTANCE vs. TEMPERATURE
vs. VHVEN
toc07
toc08
toc09
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
100
90
80
70
60
50
40
30
20
10
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
NORMALIZED TO
IOUT = 1A
NORMALIZED TO
TA = 25°C
TA = +125°C
TA = +25°C
TA = -40°C
0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
OUTPUT CURRENT (A)
0
12
24
36
48
60
-50 -25
0
25
50
75 100 125 150
VHVEN (V)
TEMPERATURE (°C)
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Typical Operating Characteristics (continued)
(V = 24V, C = 1μF, C
= 1μF, T = +25°C, unless otherwise noted.)
IN
IN
OUT
A
NORMALIZED CURRENT LIMIT
vs. TEMPERATURE
NORMALIZED CURRENT LIMIT
vs. SUPPLY VOLTAGE
CURRENT LIMIT vs. RSETI
toc12
toc11
toc10
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
1.05
6
5
4
3
2
1
0
RSETI = 37.5kΩ
NORMALIZED TO
VSN = +24V
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
RSETI = 37.5kΩ
NORMALIZED TO
TA = +25°C
5
10 15 20 25 30 35 40 45 50 55 60
SUPPLY VOLTAGE (V)
-50 -25
0
25
50
75 100 125 150
0
10
20
30
40
50
60
RSETI (kΩ)
TEMPERATURE (°C)
CURRENT SENSE RATIO
vs. OUTPUT CURRENT
SWITCH TURN-ON TIME
vs. TEMPERATURE
SWITCH TURN-OFF TIME
vs. TEMPERATURE
toc13
toc15
toc14
26000
25750
25500
25250
25000
24750
24500
24250
24000
200
180
160
140
120
100
80
10
9
8
7
6
5
4
3
2
1
0
EN TRANSITION TO IOUT FALLING
TO 10% OF INITIAL VALUE
RL = 240Ω
RL = 240Ω
60
40
20
0
-50 -25
0
25
50
75 100 125 150
0
1
2
3
4
5
6
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
OUTPUT CURRENT (A)
TEMPERATURE (°C)
REVERSE-BLOCKING RESPONSE
POWER-UP RESPONSE
CURRENT-LIMIT RESPONSE
toc18
toc16
toc17
24V
VSN
20V/div
20V/div
VSN
20V/div
20V/div
VSN
20V/div
20V/div
35V
24V
VOUT
VOUT
VOUT
VFLAG
VFLAG
5V/div
5A/div
5V/div
VFLAG
5V/div
ILIM = 6A
IL = 100mA TO SHORT ON OUT WITH 10A/s
IOUT
IIC
200mA/div
IIC
10A/div
400µs/div
200ms/div
4µs/div
Maxim Integrated
│ 9
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Typical Operating Characteristics (continued)
(V = 24V, C = 1μF, C
= 1μF, T = +25°C, unless otherwise noted.)
IN
IN
OUT
A
THERMAL FOLDBACK DUE TO
OUTPUT SHORT-CIRCUIT
AUTORETRY TIME (tRETRY
)
OUTPUT SHORT-CIRCUIT RESPONSE
toc21
toc19
toc20
VSN
20V/div
20V/div
VSN
VSN
20V/div
20V/div
20V/div
20V/div
AUTORETRY MODE
ILIM = 1A
AUTORETRY MODE
ILIM = 6A
AUTORETRY MODE
ILIM = 1A
VOUT
VOUT
VOUT
5V/div
1A/div
VFLAG
VFLAG
5V/div
1A/div
VFLAG
5V/div
1A/div
IOUT
IOUT
IOUT
4ms/div
4ms/div
200ms/div
POWER-UP RESPONSE WITH 1000µF
CURRENT LIMIT, POWER LIMIT
vs. SUPPLY VOLTAGE
CAPACITOR AT NO LOAD
OUTPUT POWER-LIMIT RESPONSE
toc23
toc24
toc22
7
6
5
4
3
2
1
0
140
120
100
80
VSN
20V/div
20V/div
VSN
20V/div
20V/div
ILIM = 1A
CL = 1000µF
VPLIM = VOUT/10
VOUT
MAX17526A
ILIM = 1A
ISTART-UP = 1.0x
VOUT
VFLAG
IOUT
1A/div
5V/div
1A/div
60
CURRENT LIMIT
POWER LIMIT
40
POUT
10W/div
IOUT
(VOUT × IOUT
)
RSETI = 6.25kΩ
VPLIM = VOUT/21
20
0
10ms/div
4ms/div
5
10
15
20
25
30
35
40
SUPPLY VOLTAGE (V)
POWER-UP RESPONSE WITH 1000µF
POWER-UP RESPONSE WITH 1000µF
CAPACITOR AT NO LOAD
CAPACITOR AT NO LOAD
toc26
toc25
VSN
VSN
20V/div
20V/div
20V/div
20V/div
MAX17526C
ILIM = 1A
MAX17526B
ILIM = 1A
VOUT
VOUT
ISTART-UP = 2.0x
ISTART-UP = 1.5x
VFLAG
VFLAG
5V/div
1A/div
5V/div
1A/div
IOUT
IOUT
4ms/div
4ms/div
Maxim Integrated
│ 10
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Pin Configuration
TOP VIEW
15
14
13
12
11
16
17
18
19
20
10
9
PLIM
FLAG
OVLO
CLMODE
SETI
MAX17526A
MAX17526B
MAX17526C
8
UVLO
SN
7
EN
6
GN
HVEN
EP
5
+
1
2
3
4
TQFN
5mm x 5mm
Maxim Integrated
│ 11
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Pin Description
PIN
1-5
6
NAME
IN
FUNCTION
Input Pins. For Hot Plug-In applications, see the Applications Information section.
GN
Gate Driver Output for External NFET.
Return for External NFET Gate Drive and Input Voltage Sense Pin. Connect to source of external NFET
as shown in the Typical Operating Circuit. Bypass SN to GND with a 4.7μF ceramic capacitor. SN serves
as the undervoltage/overvoltage sensed input when preprogrammed UVLO/OVLO is used. Connect SN
to IN if external NFET is not used.
7
SN
UVLO Adjustment Pin. Connect UVLO to GND to use the default internal UVLO threshold. Connect resis-
tive potential divider from SN/IN to GND to set the UVLO threshold externally and override the preset
internal UVLO threshold.
8
9
UVLO
OVLO
OVLO Adjustment Pin. Connect OVLO to GND to use the default internal OVLO threshold. Connect re-
sistive potential divider from SN/IN to GND to set the OVLO threshold externally and override the preset
internal OVLO threshold.
Power Limit Adjustment Pin. Connect PLIM to an external resistive potential divider to define a threshold
at which the power limit feature starts reducing the current-limit threshold. Connect PLIM to GND to dis-
able this feature and have the current-limit set only by the resistor placed on SETI.
10
PLIM
11-15
OUT
Output Pins. For a long output cable or inductive load, see the Applications Information section.
Open-Drain, Fault Indicator Output. FLAG goes low when:
●
●
●
●
The (V - V
) voltage exceeds V
.
FA
IN
OUT
16
Thermal shutdown is active.
Input voltage falls below UVLO threshold or rises above OVLO threshold.
is less than 3.2kΩ.
FLAG
R
SETI
Current-Limit Mode Selector Pin. Leave CLMODE unconnected for Continuous mode. Connect CLMODE
to GND for Autoretry mode. Connect a 220kΩ resistor between CLMODE and GND for Latch-off mode.
17
18
CLMODE
SETI
Overcurrent Limit Adjustment Pin and Current Monitoring Output. Connect a resistor from SETI to GND
to set overcurrent limit. See the Setting the Current-Limit Threshold section.
19
20
EN
Active-High Enable Input. See Table 1.
60V Capable Active-Low Enable Input. See Table 1.
HVEN
Ground/Exposed Pad. Connect GND/EP to a large GND plane with several thermal vias for best thermal
performance. Refer to the MAX17526A EV kit data sheet for a reference layout design.
-
GND/EP
Maxim Integrated
│ 12
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Functional Diagrams
GN
IN IN IN IN IN
SN
OUT
CHARGE
PUMP
OUT
OUT
OUT
OUT
SETI
IN
REVERSE
CURRENT FLOW
CONTROL
CURRENT-
LIMIT
CONTROL
CHARGE-
PUMP
CONTROL
V
SET
PLIM
UVLO
V
UVLO_SEL
FLAG
SN
CONTROL LOGIC
V
SET
EN
HVEN
OVLO
V
OVLO_SEL
GND
(EP)
CLMODE
Maxim Integrated
│ 13
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
The device can be turned On or Off through two indepen-
dent enable inputs, EN and HVEN, by a master supervi-
sory system. This allows the master supervisory system
to Turn On or Off power delivery to connected loads.
Detailed Description
The MAX17526A offers adjustable protection boundaries
for systems against input voltage faults, and overcur-
rent fault, in addition to a programmable power limiting
function. Input voltage faults (with positive polarity) are
protected up to +60V, by an internal NFET featuring low
ON-resistance (30mΩ typ). The device features fixed or
programmable overvoltage lockout (OVLO) and under-
voltage lockout (UVLO) thresholds by using internal or
external voltage-dividers. Factory preset internal fixed
thresholds may be invoked by connecting the OVLO and/
or UVLO pin(s) to GND. Input undervoltage protection
can be programmed between 5.5V and 24V, while the
overvoltage protection can be independently programmed
between 6V and 40V.
The device offers a status announcement signal (FLAG)
to indicate operational and fault signals. FLAG is an open
drain pin, and requires an external pullup resistor to the
appropriate system interface voltage. The device also
offers internal thermal shutdown protection against exces-
sive power dissipation.
Undervoltage Lockout (UVLO)
The device has a 12.4V (typ) preset UVLO threshold
on the IN pin when the voltage at the UVLO pin is less
than the external UVLO select threshold (V
).
UVLO_SEL
Connect the UVLO pin to GND to select the preset UVLO
threshold. If the voltage at the UVLO pin rises above
Input reverse polarity protection is realized using an exter-
nal NFET that is controlled by MAX17526A. The magni-
tude of reverse polarity voltage protection is dependent
on the operating load bus voltage (V
blocking capability of the external NFET. Example: for
protection down to -55V input range with V = 30V, an
external NFET rated at 85V is needed. The external NFET
is also needed for the optional reverse-current protection.
If reverse polarity protection and reverse-current protec-
tion are not needed, SN must be connected to IN and GN
must be left floating.
V
, the device enters adjustable UVLO mode.
UVLO_SEL
The device has a UVLO adjustment range from 5.5V to
24V. Connect an external resistive potential divider to the
UVLO pin as shown in the Typical Operating Circuit to
adjust the UVLO threshold voltage. Use the following
equation to adjust the UVLO threshold. The recomended
value of R1 is 2.2MΩ.
) and the voltage
OUT
OUT
R1
R2
V
= V
× 1 +
[
UVLO
SET
]
The current-limit of the device is programmed by connect-
ing a resistor from the SETI pin to GND. The current limit
can be programmed from 0.6A to 6.0A. When the current
through the device reaches or exceeds the set current limit,
the resistance of the internal NFET is modulated to limit
the current. The device offers three current limit behavioral
modes: Continuous, Auto-retry, and Latch-off modes.
where V
= 1.22V.
SET
Alternatively, R2 can be calculated using the following
equation:
R1
R2 =
V
UVLO
− 1
V
The SETI pin presents a current proportional to the device
current, under normal operation. Together with the current
limit program resistor (between SETI and GND), the SETI
pin presents a voltage that is proportional to the device
current. This voltage may be read by a monitoring system
for recording instantaneous current of the device. For best
damped measurement, the capacitance on the SETI pin
shall be limited to 30pF.
SET
When the voltage on the UVLO pin is below V
, the
SET
internal NFET remains turned Off and FLAG is asserted.
When the UVLO condition is removed, the device takes
input debounce time (t ) to start the switch turn-on pro-
DEB
cess if V
is below the V
threshold. The
OUT
UVLO_OUT
internal NFET is turned on after fault recovery internal
NFET turn-on time (t ), and the external NFET is
Power limit function is realized either at the input supply
side or output load side, by sampling the input or output
voltage, through a potential divider connecting to the PLIM
pin. The power limit feature reduces the programmed cur-
rent limit when the external voltage increases above the
programmed threshold.
ON_NFET
turned on after fault recovery external NFET turn-on time
(t ) and FLAG is deasserted.
ON_EXTNFET
Maxim Integrated
│ 14
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Alternatively, R4 can be calculated using the following
equation:
Overvoltage Lockout (OVLO)
The device has a 36.2V (typ) preset OVLO threshold
on the SN pin when the voltage at the OVLO pin is less
R3
R4 =
than the external OVLO select threshold (V
).
V
OVLO_SEL
OVLO
− 1
Connect the OVLO pin to GND to select the preset OVLO
threshold. If the voltage at the OVLO pin rises above
V
SET
V , the device enters adjustable OVLO mode.
OVLO_SEL
The OVLO reference voltage (V
the voltage at the OVLO pin exceeds V
is turned off and FLAG is asserted. When the OVLO
condition is removed, the device takes input debounce
) to start the switch turn-on process if V
threshold. The internal NFET is
turned on after fault recovery internal NFET turn-on time
) is set at 1.22V. If
SET
The device has an OVLO adjustment range from 6V to
40V. Connect an external resistive potential divider to the
OVLO pin as shown in the Typical Operating Circuit to
adjust the OVLO threshold voltage. Use the following
equation to adjust the OVLO threshold. The recomended
value of R3 is 2.2MΩ.
, the switch
SET
time (t
below the V
is
DEB
OUT
UVLO_OUT
(t ), and the external NFET is turned on after fault
ON_NFET
R3
R4
V
= V
× 1 +
[
OVLO
SET
]
recovery external NFET turn-on time (t
) and
ON_EXTNFET
the FLAG is deasserted. Figure 3 depicts typical behavior
in overvoltage conditions.
where V
= 1.22V.
SET
t
ON_EXTNFET
t
ON_NFET
t
DEB
1.22V
OVLO
V
OUT
V
UVLO_OUT
V
TO V
SN
GN
0V
I
LIMIT
I
OUT
I
LOAD
0A
SWITCH
STATUS
TIME
Figure 3. Overvoltage-Fault Timing Diagram
Maxim Integrated
│ 15
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
voltage-capable input, accepting signals up to 60V or V ,
IN
Input Debounce Protection
whichever is lower. EN is a low-voltage input, accepting
a maximum voltage of 5.5V. The device can be used to
turn on or off power delivery to connected loads using the
EN or HVEN pins. Toggling HVEN or EN resets the fault
condition once a short circuit is detected and the device
shuts down. Table 1 shows the truth table of the enable
inputs to control the switch turn on or off status.
The device features input debounce protection. The
device starts operation (turn on the internal NFET) only
if the input voltage is higher than the UVLO threshold for
a period greater than the debounce time (t ). In case
DEB
the voltage at IN falls below the UVLO threshold before
has passed, the switch remains off. If the voltage at
t
DEB
OUT is already above the undervoltage trip level on out-
put (V ) when the device is turned on through
UVLO_OUT
UVLO/OVLO conditions, there is no t
time. This is due
DEB
Table 1. Enable Inputs
to the device already being out of the power-on reset POR
condition with OUT above V . When the device
UVLO_OUT
EN
0
SWITCH STATUS
HVEN
is turned on through EN or HVEN, the t
present. Figure 4 depicts typical debounce timing diagram.
time is always
DEB
0
0
1
1
ON
ON
1
Switch Control
The device is enabled or disabled through two inde-
pendent enable inputs, HVEN and EN. HVEN is a high-
0
OFF
ON
1
t
+ t
t
ON_NFET
DEB ON_NFET
< t
< t
DEB
DEB
OVLO
UVLO
V
IN
UVLO_OUT
V
OUT
ON
ON
OFF
SWITCH
STATUS
TIME
NOTE: TIME NOT IN SCALE
Figure 4. Debounce Timing Diagram
Maxim Integrated
│ 16
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
current as possible to the output regardless of the current-
limit type selected. If the output is not charged within the
Startup Control
The device features a startup sequence that continuously
limits the current to the set current limit during the startup
startup timeout period (t
), the switch turns off and IN,
STO
EN, or HVEN must be toggled to resume normal opera-
tion. The t timeout period is also applied when there is
initial time (t ), allowing large capacitors present on
STI
STO
the output of the switch to be rapidly charged. If the tem-
perature of device rises to the thermal foldback threshold
a restart after a turn-off event caused by UVLO or OVLO.
If the output is not charged to (V - V ) level during this
IN
FA
(T
), the device enters power-limiting mode. In this
J(FB)
time, the device turns off and IN, EN, or HVEN must be
toggled to resume normal operation.
mode, the device thermally regulates the current through
the switch to protect itself while still delivering as much
t
+ t
DEB ON_NFET
t
STI
t
*
STO
OVLO
UVLO
IN
I
LIMIT
I
OUT
V
IN
OUT
GND
THERMALLY CONTROLLED
CURRENT FOLDBACK
T
JMAX
T
J
TIME
NOTE: NOT DRAWN TO SCALE
*IF OUT DOES NOT REACH V – V WITHIN t , THE DEVICE IS LATCHED OFF, AND EN, HVEN, OR IN MUST BE TOGGLED TO RESUME NORMAL
IN
FA
STO
OPERATION.
Figure 5. Startup Timing Diagram
Maxim Integrated
│ 17
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
external current-limit resistor. The voltage on the SETI pin
provides information about the IN current with the follow-
ing relationship:
Setting the Current-Limit Threshold
Connect a resistor between SETI and GND to program
the current-limit threshold in the device. Use the following
equation to calculate current-limit setting resistor:
V
(V)
SETI
I
(mA) =
× C
IRATIO
(kΩ)
IN − OUT
R
SETI
37500
R
kΩ =
)
I
(
SETI
(mA)
LIM
If SETI is left unconnected, V
≥ 1.5V. The current
SETI
regulator does not allow any current to flow. The device
performs a check on the SETI pin for the first time it exits
a shutdown condition. If the resistor placed on SETI is
below 3.2kΩ, the switch remains off and the FLAG pin
asserts.
where I
is the desired current limit in mA.
LIM
Do not use a R
current-limit thresholds for different resistor values.
smaller than 6kΩ. Table 2 shows
SETI
The device read-out of the current flowing into the IN pin.
A current mirror, with a ratio of C
using a current-sense auto-zero operational amplifier. The
mirrored current flows out through the SETI pin, into the
, is implemented,
IRATIO
Current-Limit Type Select
The MAX17526A features three selectable current-lim-
iting modes. During power-up, the device defaults to
continuous mode and follows the procedure defined in the
Startup Control section. Once the part has been success-
Table 2. Current-Limit Threshold vs.
SETI-Resistor Values
fully powered on and t
has expired, the device senses
STO
the condition of CLMODE. The CLMODE pin is used to
program the overcurrent response of the device in one of
the following three modes:
R
(kΩ)
CURRENT LIMIT (A)
SETI
62.50
0.6
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
37.50
25.00
18.75
15.00
12.50
10.71
9.37
● Autoretry mode: CLMODE is connected to GND
● Continuous mode: CLMODE pin is left unconnected
● Latch-off mode: a 220kΩ resistor is connected
between CLMODE and GND
In addition to the selectable current-limit modes, the
device has a protection feature against a severe overload
condition. If the output current exceeds 24A (typ) current,
the device turns off the internal and external NFETs. The
off duration depends on the fault condition that occurrs
after the FETs turn off, with the shortest one being < 500μs
8.33
7.50
6.82
(t
max) that occurs if there is no fault and
ON_NFET
V
> V
. If the overload is still present when
6.25
OUT
OUT_UVLO
the device turns on in current-limit, it behaves according
to the current-limit type selected.
Maxim Integrated
│ 18
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
pin asserts if the overcurrent condition is present for
Continuous Current Limit
t
and deasserts when the overload condition is
BLANK
In continuous current-limit mode, when current through the
device reaches the current limit threshold, the device lim-
its the current to the programmed current limit. The FLAG
removed. Figure 6 depicts typical behavior in continuous
current-limit mode.
tDEB+ tON_NFET
t
ON_NFET
t
t
t
STI
STI
STO
OVLO
UVLO
IN
I
LIMIT
I
OUT
THERMAL CURRENT LIMIT
THERMAL CURRENT LIMIT
V
IN
V
FA
V
OUT
V
OUT_UVLO
T
JMAX
T
J
FLAG
TIME
NOTE: NOT DRAWN TO SCALE
Figure 6. Continuous-Fault Timing Diagram
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
is on during t
the current-limit. During t
through the switch. Thus, output current is much less
than the programmed current-limit. Calculate the average
output current using the following equation:
time, the supply current is held at
Autoretry Current Limit
In autoretry current-limit mode, when current through the
device reaches the current-limit threshold, the t
timer begins counting. The FLAG pin asserts if the over-
current condition is present for t . The timer resets
BLANK
time, there is no current
RETRY
BLANK
BLANK
if the overcurrent condition resolves before t
has
BLANK
t
+ t
× K
+ t
BLANK STI
elapsed. A retry time delay (t
) starts immediately
RETRY
I
= I
LIM
LOAD
t
+ t
after t
has elapsed. During t
time, the switch
BLANK RETRY STI
BLANK
RETRY
remains off. Once t
has elapsed, the switch is
RETRY
turned back on again. If the fault still exists, the cycle is
repeated and the FLAG pin remains asserted. If the over-
current condition is resolved, the switch stays on.
With a 24ms (typ) t
720ms (typ) t
, 24ms (typ) t , K = 1 and
BLANK
STI
, the duty cycle is 6.25%, resulting in
RETRY
93.75% power reduction when compared to the switch
being on the entire time. Figure 7 depicts typical behavior
in the autoretry current-limit mode.
The autoretry feature reduces system power in case of
overcurrent or short-circuit conditions. When the switch
t
t
RETRY
t
tDEB + tON_NFET
BLANK
BLANK
t
ON_NFET
t
t
t
t
STI
STI
BLANK
RETRY
I
LIMIT
I
OUT
V
IN
V
OUT
V
FA
V
UVLO_OUT
FLAG
TIME
NOT DRAWN TO SCALE
< V < V , HVEN = LOW, EN = HIGH
V
UVLO
IN
OVLO
Figure 7. Autoretry-Fault Timing Diagram
Maxim Integrated
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
If a reverse current condition is detected ((V - V
) <
Latch-Off Current Limit
In latch-off current-limit mode, when current through the
device reaches the current-limit threshold, the t
timer begins counting. The FLAG pin asserts if an over-
current condition is present for t . The timer resets
if the overcurrent condition disappears before t
elapsed. The switch turns off and stays off if the overcur-
rent condition continues beyond t . To reset the
IN
OUT
V
), the external NFET is turned off. When the
RIBRISING_
reverse current condition no longer exists ((V - V
) >
OUT
SN
BLANK
V
), the external NFET is turned back ON after
RIBRISING_
t
. If the reverse current condition is the only
ON_EXTNFET
BLANK
fault (no UVLO, no thermal fault, no forward overcurrent
fault), then the internal NFET is kept ON, otherwise the
internal NFET is also turned OFF. Figure 9 depicts typical
behavior in slow or fast reverse current condition.
has
BLANK
BLANK
switch, either toggle the control logic (EN or HVEN) or
cycle the input voltage. Figure 8 depicts typical behavior
in latch-off current-limit mode.
The device contains two reverse-current thresholds with
slow (< 17μs) and fast (< 108ns) response time for
reverse current protection. The threshold values for slow
reverse is 5.4mV (typ) whereas for fast reverse, it is
100mV (typ). This feature results in robust operation in a
noisy environment, while still delivering fast protection for
severe fault, such as input short-circuit or hot plug-in at
the OUT pins.
Reverse Current Protection
In the device, the reverse current-protection feature is
enabled when used with external NFET and it prevents
reverse current flow from OUT to IN pins.
t
t
t
t
t
DEB+ t
t
STI
ON_NFET
BLANK
BLANK
BLANK
ON_NFET
t
STI
I
LIMIT
I
OUT
OUT
V
V
IN
V
FA
VUVLO_OUT
FLAG
INPUT OR EN CYCLE
TIME
NOTE: NOT DRAWN TO SCALE
UVLO < VIN < VOVLO
V
Figure 8. Latchoff-Fault Timing Diagram
t
ON_EXTNFET
t
t
RIB_
RIB_
t
ON_EXTNFET
t
RIB_
t
ON_NFET
V
TO V
OUT
SN
V
RIB_
V
TO V
SN
GN
UVLO
INTERNAL
NFET
STATUS
TIME
Figure 9. Reverse-Current-Fault Timing Diagram
Maxim Integrated
│ 21
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Power Limit
The device features a unique Power Limit feature that
I
× V
LIM
PLIM_TH
K
Hence,
, where I , K and V
LIM PLIM_TH
P =
allows the set current limit to be modified automatically
are essentially constants with tolerances dictated by the
design. The device is designed for ±10% power limit accu-
based on an external voltage (V ). The device moni-
EXT
tors a fraction of this external voltage on the PLIM pin and
dynamically adjusts the current limit set by the SETI pin
resistor based on the below relationship:
racy for the range V
which covers a 3x variation of external voltage (V
< V
< 3 × V
,
PLIM_TH
PLIM
PLIM_TH
).
EXT
In an input Power Limit application V is equal to V
,
IN
EXT
when V
≤ V
PLIM_TH,
PLIM
and the PLIM resistor divider is set to determine the input
voltage at which the current limit starts decreasing. By
setting this voltage and setting the maximum current limit,
the maximum “Input Power Limit” for the application is set.
The current limit can also be dynamically modified based
Current is limited to I
value set by R
LIM
SETI
when V
> V
PLIM
PLIM_TH,
I
× V
LIM
PLIM_TH
Current is limited to
V
PLIM
on the output voltage by using V
equal to V
. This
OUT
EXT
feature implements an “Output Power Limit” function that
potentially allows larger output currents to be delivered to
charge the output reservoir capacitors at low output volt-
age conditions experienced after input power returns after
an “Outage,” provided there are no thermal limitations due
to excessive power dissipation. The Power Limit feature
is disabled by connecting the PLIM pin to GND. A simpli-
fied Block diagram of the PLIM feature is shown below in
Figure 10.
Assuming the resistor-divider ratio of K for the resistors
R5, R6 configured as shown in the Typical Operating
Circuit, the above algorithm limits the power (P) delivered
by the external voltage source as shown below:
V
PLIM
= V
×K
EXT
V
EXT
×I
× V
LIM
PLIM_TH
P =
V
PLIM
CHP
I
IN
IN
CURRENT
MIRROR
R1
1/C
IRATIO
I
/C
IN IRATIO
PLIM
V
= R2 / (R1 + R2) × V
=
V
PLIM
PLIM
IN
F(1/X)
(V
× I
/ POWER) × V
PLIM_TH LIM(MAX) IN
EN
LINEAR CURRENT
LIMIT
R2
V
SEL
SETI
R
FOR V
FOR V
= V
> V
, I = I
PLIM_TH LIM LIM(MAX)
= V /I
RI LIM(MAX)
PLIM
PLIM
SETI
, I = V /POWER
PLIM_TH LIM
IN
Figure 10. Power Limit Circuit
Maxim Integrated
│ 22
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Fault Output
Thermal Shutdown Protection
The device has an open-drain fault-indicator out-
put, FLAG. It requires an external pullup resistor to a
DC supply. FLAG is held low when any of the following
conditions occur:
The device has a thermal shutdown feature to pro-
tect against overheating. The device turns off and
the FLAG pin asserts when the junction temperature
exceeds +165°C (typ). The device exits thermal shutdown
and resumes normal operation after the junction tempera-
ture cools by 10°C (typ), except in latch-off mode when
the device remains latched off.
● V - V
> V .
FA
IN
OUT
● Overcurrent duration exceeds blanking time.
● Die temperature exceeds +165°C.
The thermal limit behaves similarly to current limit. In
autoretry mode, the thermal limit works with the autoretry
timer. When the junction temperature falls below the fall-
ing thermal shutdown threshold, the device turns on after
● R
is less than 3.2kΩ (max).
SETI
● Input voltage falls below the UVLO threshold.
● Input voltage rises above the OVLO threshold.
the t
. In latch-off mode, the device latches off until
RETRY
The below table describes the status of the FETs along
with various fault condition. The FLAG pin is also 60V tol-
erant and when the open drain is on, it has a current pro-
tection that turns off the open drain if the current exceeds
4mA. The open drain is then turned back on if the fault
condition is cycled.
the power cycled or one of the enable pins is toggled.
In continuous mode, the device is only disabled while
the temperature is over the limit and turns back on after
t
when the temperature reaches the falling thermal
DEB
shutdown threshold. There is no blanking time for thermal
protection. Figure 6, Figure 7, and Figure 8 depict typical
behavior under different current limit modes.
Table 3. FETs Status During Faults
CONDITION
No Fault
INTERNAL NFET STATUS
EXTERNAL NFET STATUS
FLAG STATUS
ON
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
X**
HIGH
LOW
LOW
HIGH
LOW
LOW
LOW
LOW
UVLO
OVLO
Reverse with No Other Fault
Overcurrent
OFF
OFF
OFF
X**
Thermal Shutdown
SETI Grounded*
V
- V
> V
IN
OUT FA
*this condition is checked only at the first power on.
**the status of the FETs in this condition depends on the timing and the current limit mode selected.
Maxim Integrated
│ 23
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
current resulting in a large charging period; hence, the
possibility of a false overcurrent condition.
Applications Information
IN Capacitor
A1μF capacitor from the IN pin to EP/GND is recommended
to hold input voltage during sudden load-current changes.
In practical applications, the C
value is limited by the
MAX
thermal performance of the PCB. Poor thermal design
can cause the thermal foldback current-limiting function of
the device to kick in too early, which can further limit the
maximum capacitance that can be charged. Therefore,
good thermal PCB design is imperative to charge large
capacitor banks.
Hot Plug-In at IN Terminal
In many powering applications, an input-filtering capacitor
is required to lower the radiated emission and enhance
the ESD capability. In hot plug-in applications, parasitic
cable inductance along with the input capacitor causes
overshoot and ringing when a live power cable is con-
nected to the input terminal.
Hot Plug-In at OUT Terminal
In some applications, there might be a possibility of
applying an external voltage at the OUT terminal of the
devices with or without the presence of an input voltage.
During these conditions, devices detect any reverse cur-
rent entering at the OUT pin and flowing out of the IN pin
and turn off the external NFET. Parasitic cable inductance
along with input and output capacitors cause overshoot
and ringing when an external voltage is applied at the
OUT terminal. This causes the protection devices to see
up to twice the applied voltage, which can damage the
devices. It is recommended to maintain overvoltages such
that the voltages at the pins do not exceed the absolute
maximum ratings.
This effect causes the protection device to see almost
twice the applied voltage. A transient voltage suppressor
(TVS) is often used in industrial applications to protect
the system from these conditions. A TVS that is capable
of limiting surge voltage to 60V (max) should be placed
close to the input terminal for enhanced protection.
Input Hard Short to Ground
In many system applications, an input short-circuit pro-
tection is required. The device detects reverse current
entering at the OUT pin and flowing out of the IN pin and
turns off the external NFET. The magnitude of the reverse
current depends on the inductance of input circuitry and
any capacitance installed near the IN pins.
OUT Freewheeling Diode for Inductive Hard
Short to Ground
In applications that require protection from a sudden short
to ground with an inductive load or a long cable, a schott-
ky diode between the OUT terminal and ground is recom-
mended. This is to prevent a negative spike on the OUT
due to the inductive kickback during a short-circuit event.
OUT Capacitor
The maximum capacitive load (C
nected is a function of current-limit setting (I
startup initial time (t
ms) and the input voltage. The C
the following relationship:
) that can be con-
MAX
in A), the
LIM
in ms) and startup timeout (t
in
STI
STO
is calculated using
MAX
Layout and Thermal Dissipation
To optimize the switch response to output short-circuit
conditions, it is important to reduce the effect of undesir-
able parasitic inductance by keeping all traces as short as
possible. Place input and output capacitors as close as
possible to the device (no more than 5mm). IN and OUT
must be connected with wide short traces to the power
bus. During steady-state operation, the power dissipa-
tion is typically low and the package temperature change
is usually minimal. PCB layout designs need to meet
two challenges: high-current input and output paths and
important heat dissipation.
t
ms + t
ms
(
)
(
)
STI
STO
C
mF = I
(A)
×
(
)
MAX
LIM
V
V
IN
For example, for V = 24V, t
(typ) = 24ms, and I
(typ) = 1200ms, t
is 153mF.
IN
LIM
STO
MAX
STI
= 3A, C
Output capacitor values in excess of C
can trigger
MAX
false overcurrent conditions. Note that above expression
assumes no load current is drawn from the OUT pins. Any
load current drawn would offset the capacitor charging
Maxim Integrated
│ 24
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Maxim recommends the use of 2oz copper on an FR4 iso-
lator in a four-layer configuration. The layer stack needs
to be Top (routing), GND (plane), Power (plane, con-
ESD Protection
No capacitor is required for ±2kV (HBM) (typ) ESD on IN.
All pins have ±2kV (HBM) ESD protection. In applications
nected to V
), and Bottom (routing), in this order, from
OUT
in which an external NFET is used, see the IN Capacitor
top to bottom. Install the IC on an exposed pad landing
of minimum 100 mils x 100 mils, with at least five through
vias to the GND plane. The vias should be 32mils in diam-
eter, with a 16mils plated hole. The hole plating needs to
be at least 0.5oz copper. Provide a minimum of 1in x 1in
area of copper plane on all four layers. It is important to
remember that the inner planes do not contribute much
to heat dissipation due to FR4 isolation, but are important
from an electrical point of view. If possible, keep the top
and bottom copper areas clear of solder mask, as this
greatly improves heat dissipation. Use a similarly large
copper area connected directly to the OUT pins. A dimen-
sion of 1in x 1in is also recommended. This might look
oversized for current path requirements, but is essential
for heat dissipation. Keep in mind that heat is generated
at the drain junction of the internal nMOS pass FET, which
is then eliminated through the five OUT pins and needs to
be dissipated on this same copper area.
section.
Figure 11 shows the Human Body Model and Figure 12
shows the current waveform it generates when discharged
into low impedance. This model consists of a 100pF
capacitor charged to the ESD voltage of interest, which is
then discharged into the device through a 1.5kΩ resistor.
R
1MΩ
R
D
1.5kΩ
C
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
SOURCE
Connect all five IN pins to a copper area that is at least
150mils wide. Using 2oz copper can reduce this require-
ment to 100mils. Remember to provide the same copper
trace width on the source connection, when using the
external NMOS pass FET (with the source connected to
the IN pins). Use extreme caution when placing the decou-
pling capacitors to the IN and OUT pins. The tendency to
go as close as possible to the IC pins might interfere with
the minimum requirement of the tracewidth above. It is
important to note that the return load current does not
flow through the IC; therefore, it is important to provide
an external ground trace of at least the same width as the
input/output one. Maxim recommends the use of a GND
plane. Connect the input and output grounds to this plane
using at least four plated vias each. The vias should be
84mils in diameter (or 60mils x 60mils, if square) with a
35mils plated hole.
Figure 11. Human Body ESD Test Model
I
P
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
R
AMPERES
36.8%
10%
0
0
TIME
t
DL
t
RL
CURRENT WAVEFORM
Figure 12. Human Body Current Waveform
Maxim Integrated
│ 25
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
20 TQFN-EP*
20 TQFN-EP*
20 TQFN-EP*
INITIAL CURRENT LIMIT
POWER LIMIT FEATURE
Enabled
MAX17526AATP+T
MAX17526BATP+T**
MAX17526CATP+T**
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
1.0x
1.5x
2.0x
Disabled
Disabled
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
**Future product—contact factory for availability.
Maxim Integrated
│ 26
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MAX17526A/
MAX17526B/
MAX17526C
5.5V to 60V, 6A Current-Limiter with OV, UV,
Reverse Protection, and Power Limit
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
6/18
Initial release
—
Updated Benefits and Features, Electrical Characteristics, Reverse Current Protec-
tion, and Power Limit sections
1, 4–5
21–22
1
11/18
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2018 Maxim Integrated Products, Inc.
│ 27
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