MAX17673 [MAXIM]
Integrated 4.5V to 60V Synchronous 1.5A HV Buck and Dual 2.7V to 5.5V, 1A Buck Regulators;型号: | MAX17673 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Integrated 4.5V to 60V Synchronous 1.5A HV Buck and Dual 2.7V to 5.5V, 1A Buck Regulators |
文件: | 总27页 (文件大小:1306K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MAX17673/MAX17673A Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
General Description
Benefits and Features
MAX17673/MAX17673A power management integrated
circuits (PMIC) integrate a 60V high voltage (HV), high
efficiency synchronous DC-DC buck regulator and two
5.5V high efficiency synchronous DC-DC buck regulators.
All three regulators offer integrated power MOSFETs.
● Reduces External Components and Total Cost
• Synchronous Operation for High Efficiency
• Internal Compensation for a Wide Output Voltage
Range
• All-Ceramic Capacitors,Compact Layout
● Integrates Three DC-DC Regulators
• Wide 4.5V to 60V Input Voltage Range for the HV
Regulator. 2.7V to 5.5V Input Range for LV
Regulators.
The HV regulator operates from a 4.5V to 60V input volt-
age range and the LV regulators operate from a 2.7V to
5.5V input voltage range. The HV regulator supports load
currents up to 1.5A, and can regulate output voltages from
0.9V to 5.5V. The LV regulators support load currents up to
1A, and can regulate output voltages from 0.75V to 4.8V.
• Adjustable 0.9V to 5.5V Output for the HV Regula-
tor and 0.75V up to 4.8V Output for LV Regulators
• Delivers up to 1.5A Load Current for the HV Regu-
lator and 1A Load Current for LV Regulators
• Adjustable Switching Frequency: 250KHz to
800KHz for HV Regulator and 1MHz to 4MHz for
LV Regulators
• Programmable LV / HV Switching Frequency Ratio
(2, 3, 4, 5, 6, 7, 8)
• EN/UVLO for HV buck and EN for LV regulators
MAX17673/MAX17673A offer independent peak cur-
rent mode control, hiccup mode overcurrent protection,
ENABLE input and Power OK signal in the three regu-
lators. The switching frequency is adjustable between
1MHz and 4MHz in the LV regulators, and the HV regula-
tor can be programmed to run at a fractional switching
frequency of the LV regulators. The HV regulator offers
an adjustable soft-start function, while the LV regulators
present internally fixed soft-start. Users can choose to
operate the devices in either pulse frequency modulation
(PFM) or forced pulse width modulation (PWM) scheme.
The MAX17673A offers external clock synchronization.
● Reduces Power Dissipation
• 550μA in PFM and 10.2mA in PWM Mode
Quiescent Current
• Peak Efficiency > 92%
• Auxiliary Bootstrap LDO for Improved Efficiency
• PFM Mode for High Light-Load Efficiency
• 7.4μA Shutdown Current
The devices are available in a 28-pin, 5mm x 5mm TQFN
package and operates over a -40°C to +125°C tempera-
ture range.
● Operates Reliably in Adverse Industrial Environments
• Peak-Current Limit Protection
Applications
• Hiccup Mode Overload Protection
• Soft-Start Reduces Inrush Current During Startup
(Adjustable for HV Regulator)
• Built-In Output-Voltage Monitoring with POKH,
POKA, and POKB
● Industrial Control Power Supplies
● FPGA/CPLD Power Supplies
● Distributed Supply Regulation
● Base Station Power Supplies
● High Voltage Single Board Systems
• Monotonic Startup into Prebiased Load
• Overtemperature Protection
• Dynamic Mode Change for On-the-Fly Shift
Between PFM and PWM Mode
• -40°C to +125°C Operating Temperature Range
• Complies with CISPR22(EN55022) Class B
Conducted and Radiated Emissions
Ordering Information appears at end of data sheet.
19-100403; Rev 2; 11/19
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Absolute Maximum Ratings
INH to PGND.........................................................-0.3V to +65V
ENH to GND..........................................................-0.3V to +65V
BSTH to PGND .....................................................-0.3V to +70V
SSH, RT, FDIV to GND ............................ -0.3V to (V
+ 0.3V)
CC
LXH Total RMS Current......................................................±1.6A
LXA, LXB Total RMS Current.............................................±1.1A
PGNDA, PGNDB, PGNDH to GND........................-0.3V to 0.3V
Output Short-Circuit Duration....................................Continuous
Continuous Power Dissipation
LXH to PGND.......................................... -0.3V to (V
BSTH to LXH...........................................................-0.3V to +6V
+ 0.3V)
INH
BSTH to V .........................................................-0.3V to +65V
CC
INA, INB to PGND...................................................-0.3V to +6V
ENA, ENB to GND .................................................-0.3V to +6V
(Multilayer Board) (T = +70°C, derate
A
34.5mW/°C above +70°C.).....................................2758.6mW
Operating Temperature Range (Note 1)........... -40°C to +125°C
Storage Temperature Range............................ -65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
LXA to PGND .......................................... -0.3V to (V
LXB to PGND.......................................... -0.3V to (V
+ 0.3V)
+ 0.3V)
INA
INB
EXTVCC, V
to GND............................................-0.3V to +6V
CC
FBH, FBA, FBB, POKH, POKA, POKB,
MODE/SYNC to GND..........................................-0.3V to +6V
Note 1: Junction temperature greater than +125°C degrades operating lifetimes.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 28 TQFN
Package Code
T2855+6C
21-0140
90-0026
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD:
Junction to Ambient (θ
)
+29° C/W
+2° C /W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 2
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Electrical Characteristics
(V
= V
= 24V, V
= V
= V
= V
= V
= 5V, V
= 1V, C
= 2.2µF, R
= 0Ω, RT = LX_ = SSH = POK_
INH
ENH
EXTVCC
INA
INB
ENA
ENB
FB_
VCC
FDIV
= OPEN, V
to V
= 5V, V
= V
= V
= V
= 0V, T = T = -40°C to +125°C, unless otherwise noted.
BST
LXH
MODE/SYNC
PGND_
GND
SGND A J
Typical values are at T = +25°C. All voltages are referenced to GND, unless otherwise noted.) (Note 2)
A
PARAMETER
INPUT SUPPLY (V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
)
IN
Input Voltage Range for
HV Regulator
V
4.5
2.7
60
5.5
15
V
V
INH
Input Voltage Range for
LV Regulator A-B
V
, V
INA INB
V
= V
= V = 0V
ENB
ENH
ENA
INH Shutdown Current
I
7.3
µA
µA
IN_SH
(shutdown mode), V
= 0V)
EXTVCC
INA, INB Shutdown
Current
I
V
= V
= V = 0V (shutdown mode)
ENB
0.25
1.5
INL_SH
ENH
ENA
Normal switching, PWM mode,
= 400kHz, V = 0.9V, MODE = 0V,
INH Quiescent Current
I
_
f
10.2
8.8
mA
mA
INH QPWM
SW_HV
FBH
V
= 0V
EXTVCC
Normal switching, PWM mode,
INA, INB Quiescent
Current
I
f
= 2MHz, V
= V = 0.75V,
INL_QPWM
SW_LV
FBA
FBB
MODE = 0V, V
= 0V
EXTVCC
ENABLE/UVLO (EN)
V
ENH rising
ENH falling
1.175
1.055
1.200
1.080
1.225
1.105
Enable Threshold for
HV Regulator
ENH_R
V
V
ENH_F
Enable Input Leakage
Current for HV
Regulator
I
V
= 1.25V, T =25°C
-100
1.2
+100
0.4
nA
ENH_LKG
ENH
A
V
ENA, ENB rising
ENA, ENB falling
Enable threshold for LV
Regulator A-B
ENL_R
V
V
ENL_F
Enable Hysteresis for
LV Regulator A-B
V
150
mV
ENL_HYS
Enable Input Leakage
Current for LV Regula-
tor A-B
I
T
= T = +25°C, V , V
ENA ENB
= 5.5V
= 0V,
-250
250
nA
ENL_LKG
A
J
V
LDO
CC
V
Output Voltage
0mA ≤ I
6V < V
≤ 15mA, V
CC
VCC EXTVCC
V
4.75
20
5.00
54
5.25
V
CC
Range
< 60V
INH
V
V
Current Limit
Dropout
I
V
V
= 3.5V, V
= 4.5V
100
0.5
mA
V
CC
VCC_MAX
VCC
INH
V
= 4.5V , I
= 15mA
CC
CC_DO
INH
VCC
V
Undervoltage lockout rising
Undervoltage lockout falling
2.50
2.43
2.62
2.49
2.70
2.55
CC_UVR
V
UVLO
V
CC
V
CC_UVF
Maxim Integrated
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Electrical Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= V
= 5V, V
= 1V, C
= 2.2µF, R
= 0Ω, RT = LX_ = SSH = POK_
INH
ENH
EXTVCC
INA
INB
ENA
ENB
FB_
VCC
FDIV
= OPEN, V
to V
= 5V, V
= V
= V
= V
= 0V, T = T = -40°C to +125°C, unless otherwise noted.
BST
LXH
MODE/SYNC
PGND_
GND
SGND A J
Typical values are at T = +25°C. All voltages are referenced to GND, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL POWER SUPPLY
V
EXTVCC rising, V
> 4.5V
> 4.5V
2.83
2.80
2.89
2.86
3.00
2.95
EXTVCC Switchover
Voltage
EXTVCC_R
INH
V
V
EXTVCC falling, V
INH
EXTVCC_F
I
EXTVCC_
MAX
EXTVCC Current Limit
EXTVCC Dropout
V
= 3.3V, V
= 3V,
20
40
100
125
mA
mV
EXTVCC
VCC
V
V
= 3.3V, I
= 15mA
EXTVCC_DO
EXTVCC
VCC
HIGH-SIDE MOSFET & LOW SIDE MOSFET DRIVER
High-Side MOSFET
On-Resistance for HV
Regulator
R
I
I
= 0.1A, V
= 0.1A, V
= 5V (Note 3)
= 5V (Note 3)
290
170
600
mΩ
HSH
LXH
LXH
EXTVCC
Low-Side MOSFET
On-Resistance for HV
Regulator
R
350
+1
mΩ
µA
LSH
EXTVCC
LX Leakage Current for
HV Regulator
V
T
= (V
- 1V) to (V
+1 V);
LXH
INH
PGNDH
I
-1
LXH_LKG
= 25°C
A
High-Side MOSFET
On-Resistance for LV
Regulator A-B
V
V
, V
= 5V, I
= 3.6V (Note 3)
, I
= 190mA,
= 190mA,
INA INB
LXA LXB
R
120
60
300
mΩ
HSL
EXTVCC
Low-Side MOSFET
On-Resistance for LV
Regulator A-B
V
V
, V
= 5V, I
, I
INA INB
LXA LXB
R
100
mΩ
LSL
= 3.6V (Note 3)
EXTVCC
LX Leakage Current for
LV Regulator A-B
I
LXA, LXB = GND, or V , V
T = 25°C
-0.5
+0.5
µA
LXL_LKG
INA INB. A
SOFT-START
Soft-Start Current for
HV Regulator
I
V
= 0.5V
4.25
5.00
5.75
µA
SS_HV
SSH
Soft-Start Time for LV
Regulators
t
Time duration of output voltage ramp up
4096
cycles
SS_LV
FEEDBACK (FBH, FBA, FBB)
FBH Regulation Voltage
for HV Regulator
V
0.888
0.740
-150
0.900
0.750
0.912
0.760
+150
V
V
FBH
FBA, FBB Regulation
Voltage
V
FBL_REG
FBH Input Bias Current
for HV Regulator
0 ≤ V
INH valid
≤ 1V, T = 25°C. EXTVCC or
FBH A
I
nA
FB_HV
FBA, FBB Input Bias
Current for LV
Regulator A-B
0 < V
or INH valid
, V
< 1V, T = 25°C. EXTVCC
A
FBA FBB
I
-150
+150
nA
FB_LKG
Maxim Integrated
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Electrical Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= V
= 5V, V
= 1V, C
= 2.2µF, R
= 0Ω, RT = LX_ = SSH = POK_
INH
ENH
EXTVCC
INA
INB
ENA
ENB
FB_
VCC
FDIV
= OPEN, V
to V
= 5V, V
= V
= V
= V
= 0V, T = T = -40°C to +125°C, unless otherwise noted.
BST
LXH
MODE/SYNC
PGND_
GND
SGND A J
Typical values are at T = +25°C. All voltages are referenced to GND, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PFM/HIBERNATE MODE
FBH PFM Skip
Threshold
V
V
V
V
V
rising
falling
102
102.75
101
103.7
101.8
103.6
102.8
%
%
%
%
FBH_PFMR
FBH
FBH PFM Resume
Threshold
V
100.4
101.2
100.5
FBH_PFMF
FBL_PFMR
FBH
FBA, FBB PFM Skip
Threshold
V
, V
rising
102.5
101.7
FBA FBB
FBA, FBB PFM Resume
Threshold
V
, V
falling
FBL_PFMF
FBA FBB
CURRENT LIMIT
Peak Current Limit
Threshold for HV
Regulator
I
2.3
2.7
3.1
A
LXH_PKLMT
Negative Current Limit
Threshold for HV
Regulator
I
Current entering into LXH pin
1.1
A
A
A
LIM_NEG_HV
PFM Current Limit for
HV Regulator
I
0.82
1.70
LXH_PFM
Peak Current Limit
Threshold for LV
Regulator A-B
I
LX_PKLMT_
LV
1.40
2.05
Negative Current Limit
Threshold for LV
Regulator A-B
I
Current entering into the LXA, LXB pin
0.75
0.54
A
A
LIM_NEG_LV
PFM Current Limit for
LV Regulators A-B
I
LXL_PFM
RT/FDIV AND TIMINGS
R
R
R
R
R
R
= 0Ω
1.78
3.36
0.80
356
672
220
2.00
4.00
1.00
400
800
250
2.22
4.64
1.21
444
928
298
FDIV
Switching Frequency
for LV Regulator A-B
f
= 29.93kΩ, R
> 1.35kΩ (Note 3)
> 1.35kΩ
MHz
kHz
SW_LV
RT
FDIV
FDIV
= 229.4kΩ, R
RT
= 0Ω
FDIV
Switching Frequency
for HV Regulator
f
= 29.93kΩ, R
= 15kΩ
SW_HV
RT
RT
FDIV
= 90kΩ, R
> 89kΩ
FDIV
V
Undervoltage Trip
FB_
V
In percentage of V
60
64
70
%
OUT_HICF
FB_
Level to Cause HICCUP
HICCUP Timeout
32768
Cycles
Maxim Integrated
│ 5
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Electrical Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= V
= 5V, V
= 1V, C
= 2.2µF, R
= 0Ω, RT = LX_ = SSH = POK_
INH
ENH
EXTVCC
INA
INB
ENA
ENB
FB_
VCC
FDIV
= OPEN, V
to V
= 5V, V
= V
= V
= V
= 0V, T = T = -40°C to +125°C, unless otherwise noted.
BST
LXH
MODE/SYNC
PGND_
GND
SGND A J
Typical values are at T = +25°C. All voltages are referenced to GND, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum On-Time for
HV Regulator
t
V
= 5V, V
= 24V
73
105
ns
ON_MIN_HV
EXTVCC
INH
MAX Duty Cycle for HV
Regulator
D
93.2
38
%
ns
ns
MAX_HV
Minimum On-Time for
LV Regulator A-B
t
V
V
= 5V, V
= 5V, V
= V
= V
= 5V
55
ON_MIN_LV
EXTVCC
INA
INB
Minimum OFF time for
LV regulator A-B
t
= 3.6V
15
OFF_MIN_LV
EXTVCC
INA
INB
MODE Threshold
(MAX17673)
MODE/SYNC Threshold
(MAX17673A)
V
1.4
IH
V
V
0.4
IL
Sync Frequency
Capture Range
f
= 1MHz and f
= 4MHz
SW_LV
0.9 x
1.1 x
f
SW_LV
SW_LV
f
MHz
ns
SYNC
MAX17673A Only
f
SW_LV
Sync Pulse High Time
Sync Pulse Low Time
t
SYNC_HIGH
25
25
t
ns
SYNC_LOW
POKH, POKA, POKB (POK_)
POK_ Output Level Low
I
= 10mA
250
mV
µA
POK
POK_ Output Leakage
Current
T
= T = 25°C
-0.25
89.0
92
+0.25
A
J
V
Threshold for
OUT
V
V
falling
rising
92.0
95.0
2048
95.5
98.5
%
%
OUT_OKF
FB_
FB_
POK_ Assertion
V
Threshold for
OUT
V
V
OUT_OKR
POK_ Deassertion
POK_ delay after FB
reaches rising threshold
Cycles
THERMAL SHUTDOWN
Thermal Shutdown
Threshold
T
Temp rising
165
20
°C
°C
SHDNR
Thermal Shutdown
Hysteresis
T
SHDNHY
Note 2: All limits are production tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage
A
range are guaranteed by design and characterization.
Note 3: Not production tested. Guaranteed by design.
Maxim Integrated
│ 6
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
HV BUCK EFFICIENCY vs. LOAD CURRENT
(VOUT = 3.3V, MODE = PWM, fSW = 400kHz)
HV BUCK EFFICIENCY vs. LOAD CURRENT
LV BUCK EFFICIENCY vs. LOAD CURRENT
(VOUT = 5.0V, MODE = PWM, fSW = 400kHz)
(VOUT = 1.0V, MODE = PWM, fSW = 2MHz)
toc03
toc02
toc01
100
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
90
80
VIN = 12V
VIN = 24V
70
VIN = 5V
VIN = 3.3V
VIN = 5.0V
VIN = 12V
VIN = 24V
60
VIN = 36V
VIN = 48V
50
VIN = 36V
40
VIN = 48V
30
20
10
0
0.0
0.5
1.0
1.5
0.0
0.5
1.0
1.5
0.0
0.3
0.5
0.8
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
LV BUCK EFFICIENCY vs. LOAD CURRENT
LV BUCK EFFICIENCY vs. LOAD CURRENT
LV BUCK EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.8V, MODE = PWM, fSW = 2MHz)
(VOUT = 2.5V, MODE = PWM, fSW = 2MHz)
(VOUT = 3.3V, MODE = PWM, fSW = 2MHz)
toc06
toc04
toc05
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3.3V
VIN = 5.0V
VIN = 3.3V
VIN = 5.0V
VIN = 5.0V
0.0
0.3
0.5
0.8
1.0
0.0
0.3
0.5
0.8
1.0
0.0
0.3
0.5
0.8
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
HV BUCK EFFICIENCY vs. LOAD CURRENT
HV BUCK EFFICIENCY vs. LOAD CURRENT
LV BUCK EFFICIENCY vs. LOAD CURRENT
(VOUT = 5V, MODE = PFM, fSW = 400kHz)
(VOUT = 3.3V, MODE = PWM, fSW = 400kHz)
(VOUT = 1.0V, MODE = PFM, fSW = 2MHz)
toc07
toc08
toc09
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 48V
VIN = 36V
VIN = 3.3V
VIN = 5.0V
VIN = 48V
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 24V
VIN = 12V
VIN = 5V
0.010
0.100
1.000
0.010
0.100
LOAD CURRENT (A)
1.000
0.010
0.100
1.000
LOAD CURRENT (A)
LOAD CURRENT (A)
Maxim Integrated
│ 7
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
LV BUCK EFFICIENCY vs. LOAD CURRENT
LV BUCK EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.8V, MODE = PFM, fSW = 2MHz)
LV BUCK EFFICIENCY vs. LOAD CURRENT
(VOUT = 3.3V, MODE = PFM, fSW = 2MHz)
(VOUT = 2.5V, MODE = PFM, fSW = 2MHz)
toc12
toc10
toc11
100
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
90
80
70
VIN = 5.0V
VIN = 5.0V
VIN = 3.3V
VIN = 3.3V
VIN = 5.0V
60
50
40
30
20
10
0
0.01
0.1
LOAD CURRENT (A)
1
0.01
0.1
LOAD CURRENT (A)
1
0.010
0.100
1.000
LOAD CURRENT (A)
HV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
HV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
HV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 5V, MODE = PWM)
(VOUT = 3.3V, MODE = PFM)
(VOUT = 3.3V, MODE = PWM)
toc13
toc14
toc15
3.34
5.02
3.42
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.33
3.32
3.31
3.30
3.29
3.28
5.01
5.00
4.99
4.98
4.97
4.96
VIN = 36V
VIN = 48V
VIN = 48V
VIN = 48V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 24V
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 12V
0.0
0.5
1.0
1.5
0.0
0.5
1.0
1.5
0.0
0.5
1.0
1.5
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
HV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
LV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 5V, MODE = PFM)
(VOUT = 1.8V, MODE = PWM)
toc16
toc17
1.82
5.14
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
1.81
1.80
1.79
1.78
5.09
5.04
4.99
4.94
VIN = 5.0V
VIN = 3.3V
0.0
0.5
1.0
1.5
0.0
0.3
0.5
0.8
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Maxim Integrated
│ 8
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
LV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
LV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 3.3V, MODE = PWM)
(VOUT = 1.8V, MODE = PFM)
toc18
toc19
3.38
1.88
3.37
3.36
3.35
3.34
3.33
3.32
1.87
1.86
1.85
1.84
1.83
1.82
1.81
1.80
1.79
1.78
VIN = 5.0V
3.31
VIN = 5.0V
3.30
3.29
3.28
VIN = 3.3V
0.0
0.3
0.5
0.8
1.0
0.0
0.3
0.5
LOAD CURRENT (A)
0.8
1.0
LOAD CURRENT (A)
LV BUCK OUTPUT VOLTAGE vs. LOAD CURRENT
HV BUCK OUTPUT VOLTAGE vs. INPUT VOLTAGE
(VOUT = 3.3V, MODE = PFM)
(VOUT = 3.3V, MODE = PWM)
toc20
toc21
3.42
3.320
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.315
3.310
3.305
3.300
3.295
IOUT = 1.5A
IOUT = 1A
IOUT = 0A
IOUT = 0.5A
VIN = 5.0V
0.0
0.3
0.5
LOAD CURRENT (A)
0.8
1.0
10
20
30
INPUT VOLTAGE (V)
40
50
HV BUCK LOAD TRANSIENT RESPONSE
(VIN = 24V, VOUT = 5V, MODE = PWM
HV BUCK OUTPUT VOLTAGE vs. INPUT VOLTAGE
(VOUT = 5.0V, MODE = PWM)
LOAD CURRENT STEPPED FROM 0mA TO 750mA)
toc23
toc22
5.010
5.005
5.000
4.995
4.990
4.985
4.980
4.975
VOUT (AC)
100mV/div
IOUT = 0A
IOUT = 1.5A
IOUT = 1A IOUT = 0.5A
IOUT
500mA/div
10
20
30
40
50
100µs/div
INPUT VOLTAGE (V)
Maxim Integrated
│ 9
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
LV BUCK LOAD TRANSIENT RESPONSE
(VIN = 5V, VOUT = 3.3V, MODE = PWM
HV BUCK LOAD TRANSIENT RESPONSE
(VIN = 24V, VOUT = 5V, MODE = PWM
LOAD CURRENT STEPPED FROM 0mA TO 500mA)
LOAD CURRENT STEPPED FROM 750mA TO 1.5A)
toc25
toc24
VOUT (AC)
VOUT (AC)
50mV/div
100mV/div
500mA/div
IOUT
IOUT
500mA/div
100µs/div
100µs/div
LV BUCK LOAD TRANSIENT RESPONSE
(VIN = 5V, VOUT = 1.8V, MODE = PWM
LV BUCK LOAD TRANSIENT RESPONSE
(VIN = 5V, VOUT = 3.3V, MODE = PWM
LOAD CURRENT STEPPED FROM 0mA TO 500mA)
LOAD CURRENT STEPPED FROM 500mA TO 1A)
toc26
toc27
50mV/div
VOUT (AC)
50mV/div
VOUT (AC)
500mA/div
500mA/div
IOUT
IOUT
100µs/div
100µs/div
LV BUCK LOAD TRANSIENT RESPONSE
(VIN = 5V, VOUT = 1.8V, MODE = PWM
HV BUCK LOAD TRANSIENT RESPONSE
(VIN = 24V, VOUT = 5V, MODE = PFM
LOAD CURRENT STEPPED FROM 500mA TO 1A)
LOAD CURRENT STEPPED FROM 10mA TO 750mA)
toc28
toc29
VOUT (AC)
100mV/div
50mV/div
VOUT (AC)
500mA/div
IOUT
500mA/div
IOUT
400µs/div
100µs/div
Maxim Integrated
│ 10
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
LV BUCK LOAD TRANSIENT RESPONSE
(VIN = 5V, VOUT = 3.3V, MODE = PFM
LV BUCK LOAD TRANSIENT RESPONSE
(VIN = 5V, VOUT = 1.8V, MODE = PFM
LOAD CURRENT STEPPED FROM 10mA TO 500mA)
LOAD CURRENT STEPPED FROM 10mA TO 500mA)
toc30
toc31
VOUT (AC)
VOUT (AC)
50mV/div
50mV/div
500mA/div
500mA/div
IOUT
IOUT
40µs/div
100µs/div
HV BUCK STEADY-STATE SWITCHING WAVEFORMS
LV BUCK STEADY-STATE SWITCHING WAVEFORMS
(VIN = 24V, VOUT = 5V, MODE = PWM, LOAD = 1.5A)
(VIN = 5V, VOUT = 3.3V, MODE = PWM, LOAD = 1A)
toc33
toc32
20mV/div
VOUT (AC)
20mV/div
VOUT (AC)
2V/div
1A/div
10V/div
1A/div
VLX
VLX
ILX
ILX
2µs/div
400ns/div
LV BUCK STEADY-STATE SWITCHING WAVEFORMS
(VIN = 5V, VOUT = 1.8V, MODE = PWM
LOAD = 1A)
toc34
20mV/div
VOUT (AC)
2V/div
VLX
1A/div
ILX
400ns/div
Maxim Integrated
│ 11
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
HV BUCK STEADY-STATE SWITCHING WAVEFORMS
LV BUCK STEADY-STATE SWITCHING WAVEFORMS
(VIN = 24V, VOUT = 5V, MODE = PFM, LOAD = 15mA)
(VIN = 5V, VOUT = 3.3V, MODE = PFM, LOAD = 10mA)
toc36
toc35
50mV/div
VOUT (AC)
VOUT (AC)
200mV/div
5V/div
1A/div
20V/div
1A/div
VLX
VLX
ILX
ILX
20µs/div
100µs/div
HV BUCK STARTUP THROUGH ENABLE
LV BUCK STEADY-STATE SWITCHING WAVEFORMS
(VIN = 24V, VOUT = 5V, MODE = PWM, LOAD = 1.5A)
(VIN = 5V, VOUT = 1.8V, MODE = PFM, LOAD = 10mA)
toc38
toc37
5V/div
ENH
50mV/div
VOUT (AC)
2V/div
1A/div
5V/div
5V/div
1A/div
VOUT
ILX
VLX
POKH
ILX
2ms/div
20µs/div
LV BUCK STARTUP THROUGH ENABLE
LV BUCK STARTUP THROUGH ENABLE
(VIN = 5V, VOUT = 3.3V, MODE = PWM, LOAD = 1.0A)
(VIN = 5V, VOUT = 1.8V, MODE = PWM, LOAD = 1.0A)
toc39
toc40
2V/div
2V/div
500mA/div
500mA/div
ENA
ILX
ENB
ILX
2V/div
5V/div
2V/div
5V/div
VOUT
VOUT
POKA
POKB
2ms/div
2ms/div
Maxim Integrated
│ 12
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
LV BUCK STARTUP FROM INPUT
HV BUCK STARTUP FROM INPUT
(VIN = 5V, VOUT = 3.3V, MODE = PWM, LOAD = 1.0A)
(VIN = 24V, VOUT = 5V, MODE = PWM, LOAD = 1.5A)
toc42
toc41
20V/div
5V/div
20V/div
VIN
VLX
VIN
5V/div
2V/div
2V/div
2V/div
VLX
VOUT
VCC
5V/div
VOUT
POKA
2ms/div
2ms/div
HV STARTUP THROUGH ENABLE, 3.3V PREBIAS
LV BUCK STARTUP FROM INPUT
(VIN = 24V, VOUT = 5V, MODE = PWM, LOAD = 10mA)
(VIN = 5V, VOUT = 1.8V, MODE = PWM, LOAD = 1.0A)
toc43
toc44
5V/div
5V/div
20V/div
VIN
VLX
ENH
VLX
5V/div
2V/div
1V/div
5V/div
5V/div
VOUT
VOUT
POKB
POKH
2ms/div
4ms/div
LV STARTUP THROUGH ENABLE, 1.5V PREBIAS
LV STARTUP THROUGH ENABLE, 0.8V PREBIAS
(VIN = 5V, VOUT = 3.3V, MODE = PWM, LOAD = 10mA)
(VIN = 5V, VOUT = 1.8V, MODE = PWM, LOAD = 10mA)
toc45
toc46
2V/div
2V/div
ENA
VLX
ENB
VLX
5V/div
5V/div
2V/div
5V/div
1V/div
5V/div
VOUT
VOUT
POKA
POKB
2ms/div
2ms/div
Maxim Integrated
│ 13
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
LV BUCK STARTUP WITH OUTPUT SHORT-CIRCUIT
HV BUCK STARTUP WITH OUTPUT SHORT-CIRCUIT
(VIN = 5V, VOUT = 3.3V, MODE = PWM, LOAD = 1.0A)
(VIN = 24V, VOUT = 5V, MODE = PWM, LOAD = 1.5A)
toc48
toc47
10V/div
5V/div
VIN
VOUT
VIN
2V/div
VOUT
2V/div
VLX
5V/div
2A/div
VLX
ILX
20V/div
5A/div
ILX
4ms/div
20ms/div
LV BUCK STARTUP WITH OUTPUT SHORT-CIRCUIT
HV OUTPUT SHORT-CIRCUIT DURING STEADY-STATE
(VIN = 5V, VOUT = 1.8V, MODE = PWM, LOAD = 1.0A)
(VIN = 24V, VOUT = 5V, MODE = PWM, LOAD = 1.5A)
toc49
toc50
VOUT
5V/div
5V/div
VIN
VOUT
2V/div
10V/div
2A/div
VLX
VLX
5V/div
2A/div
ILX
ILX
4ms/div
40ms/div
OUTPUT SHORT-CIRCUIT DURING STEADY-STATE
LV OUTPUT SHORT-CIRCUIT DURING STEADY-STATE
(VIN = 5V, VOUT = 1.8V, MODE = PWM, LOAD = 1A)
(VIN = 5V, VOUT = 3.3V, MODE = PWM, LOAD = 1A)
toc52
toc51
5V/div
5V/div
VIN
VIN
VOUT
2V/div
5V/div
2A/div
VOUT
1V/div
5V/div
VLX
VLX
2A/div
ILX
ILX
10ms/div
10ms/div
Maxim Integrated
│ 14
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
EXTERNAL CLOCK SYNCHRONIZATION
(VIN = 5V, VOUT = 3.3V, LOAD = 1.0A)
EXTERNAL CLOCK SYNCHRONIZATION
(VIN = 24V, VOUT = 5V, LOAD = 1.5A)
toc53
toc54
5V/div
5V/div
VSYNC
VSYNC
20V/div
VOUT(AC)
20mV/div
5V/div
VLX
VOUT(AC)
50mV/div
1A/div
VLX
1A/div
ILX
ILX
10us/div
10us/div
EXTERNAL CLOCK SYNCHRONIZATION
(VIN = 5V, VOUT = 1.8V, LOAD = 1.0A)
HV BUCK BODE PLOT
(VIN = 24V, VOUT = 5.0V, MODE = PWM, LOAD = 1.5A)
toc55
toc56
40
30
20
10
0
110
90
5V/div
70
VSYNC
50
VOUT(AC)
20mV/div
5V/div
PHASE
30
10
GAIN
VLX
-10
-30
-50
1A/div
-10
-20
CROSSOVER FREQUENCY = 43.6kHz
PHASE MARGIN = 69.1o
ILX
1k
10k
100k
10us/div
FREQUENCY (Hz)
Maxim Integrated
│ 15
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Operating Characteristics (continued)
(V
= V
= 24V, V
= V
= V
= V
= FDIV = 0V, V
= V
= V
= V
= 5V, R = OPEN, C
=
INH
ENH
GND
PGNDH
PGNDA
PGNDB
INA
INB
ENA
ENB
RT
VCC
2.2μF, C
= 0.1μF, C = 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are
BSTH
SS
A
A
referenced to GND, unless otherwise noted.)
LV BUCK BODE PLOT
(VIN = 5V, VOUT = 1.8V, MODE = PWM, LOAD = 1A)
HV BUCK BODE PLOT
(VIN = 24V, VOUT = 3.3V, MODE = PWM, LOAD = 1.5A)
LV BUCK BODE PLOT
(VIN = 5V, VOUT = 3.3V, MODE = PWM, LOAD = 1A)
toc57
toc58
toc59
40
30
30
70
80
70
PHASE
20
10
30
20
10
50
60
50
20
30
PHASE
40
PHASE
30
0
10
10
0
20
0
10
-10
-20
-30
-40
GAIN
0
-10
-30
-50
-70
GAIN
GAIN
-10
-30
-50
-10
-20
-10
-20
-20
-40
CROSSOVER FREQUENCY = 153.0kHz
PHASE MARGIN = 57.0o
CROSSOVER FREQUENCY = 46.5kHz
PHASE MARGIN = 59.8o
CROSSOVER FREQUENCY = 125.5kHz
PHASE MARGIN = 51.5o
1k
10k
100k
10k
100k
1Meg
10k
100k
1Meg
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
RADIATED EMISSION PLOT
(C12, C19 = 220pF, C27, C28, C29 = 150pF,
toc61
L3 = SHORT, C15 = C20 = OPEN)
60
50
CISPR-22 CLASS B QP LIMIT
40
30
VERTICAL
SCAN
20
10
0
HORIZONTAL
SCAN
30
1000
100
FREQUENCY (MHz)
CONDITIONS: VIN = 24V, VOH = VINA = VINB = 5V,
IOH = 0.37A, IOA = IOB = 1A; FROM MAX17673AEVKIT#
Maxim Integrated
│ 16
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Pin Configuration
TOP VIEW
21 20 19 18 17 16 15
21 20 19 18 17 16 15
22
23
24
25
26
27
28
14
22
23
24
25
26
27
28
14
SGND
EXTVCC
FDIV
SGND
EXTVCC
FDIV
N.C.
13 FBH
12
N.C.
13 FBH
12
SSH
11 ENA
SSH
11 ENA
MAX17673
MAX17673A
ENB
ENB
10
9
10
9
INB
INA
INB
INA
PGNDA
LXA
PGNDA
LXA
PGNDB
LXB
PGNDB
LXB
EP
6
EP
6
+
+
8
8
1
2
3
4
5
7
1
2
3
4
5
7
TQFN
5mm x 5mm
TQFN
5mm x 5mm
Pin Description
PIN
NAME
FUNCTION
Feedback Inputs for LV Regulators. Connect FBA/FBB to the center of the external resistor-divider from
the output of LV regulators to GND to set the output voltage.
1, 7
FBB, FBA
Open-Drain Power Good to Monitor the Output of the HV Regulator. The POKH output is driven low if
FBH drops below 92% of its set value. POKH goes high 2048 clock cycles after FBH rises above 95%
of its set value. POKH is valid only if INH or EXTVCC is present.
2
POKH
Open-Drain Power Good to Monitor the Output of the LV Regulators. The POKA/POKB output is driven
low if FBA/FBB drops below 92% of its set value. POKA/POKB goes high 2048 clock cycles after FBA/
FBB rises above 95% of its set value. POKA/POKB is valid only if INH or EXTVCC is present.
POKB,
POKA
3, 5
Mode Selection Pin. The MODE/SYNC pin configures the devices to operate in PWM and PFM modes
of operation. Leave the MODE/SYNC pin unconnected or connected to V
for PFM operation. Con-
CC
MODE
/SYNC
4
nect MODE/SYNC to SGND for constant-frequency PWM operation at all loads. MAX17673A can be
synchronized to an external clock using this pin. See the MODE Selection and External Clock
Synchronization section for more details.
LV Regulator Switching Frequency Selection Input. Connect a resistor from RT to GND to program the
LV regulator switching frequency from 1MHz to 4MHz.
6
RT
Switching Node of LV Regulators. Connect LXA and LXB pins to the switching node of the inductors.
LXA and LXB are high impedance when the devices are in shutdown mode.
8, 28
LXA, LXB
PGNDA,
PGNDB
9, 27
Power Grounds for LV Regulators.
10, 26
INA, INB
Power Supply Input for LV Regulators. The input supply range is 2.7V to 5.5V.
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Pin Description (continued)
PIN
11, 25
12
NAME
ENA, ENB
SSH
FUNCTION
LV Regulator Enable Input. Drive ENA/ENB high to enable the LV regulators output voltage.
Soft-Start Input for HV regulator. Connect a capacitor from SSH to GND to set the soft-start time.
Feedback Input for HV Regulator. Connect FBH to the center of the resistive divider between the HV
regulator output voltage and GND.
13
14
FBH
N.C.
No Connection.
Enable Input. Drive ENH high to enable the HV regulator output voltage. Connect ENH to the center of
a resistive divider between INH and GND to set the input voltage (undervoltage threshold) at which the
devices turn on. Pull up to INH for always on operation.
15
ENH
16
17
INH
Power-Supply Input for the HV Regulator. The input supply range is from 4.5V to 60V.
Power Ground for the HV Regulator. Connect PGNDH externally to the power ground plane. Connect all
GND and PGND pins together at one single point.
PGNDH
Switching Node of the HV Regulator. Connect LXH to the switching side of the inductor. LXH is high
impedance when the devices are in shutdown mode.
18
LXH
19
20
BSTH
GND
Bootstrap Capacitor for the HV Regulator. Connect a 0.1μF ceramic capacitor between BSTH and LXH.
Analog Ground.
Internal LDO Output. Bypass V
The internal regulator is turned on if ENH, ENA, or ENB is high.
with 2.2μF ceramic capacitance to GND to enable proper operation.
CC
21
22
23
V
CC
SGND
Substrate Ground. Connect to GND.
External Power Supply Input for the Internal LDO. Applying a voltage between 2.7V and 5.5V at the
EXTVCC pin bypasses the internal LDO. If INH is present, EXTVCC is used only if it is above 3V (typ).
EXTVCC
HV Regulator Frequency Selection. Connect a resistor from FDIV to GND to select an LV/HV regulator
frequency ratio (2, 3, 4, 5, 6, 7, 8). Pin read only at startup (first rise of ENH, ENA, or ENB).
24
—
FDIV
EP
Exposed pad. Connect to the GND pin. Connect a large copper plane below the IC to improve heat dis-
sipation capability. Add thermal vias below the exposed pad. Refer to the MAX17673/MAX17673A EV
kit data sheet for a layout example.
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Functional Diagram
INH
EXTVCC
THERMAL
TSD
SHUTDOWN
V
CC
LDO SELECT
POK
BSTH
V
CC_INT
ENH
PEAK-LIMIT
CURRENT
SENSE LOGIC
CHIPEN
CURRENT-
SENSE
CS
1.2V
AMPLIFIER
TSD
HIGH-SIDE
DRIVER
DH
DL
LXH
PFM/PWM
CONTROL LOGIC
LOW-SIDE
DRIVER
SLOPE
HV
FBH
CS
PWM
ERROR
AMPLIFIER
PGNDH
EXTERNAL
SOFT-START
CONTROL
SSH
ZX/ILIMIN
COMP
SINK LIMIT
NEGATIVE
CURRENT
REF
CLK
HV
CLKHV
FDIV
FREQUENCY
DIVIDER
POKH
GND
SLOPE
HV
0.855V
FB
4096
CYCLES
CLKLV
MODE/SYNC*
TSD
TSD
ENB
1.2V
CHIPEN
ENA
INA
1.2V
UVLO
INB
UVLO
CURRENT-
SENSE
AMPLIFIER
PEAK-LIMIT
CURRENT
SENSE LOGIC
CS2
CURRENT-
SENSE
AMPLIFIER
PEAK-LIMIT
CURRENT
SENSE LOGIC
CS1
PFM/PWM
CONTROL LOGIC
PFM/PWM
CONTROL LOGIC
HIGH-SIDE
DRIVER
DH
LXA
HIGH-SIDE
DRIVER
DH
DL
LOW-SIDE
DRIVER
DL
LXB
LOW-SIDE
DRIVER
ZX/ILIMIN
COMP
PGNDA
PGNDB
NEGATIVE
CURRENT
REF
NEGATIVE
CURRENT
REF
ZX/ILIMIN
COMP
V
REF
CLK
LV
PWM
PWM
CS1
SOFT-
START
ERROR
AMPLIFIER
CLK
LV
CLK
LV
SLOPE
LV
SLOPE
LV
FBA
SLOPE
LV
FBB
CS2
ERROR
AMPLIFIER
SOFT-
START
CLK
LV
SLOPE
LV
OSCILLATOR
SLOPE
V
LV
REF
CLK
LV
POKA
POKB
0.7125V
FBA
RT
4096
CYCLES
0.7125V
FBB
SGND
4096
CYCLES
* SYNC FEATURE IS AVAILABLE ON MAX17673A
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
limit feature on the V
54mA load current.
pin, and can handle a typical
CC
Detailed Description
MAX17673/MAX17673A power management integrated
circuits (PMIC) integrate a 60V high voltage (HV), high effi-
ciency synchronous DC-DC buck regulator and two 5.5V
Low Voltage (LV) high efficiency synchronous DC-DC buck
regulators. All three regulators offer integrated MOSFETs.
The output of the HV regulator may be applied to the
EXTVCC pin, if it is above the switchover threshold.
Powering the quiescent current through the EXTVCC input
reduces the current drawn from the high voltage input INH,
and hence reduces the losses in the INH LDO. When not
used, the EXTVCC pin must be connected to GND.
The HV regulator and LV regulators are offered with inde-
pendent input pins (INH, INA, and INB), ENABLE input
pins (ENH, ENA, and ENB), switching nodes (LXH, LXA,
and LXB pins), power ground pins (PGNDH, PGNDA,
and PGNDB), and Power OK pins (POKH, POKA, and
POKB). The controllers inside the devices are powered
by linear regulators that generate the V
the INH input or from the EXTVCC input. A valid INH or
EXTVCC is required for operation of all the regulators.
Enabling the Regulators
The devices offer independent ENABLE pins for the three
internal regulators. The HV regulator enable input (ENH)
offers a programmable UVLO threshold. The LV ENABLE
inputs (ENA and ENB) offer a digital logic threshold to
enable or disable the regulators.
supply from
CC
Switching Frequency Selection
The switching frequency of the LV regulators is set by
the internal clock of the devices and can be set between
1MHz to 4MHz by connecting a resistor (R ) between
the RT pin and GND. The switching frequency (f ) is
SW
The devices feature a peak current-mode control architec-
ture. Output voltage regulation is achieved by sensing the
output voltage through independent feedback pins (FBH,
FBA, and FBB), comparing them against internal references,
and setting the peak-current references for the independent
peak current-mode control logic blocks. Stable operation is
guaranteed by three independent internal error amplifiers
with their compensation networks, and appropriate slope
compensation in the peak current-mode controllers.
RT
related to the R resistor by the following equation:
RT
R
= (266/f ) - 36.58
SW_LV
RT
Where f
is in MHz, and R is in kΩ. The LV regu-
RT
SW_LV
lators are internally clocked 180° apart to minimize the
ripple current drawn from the low voltage input source.
The RT pin offers adjustable switching frequency of the
LV regulators. The FDIV pin allows selection of HV regula-
tor switching frequency as a fraction of the LV regulators
switching frequency. The MODE and MODE/SYNC pins
allow selection of operating mode of the three regulators,
between pulse width modulation (PWM) and pulse fre-
quency modulation (PFM) modes. The MODE/SYNC pin
on the MAX17673A can be used to synchronize the inter-
nal oscillator to an external system clock. The HV regu-
lator offers a programmable soft-start function through
the SSH pin, while the LV regulators offer an internally
clocked soft-start function.
The switching frequency of the HV regulator is derived
by dividing the LV regulator switching frequency by a pro-
grammable factor. The HV regulator switching frequency
can be programmed by connecting a resistor (R
)
FDIV
between the FDIV pin and GND. This resistor is read only
at startup. The following table lists the value of R
different frequency division factors.
for
FDIV
Table 1. Switching Frequency Selection
for HV Regulator
Linear Regulator and External Supply
Input (EXTVCC)
FDIV RESISTOR
(kΩ)
HV DIVIDING FACTOR
(f
/ f
)
SW_LV SW_HV
The devices offer an internal low dropout (LDO) linear
regulator, to power the internal functions by generating
Internal RT
< 1.35
(f
= 2MHz, f
= 400kHz
SW_LV
SW_HV
the V
Supply. The V
can be generated either from
CC
CC
2.40
4.70
8.2
15
2
3
4
5
6
7
8
the INH supply, with an internal LDO or from the EXTVCC
pin. The LDO are enabled only when at least one of the
ENABLE inputs (ENH, ENA, or ENB) are asserted. The
internal LDO uses INH when INH is above EXTVCC and
EXTVCC is below the switchover threshold (3V). If INH
is below EXTVCC, the LDO is disabled and EXTVCC is
33
56
used to generate V . A 2.2µF capacitor must be con-
CC
> 89
nected from the V
pin to GND for proper operation of
CC
the linear regulators. The linear regulators offer a current
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
external clocks. The user must apply a valid clock frequency
Operating Input Voltage
The minimum and maximum operating input voltages for
a given output voltage should be calculated as follows:
for at least “t
” time:
min_sync
t
= 1024/f
+ 90us
min_sync
sw_LV
Where, f
= LV buck frequency in Hz.
SW_LV
V
+ I
R
+ R
DCR LS
(
)
O
OUT
MAX
(
)
V
=
+ I
R
− R
(
)
IN(MIN)
OUT(MAX) HS LS
PWM
D
MAX
V
Pulse width modulation (PWM) mode operation provides
constant switching frequency at all load conditions, and is
useful in frequency sensitive applications. In PWM mode,
the inductor current is allowed to go negative, and hence
remains continuous. PWM mode results in lower efficiency
at light loads, compared to PFM mode.
O
× t
V
=
IN(MAX)
f
SW(MAX)
ON(MIN)
where,
V
O
= Steady-state output voltage
I
= Maximum load current
OUT(MAX)
PFM
R
= DC resistance of the inductor
DCR
Pulse frequency modulation (PFM) mode operation disables
the negative inductor current and additionally skips pulses at
light loads for high efficiency. In PFM mode, the inductor current
is forced to a fixed peak of 820mA for HV buck and 540mA for
LV bucks, every clock cycle until the output rises to the PFM
skip threshold (i.e., 102.75% typ for HV buck and 102.5% typ
for LV bucks) of the nominal voltage. Once the output reaches
the PFM skip threshold of the nominal voltage, both the high-
side and low-side FETs are turned off and the devices enter
hibernate operation until the load current discharges the output
voltage to the PFM resume threshold (i.e., 101% typ for HV
buck and 101.7% typ for LV Buck) of the nominal voltage. Most
of the internal blocks are turned off in hibernate operation to
save quiescent current. After the outputs fall below the PFM
resume threshold of the nominal voltage, the devices come out
of hibernate operation, turns on all internal blocks, and again
commences the process of delivering pulses of energy to the
output until it reaches the PFM skip threshold of the nominal
output voltage. The advantage of the PFM mode is higher effi-
ciency at light loads because of lower quiescent current drawn
from supply. The disadvantage is that the output-voltage ripple
is higher compared to PWM modes of operation and switching
frequency is not constant at light loads.
f
t
= Maximum switching frequency
= Minimum switch on-time.
SW(MAX)
ON(MIN)
MODE Selection and External Clock
Synchronization
The devices offer programmable PWM and PFM modes of
operation. Connecting the MODE pin of MAX17673 or the
MODE/SYNC pin of MAX17673A to GND operates the part
in PWM operation. Connecting the MODE pin of MAX17673
or the MODE/SYNC pin of MAX17673A to V , or leaving
the pin open, enables the part to operate in PFM mode. The
chosen operating mode applies to all the three regulators.
CC
The MAX17673A offers external clock synchronization.
The internal oscillator of the device can be synchronized to
an external clock signal applied on the MODE/SYNC pin.
The external synchronization frequency must be between
0.9 x f
and 1.1 x f . Where f
SW_LV
is the
SW_LV
SW_LV
LV buck frequency programmed by the RT resistor. The
MAX17673A operates in PWM mode when synchronized
to an external clock.
The MAX17673A highlights a phase-locked-loop (PLL) clock
generator that allows seamless on-the-fly synchronization to
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
parator commands the first PWM pulse, at which point switch-
ing commences. The output voltage is then smoothly ramped
up to the target value in alignment with the internal reference.
Power Good Signal (POK)
The devices offer individual power good signals (POKH,
POKA, and POKB) for the three internal regulators. The
POK_ pins are open-drain output pins. The POK_ pins
must be pulled up to the desired logic level voltages
externally. The power good signals are driven high when
the output voltage of the regulators reach 95% (typ) of the
set values after soft-start is completed. The power good
signals are pulled low during the soft-start period, and
under fault conditions (thermal shutdown, or any of the
corresponding ENABLE inputs are held low).
Thermal Shutdown Protection
Thermal shutdown protection limits total power dissipation in
the devices. When the junction temperature of the devices
exceeds +165°C, an on-chip thermal sensor shuts down the
devices, allowing the devices to cool. The thermal sensor is
common to all three regulators. The thermal sensor turns
the devices on again after the junction temperature cools by
20°C. All three regulator soft-start cycle resets during ther-
mal shutdown. Carefully evaluate the total power dissipa-
tion (see the Power Dissipation section) to avoid unwanted
triggering of the thermal shutdown during normal operation.
Overcurrent and Hiccup Mode
The devices are provided with a robust overcurrent pro-
tection scheme that protects the devices during overload
and output short-circuit conditions. A cycle-by-cycle peak
current limit turns off the high-side MOSFET whenever the
high-side switch current exceeds an internal limit of 2.7A
(typ) for HV buck and 1.7A (typ) for LV bucks. In addition,
if due to a fault condition, feedback voltage (at FBH, FBA,
or FBB pins) drops to 64% of the typical feedback voltage
of the regulated value any time after soft-start is complete,
hiccup mode is triggered. In hiccup mode, the convert-
ers are protected by suspending switching for a hiccup
timeout period of 32,768 switching cycles. Once the hic-
cup timeout period expires, soft-start is attempted again.
Hiccup mode of operation ensures low power dissipation
under output short-circuit conditions. The overcurrent and
hiccup mode operation for the HV regulator and LV regu-
lators work independent of each other.
Applications Information
Input Capacitor Selection
The devices offer independent input terminals for the
three internal regulators. Input capacitors must be placed
near each of these input terminals (INH, INA, and INB)
to reduce the peak currents drawn from the input power
source, and to reduce the noise and voltage ripple on the
input terminals. The input capacitor RMS current require-
ment (I
) is calculated using following equation:
RMS
(V − V
IN
) × V
OUT
OUT
√
×
OUT(MAX)
I
=
I
RMS
V
IN
where, I
is the maximum load current. I
RMS
OUT(MAX)
has a maximum value when the input voltage equals
twice the output voltage (V = 2 x V ), so I
RMS(MAX)
Prebiased Output
IN
OUT
When the devices start into a prebiased output, both the
high-side and the low-side switches are turned off so that the
converter does not sink current from the output. High-side and
low-side switches do not start switching until the PWM com-
= I /2.
OUT(MAX)
Choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
long-term reliability. Use low-ESR ceramic capacitors with
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
high-ripple-current capability at the input. X7R capacitors
are recommended in industrial applications for their tem-
perature stability. Calculate the input capacitance using
the following equation:
0.33
1
t
=
(
+
)
RESPONSE
f
f
C
SW
where,
I
× D × (1 − D)
C
is in Farad
OUT(MAX)
=
η × f
OUT
C
IN
× ∆ V
IN
SW
I
t
= Load current step
STEP
= Response time of the controller
= Allowable output voltage deviation
RESPONSE
where,
D = V
∆V
/V is the duty ratio of the controller
= Switching frequency
OUT
OUT IN
f
= Target closed-loop crossover frequency in Hz
= Switching frequency in Hz
f
C
SW
f
∆V = Allowable input voltage ripple
SW
IN
Select f to be 1/10th of the switching frequency.
C
η = efficiency
DC and AC bias derating characteristics of ceramic
capacitors must be considered while selecting output
capacitors. Derating curves are available from all major
ceramic capacitor manufacturers.
In applications where the source is located distant from
the device input, an electrolytic capacitor should be added
in parallel to the ceramic capacitor to provide necessary
damping for potential oscillations caused by the inductance
of the longer input power path and input ceramic capacitor.
Soft-Start Capacitor Selection
Inductor Selection
The devices implement adjustable soft-start operation
for the HV regulator and fixed soft-start time for the LV
regulators to reduce inrush current. A capacitor connected
from the SSH pin to GND programs the soft-start time for
The inductors for the three regulators must be speci-
fied for operation with the MAX17673/MAX17673A. The
switching frequency and output voltage determine the
inductance value as follows
the HV regulator. The selected output capacitance (C
)
SEL
and the output voltage (V
required soft-start capacitor as follows:
) determine the minimum
1.5× V
OUT
OUT
L =
f
SW
−06
where f
is in Hertz. Select low DC resistance (DCR)
SW
C
≥
56 × 10
× C
× V
SS
SEL OUT
inductors close to the calculated values. The saturation
current rating (I ) of the inductor must be above the
peak current limit of the regulator.
SAT
The soft-start time (t ) is related to the capacitor con-
nected at SS (C ) by the following equation:
SS
SS
Output Capacitor Selection
C
SS
t
=
X7R ceramic output capacitors are preferred due to their
stability over temperature in industrial applications. The
output capacitors are typically sized to support a step load
of 50% of the maximum output current in the application,
so the output voltage deviation is contained to 3% of the
output voltage setpoint. The minimum required output
capacitance can be calculated as follows:
SS
−06
5.55 × 10
For example, to program a 2ms soft-start time, a 12nF
capacitor should be connected from the SSH pin to GND.
I
× t
STEP RESPONSE
C
=
OUT
2 × ∆ V
OUT
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Setting the Input Undervoltage Lockout
Level of the HV Regulator
The devices offer an adjustable input undervoltage lock-
out level for the HV regulator. Set the voltage at which the
device turns on with a resistive voltage-divider connected
V
INH
R1
R2
from V
to GND (Figure 1). Connect the center node of
INH
the divider to the ENH pin.
ENH
Choose R1 to be 3.3MΩ and then calculate R2 as follows:
R1 × 1.2
R2 =
(V
− 1.2)
INU
where, V
is the voltage at which the device must turns
INU
on. Ensure that V
is higher than 0.8 x V
.
INU
OUT
To reduce voltage ringing, a minimum damping resistance
of 1kΩ should be placed in series with the ENH pin, when
driven from an external signal source.
Figure 1. Setting the Input Undervoltage Lockout Level for the
HV Regulator
Adjusting Output Voltage
The devices offer independent control of output voltages,
by allowing individual sense and feedback inputs. Set the
output voltage of the three regulators by using a resistive
divider from the output voltages to the respective feed-
back (FB_) pins (Figure 2). Use the following expressions
to choose the resistive divider values.
V
OUT
R
U
For the HV regulator:
FB
R
= 2165/(C
× f
)
U
OUT
SW_HV
× 0.9
− 0.9)
R
U
R
B
R
=
B
(V
OUT
For LV regulators:
R
= (721.5/(f
× C
)) − ( 8.7× V
)
OUT
U
SW_LV
OUT
Figure 2. Setting the Output Voltage
R
× 0.75
U
R
=
B
(V
− 0.75)
OUT
where V
is in V, R and R are in kΩ, C
is in µF,
OUT
OUT
U
B
f
and f
are in MHz.
SW_HV
SW_LV
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MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
maintained at a given temperature (T ) by using proper
EP
heat sinks, the junction temperature of the device can be
estimated as:
Power Dissipation
The power dissipation inside the chip leads to an
increase in the junction temperature of the MAX17673/
MAX17673A. At a given operating condition, ensure that
the junction temperature of the devices do not exceed
+125°C. The power loss from the IC at full load can be
calculated as follows:
T
= T + θ × P
EP JC ICLOSS
J(MAX)
Junction temperatures greater than +125°C degrade
operating lifetimes.
2
OH
PCB Layout Guidelines
P
= I
D × 120m + 170m
[ ]
[
]
ICLOSS
All connections carrying pulsed currents must be very
short and as wide as possible. The inductance of these
connections must be kept to an absolute minimum due to
the high di/dt of the currents. Since inductance of a cur-
rent-carrying loop is proportional to the area enclosed by
the loop, if the loop area is made very small, inductance
is reduced. Additionally, small-current loop areas reduce
radiated EMI.
+f
28.515n + V
[
× I
× 9n
]
SW_HV
[
INH
OH
]
2
2
OB
2
2
+60m I
× D + I
× D + 60m I
+ I
OA OB
OA
A
B
(
)
(
)
+f
24.41n + 4n V
× I + V
× I
[
]
]
SW_LV
[
INA
OA
INB OB
A ceramic input filter capacitor should be placed close
to the IN_ pins of the IC. This eliminates as much trace
inductance effects as possible and gives the IC a cleaner
where,
D, D , and D = Duty cycle of the HV, LVA, and LVB
regulators, respectively
A
B
voltage supply. A bypass capacitor for the V
pin also
CC
f
and f = HV buck and LV buck switching
should be placed close to the pin to reduce effects of trace
impedance.
SW_HV
SW_LV
frequencies
I
, I and I
= Output currents of the HV buck, LVA,
OB
When routing the circuitry around the IC, the analog
small-signal ground and the power ground for switching
currents must be kept separate. They should be con-
nected together at a point where switching activity is at a
OH OA,
and LVB buck converter.
For more information regarding power losses at different
load current, switching frequency, output voltage, and
input voltage refer to EE-sim model of the MAX17673/
MAX17673A.
minimum, typically the return terminal of the V
bypass
CC
capacitor. This helps to keep the analog ground quiet.
The ground plane should be kept continuous/unbroken
as far as possible. No trace carrying high switching cur-
rent should be placed directly over any ground plane
discontinuity.
For a typical multilayer board, the thermal performance
metrics for the package are given below:
θ
= 29°C/W
= 2°C/W
JA
PCB layout also affects the thermal performance of the
design. A number of thermal vias that connect to a large
ground plane should be provided under the exposed pad
of the part, for efficient heat dissipation.
θ
JC
The junction temperature of the device can be estimated
at any given maximum ambient temperature (T
from the following equation:
)
A(MAX)
For a sample layout that ensures first pass success, refer
to the MAX17673/MAX17673A evaluation kits layout
available at www.maximintegrated.com.
T
= T
+ θ × P
(
)
J(MAX)
A(MAX) JA ICLOSS
If the application has a thermal-management system
that ensures that the exposed pad of the devices are
Maxim Integrated
│ 25
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Typical Application Circuit
V
BSTH
LXH
INH
INH
C4
0.1μF
L1
C1
4.7μF
`
22μH
V
OUT
ENH
PGNDH
5V/1.5A
EXTV
CC
C3
47μF
R1
249kΩ
PGNDH
R9
1Ω
C9
1μF
V
CC
R7
0Ω
FBH
POKH
SSH
C2
2.2μF
FDIV
R2
54.9kΩ
C10
MODE/SYNC*
RT
5600pF
MAX17673
MAX17673A
V
/ V
INA
ENA
INA OUT
C5
2.2μF
V
/ V
INB OUT
INB
C7
PGNDA
2.2μF
PGNDB
V
OUTA
ENB
LXB
LXA
L2
2.2μH
3.3V/1A
C6
22μF
V
OUTB
R3
PGNDA
L3
1.5μH
1.8V/1A
9.76kΩ
C8
22μF
R5
12.10kΩ
PGNDB
FBB
FBA
POKA
GND
R4
2.87kΩ
R6
8.66kΩ
POKB
SGND
EP
* THE SYNC FEATURE IS AVAILABLE ON MAX17673A
f
= 400kHz, f
= 2MHz
SW_LV
SW_HV
L1: XAL6060 223ME
C3: GRM32ER71A476KE15
L2: IHHP1008ABER2R2M01
C6,C8: GRM21BZ70J226ME44
L3: IHHP1008ABER1R5M01
Ordering Information
PART
MAX17673ATI+
MAX17673AATI+
PIN-PACKAGE
28 TQFN
PACKAGE SIZE
5mm x 5mm
FUNCTIONALITY
—
28 TQFN
5mm x 5mm
SYNC Feature
Maxim Integrated
│ 26
www.maximintegrated.com
MAX17673/MAX17673A
Integrated 4.5V to 60V Synchronous 1.5A HV Buck
and Dual 2.7V to 5.5V, 1A Buck Regulators
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
10/18
Initial release
—
Updated the title, and the General Description, Benefits and Features, Electrial
Characteristics, Typical Operating Characteristics, Pin Configuration and Pin
Description, Functional Diagram, Detailed Description, Operating Input Voltage, PFM,
Power Dissipation, Typical Application Circuit section, and added MAX17673AATI+ to
the Ordering Information
1
2
10/19
11/19
1‒22
Updated TOC60 and TOC61, MODE Selection and External Clock Synchronization
section, and Typical Application Circuit; corrected typo
16, 21, 26
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 27
相关型号:
MAX17673AATI
Integrated 4.5V to 60V Synchronous 1.5A HV Buck and Dual 2.7V to 5.5V, 1A Buck Regulators
MAXIM
MAX17673ATI
Integrated 4.5V to 60V Synchronous 1.5A HV Buck and Dual 2.7V to 5.5V, 1A Buck Regulators
MAXIM
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