MAX17853_技术文档

EVALUATION KIT AVAILABLE

Click here for production status of speciﬁc part numbers.

MAX17853

14-Channel High-Voltage Data-Acquisition System

General Description

Beneﬁts and Features

● AECQ-100 Grade 1 Temperature Range -40°C to

The MAX17853 is a flexible data-acquisition system for

the management of high-voltage and low-voltage battery

modules. The system can measure 14 cell voltages and a

combination of six temperatures or system voltage mea-

surements with fully redundant measurement engines in

263µs, or perform all inputs solely with the ADC measure-

ment engine in 156µs. There are 14 internal balancing

switches rated for > 300mA for cell-balancing current,

each supporting extensive built-in diagnostics. Up to 32

devices can be daisy-chained to manage 448 cells and

monitor 192 temperatures.

125°C

● 65V Operating Voltage

● Ultra-Low-Power Operation

• Standby Mode: 2mA

• Shutdown Mode: 2µA

● Redundant ADC and Comparator (COMP) Acquisitions

● Simultaneous Cell and Bus-Bar Voltage Acquisitions

● 14 Cell-Voltage Measurement Channels

• 1mV Accuracy (3.6V, 25°C)

Cell and bus-bar voltages ranging from -2.5V to +5V

are measured differentially over a 65V common-mode

range, with a typical accuracy of 1mV (3.6V cell, 25°C).

If oversampling is enabled, up to 128 measurements per

channel can be averaged internally with 14-bit resolution

and combined with digital post-processing IIR filtering

for increased noise immunity. The system can shut itself

down in the event of a thermal overload by measuring its

own die temperature.

• 2mV Accuracy (5°C to 40°C)

• 4.5mV Accuracy (-40°C to +125°C)

● 14 Cell-Balancing Switches

• > 300mA Software-Programmable Balancing Current

• Optimized Driving and Parking Balancing Modes

• Automated Balancing with Individual Cell Timers

• Automated Balancing by Cell Voltage

• Emergency Discharge Mode

● Six Configurable Auxiliary Inputs for Temperature,

For robust communications, the system uses a Maxim

battery-management UART or SPI protocol, and is

optimized to support a reduced feature set of internal

diagnostics and rapid-alert communication through both

embedded communication and hardware-alert interfaces

to support ASIL D and FMEA requirements.

Voltage, or GPIO

● Integrated Die-Temperature Measurement

● Automatic Thermal Protection

● Individually Configurable Safety Alert

• Overvoltage, Undertemperature Faults

• Undervoltage, Overtemperature Faults

• One Cell-Mismatch Alert

Applications

● High-Voltage Battery Stacks

● Electric Vehicles (EVs)

● Hybrid Electric Vehicles (HEVs)

● Electric Bikes

● Support ASIL D Requirements for Cell Voltage,

Temperature, Communication

● Selectable UART, Dual UART, or SPI Interface

● Battery-Management UART Protocol

• Daisy-Chain Up to 32 Devices

● Battery-Backup Systems (UPS)

● Super-Cap Systems

• Capacitive Communication-Port Isolation

• Up to 2Mps Baud Rate (auto-detect)

• 1.5µs Propagation Delay (per device)

• Packet-Error Checking (PEC)

● Battery-Powered Tools

● Configurable Hardware-Alert Interfaces

● Factory-Trimmed Oscillator

• No External Crystals Required

Ordering Information appears at end of data sheet.

● 32-Bit Unique Device ID

● 64-Pin (10mm x 10mm) LQFP Package

19-100355; Rev 5; 5/20

MAX17853

14-Channel High-Voltage Data-Acquisition System

TABLE OF CONTENTS

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

MAX17853 Simplified Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

UART Interface with Single-Ended Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

UART Interface with Differential Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SPI Interface with Single-Ended Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Terms, Definitions, and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Data Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Data Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Factory Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Factory-Programmed Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Flexible Battery-Pack Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Flexible-Pack Interaction with Acquisitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Power-Multiplexing Operation (Cell Balancing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Flexible Pack Alert. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Cell Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Bus-Bar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Block-Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Auxiliary Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Auxiliary Inputs: Ratiometric Temperature

Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Ratiometric Auxiliary Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Computing Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Auxiliary Inputs: Absolute-Voltage Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Absolute Auxiliary Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Auxiliary Inputs: Mixed-Mode Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Auxiliary-Input Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Maxim Integrated │ 2

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Power-On (Standby Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Shutdown-to-Standby State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Shutdown State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Power-On and Shutdown Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Precision Internal Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Scan Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

ADC Input Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Comparator Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Scan Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

ADC Configurations and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

ADC Polarity Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

ADC Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Pyramid Mode Acqusition Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

ADC Pyramid Mode Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

ADC Acquisition Timing (Pyramid Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Pyramid Mode Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Ramp-Mode Acquisition Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

ADC Ramp-Mode Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Ramp-Mode Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

ADC Acquisition Timing (Ramp Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

ADC Acquisition Time Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Comparator Configuration and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Comparator-Scan Properities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Comparator Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Comparator-Acquisition Process ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 74

Comparator Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Comparator Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Comparator Acquisition Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Comparator Scan Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

ADC+COMP Configuration and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

ADC+COMP Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

ADC+COMP Acquisition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

ADC+COMP Scan Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ADC+COMP Acquisition Time Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Maxim Integrated │ 3

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

On-Demand Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Calibration Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

ADC Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Oversampling Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Comparator Oversampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

100Hz and 120Hz Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Acquisition Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Data Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Acquisition Data Transfer and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Calibration Data Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Filter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

IIR Data Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

AMENDFILT and RDFILT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

ALRTFILTSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

IIR Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Single-Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Double-Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Out-of-Scan Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Cell Balancing with

Embedded-Measurement Data Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Measurement Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Voltage Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Cell Mismatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Cell Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Temperature Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Cell-Balancing Mode Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

AUTOBALSWDIS Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Manual Cell-Balancing Mode with FlexPack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Auto-Individual Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Auto-Group Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Emergency-Discharge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Cell-Balancing Modes Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Auto-Even/Odd Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Maxim Integrated │ 4

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

Cell-Balancing Timer (CBTIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

CBRESTART Usage in Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Emergency-Discharge Mode and CBDUTY Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Notification Alerts Using CBNTFYCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Cell-Balancing Expiration Timer Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Cell-Balancing UV Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Cell-Balancing Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Cell-Balancing IIR Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Cell-Balancing Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Calibration Out-of-Range During Cell Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Transfer-Measurement Results Using CBSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Cell-Balancing Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Automatic SHDNL Control Using HOLDSHDNL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Cell Balancing with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Cell-Balancing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Cell-Balancing Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Example: Autonomous-Cell Balancing by Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Example: Autonomous-Cell Balancing

with Programmable UV Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Single-UART Interface with External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Single UART with Internal Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Dual-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Dual-UART Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Dual-UART Master/Slave Interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

UART Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

UART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

SHDNL Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

UART Rx Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Baud-Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Tx Adaptive Mode for Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Battery-Management UART Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Command Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Preamble Character. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Data Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Maxim Integrated │ 5

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

Stop Character. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

UART Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

UART Communication Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Command Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Command-Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Data-Check Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

PEC Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Alive-Counter Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Fill Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Battery-Management UART

Protocol Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

HELLOALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

HELLOALL Operation in Dual-UART Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

HELLOALL Operation In a

Single-UART Configuraiton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

HELLOALL Address Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

WRITEALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

WRITEDEVICE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

READALL Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

READDEVICE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

READBLOCK Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

DOWNHOST Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

UPHOST Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

ALERTPACKET Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

System-Level Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Supported Transaction Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Safety Pulup/Pulldown Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

SPI Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

SPI Write-Mode Transcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

SPI Write-Mode Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Write Bit — R/WB = 0 (DI[31]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Address — A[7:0] (DI[30:23]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Address Cyclic-Redundancy Check — CRCA[2:0] (DI[22:20]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Maxim Integrated │ 6

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

Input Data — DIN[15:0] (DI[19:4]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Repeated-Write Bit — R/WB‘ = 0 (DI3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Input Data Cyclic-Redundancy

Check — CRCD[2:0] (DI[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

SPI Write-Mode Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Status Information — STAT[4:0] (DO[31:27]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Status Cyclic-Redundancy Check — CRCS[2:0] (DO[26:24]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Address Confirmation — A‘[7:0] (DO[23:16]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Input Data Confirmation — DIN‘[7:0] (DO[15:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

SPI Write-Mode Qualification Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

SPI Read-Mode Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

SPI Read-Mode Input-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Read Bit — R/WB = 1 (DI[31]): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Address — A[7:0] (DI[30:23]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Address Cyclic Redundancy Check — CRCA[2:0] (DI[22:20]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Input Data — DIN[15:0] (DI[19:4]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Repeated-Read Bit — R/WB‘ = 1 (DI[3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Input-Data Cyclic-Redundancy Check – CRCD[2:0] (DI[2:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

SPI Read-Mode Output-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Status Information – STAT[4:0] (DO[31:27]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Status Cyclic-Redundancy Check — CRCS[2:0] (DO[26:24]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Read Confirmation Bits — F\h (DO[23:20]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Output Data — DOUT[15:0] (DO[19:4]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Read OK Bit — ROK (DO[3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Output-Data Cyclic-Redundancy Check — CRCO[2:0] (DO[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

SPI Read-Mode Qualification Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

General-Transaction Information (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Status and Status CRC Output Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Status Information — STAT[4:0] (DO[31:27]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

SPI ALERT Bit-Masking Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Status Cyclic Redundancy Check — CRCS[2:0] (DO[26:24]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

SPI CRC Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

SPI CRC Pseudocode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

SPI Timeout Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Alert Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

UART-Mode Alert Detection (UARTSEL=1'b1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

SPI Mode Alert Operation (UARTSEL=1'b0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Alert Interface Masking Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Maxim Integrated │ 7

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

Alert Packet Status Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Alert-Masking TOPCELL1/2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Low-Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

HV Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

ALERTOUT Pin-to-Pin Short Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

CELL Pin Open Diagnositics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Die-Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Die-Temperature Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

V

AA

Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

ALTREF Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Comparator Signal-Path Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Cell Gain-Calibration-Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Offset-Calibration Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

THRM Offset-Calibration Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

LSAMP Offset-Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Zero-Scale ADC Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Full-Scale ADC Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

DAC 1/4 Scale Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

DAC 3/4 Scale Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

BALSW Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

BALSW Short Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

BALSW Open Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Even/Odd Sense-Wire Open Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Examples of Normal Sense-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Examples of Broken Sense-Wire Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Sense-Wire Open-Fault-Detection Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Examples of Broken Internal Switch and

Trace-Fault Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

ADC End-of-Scan Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

MAX17853 User Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Register Map Usage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Interface Protocol Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Unused Bitfields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

STATUS Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 176

Maxim Integrated │ 8

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

GENERAL CONFIGURATION Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 177

ALERT CONFIGURATION Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 178

THRESHOLD Registersꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 178

DIAGNOSTIC THRESHOLD Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 180

CELL DATA Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 180

TOTAL DIAG AUX DATA Registersꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 181

SCAN SETTINGS Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 181

SCAN CONTROL Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 182

DIAGNOSTIC SETTINGS Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 182

DIAGNOSTIC CONTROL Registers ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 182

CELL-BALANCING Registersꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 182

ROM SUPPORT Registersꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 184

Reserved Bitfields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Register Blocks and Transaction-Reject Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Register Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

VERSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

STATUS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

STATUS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

STATUS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

FMEA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

FMEA2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

ALRTSUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

ALRTOVCELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

ALRTUVCELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

MINMAXCELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

ALRTAUXPRTCTREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

ALRTAUXOVREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

ALRTAUXUVREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

ALRTCOMPUVREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

ALRTCOMPAUXOVREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

ALRTCOMPAUXUVREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

ALRTBALSWREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

SWACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

DEVCFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

DEVCFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

AUXGPIOCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

GPIOCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Maxim Integrated │ 9

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

PACKCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

ALRTIRQEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

ALRTOVEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

ALRTUVEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

ALRTAUXOVEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

ALRTAUXUVEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

ALRTCALTST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

OVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

OVTHSETREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

UVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

UVTHSETREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

MSMTCHREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

BIPOVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

BIPOVTHSETREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

BIPUVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

BIPUVTHSETREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

BLKOVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

BLKOVTHSETREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

BLKUVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

BLKUVTHSETREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

AUXROVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

AUXROVTHSETREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

AUXRUVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

AUXRUVTHSETREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

AUXAOVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

AUXAOVTHSETREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

AUXAUVTHCLRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

AUXAUVTHSETREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

COMPOVTHREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

COMPUVTHREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

COMPAUXROVTHREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

COMPAUXRUVTHREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

COMPAUXAOVTHREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

COMPAUXAUVTHREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

COMPOPNTHREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

COMPAUXROPNTHREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

COMPAUXAOPNTHREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

COMPACCOVTHREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

Maxim Integrated │ 10

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

COMPACCUVTHREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

BALSHRTTHRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

BALLOWTHRREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

BALHIGHTHRREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

CELL1REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

CELL2REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

CELL3REG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

CELL4REG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

CELL5REG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

CELL6REG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

CELL7REG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

CELL8REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

CELL9REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

CELL10REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

CELL11REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

CELL12REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

CELL13REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

CELL14REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

BLOCKREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

TOTALREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

DIAG1REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

DIAG2REG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

AUX0REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

AUX1REG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

AUX2REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

AUX3REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

AUX4REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

AUX5REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

POLARITYCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

AUXREFCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

AUXTIMEREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

ACQCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

BALSWDLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

MEASUREEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

MEASUREEN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

SCANCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

ADCTEST1AREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

ADCTEST1BREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

Maxim Integrated │ 11

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

ADCTEST2AREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

ADCTEST2BREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

DIAGCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

CTSTCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

AUXTSTCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

DIAGGENCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

BALSWCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

BALEXP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

BALEXP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

BALEXP3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

BALEXP4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

BALEXP5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

BALEXP6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

BALEXP7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

BALEXP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

BALEXP9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

BALEXP10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

BALEXP11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

BALEXP12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

BALEXP13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

BALEXP14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BALAUTOUVTHR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BALDLYCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

BALCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

BALSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282

BALUVSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

BALDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

ID1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

ID2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

OTP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

OTP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

OTP4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

OTP5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

OTP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

OTP7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

OTP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

OTP9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

Maxim Integrated │ 12

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

TABLE OF CONTENTS CONTINUED

OTP10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

OTP11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

OTP12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

Calibration-Alert Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

Supply Connection Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Vehicle Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Battery-Management Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Daisy-Chain System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Distributed CAN Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Standard Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Power-Supply Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Connecting Cell Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Flexible Pack Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

Power Supply, Cell Input Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

External Cell Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

External Cell-Balancing using FET Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

External Cell-Balancing Using BJT Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

External Cell-Balancing Short-Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

High-Z Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

UART Supplemental ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Single-Ended Rx Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

UART Isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

UART Transformer Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

UART Optical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

ALERT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

Device Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

PEC Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

PEC Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

PEC Calculation Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

ROMCRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

PCB Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

Layout Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

Maxim Integrated │ 13

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

LIST OF FIGURES

Figure 1. MAX17853 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 2. MAX17853 ESD Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 3. MAX17853 Analog Front-End. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 4. Flexible-Pack Configuration for 12-Cell Pack on 14-Channel CMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 5. Flexible-Pack Power-On Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 6. Cell Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 7. Bus-Bar Switch Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 8. Block-Measurement Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 9. Auxiliary Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 10. Auxiliary-Temperature Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 11. Operational-Mode State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 12. Power-On Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 13. Shutdown Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 14. UART Operation (Shutdown Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 15. SPI Operation (Shutdown Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 16. Power-On Timing (UART-Communication Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 17. Power-On Shutdown Timing (SPI Directed Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 18. Power-On and Shutdown Timing (UART Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 19. Power-On and Shutdown Timing (SPI Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 20. Acquisition (SCANCFG=0h, SCANMODE=0, OVSAMPL=0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1 >

0h, DIAGSEL2 > 0h, AUXEN=3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 21. Acquisition (SCANCFG=0h, SCANMODE=0, OVSAMPL = 0h, TOPCELL1/2 = 14, ALTMUXSEL=1,

BLOCKEN=1, DIAGSEL1 > 0h, DIAGSEL2 > 0h, AUXEN=3F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 22. Acquisition - SCANCFG=0h, SCANMODE=0, OVSAMPL > 0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1

> 0h, DIAGSEL2 > 0h, AUXEN=3Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 23. Acquisition (SCANCFG=0h, SCANMODE=0, OVSAMPL > 0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1 >

0h, AUXEN=03h, FOSR > 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 24. Acquisition (SCANCFG=0h, SCANMODE=1, OVSAMPL=0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1 >

0h, DIAGSEL2 > 0h, AUXEN=3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 25. Acquisition (SCANCFG=0h, SCANMODE=1, OVSAMPL = 0h, TOPCELL1/2=14, ALTMUXSEL=1,

BLOCKEN=1, DIAGSEL1 > 0h, DIAGSEL2 > 0h, AUXEN=3Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 26. Comparator Single-Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 27. Comparator Single-Scan with Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 28. Simultaneous ADC+COMP Scan Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 29. Simultaneous ADC+COMP Scan With Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 30. On-Demand Calibration Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 31. 100Hz Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 32. 120Hz Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 33. Acquisition-Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Maxim Integrated │ 14

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

LIST OF FIGURES CONTINUED

Figure 34. Data-Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 35. IIR Filter Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 36. 100mV IIR Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 37. Single-Buffer Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 38. Double-Buffer Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 39. Cell Voltage-Alert Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 40. Logic Diagram when Balancing Switches are Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 41. AUTOBALSWDIS Measurement Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 42. Auto Even/Odd Cell Balancing without UV Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 43. Auto Even/Odd Cell Balancing with UV Detection, ADC with OVSAMPL . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 44. Cell-Balancing Expiration Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 45. Cell-Balancing UV-Threshold Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 46. Cell Balancing with No Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 47. Cell Balancing with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 48. Cell-Balancing Stop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 49. SHDNL Pullup Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 50. Internal Cell-Balancing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 51. Typical Balancing-Current Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Figure 52. Single UART with External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Figure 53. Single UART with Differential Alert Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Figure 54. Dual-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Figure 55. Dual-UART Master/Slave Interaction (Timing Considerations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Figure 56. Dual-UART Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Figure 57. UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Figure 58. UART Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Figure 59. SHDNL Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Figure 60. Command Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Figure 61. Preamble Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Figure 62. Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Figure 63. Stop Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 64. Communication Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Figure 65. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 66. SPI Device Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 67. SPI Supported Transaction Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 68. SPI Write-Mode Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 69. SPI Read-Mode Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 70. SPI CRC Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 71. UART-Mode Alert-Detection Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Maxim Integrated │ 15

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

LIST OF FIGURES CONTINUED

Figure 72. Low-Voltage Regulator and Thermal-Shutdown Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 73. HV Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 74. Die-Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 75. V_AADiagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 76. ALTREF Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 77. Comparator Signal Path to ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 78. Comparator Accuracy Diagnostic Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 79. Comparator Accuracy End of Scan Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 80. Cell Gain Calibration-Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 81. Offset-Calibration Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 82. THRM Offset-Calibration Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 83. LSAMP Offset Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 84. ADC Zero-Scale Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 85. Full-Scale ADC Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 86. DAC 1/4 and 3/4 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 87. Balancing Switch Short. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 88. BALSW Short-Diagnostic Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 89. BALSW Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 90. Sense-Wire Open-Diagnostic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 91. Cell Sense-Wire Open-Diagnostic Operations (Normal Operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 92. Cell Sense-Wire Open-Diagnostic Operations (Normal Operation, Including Bus Bars) . . . . . . . . . . . . .170

Figure 93. Cell Sense-Wire Open-Diagnostic Operations (Example with Odd Sense-Wire Fault). . . . . . . . . . . . . . .171

Figure 94. Cell Sense-Wire Open-Diagnostic Operations (Example with Even Sense-Wire Fault) . . . . . . . . . . . . . .171

Figure 95. Cell Sense-Wire Open-Diagnostic Operations (Example with Broken BALSW or Internal Trace) . . . . . .174

Figure 96. Electric Vehicle System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Figure 97. Daisy-Chain System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Figure 98. Distributed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Figure 99. Power-Supply Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 100. External-Balancing FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 101. External Cell-Balancing BJT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 102. UART Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 103. High-Z Idle Mode Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 104. External ESD Protection for UART Tx Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 105. External ESD Protection for UART Rx Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 106. Application Circuit for Single-Ended UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 107. UART Transformer Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 108. UART Optical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 109. 5V SPI Supply from System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Maxim Integrated │ 16

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

LIST OF FIGURES CONTINUED

Figure 110. 3.3V SPI Supply from Device V_AALDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Figure 111. Single-End ALERT Interface in UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 112. Single-End ALERT Interface in SPI mode - Active Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 113. Single-End ALERT Interface in SPI mode - Passive Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 114. Device Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 115. PEC CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 116. ROMCRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

LIST OF TABLES

Table 1. System Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 2. Data-Acquisition Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 3. Numeric Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 4. THRM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 5. AUXTIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 6. Auxiliary-Temperature Input Range: ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 7. Auxiliary-Temperature Input Range: Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 8. Auxiliary-Voltage Input Range: ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 9. Auxiliary-Voltage Input Range: Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 10. GPIO/Auxiliary Enable Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 11. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 12. Shutdown Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 13. ADC Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 14. Comparator Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 15. ADC Pyramid Mode (SCANMODE = 0) Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 16. ADC Ramp Mode (SCANMODE = 1) Acquisition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 17. ADC Acquisition Time Examples (with AUXTIME[9:0] = 000h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 18. Comparator Acquisition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 19. Comparator Acquisition-Time Examples (with AUXTIME[9:0] = 000h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 20. ADC+COMP Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 21. ADC+COMP Acquisition Time Examples (with AUXTIME[9:0] = 000h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 22. Measurement Path Calibration Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 23. Comparator Faults for Alerts vs. Oversampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 24. Watchdog-Timeout Duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 25. FOSR Notch-Filter Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 26. IIR 100mV Step Response Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 27. IIR Data-Control Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 28. Measurement Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Maxim Integrated │ 17

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

LIST OF TABLES CONTINUED

Table 29. Set- and Clear-Threshold Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 30. Temperature-Alert Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 31. Cell-Balancing Register Write Behavior when Cell Balancing is Selected . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 32. Cell-Balancing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 33. Emergency-Discharge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 34. Cell-Balancing Measurement Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 35. Cell-Balancing Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 36. Calibration Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 37. UART Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 38. UART Rx Modes (Post ALRTRST Being Cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 39. UART Rx Modes (Prior to ALRTRST Being Cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 40. Data Character Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 41. Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Table 42. Command Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 43. Battery-Management Protocol (Command-Byte Encoding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 44. Data-Check Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 45. HELLOALL Command Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 46. HELLOALL Up-Path Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 47. HELLOALL Down-Path Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 48. WRITEALL Sequencing (Unchanged by Daisy-Chain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 49. WRITEDEVICE Sequencing (Unchanged by Daisy-Chain). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 50. READALL Command Sequencing In Single-UART or

Dual-UART Up Path (z = Number of Devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 51. READALL Command Sequencing In Dual-UART Down Path

(z = Number of Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 52. READDEVICE Sequencing In Single-UART or Dual-UART Up Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 53. READDEVICE Sequencing In Dual-UART Down Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 54. READBLOCK Sequencing In Single-UART or Dual-UART Up Path (Block Size = 1) . . . . . . . . . . . . . . . 130

Table 55. READBLOCK Sequencing In Single-UART or Dual-UART Up Path (Block Size = 1) . . . . . . . . . . . . . . . 130

Table 56. READBLOCK Sequencing In Dual-UART Down Path (Block Size = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Table 57. READBLOCK Sequencing In Single-UART or Dual-UART Down Path (Block Size = 2) . . . . . . . . . . . . .131

Table 58. DOWNHOST Sequencing (z = Total Number of Devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 59. UPHOST Sequencing (z = total number of devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 60. ALERTPACKET Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 61. SPI CRC Operation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 62. Alert-Interface Configuration in UART Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 63. Alert Output Driver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 64. Low-Voltage Regulator Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Maxim Integrated │ 18

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(

)

LIST OF TABLES CONTINUED

Table 65. Low-Voltage Regulator Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Table 66. HV Charge-Pump Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 67. Oscillator Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 68. Summary of Built-In Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 69. Comparator Signal-Path Diagnostic Verification Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 70. BALSW Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 71. BALSW-Short Diagnostics Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 72. BALSW Short Diagnostic Auto-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 73. BALSW Open-Diagnostic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 74. BALSW Open-Diagnostic Auto-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 75. Sense-Wire Open-Diagnostic Automatic Configuration Overrides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 76. Odd Sense-Wire Open-Measurement Results for Broken Sense Wires. . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 77. Even Sense-Wire Open-Measurement Results for Broken Sense Wires . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 78. Odd and Even Sense-Wire Open-Measurement Results Overlay for Broken Sense Wires. . . . . . . . . . . 173

Table 79. Odd and Even Sense-Wire Open-Measurement Results Overlay for Broken Sense Wires. . . . . . . . . . . .174

Table 80. FET-Balancing Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Table 81. BJT Balancing Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Maxim Integrated │ 19

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

MAX17853 Simpliﬁed Application Diagrams

UART Interface with Single-Ended Alert

4.7µF

50V

MODULE N+1

CELL STACK

10Ω

100Ω

HV

DCIN

VBLK

CPP

2.2µF

100V

V

AA

0.1µF

100V

CPN

UARTSEL

SHDNL/

10kΩ

1.0nF

25V

V

AA

BLOCK-FILTER

MAX17853

1.0µF

NETWORK (OPTIONAL)

AGND

V

DDL1

0.47µF

GNDL1

C14

V

DDL2

SW14

C13

CELL 14

GNDL2

SW13

C12

V

DDL3

GNDL3

SW12

C11

CELL 13

CELL 12

UART DAISY-CHAIN FROM

UPPER MODULE OR SYSTEM

CONTROLLER

SW11

C10

MAX17853

UPPER-UART

INTERFACE

SW10

C9

TXUP

TXUN

RXLP

RXLN

SW9

C8

RXUP

RXUN

TXLP

TXLN

MODULE N+1

SW8

C7

CELL INPUT-FILTER

NETWORK

UART DAISY-CHAIN FROM

LOWER MODULE OR

SYSTEM CONTROLLER

SW7

C6

CELL 4

CELL 3

CELL 2

CELL 1

SW6

C5

MAX17853

TXLP

TXLN

RXUP

RXUN

LOWER-UART

INTERFACE

SW5

C4

RXLP

RXLN

TXUP

TXUN

SW4

C3

MODULE N-1

SW3

C2

ALERTIN

ALERTOUT

THRM

MODULE N+1

MODULE N-1

ALERT INTERFACE

(OPTIONAL)

SW2

C1

SW1

AUXIN0/GPIO0

AUXIN1/GPIO1

AUXIN2/GPIO2

AUXIN3/GPIO3

AUXIN4/GPIO4

AUXIN5/GPIO5

C0

AUXILLARY- /GPIO-/

ABSOLUTE-

MEASUREMENT

CIRCUIT

NTC NETWORK

SW0

AGND

AUXGND

CAPACITOR RATINGS SHOWN IN THIS DATA SHEET ARE BASED ON

EXPECTED REFERENCE- CIRCUIT CONDITIONS AND MAY BE MODIFIED

BASED ON FINAL APPLICATION REQUIREMENTS.

MODULE N-1 CELL STACK

OR CELL STACK GROUND

Maxim Integrated │ 20

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

MAX17853 Simpliﬁed Application Diagrams (continued)

UART Interface with Diﬀerential Alert

4.7µF

50V

MODULE N+1

CELL STACK

10Ω

100Ω

HV

DCIN

VBLK

CPP

2.2µF

100V

V

AA

0.1µF

100V

CPN

UARTSEL

SHDNL/

10kΩ

1.0nF

25V

BLOCK-FILTER

V

AA

NETWORK (OPTIONAL)

MAX17853

1.0µF

AGND

V

DDL1

0.47µF

GNDL1

C14

V

DDL2

SW14

C13

CELL 14

GNDL2

SW13

C12

V

DDL3

GNDL3

SW12

C11

CELL 13

CELL 12

UART DAISY-CHAIN FROM

UPPER MODULE OR SYSTEM

CONTROLLER

SW11

C10

MAX17853

UPPER-UART

INTERFACE

SW10

C9

TXUP

TXUN

RXLP

RXLN

SW9

C8

RXUP (DIFF ALERT)

RXUN (DIFF ALERT)

TXLP (DIFF ALERT)

TXLN (DIFF ALERT)

MODULE N+1

SW8

C7

CELL INPUT-FILTER

NETWORK

UART DAISY-CHAIN FROM

LOWER MODULE OR

SYSTEM CONTROLLER

SW7

C6

CELL 4

CELL 3

CELL 2

CELL 1

SW6

C5

MAX17853

RXUP (DIFF ALERT)

RXUN (DIFF ALERT)

TXLP (DIFF ALERT)

TXLN (DIFF ALERT)

LOWER-UART

INTERFACE

SW5

C4

RXLP

RXLN

TXUP

SW4

C3

TXUN

MODULE N-1

SW3

C2

ALERTIN

ALERTOUT

THRM

SW2

C1

SW1

AUXIN0/GPIO0

AUXIN1/GPIO1

AUXIN2/GPIO2

AUXIN3/GPIO3

AUXIN4/GPIO4

AUXIN5/GPIO5

AUXILLARY- /GPIO-/

ABSOLUTE-

MEASUREMENT

CIRCUIT

C0

NTC NETWORK

SW0

AGND

AUXGND

CAPACITOR RATINGS SHOWN IN THIS DATA SHEET ARE BASED ON

EXPECTED REFERENCE CIRCUIT CONDITIONS AND MAY BE MODIFIED

BASED ON FINAL APPLICATION REQUIREMENTS.

MODULE N-1 CELL STACK

OR CELL STACK GROUND

Maxim Integrated │ 21

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

MAX17853 Simpliﬁed Application Diagrams (continued)

SPI Interface with Single-Ended Alert

4.7µF

50V

MODULE N+1

CELL STACK

10Ω

100Ω

HV

DCIN

VBLK

CPP

2.2µF

100V

0.1µF

100V

CPN

UARTSEL

SHDNL/

10kΩ

V

AA

BLOCK-FILTER

NETWORK (OPTIONAL)

MAX17853

1.0µF

AGND

V

DDL1

0.47µF

GNDL1

C14

V

or

AA

V

DDL2

SW14

C13

MICRO

CELL 14

GNDL2

SW13

C12

V

DDL3

GNDL3

SW12

C11

CELL 13

CELL 12

SW11

C10

SPI COMMUNICATION FROM

SYSTEM CONTROLLER

SW10

C9

TXUP/CSB

TXUN/SCLK

SW9

C8

RXUP

RXUN

MICROCONTROLLER

GPO

SW8

C7

CSB

SCLK

CELL INPUT-FILTER

NETWORK

SW7

C6

TXLP/SDO

TXLN/ SDI

MISO

MOSI

CELL 4

CELL 3

CELL 2

CELL 1

SW6

C5

SW5

RXLP

RXLN

GPI

C4

SW4

C3

ALERTIN

SW3

C2

ALERTOUT

THRM

SW2

C1

SW1

AUXIN0/GPIO0

AUXIN1/GPIO1

AUXIN2/GPIO2

AUXIN3/GPIO3

AUXIN4/GPIO4

AUXIN5/GPIO5

AUXILLARY-/GPIO-/

ABSOLUTE-

MEASUREMENT

CIRCUIT

C0

NTC NETWORK

SW0

AGND

AUXGND

MODULE N-1 CELL STACK

OR CELL STACK GROUND

CAPACITOR RATINGS SHOWN IN THIS DATASHEET ARE BASED

ON EXPECTED REFERENCE CIRCUIT CONDITIONS AND MAY BE

MODIFIED BASED ON FINAL APPLICATION REQUIREMENTS.

Maxim Integrated │ 22

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Absolute Maximum Ratings

HV to AGND..........................................................-0.3V to +80V

DCIN, SWn, VBLK,

RXLP, RXLN, RXUP, RXUN, ALERTIN to AGND...-30V to +30V

TXLP, TXLN, ALERTOUT to GNDL2.......................-0.3V to +6V

TXUP, TXUN to GNDL3 ..........................................-0.3V to +6V

Cn to AGND........................-0.3V to min (V

+ 0.3V or 72V)

HV

Cn to Cn-1..............................................................-72V to +72V

UARTSEL to AGND.................................-0.3V to V

+ 0.3V

DDL1

SWn to SWn-1.......................................................-0.3V to +16V

CPP to AGND....................................... V

- 1V to V

+ 1V

DCIN

HV

V

to AGND...........................................................-0.3V to +4V

CPN to AGND.......................................... -0.3V to V

Maximum Continuous Current

into Any Pin (Note 1) .................................... -20mA to +20mA

Maximum Continuous Current

into SWn Pin (Note 2)............................... -650mA to +650mA

Maximum Average Power for ESD Diodes (Note 3)... 14.4W/√T

Package Continuous Power (Note 4)............... mW to 2000mW

Operating Temperature Range......................... -40°C to +125°C

Storage Temperature Range............................ -55°C to +150°C

Junction Temperature (Continuous) ..................................150°C

Soldering Lead Temperature (10s max)............................300°C

+ 0.3V

AA

DDL2 DDL3

DCIN

, V

to V ...........................................-0.3V to +6.0V

AA

to GNDL1.....................................................-0.3V to +4V

to GNDL2.....................................................-0.3V to +6V

to GNDL3.....................................................-0.3V to +6V

DDL1

DDL2

DDL3

AA

to V

.......................................................-0.3V to +0.3V

DDL1

AGND to GNDL1, GNDL2, GNDL3......................-0.3V to +0.3V

AGND to AUXGND............................................................. -0.3V

GPIOn/AUXINn........................................-0.3V to V

THRM to AGND...........................................-0.3V to V + 0.3V

+ 0.3V

DDL2

AA

SHDNL to AGND..................................... -0.3V to V

+ 0.3V

DCIN

Note 1: Balancing switches disabled.

Note 2: One balancing switch enabled, 60s (max).

Note 3: Average power for time period T, where T is the time constant (in µs) of the transient diode current during hot-plug event.

For, example, if T is 330µs, the maximum average power is 0.793W. Peak current must never exceed 2A. Actual average

power during hot-plug must be calculated from the diode current waveform for the application circuit and compared to the

maximum rating.

Note 4: Multilayer board. For T > +70°C, derate 25mW/°C.

A

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

LQFP

Package Code

C64+18

21-0083

90-0141

Outline Number

Land Pattern Number

Thermal Resistance, Four-Layer Board:

Junction to Ambient (θ

)

40°C/W

8°C/W

JA

Junction to Case (θ

)

JC

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Maxim Integrated │ 23

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER

POWER REQUIREMENTS

Supply Voltage, DCIN

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

9

65

V

DCIN

Supply Voltage, V

, V

V

, V

V

AA

5.5

DDL2 DDL3

DCIN Current, Shutdown Mode

I

V

= 0V

0.1

2.3

µA

DCSHDN

SHDNL

> 1.8V, UART in idle mode,

DCIN Current, Standby Mode

(Note 6)

not in acquisition mode, balance

switches, test current sources, and

alert interface disabled

I

1.7

2.9

mA

DCSTBY

DCIN Current, ADC

Acquisition Mode (Note 6)

All cell and auxiliary measurements

enabled, OVSAMPL[2:0]=000b

I

5.4

6

8.0

7.7

8.4

mA

DC_ADC

DCIN Current, COMP

Acquisition Mode (Note 6)

All cell and auxiliary measurements

enabled

I

DC_COMP

DCIN Current, ADC + COMP

Acquisition Mode (Note 6)

All cell and auxiliary measurements

enabled

I

6.8

DC_ADCCOMP

V

> 1.8V, all channels

SHDNL

DCIN Incremental Current, SPI

Communication Mode (Note 6)

I

disabled, all test current sources

disabled, acquisition disabled

170

300

1.3

µA

DCCOMM_SPI

Baud rate = 2Mbps (0% idle time in

preambles mode), 200pF load on

TXUP and TXUN, TXL not active,

not in acquisition mode, BALSWEN,

CTSTEN = 0000h

DCIN Incremental Current,

UART Communication Mode

(Note 6)

I

DCCOMM_UART

ADC-only acquisition, all cells and

auxiliary channels enabled,

HV Current, ADC

Acquisition Mode

I

0.9

1.1

1.8

mA

HVMEAS

V

= V

+ 5.5V

HV

DCIN

COMP-only acquisition, all cells and

auxiliary channels enabled,

HV Current, Comparator

(COMP) Scan Mode

I

mA

µA

HVCOMP

V

= V

+ 5.5V

HV

DCIN

Incremental HV Current,

Cell-Balancing Mode

V

= V

+ 5.5V, n balancing

(n + 1) (n + 1)

(n + 1)

x 26

HV

DCIN

I

HVBAL

switches enabled

x 5

x 15.5

CELL VOLTAGE INPUTS (Cn, VBLK)

Unipolar mode

0

5

Diﬀerential Input Range

(Note 7)

V

CELLn

Bipolar mode

-2.5

+2.5

Common-Mode Input Range

V

Not connected to SWn inputs

0

65

+100

20

V

CnCM

Input Leakage Current

VBLK Input Resistance

HVMUX Switch Resistance

I

Not in acquisition mode, V = 65V

-100

4.5

1.7

±10

10

nA

MΩ

kΩ

LKG_Cn

Cn

R

V

= V

= 57.6V

VBLK

DCIN

R

CTSTDAC[3:0] = Fh

3.3

5

HVMUX

Maxim Integrated │ 24

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CELL-BALANCING INPUTS (SWn)

Leakage Current

I

V

= 0V, V

= 5V, V -1 = 0V

SWn

-1

+1

µA

LKG_SW

SW0

SWn

Resistance, SWn to SWn-1

R

BALSWEN[n-1] = 1, I

= 100mA

0.5

1.25

1.3

2.25

Ω

SW

SWn

Resistance, SWn to SWn-1

(Note 8)

R

BALSWEN[n-1] =1, I

= 300mA

SWn

T = +125°C, CBMEASEN= 0x00,

J

FLXPCKEN=0, all even or all odd

channels enabled

Maximum Allowed Balancing

Current (Note 9)

I

650

mA

BAL_MAX

AUXILIARY INPUTS (AUXINn)

V

= V

or V

based

ADCREF

THRM

REF

Input Voltage Range

V

0

V

AUXIN

ADCREF

on AUXREFSEL

Not in acquisition mode,

Input Leakage Current

I

-400

10

25

+400

nA

LKG_AUX

V

= 1.65V

AUXINn

THRM OUTPUT

Switch Resistance, V to THRM

AA

R

70

+1

Ω

THRM

Leakage Current

I

= 3.3V

-1

µA

LKG_THRM

THRM

MEASUREMENT ACCURACY

Unipolar mode,V

SCANMODE=0x0, 0x1

= 3.6V,

CELLn

±0.45

ADC Measurement

Error, HVMUX Inputs

(Note 10)

V

mV

CELLnERR

Bipolar mode,V = 1.1V, SCAN-

CELLn

MODE=0x0, 0x1

Unipolar mode, 0.2V ≤ VCELLn ≤ 4.8V,

SCANMODE=0x0, 0x1

-4.5

+4.5

ADC Measurement

Error, HVMUX Inputs

(Note 10)

V

mV

CELLnERR

Bipolar mode, -2.3V ≤ VCELLn ≤ 2.3V,

SCANMODE=0x0, 0x1

ADC Measurement

Error, HVMUX Inputs

(Note 10)

Unipolar mode, 1.9V ≤ VCELLn ≤ 4.2V,

SCANMODE=0x0, 0x1,

5°C < Temp < 40°C

-2

+2

CELLnERR

Unipolar mode,V

SCANMODE=0x0, 0x1

= 3.6V,

CELLn

±0.45

Bipolar mode,V = 1.1V, SCAN-

CELLn

ADC Measurement

Error, ALTMUX Inputs

(Note 10)

MODE=0x0, 0x1

V

mV

SWnERR

Unipolar mode, 0.2V ≤ VCELLn ≤ 4.8V,

SCANMODE=0x0, 0x1

-4.5

+4.5

Bipolar mode, -2.3V ≤ VCELLn ≤ 2.3V,

SCANMODE=0x0, 0x1

Maxim Integrated │ 25

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER SYMBOL

CONDITIONS

≤ 65V, V = 65V,

MIN

TYP

MAX

UNITS

9V ≤ V

BLK

DCIN

-110

+110

SCANMODE=0x0, 0x1

ADC Measurement

Error, VBLK Input (Note 11)

V

mV

BLKERR

9V ≤ V ≤ 58.8V, V = 58.8V,

DCIN

BLK

-100

-3.5

-2.5

-5

+100

+3.5

+2.5

+5

SCANMODE=0x0, 0x1

ADC Measurement

Error, AUXIN Inputs (Note 11)

AUXREF[n] = 0b, SCANMODE = 0x0,

0x1

V

mV

°C

OS_AUX_RATIO

ADC Measurement

Error, AUXIN Inputs (Note 11)

AUXREF[n]=1b, SCANMODE = 0x0,

0x1

V

OS_AUX_ABS

Total Measurement Error, Die

Temperature (Note 8)

T = -40°C to +125°C,

J

OVSAMPL[2:0] = 000b

T

0

DIE_ERR

Channel Noise (Note 8)

V

OVSAMPL[2:0] = 0x3h

250

±1.0

μV

RMS

CELLNOISE

DNL

Diﬀerential Nonlinearity

(Any Conversion)

LSbs

bits

ADC Resolution

12

Level-Shifting Ampliﬁer Oﬀset

(Note 12)

V

DIAGSEL[2:0] = 011b

-200

-10

+200

mV

OS_LSAMP

COMPARATOR

Comparator Accuracy

V

0.2V ≤ VCELLn ≤ 4.8V

-20

+20

0.6

mV

OS_COMP

SHDNL INPUT AND CHARGE PUMP

Input Low Voltage

Input High Voltage

V

IL_SHDNL

V

1.8

8

IH_SHDNL

V

≥ 12V

9.5

6.7

4.7

12

DCIN

Regulated Voltage

V

SHDNLIMIT

= 9V

Pulldown Resistance

Input Leakage Current

R

FORCEPOR = 1

2.5

8

1

kΩ

µA

FORCEPOR

V

= 3.3V

= 65V

SHDNL

I

LKG_SHDNL

40

75

Charge-Pump Current,

UARTL/UARTU (Note 13)

< V

,

SHDNLIMIT

I

15

117

350

µA

SHDNL

baud rate = 2Mbps

UARTSEL

UARTSEL Input Low Voltage

UARTSEL Input High Voltage

UARTSEL Pullup Resistance

GENERAL-PURPOSE I/O (GPIOn)

Input Low Voltage

V

0.3 x V

V

IL_UARTSEL

AA

V

0.7 x V

IH_UARTSEL

AA

R

100

kΩ

UARTSEL

V

0.3 x V

V

IL_GPIO

DDL2

Input High Voltage

V

0.7 x V

IH_GPIO

DDL2

Maxim Integrated │ 26

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER

Pulldown Resistance

Output Low Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX

7.5

UNITS

MΩ

AUXINn/GPIOn conﬁgured as GPIO

R

0.5

2

GPIO

input

V

I

= 3mA

0.4

V

OL_GPIO

OH_GPIO

SINK

V

DDL2

- 0.4

Output High Voltage

V

I

= 3mA

V

SOURCE

ALERTIN

ALERTIN High-Comparator

Thershold

-V /2

AA

- 0.4

-V /2 +

AA

V

-V /2

AA

V

CH

0.4

ALERTIN Zero-Crossing

Comparator Threshold

V

-0.4

0

+0.4

ZC

ALERTIN Low-Comparator

Threshold

V

- 0.4

/2

V

+ 0.4

/2

AA

V

V /2

AA

V

CL

ALERTIN Comparator

Hysteresis

V

75

/3

mV

V

HYS_ALERTIN

ALERTIN Common-Mode

Voltage Bias

V

CM

AA

Leakage Current

Input Capacitance

I

V

= 1.5V

±1.0

2

µA

pF

LKG_ALERTIN

ALERTIN

C

ALERTIN

1/

Bit Period (Note 14)

t

8

BIT

f

OSC_16M

ALERTIN Fall Time

(Notes 8, 15)

t

0.5

t

ALERTIN_FALL

ALERTIN_RISE

BIT

ALERTIN Rise Time

(Notes 8, 15)

t

BIT

µs

ALERTIN Qualiﬁcation Time

t

25

ALERTIN_QUAL

Propagation Delay (ALERTIN

Port to ALERTOUT Port)

t

2.5

3

t

ALERT_PROP

BIT

Startup Time from SHNDL High

and V = 0V to ALERTIN Valid

AA

t

1

ms

ALERTIN_STARTUP

ALERTOUT

Output Low Voltage

V

I

= 20mA

0.4

V

OL_ALERTOUT

OH_ALERTOUT

LKG_ALERTOUT

SINK

V

DDL2

- 0.4

Output High Voltage

V

= 20mA

SOURCE

Leakage Current

REGULATOR

I

V

= 1.5V

-1

+1

µA

ALERTOUT

Output Voltage

V

0 ≤ I < 20mA

3.2

30

3.3

3.4

V

AA

Short-Circuit Current

I

V

shorted to AGND

AA

mA

AASC

Maxim Integrated │ 27

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER SYMBOL

CONDITIONS

MIN

TYP

2.95

3

MAX

3.02

3.1

UNITS

V

falling

rising

2.85

PORFALL

AA

V

POR Threshold

PORRISE

V

40

mV

°C

PORHYS

Thermal-Shutdown

Temperature (Note 8)

T

Temperature rising

145

SHDN

Thermal-Shutdown Hysteresis

(Note 8)

T

15

°C

HYS

HV CHARGE PUMP

9V ≤ V

≤ 12V, I

= 1.5mA

5.9

6.2

6.5

DCIN

LOAD

Output Voltage (V

Output Voltage

- V

)

V

HV-DCIN

V

HV

DCIN

12V ≤ V

≤ 65V, I

= 3mA

= 3mA,

DCIN

LOAD

14V ≤ V

FLXPACKEN1/2

LOAD

V

10.2

11

V

HV-DCIN_FLEX

(V

- V

)

HV

TOPCELL

Charge-Pump Eﬃciency

(Note 16)

Eﬀ

V

= 57.6V

38

%

HVCP

DCIN

OSCILLATORS

32kHz Oscillator Frequency

16MHz Oscillator Frequency

f

32.11

15.68

32.768

16

33.42

16.32

kHz

OSC_32K

f

MHz

OSC_16M

DIAGNOSTIC TEST SOURCES

CTSTDAC[3:0] = 9h, V < V

-

C0

AA

50

36

62.5

45

75

54

1.4V, V = 3.3V

AA

CTSTDAC[3:0] = 6h, V < V

C0

AA

1.4V, V = 3.3V

AA

Cell Test Source Current

I

µA

TSTCn

CTSTDAC[3:0] = 6h, V

>

C1–C14

-54

-75

25

-45

-36

-50

37.5

27

V

+ 1.4V

AGND

CTSTDAC[3:0] = 9Fh, V

>

C1–C14

-62.5

31.25

22.5

62.5

45

V

+ 1.4V

AGND

CTSTDAC[3:0] = 9h, V < V

-

Cn

HV

1.4V, V

= 53.5V

HV

HVMUX Test Source Current

AUXIN Test Source Current

I

TSTHVMUX

CTSTDAC[3:0] = 6h, V < V

Cn

18

1.4V, V

= 53.5V

HV

CTSTDAC[3:0] = 9h, V

<

>

AUXINn

50

75

V

- 1.4V, V

= 3.3V

DDL2

CTSTDAC[3:0] = 6h, V

AUXINn

36

54

V

- 1.4V, V

= 3.3V

DDL2

I

TSTAUXIN

CTSTDAC[3:0] = 6h, V

AUXINn

-54

-75

-45

-36

-50

V

+ 1.4V

AGND

CTSTDAC[3:0] = 9h, V

+ 1.4V

-62.5

V

AGND

Maxim Integrated │ 28

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIAGNOSTIC REFERENCES

ALTREF Voltage (Note 12)

V

A

DIAGSEL[2:0]=001b

1.23

1.242

±25

1.254

V

ALTREF

ALTREF Temperature

Coeﬃcient (∆VALTREF/∆T)

(Note 8)

ppm/°C

ALTREF

PTAT Output Voltage (Note 8)

V

T = +120°C

1.2

V

PTAT

J

PTAT Temperature Coeﬃcient

(∆VPTAT/∆T) (Note 8)

A

3.02

mV/°C

V_PTAT

PTAT Temperature Oﬀset

(Note 8)

T

-8.3

°C

OS_PTAT

ALERTS

ALRTVDDLn Threshold

ALRTGNDLn Threshold

V

= 3.3V

AA

3

3.15

0.15

3.25

0.3

V

VDDL_OC

V

AGND = 0V

0.05

GNDL_OC

V

- V

falling, FLXPACK-

DCIN

HV

4.5

8.5

4.75

5.0

EN1/2=0

ALRTHVUV Threshold

V

HVUV

V

- V

falling, FLXPACK-

rising

DCIN

HV

DCIN

9.25

16

9.5

20

EN1/2=1

ALRTHVOV Threshold

V

- V

14

4.7

115

V

HVOV

HV

ALRTHVHDRM Threshold

ALRTTEMP Threshold (Note 8)

ALRTTEMP Hysteresis (Note 8)

V

ALRTHVHDRM=0

HVHDRM

T

120

2

125

0.4

°C

ALRTTEMP

T

ALRTTEMPHYS

UART OUTPUTS (TXLP, TXLN, TXUP, TXUN)

Output Low Voltage

V

I

= 20mA

SINK

V

OL

Output High Voltage

(TXLP, TXLN)

V

DDL2

- 0.4

V

= 20mA

OH

SOURCE

Output High Voltage

(TXUP, TXUN)

V

DDL3

- 0.4

I

V

OH

Leakage Current

I

V

= 1.5V

TX

-1

+1

µA

LKG_TX

UART INPUTS (RXLP, RXLN, RXUP, RXUN)

Input Voltage Range

V

-25

+25

V

RX

CH

Receiver High Comparator

Threshold (Note 17)

V

/2

V

/2

AA

V

/2

AA

- 0.4

+ 0.4

Receiver Zero-Crossing

Comparator Threshold

(Note 17)

V

-0.4

0

+0.4

V

ZC

Receiver Low Comparator

Threshold (Note 17)

-V /2

AA

- 0.4

-V /2

AA

+ 0.4

V

-V /2

AA

CL

Maxim Integrated │ 29

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Receiver Comparator

Hysteresis (Note 17)

V

75

mV

HYS_RX

Receiver Common-Mode

Voltage Bias (Note 17)

V

/3

V

CM

AA

Leakage Current

I

V

= 1.5V

±1.0

µA

pF

LKG_RX

RX

Input Capacitance

(RXLP, RXLN)

C

4

RXL

Input Capacitance

(RXUP, RXUN)

C

pF

RXU

UART TIMING

Baud rate = 2Mbps

Baud rate = 1Mbps

Baud rate = 0.5Mbps

8

1/

Bit Period (Note 14)

t

16

32

BIT

f

OSC_16M

Rx Idle to Start Setup Time

(Note 8)

t

0

1

t

RXSTSU

BIT

STOP Hold Time to Idle

(Note 8)

t

0.5

SPHD

Rx Minimum Idle Time (Stop Bit

to Start Bit) (Note 8)

t

RXIDLESPST

Rx Fall Time (Notes 8, 15)

Rx Rise Time (Notes 8, 15)

t

0.5

t

FALL

BIT

t

RISE

Propagation Delay

(RX Port to Tx Port)

t

2.5

1

3

t

PROP

BIT

Startup Time from SHNDL High

and V = 0V to RXUP/RXUN

t

ms

AA

STARTUP

Valid

SERIAL PERIPHERAL INTERFACE (SPI)

SPI ELECTRICAL CHARACTERISTICS: POWER REQUIREMENTS

V

= V

for SPI

DDIO

DDL2

DDL3

I/O Supply Voltage

V

5

5.5

V

DDIO

AA

applications

Static I/O Supply Current

(Note SPI-1)

I

Static inputs, all outputs unloaded

±25

μA

DDIO

SPI ELECTRICAL CHARACTERISTICS: DIGITAL INPUT CHARACTERISTICS (SCLK, SDIN, CSB)

Input High Voltage

Input Low Voltage

V

3.0V < V

< 5.5V

0.7 x V

DDIO

V

IH

DDIO

V

3.0V < V

0.3 x V

DDIO

IL

Input Leakage Current

(Note SPI-2)

I

V

= 0V or V

±1

μA

kΩ

IN

DDIO

R

SDI, SCLK pulldown to GND

CSB pulup to V

40

100

160

Internal Safety Impedance

(Note SPI-3, SPI-4)

PD

PU

DDIO

Maxim Integrated │ 30

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

PARAMETER SYMBOL

Input Capacitance

Hysteresis Voltage

SPI ELECTRICAL CHARACTERISTICS: DIGITAL OUTPUT CHARACTERISTICS (SDO)

CONDITIONS

MIN

TYP

20

MAX

UNITS

pF

C

IN

V

0.15

V

H

V

DDIO

- 0.4

Output High Voltage

Output Low Voltage

V

> 3.0V, I

= 5mA

SOURCE

V

OH

DDIO

V

> 3.0V, I = 5mA

SINK

0.4

±1

V

OL

I

600

220

mA

SOURCE

SINK

Output Short-Circuit Current

I

OSS

Output Three-State Leakage

Output Three-State Capacitance

SPI TIMING CHARACTERISTICS

SCLK Frequency (Note SPI-5)

SCLK Period

I

µA

pF

OZ

C

20

OZ

f

t

0.1

100

40

10

MHz

ns

SCLK

t

10,000

CP

SCLK Pulse Width High

t

ns

CH

SCLK Pulse Width Low

t

40

ns

CL

CSB Fall to SCLK Rise

Setup Time

Applies to 1st SCLK rising edge

40

25

15

ns

CSS0

CSH0

CSH1

CSB Fall to SCLK Rise

Hold Time

Applies to inactive rising edge

preceding 1st rising edge

t

SCLK Rise to CSB Rise

Hold Time

Applies to 32nd rising edge

Applies to 32nd rising edge, guarantees

aborted (unqualiﬁed) sequence

t

CSA

CSB Rise to SCLK Rise

ns

Applies to 33rd rising edge,

guarantees qualiﬁed sequence

t

15

CSQ

CSB Pulse Width High

t

400

100

ns

CSPW

CSB Pulse Width High After

SWPOR

Applies after an accepted/executed

SWPOR command.

t

μs

CSPWSP

SDI to SCLK Rise Setup Time

SDI to SCLK Rise Hold Time

SCLK Fall to SDO Transition

SCLK Fall to SDO Hold

t

10

ns

DS

t

DH

t

C

= 20pF

= 0pF

30

DOT

LOAD

t

2

DOH

CSB Fall to SDO Transition

CSB Rise to SDO Hi-Z

t

= 20pF

30

25

DOE

t

Output disable time

DOZ

Transactions exceeding this duration

be rejected

Time Out Period (Note SPI-6)

t

360

μs

TO

Maxim Integrated │ 31

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Electrical Characteristics (continued)

(V

= +56V, T = T

to T

unless otherwise noted, where T

= -40°C and T

= +125°C. Typical values are at T = +25°C.

DCIN

A

MIN

MAX

MIN

MAX A

Operation is with the recommended application circuit.) (Note 5)

Note 5:

Unless otherwise noted, limits are 100% production tested at T = +25°C. Limits over the operating temperature range

A

and relevant supply voltage range are guaranteed by design and characterization.

Note 6:

Acquisition mode (ADC conversions) is entered when the SCAN bit is set and ends when SCANDONE is set. With

the typical acquisition duty cycle very low, the average current I

is much less than I

. Total supply current

DCIN

DCMEAS

during communication I

= I

+ I

.

DCIN

DCCOMM

DCSTBY

Note 7:

Note 8:

Note 9:

Measurement-accuracy range is guaranteed from V

Guaranteed by design and not production tested.

Not production tested. See the Cell-Balancing Current section for details on the maximum allowed balancing current.

+ 0.2V and V

- 0.2V.

CELLn_min CELLn_max

Duty cycle is calculated for a 10-year device lifetime.

Note 10:

V

= V - V

, V

= V

, and V

= 14 x │V

│ (V

= 9V minimum). Accuracy measure-

DCIN

CELLn

Cn

Cn-1 CELLn

CELLn-1

DCIN

CELLn

ment represents initial total measurement error with the input noise oversampled below 1LSB and over the tempera-

ture range of -20°C to +125°C. For specific measurement criteria, contact Maxim.

Accuracy measurement represents initial total measurementeror with the input noise oversampled below 1LSB.

As measured during specified diagnostic mode.

Note 11:

Note 12:

Note 13:

Note 14:

I

measured with V

= 0.3V, STOP characters, zero idle time, V

= 3.3V.

SHDNL

RX_PEAK

In daisy-chain applications, the bit time of the second stop bit may be less than specified to account for clock-rate

variation and sampling error between devices.

Note 15:

Fall time measured 90% to 10%; rise time measured 10% to 90%.

Note 16:

Charge-pump efficiency = ∆I

/∆I

, where I

is applied from HV to AGND; ∆I

= 5mA, and

LOAD

LOAD SUPPLY

LOAD

∆I

= I

(for I

= 5mA) - I

(for I

= 0).

SUPPLY

DCIN

LOAD

DCIN

LOAD

Note 17:

Differential signal (V

- V

) where V

and V

do not exceed a common-mode voltage range of ±25V.

RXP

RXN

RXP

RXN

Note SPI-1: Static logic inputs with V = GNDL2/GNDL3 and V = V

(Note 1). CSB = V (if pullup active).

IH

IL

IH

DDIO

Note SPI-2: No internal safety pullup/pulldown impedances active, input buffers only.

Note SPI-3: Internal safety pullup/pulldown impedances available with enable function.

Note SPI-4: If pulup is supported, note CSB connection and diode to V

; this diode is present regardless of enable mode.

DDL2

Note SPI-5: Applications must afford time for the device to drive data on the SDO bus and meet the µC setup time prior to the

µC latching in the result on the following SCLK rising edge. In practice, this can be determined by loading and µC

characteristics, and the relevant t

/t

.

DOT DOE

Note SPI-6: Minimum specification is 32 x T

and must account for the fastest possible frequency of the internal 16MHz

CP_MAX

oscillator (proposed numbers assume 5% variation over T ).

PV

Maxim Integrated │ 32

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Typical Operating Characteristics

(V

= 56V, V = 3.3V, T = +25°C, unless otherwise noted.)

AA A

DCIN

CELL ACCURACY

vs. INPUT VOLTAGE

VBLK ACCURACY

vs. INPUT VOLTAGE

toc02

toc01

110

88

2.0

1.5

66

1.0

44

0.5

22

0

0.0

-22

-44

-66

-88

-110

-0.5

-1.0

-1.5

-2.0

ALL CELL AVERAGE

OVSAMPL = 0x5

51

9

23

37

65

0

1

2

3

4

5

INPUT VOLTAGE (V)

SINGLE-CHANNEL BALANCING-SWITCH

RESISTANCE vs. BALANCING CURRENT

AUX ACCURACY

vs. INPUT VOLTAGE

toc04

toc03

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

5

4

T_A= +105⁰C

3

T_A= +25⁰C

T_A= -40⁰C

2

1

0

-1

-2

-3

-4

-5

AUXREFSEL = 0x0

OVSAMPL = 0x5

0

1

2

3

100

200

300

400

INPUT VOLTAGE (V)

BALANCING CURRENT (mA)

7 BALANCING SWITCHES ACTIVE,

300mA PERSWITCH

TEMPERATURE RISE

vs. BALANCING CURRENT

toc06

toc05

30

25

20

15

10

5

V_DCIN= 56V

EVEN BALSW ENABLED

0

50

100

150

200

250

300

BALANCING CURRENT(mA)

Maxim Integrated │ 33

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Typical Operating Characteristics (continued)

(V

= 56V, V = 3.3V, T = +25°C, unless otherwise noted.)

AA A

DCIN

DIE TEMP ERROR

vs. AMBIENT TEMP

CELL LEAKAGE

vs. TEMPERATURE

toc07

toc08

5

4

100

80

3

60

2

40

1

20

0

-1

-2

-3

-4

-5

-20

-40

-60

-80

-100

DIAGSEL1/2 = 0x1

OVSAMPL = 0x5

-40

-20

0

20

40

60 80

100

-40 -20

0

20

40

60

80 100 120

TEMPERATURE (°C)

AUX LEAKAGE

vs. TEMPERATURE

V_AALOAD REGULATION

toc10

toc09

3.30

3.29

3.28

3.27

3.26

3.25

3.24

3.23

100

80

60

40

20

0

-20

-40

-60

-80

-100

0

10

20

30

40

-40 -20

0

20

40

60

80 100 120

I_VAA(mA)

TEMPERATURE (°C)

CHARGE PER PREAMBLE BYTE

KEEP-ALIVE OPERATION

toc11

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

UART = 500Kbps

UART = 1Mbps

UART = 2Mbps

3.0

3.1

3.2

3.3

3.4

V_AA(V)

Maxim Integrated │ 34

www.maximintegrated.com

MAX17853

Pin Conﬁguration

TOP VIEW

14-Channel High-Voltage Data-Acquisition System

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

SHDNL

AGND

1

2

3

4

5

6

7

8

9

48 C9

47 SW8

46 C8

V

AA

UARTSEL

45 SW7

44 C7

V

DDL1

GNDL1

ALERTIN

43 SW6

42 C6

GNDL3

41 SW5

MAX17853

TXUN/SCLK

40 C5

TXUP/CSB 10

11

39 SW4

38 C4

V

DDL3

RXUN 12

RXUP 13

37 SW3

36 C3

GNDL2 14

35 SW2

34 C2

TXLP/SDO 15

TXLN/SDI 16

33 SW1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Maxim Integrated │ 35

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Pin Description

REF

SUPPLY

NAME

FUNCTION

TYPE

Shutdown Active-Low Input. Drive > 1.8V to enable operation and drive < 0.6V to reset

device and place in shutdown mode. +72V tolerant.

UART Operation: If not driven externally, this input can be controlled solely through

UART communication and software control. Bypass with a 1nF capacitor to AGND. For

single-ended UART, SHDNL must be driven externally.

1

SHDNL

AGND

Input

SPI Operation: SHDNL must be driven external

2, 28

3

Analog Ground. Connect to negative terminal of cell 1 and ground plane.

DCIN

Ground

Power

V

Output Used to Supply V

, and optionally V

and V

. Bypass with a

DDL3

AA

DDL1

DDL2

V

AGND

AA

1µF capacitor to AGND.

UART/SPI Interface Selection. Connect to V for UART interface, pull to AGND for

AA

SPI interface.

4

5

UARTSEL

V

Input

DDL1

3.3V Digital Supply. Connect externally to V and bypass with 0.47µF capacitor to

AA

GNDL1.

V

GNDL1

Power

DDL1

6

7

8

GNDL1

ALERTIN

GNDL3

Digital Ground. Connect to ground plane.

V

Ground

Input

DDL1

Fault Alert Input. Connect to upper daisy-chain device.

Ground for Upper-Port Transmitter. Connect to ground plane.

Negative Output for Upper-UART Transmitter or SCLK Input for SPI Interface

V

AA

V

Ground

DDL3

Output/

Input

9

TXUN/SCLK

TXUP/CSB

V

DDL3

Depending on the UARTSEL Selection. Driven between V

and GNDL3.

DDL3

Positive Output for Upper-UART Transmitter or CSB Input for SPI Interface Depending

on UARTSEL Selection. Driven between V and GNDL3.

Output/

Input

10

DDL3

Supply for Upper-UART Transceiver, SPI Multifunctional Pins, and ALERT Pins.

Connect externally to VDDL2 and bypass with 0.47µF capacitor to GNDL3. V

11

12

13

V

GNDL3

Power

Input

DDL3

must be ≥ V

AA

Negative Input for Upper-UART Port Receiver. If not used, pins can be unconnected

or connected to GNDL3. Tolerates ±30V.

RXUN

RXUP

V

AA

Positive Input for Upper-UART Port Receiver. If not used, pins can be left unconnected

or connected to GNDL3. Tolerates ±30V. If conﬁgured for single-ended UART,

connect to GNDL3.

14

15

GNDL2

Ground for Lower-Port Transmitter. Connect to ground plane.

V

Ground

Output

DDL2

Positive Output for Lower-UART Transmitter or SDO Output (MISO) for SPI Interface

TXLP/SDO

V

Depending on UARTSEL Selection. Driven between V

and GNDL2.

DDL2

Negative Output for Lower-UART Transmitter or SDI (MOSI) Input for SPI Interface

Depending on UARTSEL Selection. Driven between V and GNDL2.

Output/

Input

16

17

TXLN/SDI

RXLP

DDL2

Positive Input for Lower-UART Port Receiver. If not used pins can be left unconnected

or connected to GNDL3. Tolerates ±30V. If conﬁgured for single-ended UART, connect

to GNDL3.

V

Input

AA

Negative Input for Lower-UART Port Receiver. If not used, pins can be unconnected or

connected to GNDL2. Tolerates ±30V.

18

19

RXLN

Input

Supply for Lower-UART Transceiver, SPI Multifunctional Pins, and ALERT Pins. Connect

GNDL2

Power

V

DDL2

externally to V

and bypass with 0.47µF capacitor to GNDL2. V

must be ≥ V

.

DDL3

DDL2

AA

Alert Output Interface. Conﬁgured using SPIDRVINT bit as daisy-chained CMOS output

ALERTOUT (connected to ALERTIN), or open-drain output (connected to external 10kΩ pullup to

, V ).

20

V

Output

DDL2

V

DDL2 DDL3

Maxim Integrated │ 36

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Pin Description (continued)

REF

SUPPLY

NAME

FUNCTION

TYPE

Conﬁgurable Between Auxiliary Input or General-Purpose I/O.

When conﬁgured as a ratiometric auxiliary input for temperature measurement, connect

to a voltage-divider consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to

AGND.

AUXIN0/

GPIO0

Input/

Output

21

V

DDL2

If not used, connect to the pullup only.

When conﬁgured to GPIO, it is driven between V

2MΩ internal pulldown when the pin is conﬁgured as an input.

and GNDL2.

DDL2

Conﬁgurable Between Auxiliary Input or General-Purpose I/O.

When conﬁgured as a ratiometric auxiliary input for temperature measurement, connect

to a voltage-divider consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to

AGND.

AUXIN1/

GPIO1

Input/

Output

22

23

If not used, connect to the pullup only.

When conﬁgured to GPIO, it is driven between V

2MΩ internal pulldown when the pin is conﬁgured as an input.

and GNDL2.

DDL2

Conﬁgurable Between Auxiliary Input or General-Purpose I/O.

When conﬁgured as a ratiometric auxiliary input for temperature measurement, connect

to a voltage-divider consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to

AGND.

AUXIN2/

GPIO2

Input/

Output

If not used, connect to the pullup only.

When conﬁgured to GPIO, it is driven between V

2MΩ internal pulldown when the pin is conﬁgured as an input.

and GNDL2.

DDL2

Conﬁgurable Between Auxiliary Input or General-Purpose I/O.

When conﬁgured as a ratiometric auxiliary input for temperature measurement, connect

to a voltage-divider consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to

AGND.

AUXIN3/

GPIO3

Input/

Output

24

25

26

If not used, connect to the pullup only.

When conﬁgured to GPIO, it is driven between V

pulldown when the pin is conﬁgured as input.

and GNDL2. 2MΩ internal

DDL2

AUXGND

Connect to AGND ground plane

V

Power

AA

Conﬁgurable Between Auxiliary Input or General-Purpose I/O.

When conﬁgured as a ratiometric auxiliary input for temperature measurement, connect

to a voltage-divider consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to

AGND.

AUXIN4/

GPIO4

Input/

Output

V

DDL2

If not used, connect to the pullup only.

When conﬁgured to GPIO, it is driven between V

pulldown when the pin is conﬁgured as input.

and GNDL2. 2MΩ internal

DDL2

Conﬁgurable Between Auxiliary Input or General-Purpose I/O.

When conﬁgured as a ratiometric auxiliary input for temperature measurement, connect

to a voltage-divider consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to

AGND.

AUXIN5/

GPIO5

Input/

Output

27

V

If not used, connect to the pullup only.

When conﬁgured to GPIO, it is driven between V

pulldown when the pin is conﬁgured as input.

and GNDL2. 2MΩ internal

DDL2

Switched Output Connected Internally to V . THRM is used to drive the external NTC

AA

29

30

THRM

C0

voltage-divider for the auxiliary inputs. The output is enabled only during measurements AUXGND Power

or as conﬁgured by THRMMODE[1:0]. This output can source up to 2mA.

Voltage Input for Cell 1 Negative. Connect to AGND.

—

Input

Maxim Integrated │ 37

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Pin Description (continued)

REF

SUPPLY

NAME

FUNCTION

TYPE

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

SW0

C1

Balance Input for Cell 1 Negative

—

Input

Voltage Input for Cell 1 Positive (Cell 2 Negative)

Balance Input for Cell 1 Positive (Cell 2 Negative)

Voltage Input for Cell 2 Positive (Cell 3 Negative)

Balance Input for Cell 2 Positive (Cell 3 Negative)

Voltage Input for Cell 3 Positive (Cell 4 Negative)

Balance Input for Cell 3 Positive (Cell 4 Negative)

Voltage Input for Cell 4 Positive (Cell 5 Negative)

Balance Input for Cell 4 Positive (Cell 5 Negative)

Voltage Input for Cell 5 Positive (Cell 6 Negative)

Balance Input for Cell 5 Positive (Cell 6 Negative)

Voltage Input for Cell 6 Positive (Cell 7 Negative)

Balance Input for Cell 6 Positive (Cell 7 Negative)

Voltage Input for Cell 7 Positive (Cell 8 Negative)

Balance Input for Cell 7 Positive (Cell 8 Negative)

Voltage Input for Cell 8 Positive (Cell 9 Negative)

Balance Input for Cell 8 Positive (Cell 9 Negative)

Voltage Input for Cell 9 Positive (Cell 10 Negative)

Balance Input for Cell 9 Positive (Cell 10 Negative)

Voltage Input for Cell 10 Positive (Cell 11 Negative)

Balance Input for Cell 10 Positive (Cell 11 Negative)

Voltage Input for Cell 11 Positive (Cell 12 Negative)

Balance Input for Cell 11 Positive (Cell 12 Negative)

Voltage Input for Cell 12 Positive (Cell 13 Negative)

Balance Input for Cell 12 Positive (Cell 13 Negative)

Voltage Input for Cell 13 Positive (Cell 14 Negative)

Balance Input for Cell 13 Positive (Cell 14 Negative)

Voltage Input for Cell 14 Positive

—

SW1

C2

—

SW2

C3

—

SW3

C4

—

SW4

C5

—

SW5

C6

—

SW6

C7

—

SW7

C8

—

SW8

C9

—

SW9

C10

SW10

C11

—

SW11

C12

SW12

C13

SW13

C14

SW14

VBLK

—

Balance Input for Cell 14 Positive

—

Block Voltage Positive Input. Internal pulldown resistor of R

.

DCIN

VBLK

DC Supply for the Low-Voltage Regulator, HV Charge Pump, and SHDNL Charge

Pump. Connect to a voltage source between 9V and 65V through a 100Ω series

resistor. Bypass with a 100V, 2.2μF capacitor to ground.

61

DCIN

—

Power

62

63

CPN

CPP

Negative Capacitor Connection for the HV Charge Pump

—

Power

Positive Capacitor Connection for the HV Charge Pump. Connect a 100V, 0.1µF

capacitor from CPP to CPN.

Decoupling Capacitor Connection for the HV Charge Pump. Bypass with a 50V, 4.7µF

capacitor to DCIN.

64

HV

—

Power

Maxim Integrated │ 38

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Detailed Description

The data-acquisition system consists of the major blocks shown in Figure 1 and described in Table 1.

Table 1. System Blocks

BLOCK

DESCRIPTION

Analog-to-digital converter. Uses a 12-bit successive-approximation register (SAR) with a reference

ADC

voltage of 2.307V and is supplied by V

.

AA

HVMUX

14-channel high-voltage (65V) diﬀerential multiplexer for the C0–C14 inputs.

High-voltage charge-pump supply for the HVMUX, ALTMUX, BALSW, and LSAMP circuits that must

switch high-voltage signals. Supplied by DCIN.

HV CHARGE PUMP

Level-shifting ampliﬁer with a gain of 6/13. The result is a 5V diﬀerential signal attenuated to 2.307V,

which is the reference voltage for the ADC.

LSAMP1

LVMUX

Multiplexes various low-voltage signals including the level-shifted signals and temperature signals to

the ADC for subsequent A-to-D conversion.

ALTMUX

BALSW

12-channel, high-voltage diﬀerential multiplexer for the SW0–SW14 inputs.

Cell-balancing switches.

LINREG

3.3V (V ) linear regulator used to power the ADC and digital logic. Supplied by DCIN.

AA

REF

2.307V precision reference voltage for ADC and LINREG. Temperature-compensated.

1.242V precision reference voltage used for diagnostics.

ALTREF

16MHz OSC

32kHz OSC

16MHz oscillator with 2% accuracy for clocking state machines and UART timing.

32,768Hz oscillator for driving charge pumps and timers.

Diﬀerential UART for communication with host or down-stack devices. Autodetects baud rates of

0.5Mbps, 1Mbps, or 2Mbps.

LOWER PORT

UPPER PORT

Diﬀerential UART for communication with up-stack devices.

CONTROL AND STATUS ALUs, control logic, and data registers.

DIE TEMP

A proportional-to-absolute-temperature (PTAT) voltage source used to measure the die temperature.

COMPARATOR

A comparator path to detect OV/UV for cell voltage and AUXIN.

Level-shifting ampliﬁer with a gain of 1. The result is a 5V diﬀerential signal that is compared against

programmable OV and UV DAC thresholds.

LSAMP2

SPI INTERFACE

SPI interface for communication with host.

Maxim Integrated │ 39

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Block Diagrams

DCIN

VAA

16MHZ

OSC

32kHZ

OSC

LINEAR

REGULATOR

+3.3V

THRM

VBLK

HV CHARGE

PUMP

RXUP

RXUN

POR

HV

DIE

TEMPERATURE

C14

C13

ALTVREF

1.23V

VBLKP

VREF 2.307V

UART UP

PATH

C12

C11

VAA

VREF

C10

C9

TXUP

TXUN

CELL

CALIBRATION

C8

LSAMP1

ADC CONFIGURATION/ DATA

REGISTERS

C7

ADC

C6

RXLP (SCLK)

RXLN (CS)

C5

C4

C3

C2

AUX

CALIBRATION

C1

C0

UART DOWN

PATH

TXLP (SDO)

TXLN (SDI)

AUXIN5/GPIO5

AUXIN4/GPIO4

AUXIN3/GPIO3

AUXIN2/GPIO2

AUXIN1/GPIO1

AUXIN0/GPIO0

UARTSEL

PROGRAMMABLE

VOLTAGE REFERENCE

TXUN

(SCLK)

AUXIN/GPIO

MUX

COMP

TXUP

(CSB)

LSAMP2

COMP CONFIGURATION/DATA

REGISTERS

SPI

TXLP

(SDO)

GPIO CONTROL

TXLN

(SDI)

FAULT DETECTION

SUPPORT CIRCUITRY

ALTMUX

HV

ALERTIN

ALERT

CELL BALANCING

ALERTOUT

AGND

Figure 1. MAX17853 Functional Block Diagram

Maxim Integrated │ 40

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Block Diagrams (continued)

HV

CPP

ESD DIODES

DCIN

SHDNL, CPN

V

AA

THRM

RXUn

SW14

SW13

V

DDL3

TXUP, TXUN

GNDL3

SW2 TO SW12

MATCH OTHER

SWn INPUT

STRUCTURES

RXLn

SW1

V

DDL2

GPIOn/AUXINn

TXLP, TXLN

GNDL2

SW0

Cn, VBLK

C1 THRU C13

HAVE

IDENTICAL

STRUCTURES

V

DDL1

GNDL1

AGND

AUXGND

Figure 2. MAX17853 ESD Diodes

Notes:

1) All diodes are rated for ESD-clamping conditions; they are not intended to accurately clamp DC voltages.

2) All diodes have a parasitic diode from AGND to their cathode that is omitted for clarity. These parasitic diodes have

their anode at AGND.

Maxim Integrated │ 41

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Block Diagrams (continued)

VBLK/28.25

VBLK

HVMUX

INPUT TEST SOURCE

CTST14

AGND

C14

C13

C12

ALTREF

REF

CTST13

CTST12

C11

C10

CTST11

CTST10

CTST9

CTST8

CTST7

CTST6

CTST5

CTST4

CTST3

CTST2

CTST1

CTST0

C9

C8

C7

+

CELL CAL

LSAMP1

C6

C5

NETWORK

VAA

-

THRM

REF

C4

C3

C2

AUXIN CAL

NETWORK

ADC IN +

ADC IN -

LV

MUX

C1

C0

ADC

VAA

DIE TEMPERATURE

AGND

HVMUX TEST SOURCES

AUXTST5

AUXTST4

GPIO4

AUXIN5

AUXIN4

AUXTST3

AUXTST2

GPIO3

GPIO2

AUXIN3

AUXIN2

AUXTST1

AUXTST0

GPIO1

GPIO0

AUXIN1

THRM

REF

AUXIN0

+

-

LSAMP2

DAC

AUXGND

COMPARATOR

Figure 3. MAX17853 Analog Front-End

Maxim Integrated │ 42

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Terms, Deﬁnitions, and Data Conventions

Data Acquisition

Data acquisition is composed of the distinct processes

defined in Table 2 and controlled by various configuration

registers described in this section.

Factory Trimming

The acquisition system is trimmed at the factory. The

trim parameters are stored in a ROM consisting of 11

read-only registers (OTP2–OTP12). ROMCRC is an 8-bit

CRC value based on the calibration ROM and is stored

in OTP12[15:8] at the factory. ROMCRC can be used

to check the integrity of the trim, as described in the

Diagnostics section.

Configuration changes should be made prior to the acqui-

sition in which the changes are to be effected.

Data Conventions

The factory trim can be further supplemented with a user

on-demand calibration when used in a specific customer

application.

Representation of data follows the conventions shown in

Table 3. All registers are 16-bit words.

Table 2. Data-Acquisition Process

PROCESS

DESCRIPTION

Conversion

Scan

The ADC samples a single input channel, converts it into a 12-bit binary value, and stores it in an ALU register.

The ADC sequentially performs conversions on all enabled cell-input channels.

The ADC performs two scans for the purpose of minimizing errors in uncalibrated conﬁgurations. The conver-

sions (two for each input channel) are averaged together to form a single 14-bit binary value called a measure-

ment or sample.

Measurement

Cycle or Sample

If oversampling is enabled, the ADC takes sequential measurements and averages them together to form one

14-bit binary value for each input channel sampled. If there is no oversampling, the acquisition is essentially a

single measurement cycle.

Acquisition or

Acquisition Mode

The measurement and correction factor applied to a measurement cycle or sample based on current operating

conditions.

Calibration can be applied to a single scan in addition to the two-scan process to minimize errors in the same

fashion as a measurement cycle or sample

Calibration

Note: A single scan should not be implement without a valid calibration for the accuracy requirements deﬁned

in the Electrical Characteristics section.

Table 3. Numeric Conventions

DESCRIPTION

Binary number

CONVENTION

0b preﬁx

EXAMPLE

0b01100001 = 61h

0x61

Hexadecimal address

Hexadecimal data

Decimal data

0x preﬁx

h suﬃx

61h

d suﬃx

61d

Register bitﬁeld

Register name [x]

Field name [x:y]

Register name:bitﬁeld

{xxxx, yyyy}

STATUS15 = 1

DA[4:0] = 0b01100 = 0Ch = 12d

ADDRESS:DA

{DA[4:0], 0b001} = 61h

Register ﬁeld

Register ﬁeld and bitﬁeld

Concatenated numbers

Maxim Integrated │ 43

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

disables the flexible battery-pack configuration. Prior to

Factory-Programmed Device ID

SDHNL being actively controlled, the DCIN voltage is

driven towards HV and clamped at the highest voltage

applied at the SW8–SW14 inputs. When SHDNL is assert-

ed, DCIN is driven to within 1V below the highest stacked

cell, if no external DCIN is provided. In this case, the host

must define the TOPCELL1[3:0] and TOPCELL2[3:0]

of the stack by writing to the PACKCFG register and

by asserting the FLXPCKEN1 and FLXPCKEN2 bits.

TOPCELL_[3:0] selection configures the top-cell position

if less than 14 channels are used. TOPCELL_[3:0] selec-

tions 0x0–0x7 and 0xF are not supported and are mapped

to an OFF position (power-on default).

The ID1 register together with ID2 provides a 32-bit

manufacturing identification number, DEVID[31:0]. This

ID will be unique among all devices with the same model

type and version (VERSION:MOD,VER, respectively);

taken together, VERSION, ID1, and ID2 provide a means

to uniquely identify all devices shipped by the factory.

Although not required, the manufacturing date informa-

tion provided on the package provides further means of

device tracking. A device ID of zero is invalid.

Introduction

The MAX17853 is a software-configured ASIL D data-

acquisition system for both high-voltage- and low-voltage

(48V)-rated applications, supporting a flexible configura-

tion of cell-voltage measurements, pack-voltage measure-

ments, temperature measurements, and auxiliary-voltage

measurements. All measurements are synchronously sam-

pled within an acquisition and have minimal delay between

acquired samples. Additional programmability is available

for balancing currents, as well as system-interconnect

measurements (bus bars) to provide a complete measure-

ment solution independent of hardware configuration.

If FLXPACKEN1/2 is unintentionally deasserted while the

SHDNL is driven high with no external DCIN connection,

it is expected that voltage seen at the DCIN pin will fall at

a rate proportional to the current consumption of the part

and the external decoupling capacitance, until the POR

threshold is reached. This resets the digital logic and

returns the FLXPCKEN return to the desired power-on

reset state.

If FLEXPCKEN1 and FLEXPCKEN2, or TOPCELL1 and

TOPCELL2 are not the same, the power-on default values

will be applied.

The following sections describe device operation, feature

set, and programming of the MAX17853.

Note: It is important that TOPCELL1 and TOPCELL2

select the highest applied cell input, as an invalid configu-

ration can create an internal path that would connect the

highest battery voltage to the selected TOPCELL1/2 input.

Flexible Battery-Pack Conﬁguration

The main supply voltage (DCIN) can be routed internally

using the SW8–SW14 inputs of the highest stacked cell.

This allows for a single hardware configuration to serve

multiple battery modules without requiring external hard-

ware or wiring-harness changes.

A second mux internally connects VBLK to a selected

cell input after the host defines the TOPCELL_[3:0] of the

stack and asserts the FLXPCKEN_ bit. TOPBLOCK[3:0]

selects the Cn pin to be connected to the VBLOCK

resistive divider. 0xF (default) selects the VBLK pin.

TOPBLOCK_ selections 0x0–0x7 are not supported and

will be mapped to 0xF (VBLK, default).

The flexible battery-pack configuration is enabled by

default using the FLXPACKEN1/2 bit, to allow for internal

powering conditions. If this configuration is not required,

the DCIN can still be driven externally, which effectively

Maxim Integrated │ 44

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

HV

C17

4.7uF

R15

100Ω

DCIN

R14

100Ω

C17

2.2uF

VBLK

C14

R14

1kΩ

C17

0.47uF

R14

1kΩ

C14

100nF

R34

22Ω

SW14

C13

R13

1kΩ

C13

100nF

R33

22Ω

SW13

C12

R12

1kΩ

C12

100nF

R32

CELL 12

CELL 11

CELL 10

CELL 9

CELL 8

CELL 7

CELL 6

CELL 5

CELL 4

CELL 3

CELL 2

CELL 1

22Ω

SW12

C11

C26

100nF

R11

1kΩ

C11

100nF

R31

22Ω

SW11

C10

C25

100nF

R10

1kΩ

C10

100nF

R30

22Ω

SW10

C9

C24

100nF

R9

1kΩ

C9

100nF

R29

22Ω

SW9

C8

C23

100nF

R8

1kΩ

C8

100nF

R28

22Ω

SW8

C7

C22

100nF

R7

1kΩ

C7

100nF

R27

22Ω

SW7

C6

C21

100nF

R6

1kΩ

C6

100nF

R26

22Ω

SW6

C5

C20

100nF

R5

1kΩ

C5

100nF

R25

22Ω

SW5

C4

C19

100nF

R4

1kΩ

C4

100nF

R24

22Ω

SW4

C3

C18

100nF

R3

1kΩ

C3

100nF

R23

22Ω

SW3

C2

C17

100nF

R2

1kΩ

C2

100nF

R22

22Ω

SW2

C1

C16

100nF

R1

1kΩ

C1

100nF

R21

22Ω

SW1

C0

C15

100nF

R0

1kΩ

C0

100nF

R20

22Ω

SW0

C14

1uF

AGND

Figure 4. Flexible-Pack Configuration for 12-Cell Pack on 14-Channel CMC

Maxim Integrated │ 45

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the internal power multiplexing is configured. This configu-

ration creates a voltage drop in the DCIN supply equivalent

to a cell voltage that can result in large measurement errors

of the top-cell reading with both the HVMUX and ALTMUX

configured.

Flexible-Pack Interaction with Acquisitions

If FLXPACKEN1/2 and FLXPCKSCAN are asserted, the

switch input denoted in the TOPCELL1 and TOPCELL2

bitfields is disconnected from DCIN and the internal

power consumption will be supplied by the external

decoupling/hold-up capacitance on the DCIN pin. A 30µs

delay will be inserted prior to the TOPCELL conversion,

allowing the external switch-filter network to settle before

converting the input voltage.

TOPCELL_[3:0] and FLXPCKEN_ must refer to the top

cell in the pack and not a bus bar, if the top-used channel

in the pack is a bus bar. TOPBLOCK_ can refer to cells

above TOPCELL_.

Note: FLXPCKSCAN only affects ALTMUX acquisitions.

If the ALTMUX accuracy is not required for the applica-

tion, no changes are required to the application circuit

regardless of the FLXPCKSCAN setting. It is however,

recommended to set FLXPCKSCAN=0 to ensure the

quickest sampling rate is achieved.

Flexible Pack Alert

An ALRTDCINMUX is triggered to indicate a fault in the

DCINMUX switch. A high condition indicates the enabled

DCINMUX is not functioning properly in a Flex Pack appli-

cation. Performance may be impacted, and/or other relat-

ed faults may be issued. The ALRTDCINMUX is gated

until clear of ALRTRST after power-up has occurred.

Power-Multiplexing Operation (Cell Balancing)

The top two balancing switches should not be configured

simultaneously while in manual Cell-Balancing mode when

HV

HOT PLUG

(SW PINS

CONNECTED TO

BATTERY STACK)

HVCP TURNS ON

SW_TOPCELL1/2

HV (SW_TOP – 1V)

DCIN

SW(TOPCELL1/2) ENABLED

SHDNL

V

AA

FLXPACKEN1/2

USER WRITE TO SET TOPCELL1/2

TOPCELL[3:0]

0B0000

Figure 5. Flexible-Pack Power-On Timing

Maxim Integrated │ 46

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

filter. Due to the parallelism of the external filter network,

as well as the internal block structures, the ALTMUX

path selection also allows for independent measurement

redundancy improving safety performance and device

robustness.

Cell Inputs

Up to 14 voltage measurements can be sampled dif-

ferentially from the 15 cell inputs. The differential signal

V

is defined as V - V

where n = 1 to 14.

CELLn

Cn

Cn-1

The cell inputs are selected by the corresponding CELLEN

bits in the MEASUREEN1 register. Additionally, the input

path for the measurement acquisition is selected using

SCANCTRL:ALTMUXSEL. The ALTMUXSEL bit allows

for two different measurement configurations: HVMUX

and ALTMUX acquisitions. The HVMUX path selection is

used for the primary measurement acquisition due to the

higher filtering achieved by the external input network.

Alternatively, the ALTMUX path selection is primarily used

for cell balancing and typically does not have a large RC

During the scan, the selected signal is multiplexed into the

level-shifting amplifier (LSAMP1 or LSAMP2) as shown

in Figure 6. Since the common-mode range of the input

signals is 0V to 65V, the signal must be level-shifted to

the common-mode range of the amplifier. Both ADC and

comparator signal paths have a gain of 6/13 so that a 5V

differential signal is attenuated to the ADC and Comparator

full-scale reference voltage (V

).

REF

R

FILTER

C14

C13

+

LSAMP1

-

TO ADC

R

FILTER

C2

C1

R

FILT

C0

R

BALANCE

SW14

SW13

+

LSAMP2

-

TO COMP

R

BALANCE

SW2

SW1

R

BALANCE

R

SW0

Figure 6. Cell Signal Path

Maxim Integrated │ 47

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Once the signal is properly conditioned, the ADC starts

the conversion. The 12-bit conversion is stored in an

ALU register where it can be averaged with subsequent

conversions for increased resolution. The ALU output is a

14-bit value, relating to a 305μV voltage resolution, and is

ultimately stored in a 16-bit register, CELLnREG, with the

two least-significant bits 0. Disabled channels maintain

their previous measurement result. Unless stated other-

wise, measurement values are assumed to be 14-bit val-

ues. The 16-bit register values can be converted to 14-bit

values by dividing by 4 (and vice-versa). To convert the

measurement value in register CELLnREG to a voltage,

convert the 14-bit hexadecimal value to a decimal value

and then convert to voltage as follows:

Bus-Bar Inputs

Bus-bar inputs can be applied to any of the 14 cell inputs.

Due to the resistive nature of the bus bar, the current

applied to the battery pack or discharged from the battery

pack affect the polarity of the voltage measurement. To

support this requirement, the POLARITY bits correspond-

ing to the bus-bar location must be configured for bipolar

conversion (POLARITY[n] = 1b).

Due to the negative voltage that can be generated across

the bus bars SW to SW

inputs, it is recommended to

n

n-1

place an external Schottky diode in across these inputs to

the reverse voltage see by the body diode of the internal

balancing switch as shown below to shunt current away

from the internal conduction path.

V

= CELLnREG[15:2] x 5 V/16384 =

CELLn

CELLnREG[15:2] x 305.176µV

TO CELL

N+1

MAX1785x

SENSE WIRE

R

C

N

FILTER

TO

HVMUX

C

FILTER

R

SW

N

BIAS

TO

ALTMUX

HV

BALSW

N

R_BUSBAR

R

SW

N-1

BIAS

TO

ALTMUX

SENSE WIRE

R

C

N-1

FILTER

TO

HVMUX

C

FILTER

AGND

TO CELL

N-1

Figure 7. Bus-Bar Switch Configuration

Maxim Integrated │ 48

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Auxiliary Inputs: Ratiometric Temperature

Measurement

Block-Voltage Input

The VBLK input pin to the MAX17853 allows for the pack

voltage (total cell voltage) to be measured independently

of summing the individual cell voltages from an acquisi-

tion. This comparison provides an extra layer of measure-

ment redundancy within the system.

Individual auxiliary ports can be configured to measure

external temperatures through enabling auxiliary mea-

surements using the AUXEN bits in the MEASUREEN2

register as well as configuring the conversion voltage

as ratiometric using the AUXREFSEL bits in the

AUXREFCTRL register.

The VBLK voltage is attenuated by a voltage-divider of

28.17 for the acquisition process to translate the 65V

full-scale block input voltage into the full-scale ADC input

Note: If the individual auxiliary port is configured as a

GPIO using GPIOEN bits in the AUXGPIOCFG register

while the corresponding AUXEN bit is high, then the aux-

iliary setting be ignored and the port be configured as a

GPIO.

voltage (V

)

REF

Outside of the acquisition the VBLK input path is opened to

avoid power consumption from the internal 10MΩ divider.

The measurement is enabled in a an acquisition by

asserting BLOCKEN in MEASUREEN1 register. The

measurement is stored in the VBLOCK[13:0] bits of the

BLOCKREG register where each bit has a resolution of

3.967mV.

The ratiometric configuration selects the conversion volt-

age of both the ADC and Comparator to V

while also

AA,

outputting V

on the THRM pin. An external resistive

AA

divider can then be created with a pullup resistor to the

THRM pin and a NTC connected to the AUXGND pin as

shown in Figure 9:

Auxiliary Inputs

The MAX17853 has 6 auxiliary ports that can be used to

measure external temperatures, measure external voltag-

es, or that can be re-purposed for digital functions (GPIO).

V

REF

VBLK

C14

THRM

C8

10.5MΩ

ADC IN +

VBLK/28.17

L

V

M

U

X

ADC

ADC IN -

385kΩ

AGND

Figure 8. Block-Measurement Path

Maxim Integrated │ 49

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

THRM

THERMISTOR

WIRE

HARNESS

10kΩ

NTC

THERMISTORS

R

AUX_FILTER

AUXINn

R

AUX_FILTER

AUXIN1

AUXIN0

T

C

AUX_FILTER

THRM

AUX_FILTER

R

THn

TH0

TH1

AUXGND

Figure 9. Auxiliary Application Circuit

V

AA

AUXREFSEL

THRMMODE

AUXREFSEL=0

THRM

AUXREFSEL=1

V

REF

AUXIN0

AUXIN1

ADC

REFERENCE

INPUT

ADC IN

LV

MUX

ADC

AUXINn

AUXGND

AUXDIAGSEL

AGND

Figure 10. Auxiliary-Temperature Measurements

Maxim Integrated │ 50

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Explicit control on the THRM pin output is provided using

the THRMMODE bits in the ACQCFG register. Setting

THRMMODE to 00b or 01b enables automatic mode

where the THRM switch be closed at the beginning of an

acquisition. Setting THRMMODE = 11b enables manual

mode where the THRM switch is always closed. The abil-

ity to configure THRMMODE allows for the application

tradeoffs between the external NTC network's power con-

to the first AUXINn measurement. For an acquisition with

nondeterministic scan rates the AUXTIME be allowed to

settle through the cell, block, and diagnostic measurement

intervals of the first scan. However, for acquisitions requir-

ing deterministic timing, such as 50Hz/100Hz rejection and

60Hz/120Hz rejection, the AUXTIME be applied prior to

the beginning of the acquisiton. Refer to the Oversampling

section for further details on FOSR and deterministic

acquisitions.

sumption on V and the need to settle the external NTC

AA

network to achieve the highest accuracy measurements.

The auxiliary measurements are oversampled to 14-bit

values using the OVSAMPL bits in the SCANCTRL

register and the output of each auxiliary measurement

is stored in the corresponding AUX0 to AUX6 registers.

Refer to the Oversampling section and ADC, Comparator,

and ADC+COMP Acquisitions sections for further details.

Depending on the external temperature network, there

may be insufficient settling time to provide accurate mea-

surements. To support the flexibility for different networks,

the AUXTIME bits in the AUXTIMEREG register may be

configured to impose a fixed delay of 0ms to 6.14ms prior

Table 4. THRM Output

MODE

THRM MODE

DESCRIPTION

00b

01b

10b

11b

THRM outputs V (dynamically enabled at the beginning of the acquisition and

AA

disabled at the end of the acquisition)

Automatic

THRM output disabled (static)

Manual

THRM outputs V (static)

AA

Table 5. AUXTIME

ADDITIONAL SETTLING TIME PER ENABLED

AUXILIARY CHANNEL = (AUXTIME x 6µs)

AUXTIME[9:0]

0x000

0x001

0x002

…

0μs

6μs

12μs

…

0x3FF

6138μs

Maxim Integrated │ 51

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The resistance of an NTC thermistor increases as the

Ratiometric Auxiliary Input Range

temperature decreases and is typically specified by its

resistance R = 10kΩ at T = 25°C = 298.15K and a

material constant β (3400K typical). To the first order, the

Temperature measurements are converted ratiometrically

to eliminate error due to the biasing of the NTC network.

Thus, the conversion range is proportional to the VTHRM

0

resistance R at a temperature T in Kelvin can be com-

TH

(V ) reference as shown below.

AA

puted as follows:

Both ADC and comparator conversions use the same

reference during the conversion and thus have the same

input range; however, the resolution for both differ in

accordance with Table 6 and Table 7.











1

β×

−







T T



0 





R

= R × e

0

TH

Computing Temperature

As shown in Figure 9:

The temperature T of the thermistor (in °C) can then be

calculated as follows:

V

= V

x R /(10kΩ + R

)

TH

AUXINn

THRM

TH

This measurement is stored in the AUXn register. The

thermistor resistance can then be solved as follows:

T (in °C) = (β/(ln(R /10kΩ)

+(β/298.15K)) - 273.15K

TH

R

= (V

x 10kΩ)/(V

- V

)

TH

AUXINn

THRM

AUXINn

where V

= 3.3V (nom)

THRM

Table 6. Auxiliary-Temperature Input Range: ADC

AUXILIARY INPUT

AUXn

(14 BITS)

AUXNREG[15:0]

VOLTAGE

(16 BITS)

Ratiometric mode

0V

Hexadecimal

0000h

Decimal

0d

0000h

8000h

FFFCh

V

/2

2000h

8192d

16383d

AA

V

3FFFh

AA

Table 7. Auxiliary-Temperature Input Range: Comparator

COMPOVTH, COMPUVTH,

COMPAUXROVTH, COMPAUXRUVTH

COMPAUXAOTH, COMPAUXAUVTH (10 BITS)

COMPOVTHREG[15:0], COMPUVTHREG[15:0]

COMPAUXROVTHREG[15:0],

AUXILIARY INPUT

VOLTAGE

COMPAUXRUVTHREG[15:0]

COMPAUXAOTHREG[15:0],

COMPAUXAUVTHREG[15:0] (16 BITS)

Ratiometric mode

0V

Hexadecimal

Decimal

000h

200h

3FFh

0d

0000h

8000h

FFC0h

V

/2

512d

1024d

AA

V

AA

Maxim Integrated │ 52

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

will saturate and result in a loss of resolution. Both ADC

and comparator conversions use the the same reference

during the conversion but have different resolutions as

shown in Table 8 and Table 9.

Auxiliary Inputs: Absolute-Voltage Measurements

Individual auxiliary ports can be configured to measure

absolute voltages through enabling auxiliary measure-

ments using the AUXEN bits in the MEASUREEN2 register

as well as configuring the conversion voltage as absolute

using the AUXREFSEL bits in the AUXREFCTRL register.

Auxiliary Inputs: Mixed-Mode Measurements

Ratiometric measurements and absolute-voltage measure-

ments can both be performed during the same acquisition.

Each measurement type has individual OV and UV alert-

threshold settings, as described in the Measurement Alerts

section.

The absolute configuration selects the conversion voltage

of both the ADC and Comparator to V

An external

REF.

voltage can be accurately measured as long as the volt-

age remains below V . If higher voltages are required

REF

to be measured, a resistive divider must be used to

ensure that maximum auxiliary input does not exceed

Note: Auxiliary mixed-mode measurement data for the

ADC is output to the AUXn registers. The appropriate con-

version, as determined by the AUXREFSEL configuration,

must be applied to obtain correct voltage reading.

V

REF

; otherwise, the voltage measurements saturate

to full scale. Additionally, the user should be careful, so

if a single-point failure on the external network occurs,

the maximum auxiliary input doesn't exceed the absolute

maximum rating on the port.

Ratiometric-Voltage Conversion:

V

AUXn

= AUXn[14:0] x V /16384d = AUXn[14:0] x

AA

201.42μV, or alternatively AUXnREG[15:2] x 201.42μV

If all AUXREFSEL bits are set to 0b1 (using V

for the

REF

ADC reference), it is recommended that THRMMODE be

set to 0b10 (THRM switch always OFF).

where V is nominally 3.3V

AA

Absolute-Voltage Conversion:

Absolute Auxiliary Input Range

V

= AUXn[14:0] x V

/16384d = AUXn[14:0] x

AUXn

REF

Absolute voltage measurements are converted using a

140.81μV, or alternatively AUXnREG[15:2] x 140.81μV

fixed precision reference (V

). All voltages must meet

REF

the input-range requirements; otherwise, the digital output

Table 8. Auxiliary-Voltage Input Range: ADC

AUXILIARY-INPUT

AUXn

(14 BITS)

AUXNREG[15:0]

VOLTAGE

(16 BITS)

Absolute Mode

Hexadecimal

0000h

Decimal

0d

0V

0000h

8000h

FFFCh

V

2

2000h

8192d

16383d

REF/

V

3FFFh

REF

Table 9. Auxiliary-Voltage Input Range: Comparator

COMPOVTH, COMPUVTH,

COMPOVTHREG[15:0], COMPUVTHREG[15:0]

COMPAUXROVTHREG[15:0],

AUXILIARY-INPUT

COMPAUXROVTH, COMPAUXRUVTH

COMPAUXAOTH,COMPAUXAUVTH

(10 BITS)

VOLTAGE

COMPAUXRUVTHREG[15:0]

COMPAUXAOTHREG[15:0],

COMPAUXAUVTHREG[15:0] (16 BITS)

Absolute mode

Hexadecimal

000h

Decimal

0d

0V

0000h

8000h

FFC0h

V

/2

200h

512d

REF

V

3FFh

1024d

REF

Maxim Integrated │ 53

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Auxiliary-Input Protection

Table 10. GPIO/Auxiliary Enable Selection

The voltage on the AUXIN0–AUXIN5 pins should never

exceed V when configured as an auxiliary input.

GPIOEN

FUNCTION

Auxiliary Input

GPIO

AA

0

1

If this condition does occur, the affected input self-

protects, becoming an open circuit. The associated

ALRTAUXPRTCT bit will be set indicating the overvoltage

condition. To retry AUX operation and clear the fault con-

dition, the user must rewrite the desired configuration to

the AUXGPIOCFG register.

Table 11. GPIO Configuration

GPIOEN

GPIODIR

FUNCTION

Auxiliary Input

Digital Input

All six ALRTAUXPRTCT bits will be logically OR'd togeth-

er to form the ALRTAUXPRTCTSUM bit in the FMEA2

register.

0

1

x

0

1

Digital Output

GPIO Conﬁguration

Any of the six auxiliary ports can be configured as a

general-purpose input/output (GPIO) using the GPIOEN

bits in the AUXGPIOCFG register. When a GPIOEN bit

is high, the corresponding auxiliary port is configured as

a GPIO. When a GPIOEN bit is low, the corresponding

GPIO buffer is three-stated, and the pin is configured as

an auxiliary-voltage input.

Operational Modes

There are three different operational modes supported,

shutdown mode, standby mode, and acquisition mode.

Shutdown mode is controlled by the applied voltage

on the SHDNL pin. When the applied voltage is below

V

the device is in an ultra-low-power shutdown

IL_SHDNL

mode, and the various elements of the internal circuitry

are disabled. If the voltage is above V , the

In the GPIO configuration, the I/O status is determined by

the GPIODIR bits of the AUXGPIOCFG register. When a

GPIODIR bit is programmed to 0b0, the corresponding

port is configured as a digital input. The digital input has

a 2MΩ pulldown resistance to ensure the input does not

float and cause excessive power dissipation. When the

GPIODIR bit is programmed to 0b1, the pin is config-

ured as a digital output. Each GPIO port configured as a

digital output can be configured to drive a logic-high level

or logic-low level determined by the assignment in the

GPIODRV bits of the GPIOCFG register.

IH_SHDNL

device is in standby mode and act upon qualified interface

commands. The device remains in standby mode until the

user commands an acquisition, at which point the device

transitions into acquisition mode until completed, as sig-

naled by SCANDONE. Alternatively, the transition from

sleep mode to acquisition mode will be handled indepen-

dent of user interaction, only when long-term autonomous

cell balancing with voltage measurements are enabled

(see the Cell Balancing section for further information).

The sections that follow further detail the operational

modes and device interactions.

The GPIORD bits in the GPIOCFG register monitor the

pin logic level, regardless of whether the port is defined as

an input or an output. If a pin is configured as an auxiliary-

voltage input (GPIOEN=0b0), the corresponding GPIORD

bit always reads back 0b0.

Maxim Integrated │ 54

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

SHUTDOWN

MODE

SHDNL < V

OR

DEVICE POR

OR

IL_SHDNL

SHDNL > V

IH_SHDNL

THERMAL SHUTDOWN

SHDNL < V

OR

IL_SHDNL

DEVICE POR

OR

THERMAL SHUTDOWN

STANDBY

MODE

SCANDONE=1

OR

AUTO CELL

BALANCING

EVEN/ODD

SCAN =1

OR

AUTO CELL BALANCING

MEASUREMENT PHASE

ACQUISITION

MODE

Figure 11. Operational-Mode State Diagram

Note: When configured as a single-ended UART inter-

face, the SHDNL pin must be driven by an external con-

nection to a host controller. The power-on of the device

can then be controlled by the host driving the SHDNL pin

Power-On (Standby Mode)

The configuration of the communication interface, as

defined by the UARTSEL pin, determine the appropriate

method to transition the device from shutdown mode into

standby mode.

above the V

threshold.

IH_SHDNL

When configured as an SPI interface selection (UARTSEL

)

When configured as a differential UART interface

< V , the SHDNL input must be driven externally, as done

IL

(UARTSEL > V ), the SHNDL input can be driven exter-

IH

with the single-ended UART configuration. It is recom-

mended that the unused RXLP/RXLN and RXUP/RXUN

inputs should be pulled low to ensure that the charge pump

remains inactive and does not inadvertently contend with

the external driver.

nally above the V

threshold, or driven using inter-

IH_SHDNL

nal charge pumps on the UART RXLP/RXLN and RXUP/

RXUN inputs. If the SHDNL pin has no external connection

to a host controller, the device must rely on the UART inter-

face to drive the external network on the SHDNL pin. The

recommended configuration with a 1nF capacitor allows

the device to drive the SHDNL pin above V

200µs. The charge pump self-regulates to V

and can maintain V

UART idles 98% of the time. The internal charge-pump

operation requires a differential UART signal.

Once the V

threshold is reached, the LDO out-

IH_SHDNL

in

put is enabled and V output voltage begins to rise. At

IH_SHDNL

AA

3V (typ), the POR signal is deasserted and the oscillators

and HV charge pump enabled. Once the HV charge pump

is stable, the logic is enabled and the ALRTRST status

bit set. The device is fully operational (standby mode)

within 1ms from the time communication is first received

in shutdown mode. Figure 12 details the power-on state

transition.

SHDNLIMIT

at a logic one even with the

SHDNL

Maxim Integrated │ 55

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Shutdown-to-Standby State Diagram

REGULATOR

DISABLED

VOLTAGE APPLIED TO

DCIN

POR CLEARED

CHECK DIE

TEMPERATURE

32kHz OSCILLATOR

ENABLED

YES

DIE TEMP > 145ºC ?

NO

906µs

CHECK SHDNL

CHARGE PUMP AND

DIGITAL LOGIC

ENABLE

YES

SHDNL ACTIVE ?

NO

ALRTRST BIT SET

REGULATOR

ENABLED

3ms DELAY

CHECK V

AA

CHARGE PUMP

SETTLED

YES

V

< V

AA

POR_RISING

NO

DIE TEMP > 145ºC ?

SHDNL ACTIVE

REGULATOR

DISABLED

Figure 12. Power-On Sequence

Maxim Integrated │ 56

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the FORCEPOR bitfield can be utilized, which enables a

Shutdown Mode

4.7kΩ pulldown to create a 4.7µs time constant.

Shutdown mode is entered when SHDNL < V

.

IL_SHNDL

In shutdown, the low-voltage regulator and HV charge

pump are disabled as soon as the SHDNL pin goes low.

Note: When deciding on an external pulldown resistor

to control the shutdown time, attention should be paid

as this resistor creates a voltage-divider with the internal

Emergency-Discharge mode pullup resistance and could

force the device into shutdown unintentionally when

HOLDSHNDL is enabled. It is therefore recommended to

use a minimum 4.7kΩ resistor to avoid any interaction.

When the V and V

decoupling capacitors discharge

AA

DDL

below the POR threshold (2.95V, typ) the device registers

are reset. The device is then in an ultra-low-power state

until SHDNL is brought high. The control to enter this state

is achieved using separate methods depending on the

interface configuration which has been optimized for the

end application.

If only a register reset is required, the host can issue a

soft-reset by enabling the SWPOR bitfield. This resets

all non-interface-related device bitfields (UARTCFG,

TXUIDLEHIZ, TXLIDLEHIZ, ADAPTTXEN, UARTHOST,

SFTYCSB, SFTYSCLK, SFTYSDI, SPIDRVINT,

ALERTEN).

When the device is configured in UART communica-

tion (UARTSEL > V ), shutdown is enabled

IH_UARTSEL

by externally driving SHDNL low, stopping commanded

and keep-alive communication through the differential

UART, or commanding a register write to enable the

FORCEPOR bit. In the latter two conditions, the rate at

which shutdown mode is entered is controlled by the time

When the device is configured for SPI communication

(UARTSEL < V ), the recommended method

IL_UARTSEL

to enter shutdown is enabled by externally driving SHDNL

low. Although, not recommended, if the FORCEPOR bit-

field will be utilized, the external driver must have some

series-limiting resistance to ensure that a voltage-divider

constant associated with the external C

and the

SHDNL

equivalent resistance. Through halting communication to

the device, there is no charge pumping and the capacitor

discharges through an internal 10MΩ resistor with a 10ms

time constant. If a faster shutdown rate is required, a

200kΩ resistor can be connected externally from SHDNL

to AGND to create a 200µs time constant. Alternatively,

is created to allow SHDNL to fall below V

IL_SHNDL.

Table 12. Shutdown Timing

SHUTDOWN METHOD

1. External controller

R

C

RC

N/A

PULLDOWN

SHDNL

N/A

External

2. External SHDNL resistance to AGND

3. Register conﬁgured FORCEPOR

4. Disconnect DCIN

4.7kΩ

External

Internal

External

Internal

4.7µs

1nF

4.7µs

200kΩ

10MΩ

200µs

10,000µs

5. Host places UART in idle mode

Maxim Integrated │ 57

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Shutdown State Diagram

POR INACTIVE

CHECK V

AA

YES

V

> V

AA

POR_RISING

NO

POR ACTIVE

OSCILLATOR,

CHARGE PUMP,

DIGITAL LOGIC

DISABLED

Figure 13. Shutdown Sequence

Maxim Integrated │ 58

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

RXLP

RXLN

RXUP

RXUN

t

FORCEPOR

FRPOR

SHDNL

V

IH

V

IL

t

RXFD-VAA

V

AA

V

PORFALL

t

VAAFD-POR

POR

Figure 14. UART Operation (Shutdown Timing)

Maxim Integrated │ 59

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

V

, V

≥ V

DDL2 DDL3 AA

V

DDL2

DDL3

SCLK

SDI

SDO

CSB

t

FORCEPOR

FRPOR

SHDNL

V

IH

V

IL

t

SHDNL-VAA

V

AA

V

PORFALL

t

VAAFD-POR

POR

Figure 15. SPI Operation (Shutdown Timing)

Maxim Integrated │ 60

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

as discussed in the Single-Ended Rx Mode section. In

Power-On and Shutdown Timing

this case the directed control of the SHDNL pin remain

the same.

The following diagrams provide details regarding the

power-on control and shutdown timing as well as supply

sequencing in a high-voltage daisy-chained system con-

trolled by UART communication, as well as a low-voltage

(48V) system with directed control over the SHDNL pin.

It is important to note that the UART can also be used in

low-voltage systems with single-ended communication,

Note: As shown in Figure 14 and Figure 15, the shutdown

can also be controlled by writing the specific FORCEPOR

bit. If SHDNL is actively driven, the application circuit

should ensure there is no contention and this is driven

below V

IL_SHDNL.

RXLP

RXLN

RXUP

RXUN

V

IL

SHDNL

V

SHDNLIMIT

V

IH

t

RXRU-VAA

t

RXFD-VAA

V_PORRISE

V

AA

V

PORFALL

t

VAARU-POR

t

VAAFD-POR

POR

t

PORUP-TX

TXUP

TXUN

Figure 16. Power-On Timing (UART-Communication Control)

Maxim Integrated │ 61

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

V

, V

≥ V

DDL2 DDL3 AA

V

DDL2

DDL3

V

IL

SHDNL

V

SHDNLIMIT

t

V

IH

SHDNL-VAA

t

SHDNL-VAA

V_PORRISE

V

AA

V

PORFALL

t

VAA-POR

t

VAAFD-POR

POR

t

PORUP-SPI

SCLK

SDI

SDO

CSB

t

SDO_STOP

Figure 17. Power-On Shutdown Timing (SPI Directed Control)

Maxim Integrated │ 62

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

RXLP

RXLN

RXUP

RXUN

V

IL

SHDNL

V

SHDNLIMIT

V

IH

t

RXRU-VAA

t

RXFD-VAA

V_PORRISE

V

AA

V

PORFALL

t

VAARU-POR

t

VAAFD-POR

POR

t

PORUP-TX

TXUP

TXUN

Figure 18. Power-On and Shutdown Timing (UART Control)

Maxim Integrated │ 63

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

V

, V

≥ V

DDL2 DDL3 AA

V

DDL2

DDL3

V

IL

SHDNL

V

SHDNLIMIT

t

V

SHDNL-VAA

IH

t

SHDNL-VAA

V

PORRISE

V

AA

V

PORFALL

t

VAAFD-POR

t

VAA-POR

POR

t

PORUP-SPI

SCLK

SDI

SDO

CSB

t

SDO_STOP

Figure 19. Power-On and Shutdown Timing (SPI Control)

Maxim Integrated │ 64

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

POLARITY[13:0] bits in the POLARITYCTRL register. In

Active Mode

the unipolar configuration the input range is nominally 0V

to 5V. In the bipolar configuration, the nominal input range

is nominally -2.5V to 2.5V. Through combining the conver-

sion data from the two scan configurations the input range

can effectively be extended from -2.5V to 5V where any

bipolar measurements over 2.3V should be supplemented

with the unipolar measurements.

The device enter acquisition mode upon receiving a

SCAN command or during cell-balancing operation with

UV threshold detection. The overall time spent in acquisi-

tion mode is determined by the settings defined by the

SCANCTRL and ACQCFG registers. Once the acquisition

is completed (signified by SCANDONE and DATARDY),

the device enter the low power standby mode opera-

tion. During any point within acquisition mode, SHDNL

The flexibility to support both unipolar and bipolar con-

versions ensures that both cell measurements as well

as bus-bar measurements are able to be simultaneously

captured within the same acquisition which help optimize

acquisition time and interface throughput.

is pulled below V

, T

is exceeded, or

IL_SHDNL

SHDNL

V

AA

transitions below the POR threshold, the device exit

acquisition and enter shutdown mode.

Precision Internal Voltage References

Note: Conversions for some diagnostic modes automati-

cally preconfigure the device to use either bipolar or uni-

polar mode regardless of the POLARITY_n bit value in

the POLARITYCTRL register.

The measurement system uses two precision, tempera-

ture-compensated voltage references. The references are

completely internal to the device and do not require any

external components. The primary voltage reference, or

REF, is used to derive the linear regulator output voltage

and to supply the ADC reference. An alternate, indepen-

dent reference (ALTREF) can be used to verify the primary

reference voltage as described in the Diagnostics section.

The ADC also supports both ratiometric and absolute

acquisitions for the auxiliary inputs through the con-

figuration setting of the AUXREFSEL[5:0] bits in the

AUXREFCTRL register. Ratiometric acquisitions are pri-

marily used for NTC based temperature measurements

Scan Methods

and support an input range of 0V to V . Absolute

AA

The MAX17853 has two parallel measurements engines

(ADC and Comparator) that are capable of providing

three different acquisitions (ADC Acquisition, Comparator

Acquisition, and Simultaneous ADC + Comparator

Acquisition). The combination of both measurement block

provides hardware redundancy to accelerate fault detec-

tion and ensure added system reliability.

acquisitions can be used for any on supplemental voltage

measurement required by the application and supports

an input range of 0V to V

. To ensure the highest

REF

accuracy for the application, the appropriate mode should

be configured (it is not recommended to perform an ratio-

metric acquisition for an absolute measurement such as

a supply voltage as the variability in the reference (V

can introduce unwanted measurement error).

)

AA

All modes are able to process the cell and auxiliary temper-

ature/auxiliary-voltage measurements and each have their

own unique alert threshold settings to accelerate the com-

munication of a system fault. Alert settings are described in

further detail in the Measurement Alerts section.

The auxiliary configuration supports simultaneous acqui-

sition of both absolute and ratiometric measurements to

help optimize acquisition time and interface throughput.

Note: In all ADC configurations, reduced linearity may

occur near the zero-scale and full-scale limits. Refer to

the Electrical Characteristics table for device accuracy

specification.

ADC Input Range

The ADC supports unipolar and bipolar cell input

acquisitions through the configuration settings of the

Table 13. ADC Input Range

CELLn[15:2]

AUXn[15:2]

(14 BITS)

AUX RATIO AUX ABSOLUTE

CELLn[15:0]

AUXn[15:0]

(16 BITS)

CELL INPUT VOLTAGE

INPUT

VOLTAGE

BIPOLAR MODE UNIPOLAR MODE

HEXADECIMAL

DECIMAL

0d

-2.5V

0V

2.5V

5V

0V

0000h

2000h

3FFFh

0000h

8000h

FFFCh

V

/2

V

/2

8192d

16383d

AA

REF

2.5V

V

REF

AA

Maxim Integrated │ 65

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OVSAMPL allows for specific frequency rejection at either

Comparator Input Range

50Hz/100Hz or 60Hz/120Hz. If not configured, the user

may specifically control the sample interval through the

timing of the interface to support any desired post pro-

cessing on the host controller.

The comparator supports a unipolar cell input range

from 0V to 5V input through the configuration of the

POLARITY[13:0] bit in the POLARITYCTRL registers. If

the individual POLARITY bit is configured for a bipolar

acquisition the comparator cell measurement be omitted

from the scan.

Note: The Balance Switch and Cell Sense acquisitions

immediately configure the internal balance switches once

the SCANCFG bitfield is written. Refer to the BALSW

Diagnostic Section for details on the operation of this

acquisition mode

The comparator also supports ratiometric and absolute

acquisition for the auxiliary input that follows the same

configuration as described in the ADC Input Range sec-

tion. Ratiometric acquisitions support an input range of 0V

ADC Conﬁgurations and Properties

ADC Polarity Conﬁguration

to V and absolute acquisitions supports an input range

AA

of 0V to V

.

REF

Unipolar and bipolar measurements are supported within

a single acquisitions to capture all cell and bus bar data

without the need to reconfigure multiple scan configura-

tion registers or perform multiple acquisitions. Cell polarity

is configured using the POLARITYCTRL register where all

cells are defaulted to unipolar measurements (POLARITY

[13:0] = 0000h).

Scan Conﬁguration

The SCANCFG bits in the SCANCTRL register selects

the acquisition that is to be performed. All available con-

figurations are listed below.

1) ADC Acquisition

2) ADC and Comparator (ADC+COMP) Acquisition

3) Comparator Acquisition

4) Calibration

Bipolar cells are fault masked during BALSWDIAG ADC

Measurement scans. MINMAXPOL determines wheth-

er Bipolar cells are included in MIN/MAXCELL and

ALRTMSMTCH calculations.

5) Balancing Switch Short

6) Balancing Switch Open

7) Cell Sense Open Odds

8) Cell Sense Open Evens

Bipolar cell measurements are checked against BIPOVTH

and BIPUVTH thresholds rather than OVTH and UVTH

thresholds.

Bipolar cells are not included in Comparator Measurement

scans, and ALRTCOMPOV/ALRTCOMPUV alerts are not

evaluated.

ADC, Comparator, and ADC+COMP acquisitions have

programmable sample intervals through the configura-

tion of the FOSR bit. This setting when coupled with the

Table 14. Comparator Input Range

COMPOVTH, COMPUVTH,

COMPAUXROVTH, COMPAUXRUVTH

COMPAUXAOTH,COMPAUXAUVTH

(10 BITS)

COMPOVTH[15:0],

COMPUVTH[15:0] COMPAUX

ROVTH[15:0],COMPAUXRUV

TH[15:0] COMPAUXAOTH[15:0],

COMPAUXAUVTH[15:0]

(16 BITS)

AUX RATIO AUX ABSOLUTE

CELL INPUT

VOLTAGE

INPUT

VOLTAGE

HEXADECIMAL

DECIMAL

0V

2.5V

5V

0V

000h

200h

3FFh

0d

0000h

8000h

FFC0h

V

/2

V

/ 2

REF

512d

1024d

AA

V

REF

AA

Maxim Integrated │ 66

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

4) All enabled cell conversions (second phase), if

ADC Acquisition

enabled

ADC acquisitions can be configured for the {adc_blocks}.

The acquisition is initiated by writing a logic one to the

SCAN bit in the SCANCTRL register. This write acts as a

strobe, and the SCAN bit content is automatically cleared

reading back a logic zero is polled. In daisy-chained

devices, acquisitions in either UART path (depending

on the Master configuration) be delayed by the propaga-

a) descending order (14 through 1)

5) VBLK conversion (second phase), if enabled

6) <End of Pyramid>

7) DIAG1 conversion (ﬁrst phase), if enabled

8) DIAG1 conversion (second phase), if enabled

9) DIAG2 conversion (ﬁrst phase), if enabled

10) DIAG2 conversion (second phase), if enabled

11) Auxiliary conversions, if enabled

tion delay, t , of the command packet through each

PROP

device. The acquisition for device is signaled complete

when SCANDONE bit is a logic one.

Note: If any additional write to the SCANCFG is issued

prior to the SCANDONE bit being cleared this command

be ignored.

12) Enable HV charge pump for recovery period unless

a) OVSAMPL = 000b (no oversampling) or

b) all oversample measurements are complete

Pyramid Mode Acqusition Sequence

13) Repeat steps 1 through 11 until all oversamples are

done

The ADC acquisition process for Pyramid Mode

(SCANMODE = 0) is outlined below:

14) Set SCANDONE bit

1) Disable HV charge pump

2) VBLK conversion (ﬁrst phase), if enabled

3) All enabled cell conversions (ﬁrst phase), if enabled

a) ascending order (1 through 14)

ADC Pyramid Mode Figures

INPUT

CHANNEL

SIMULTANEOUS CELL

SAMPLING POINT

TIME

T₀

Figure 20. Acquisition (SCANCFG=0h, SCANMODE=0, OVSAMPL=0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1 > 0h,

DIAGSEL2 > 0h, AUXEN=3Fh)

Maxim Integrated │ 67

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

SIMULTANEOUS CELL

SAMPLING POINT

INPUT

CHANNEL

TIME

T₀

Figure 21. Acquisition (SCANCFG=0h, SCANMODE=0, OVSAMPL = 0h, TOPCELL1/2 = 14, ALTMUXSEL=1, BLOCKEN=1,

DIAGSEL1 > 0h, DIAGSEL2 > 0h, AUXEN=3F)

INPUT

CHANNEL

SIMULTANEOUS CELL

SAMPLING POINT

54µs

HVCP

REFRESH

TIME

T₀

Figure 22. Acquisition - SCANCFG=0h, SCANMODE=0, OVSAMPL > 0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1 > 0h,

DIAGSEL2 > 0h, AUXEN=3Fh

Maxim Integrated │ 68

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

INPUT

CHANNEL

SIMULTANEOUS CELL

SAMPLING POINT

HVCP

REFRESH TIMEOUT

FOSR

+

TIME

T₀

625µs (FOSR = 01)

520µs (FOSR = 1x)

Figure 23. Acquisition (SCANCFG=0h, SCANMODE=0, OVSAMPL > 0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1 > 0h,

AUXEN=03h, FOSR > 0h)

Maxim Integrated │ 69

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Pyramid Mode Acquisition Time

The total time for ADC Pyramid Mode acquisitions can be calculated by summing all the conditional process times as

shown in following tables. There is one measurement cycle per oversample acquisition.

ADC Acquisition Timing (Pyramid Mode)

Table 15. ADC Pyramid Mode (SCANMODE = 0) Acquisition Time

PROCESS

Initialization

TIME (µs)

CONDITION

FREQUENCY

15

Always

Once per Acquisition

THRMMODE = Automatic Mode and

FOSR = 1.6kHz, 1.92kHz Mode

6 * AUXTIME[9:0]

AUXIN Settling

(if enabled)

- t

Initialization

VBLK

Once per Acquisition

THRMMODE = Automatic Mode and

FOSR = Free Run Mode

Cell_Scan_Setup

t

- Cell_Scan

- t

Diag_Total

VBLK Measurement

(if enabled)

27.75

BLOCKEN =1

Cell Scan Setup

6.38

For any cell(s) enabled

Cell Measurement

9 x y

32.44

23.81

8.44

For y = # of enabled cell inputs

Die Temperature Diagnostic

V

Diagnostic

AA

DIAG1 Measurement

AND/OR

DIAG2 Measurement

(if enabled)

Comp Signal Path Diagnostic

Cell Gain Calibration Diagnostic

Every Measurement Cycle

24.28

86.44

19.5

V

Diagnostic

ALTREF

DAC 3/4, DAC 1/4

5.44

All Other Diagnostics

AUXIN Measurement

(if enabled)

5.44 * x

57 * (z-1)

11.2

For x = # of enabled AUXIN Inputs

For z = # of oversamples

ADCZSFSEN = 1

HV Recovery

(if oversampling enabled)

Every Measurement Cycle

Except Last

ADCZSFS Diagnostic

(if enabled)

End of Acquisition

COMPACC Diagnostic

(if enabled)

13.5

COMPACCEN = 1

Maxim Integrated │ 70

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

6) DIAG1 conversion, if enabled

Ramp-Mode Acquisition Sequence

TheADCacquisitionprocessforRampMode(SCANMODE

= 0) is outlined below:

7) DIAG2 conversion, if enabled

8) Auxiliary conversions, if enabled

1) Disable HV charge pump

9) Enable HV charge pump for recovery period unless

a) OVSAMPL = 000b (no oversampling) or

2) VBLK conversion (ﬁrst phase), if enabled

3) All enabled cell conversions (1 through 14), if enabled

4) VBLK conversion (second phase), if enabled

5) <End of Ramp>

b) all oversample measurements are complete

10) Repeat steps 1 through 7 until all oversamples are

done

11) Set SCANDONE bit

ADC Ramp-Mode Figures

INPUT

CHANNEL

TIME

T₀

Figure 24. Acquisition (SCANCFG=0h, SCANMODE=1, OVSAMPL=0h, ALTMUXSEL=0, BLOCKEN=1, DIAGSEL1 > 0h,

DIAGSEL2 > 0h, AUXEN=3Fh)

Maxim Integrated │ 71

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

INPUT

CHANNEL

TIME

T₀

Figure 25. Acquisition (SCANCFG=0h, SCANMODE=1, OVSAMPL = 0h, TOPCELL1/2=14, ALTMUXSEL=1, BLOCKEN=1,

DIAGSEL1 > 0h, DIAGSEL2 > 0h, AUXEN=3Fh)

Maxim Integrated │ 72

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Ramp-Mode Acquisition Time

The total time for ADC ramp-mode acquisitions can be calculated by summing all the conditional process times, as shown

in Table 16. There is one measurement cycle per oversample acquisition.

ADC Acquisition Timing (Ramp Mode)

Table 16. ADC Ramp Mode (SCANMODE = 1) Acquisition Time

PROCESS

Initialization

TIME (µs)

CONDITION

FREQUENCY

15

Always

Once Per Acquisition

THRMMODE = Automatic

mode,

FOSR = 1.6kHz, 1.92kHz

mode

6 * AUXTIME[9:0]

AUXIN Settling

(if enabled)

6 * AUXTIME[9:0]

Once Per Acquisition

- t

Initialization

VBLK

THRMMODE = Automatic

mode

FOSR = Free-run mode

Cell_Scan_Setup

t

- Cell_Scan

- t

Diag_Total

VBLK Measurement

(if enabled)

27.75

BLOCKEN=1

Cell Scan Setup

3.19

For any cell(s) enabled

Cell Measurement

4.5 * y

32.44

23.81

8.44

For y = # of enabled cell inputs

Die Temperature Diagnostic

V

Diagnostic

AA

Comp Signal-Path Diagnostic

DIAG1 Measurement

and/or

DIAG2 Measurement

(if enabled)

Every Measurement Cycle

Cell-Gain Calibration

Diagnostic

24.44

86.44

19.5

5.44

V

Diagnostic

ALTREF

DAC 3/4, DAC 1/4

All Other Diagnostics

AUXIN Measurement

(if enabled)

For x = # of enabled AUXIN

Inputs

5.44 * x

57 * (z-1)

11.2

HV Recovery

(if oversampling enabled)

Every Measurement Cycle

Except Last

For z = # of oversamples

ADCZSFSEN=1

ADCZSFS Diagnostic

(if enabled)

End of Acquisition

COMPACC Diagnostic

(if enabled)

13.5

COMPACCEN=1

Maxim Integrated │ 73

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADC Acquisition Time Example

Table 17 provides an example of common configuration and the associated acquisition time that can be achieved.

Table 17. ADC Acquisition Time Examples (with AUXTIME[9:0] = 000h)

ENABLED

MEASUREMENTS

NO OVERSAMPLING

(OVSAMPL[2:0] = 0h)

8x OVERSAMPLING

(OVSAMPL[2:0] = 2h)

16x OVERSAMPLING

(OVSAMPL[2:0] = 3h)

Pyramid Scan

148.3μs

Ramp Scan

82.1μs

Pyramid Scan

1480.5μs

Ramp Scan

951μs

Pyramid Scan

3003.1μs

Ramp Scan

1944μs

14 Cells

14 Cells, VBLK

14 Cells, 6 Aux

175.7μs

181μs

109.5μs

114.8μs

1699.5μs

1741.7μs

1170μs

3441.1μs

3525.3μs

2382μs

1212.1μs

2466.3μs

14 cells, VBLK, 6

Aux

208.3μs

240.6μs

142.1μs

174.4μs

1960.7μs

2218.7μs

1431.1μs

1689.1μs

3963.3μs

4479.3μs

2904.3μs

3420.3μs

14 cells, VBLK, Die

Temp DIAG, 6 Aux

Comparator-Acquisition Process

1) Disable HV charge pump

2) Perform overvoltage conversion on all enabled Cell

Inputs (MEASUREEN1) against COMPOVTH

threshold

a) ascending order (1 through 14)

3) Update ALRTCOMPOV Register (MEASUREEN1 &

ALRTOVEN)

4) Perform undervoltage conversion on all enabled Cell

Inputs (MEASUREEN1) against COMPUVTH

threshold

b) descending order (14 through 1)

5) Update ALRTCOMPUV Register (MEASUREEN1

and ALRTUVEN)

6) Perform overvoltage conversion on all enabled

Auxiliary Inputs (MEASUREEN2) against

COMPAUXOVTH

Comparator Conﬁguration and Properties

Comparator-Scan Properities

The comparator acquisition can be configured for uni-

polar Cell measurements and Auxiliary measurements.

If a cell input is configured for bipolar operation in

the POLARITYCTRL register, the comparator measure-

ment is idle for this acquisition period and the associ-

ated alert reporting in the ALRTCOMPOVREG and

ALRTCOMPUVREG register not be updated. If acqui-

sition time is of critical importance for a comparator

scan, it is recommended to disable bipolar inputs in the

MEASUREEN1 register to prior to issuing a SCAN as this

omit these measurements from the acquisition.

The SCANMODE bit configuration also does not apply to

the comparator acquisition and the comparator operate

only on the inputs indicated by the MEASUREEN1 and

ALRTOVEN, ALRTUVEN registers. This is illustrated in

the comparator acquisition process defined below.

c) ascending order (0 through 5)

7) Update ALRTCOMPAUXOV Register

(MEASUREEN2 and ALRTAUXOVEN)

8) Perform undervoltage conversion on all enabled

Auxiliary Inputs (MEASUREEN2) against

COMPAUXUVTH

d) ascending order (0 through 5)

9) Update ALRTCOMPAUXUV Register (MEASU-

REEN2 and ALRTAUXUVEN)

Comparator Acquisition

The acquisition is initiated by writing a logic one to the

SCAN bit in the SCANCTRL register. This write acts as a

strobe, and the SCAN bit content is automatically cleared

reading back a logic zero if polled. In daisy-chained

devices, acquisitions in either UART path (depending

on the Master configuration) be delayed by the propaga-

tion delay, t , of the command packet through each

PROP

10) HV charge-pump refresh

11) Repeat steps 2-6 until all oversamples complete

device. The acquisition for device is signaled complete

when SCANDONE bit is a logic one.

12) Compare results against comparator thresholds and

update alert status

13) Enable HV Charge Pump

Note: Comparator results are only available when the

corresponding OV/UV alerts are enabled.

Note: If any additional write to the SCANCFG is issued

prior to the SCANDONE bit being cleared this command

be ignored.

Maxim Integrated │ 74

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

measurements respectively. Note: for the auxiliary inputs

Comparator Thresholds

since the full scale is dependent on V this may have an

impact on the resolution of the comparator over loading

and temperature conditions.

AA

The comparator cell measurements and auxiliary mea-

surements can be programmed with OV and UV thresh-

olds that are independent of the ADC OV and UV thresh-

olds. However, all cell measurements share the same

threshold settings as defined by the COMPOVTHand

COMPUVTHregisters. Additionally, all ratiometric auxil-

iary measurement share the same thresholds settings as

defined by the COMPAUXROVTH and COMPAUXRUVTH

registers and all absolute auxiliary measurements

share the same threshold settings as defined by the

COMPAUXAOVTH and COMPAUXAUVTH registers.

If the pin configuration for the auxiliary inputs is set to

GPIO mode, both ALRTAUXOVEN and ALRTAUXUVEN

are disabled (logic 0).

Comparator Acquisition Time

The total time for Comparator acquisitions can be calcu-

lated by summing all the conditional process times (see

Table 18). There is one measurement cycle per overs-

ample acquisition.

As defined in the Compartor Input Range section, each

threshold register is programmable up to 10 bits allow-

ing for 4.9mV, 3.2mV, and 2.2mV of adjustable resolution

on the cell, ratiometric auxiliary, and abosulte auxiliary

Comparator Acquisition Timing Example

Table 18 provides an example of common configuration

and the associated acquisition time that can be achieved

Table 18. Comparator Acquisition Time

PROCESS

Initialization

TIME (µs)

CONDITION

FREQUENCY

15

Always

Once per Acquisition

THRMMODE = Automatic

mode and

FOSR = 1.6kHz, 1.92kHz

mode

6 * AUXTIME[9:0]

AUXIN Settling

(if enabled)

6 * AUXTIME[9:0]

Once per Acquisition

- t

Initialization

VBLK

THRMMODE = Automatic

mode and

FOSR = Free-Run mode

Cell_Scan_Setup

t

- Cell_Scan

- t

Diag_Total

Cell Scan Setup

6.38

For any cell(s) enabled

Cell Measurement

12 * y

For y = # of enabled cell inputs

Every Measurement Cycle

AUXIN Measurement

(if enabled)

For x = # of enabled AUXIN

Inputs

12.56 x

57 * (z-1)

13.5

HV Recovery

(if oversampling enabled)

Every Measurement Cycle

Except Last

For z = # of oversamples

COMPACCEN=1

COMPACC Diagnostic

(if enabled)

End of Acquisition

Table 19. Comparator Acquisition-Time Examples (with AUXTIME[9:0] = 000h)

ENABLED

MEASUREMENTS

NO OVERSAMPLING

(OVSAMPL[2:0] = 0h)

8x OVERSAMPLING

(OVSAMPL[2:0] = 2h)

16x OVERSAMPLING

(OVSAMPL[2:0] = 3h)

14 Cells

190.3μs

265.7μs

1816.5μs

2419.4μs

3675.1μs

4880.8μs

14 Cells, 6 Aux

Maxim Integrated │ 75

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Comparator Scan Figures

INPUT

CHANNEL

CELL OV QUALIFICATION

CELL UV QUALIFICATION

AUX OV/UV QUAL

TIME

T₀

Figure 26. Comparator Single-Scan Mode

INPUT

CHANNEL

HVCP

REFRESH

CELL OV QUALIFICATION

CELL UV QUALIFICATION

AUX OV/UV QUAL

TIME

T₀

Figure 27. Comparator Single-Scan with Oversampling

Maxim Integrated │ 76

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

applied to both ADC and comparator with each capable

of setting it unique threshold. If any OV or UV Alert is

disabled the ADC measurement still occurs, however the

comparator is idle during this portion of the acquisition.

ADC+COMP Conﬁguration and Properties

ADC+COMP Scan Mode

ADC+COMP acquisitions can be applied to the Cell,

Auxiliary, Block, and Diagnostics measurements. Each

measurement engine (ADC or Comparator) retain the

functionality discussed previously with additional clarifica-

tion detailed below.

In ADC+COMP scan mode, the ADC acquisition only

operates in pyramid mode and the SCANMODE bit is

ignored.

ADC+COMP Acquisition Time

The comparator acquisition is applied to the unipolar Cell

and Auxiliary inputs and be idle during bipolar Cell, Block,

and Diagnostics measurements. OV and UV alerts for

the the cell path, (OVALRTEN and UVALERTEN) and

Auxiliary path (AUXOVALRTEN and AUXUVALRTEN) are

The total time for ADC+COMP acquisitions can be cal-

culated by summing all the conditional process times as

shown in following tables. There is one measurement

cycle per oversample acquisition

Table 20. ADC+COMP Acquisition Time

PROCESS

Initialization

TIME (µs)

CONDITION

FREQUENCY

15

Always

Once per Acquisition

THRMMODE = Automatic mode and

FOSR = 1.6kHz, 1.92kHz mode

6 * AUXTIME[9:0]

AUXIN Settling

(if enabled)

- t

Initialization

VBLK

Once per Acquisition

THRMMODE = Automatic mode and

FOSR = Free Run Mode

Cell_Scan_Setup

t

- Cell_Scan

- t

Diag_Total

VBLK Measurement

(if enabled)

27.75

BLOCKEN=1

Cell Scan Setup

6.38

For any cell(s) enabled

Cell Measurement

12 * y

32.44

23.81

8.44

For y = # of enabled cell inputs

Die Temperature Diagnostic

V

Diagnostic

AA

DIAG1 Measurement

AND/OR

DIAG2 Measurement

(if enabled)

Comp Signal Path Diagnostic

Cell Gain Calibration Diagnostic

Every Measurement Cycle

24.44

86.44

19.50

5.44

V

Diagnostic

ALTREF

DAC 3/4, DAC 1/4

All Other Diagnostics

AUXIN Measurement

(if enabled)

12.56 * x

57 * (z-1)

11.2

For x = # of enabled AUXIN Inputs

For z = # of oversamples

ADCZSFSEN=1

HV Recovery

(if oversampling enabled)

Every Measurement Cycle

Except Last

ADCZSFS Diagnostic

(if enabled)

End of Acquisition

COMPACC Diagnostic

(if enabled)

13.5

COMPACCEN=1

Maxim Integrated │ 77

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADC+COMP Acquisition Time Example

Table 21 provides examples of common configuration and the associated acquisition time that can be achieved.

Table 21. ADC+COMP Acquisition Time Examples (with AUXTIME[9:0] = 000h)

ENABLED

MEASUREMENTS

NO OVERSAMPLING

(OVSAMPL[2:0] = 0h)

8x OVERSAMPLING

(OVSAMPL[2:0] = 2h)

16x OVERSAMPLING

(OVSAMPL[2:0] = 3h)

14 Cells

187.1μs

214.5μs

262.5μs

1791μs

2010μs

3624μs

4062μs

14 Cells, VBLK

14 Cells, 6 Aux

2393.9μs

4829.8μs

14 Cells, VBLK,

6 Aux

289.9μs

2612.9μs

5267.8μs

14 Cells, VBLK,

Die Temp DIAG,

6 Aux

322.1μs

2870.9μs

5783.8μs

ADC+COMP Scan Figures

INPUT

CHANNEL

ADC SIMULTANEOUS CELL

SAMPLING POINT

CELL OV QUALIFICATION

CELL UV QUALIFICATION

AUX OV/UV QUAL

TIME

T₀

Figure 28. Simultaneous ADC+COMP Scan Mode

Maxim Integrated │ 78

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

INPUT

CHANNEL

ADC SIMULTANEOUS CELL

SAMPLING POINT

HVCP

REFRESH

CELL OV QUALIFICATION

CELL UV QUALIFICATION

AUX OV/UV QUAL

TIME

T₀

Figure 29. Simultaneous ADC+COMP Scan With Oversampling

Maxim Integrated │ 79

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Note: The calibration acquisition is independent of the

Scan Control Registers and Scan Setting Registers

(POLARITYCTRL, SCANCTRL, ACQCFG) .

On-Demand Calibration

The MAX17853 supports an integrated "On-Demand" cal-

ibration procedure which can be commanded by the user

to improve the internal measurement accuracy from inac-

curacies of the internal signal chain. It should however be

noted that the calibration process not correct for inaccura-

cies within the external application components. The cali-

brated accuracy are described within the measurement

accuracy section of the electrical characteristics.

The ADCCALEN bit must be set for the calibration coef-

ficients to be applied to the measurement results. If

ADCCALEN disabled, even with the successful comple-

tion of a calibration acquisition, the measurement results

not have the calibration coefficients applied.

Note: The "On-Demand" calibration is independent of the

factory calibration. In the event that the "On-Demand" cal-

ibration is applied, the device retain its factory calibration

setting. The factory calibration setting can never be over-

written and can be verified using the ROM CRC diagnos-

tic in the Diagnostics section. See ADC Scan Properties

for details on using calibration to maintain Ramp Mode

accuracy over DCIN voltage range; factory calibration

defaults are programmed using a 50V DCIN voltage.

For a valid "On-Demand" calibration, a calibration acqui-

sition must be commanded using the SCANCFG bits of

the SCANCTRL register. The calibration acquisition auto-

matically configures the internal calibration sources and

performs ADC acquisitions to calculate and store calibra-

tion coefficients for the Cell Inputs, Auxiliary Inputs, and

Block Input. The completion of the calibration acquisition

be signaled by the issuance of the SCANDONE bit like

any other acquisition. Any commands that are sent before

the calibration acquisiton is completed be ignored but still

propagate through the daisy-chain.

Table 22 indicates which calibration alerts are associated

to the various measurement path

The calibration time is 3.75ms.

Table 22. Measurement Path Calibration Alerts

MEASUREMENT PATH

CALIBRATION ALERTS

Cell Input - Pyramid

(SCANMODE = 0b)

ALRTCALGAINP, ALRTCALOSADC

Cell Input - Ramp

(SCANMODE = 1b)

ALRTCALGAINR, ALRTCALOSR

ALRTCALOSADC

Auxiliary Input - Absolute

(REFSEL = 1b)

Auxiliary Input - Ratio metric

(REFSEL = 0b)

ALRTCALOSTHRM

Block Input

CSA Input

ALRTCALOSADC

The "On-Demand" calibration adjustments can be verified by using the Cell Calibration and Offset Calibration commands

in the DIAGSEL1 and DIAGSEL2 bits. See the Diagnostics section for further details.

Maxim Integrated │ 80

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

VBLK

AGND

DIE

HVMUX

TEMPERATURE

C14

C13

V_REF

VAA

ADC OFFSET

V_REF

Cn

CALIBRATION

+

-

Cn-1

LSAMP

ADC IN+

ADC IN-

ADC

C2

C1

LV

MUX

C0

AGND

SIGNAL PATH

CALIBRATION NETWORK

AUXINn

AUXINn-1

AUXIN1

DIGITAL

CONTROL

AUXIN0

Figure 30. On-Demand Calibration Block Diagram

Calibration Alerts

Oversampling

Internal safety mechanisms are implemented to ensure

that the applied calibration coefficients are within pre-

determined bounds. If a calibration coefficient were to

fall outside of these bounds, this would immediately

raise an fault in the ALRTSUM register for the affected

calibration process (ALRTCALOSADC, ALRTCALOSR,

ALRTCALOSTHRM,ALRTCALGAINP,ALRTCALGAINR).

This fault condition then propagates to the STATUS1 alert

register which is capable of flagging an issue within the

Data Check Byte or within the hardware alert interface.

ADC Oversampling

Oversampling performs multiple measurement cycles in

a single acquisition and averages the samples to reduce

the measurement noise and effectively increase the reso-

lution of each acquisition. The net increase of the mea-

surement resolution depends on the number of oversam-

2n

ples. To add n bits of measurement resolution at least 2

oversamples are required. Since the ADC resolution is 12

bits, 13-bit resolution requires at least 4 oversamples. In

order to achieve the maximum 14-bit resolution, at least

16 oversamples are required. Therefore with no overs-

ampling, only the higher 12 bits of the measurement are

statistically significant. With 4 or 8 oversamples, only the

highest 13-bits are statistically significant. Taking more

than 16 oversamples further reduces the measurement

variation. With no oversampling, measurements can be

averaged externally to achieve increased resolution but

at a higher computational cost for the host.

If the integrity of the calibration coefficients is question-

able, it is recommended to issue an new calibration to

verify and/or correct the fault, or to de-assert ADCCALEN

and use the factory default calibration.

Maxim Integrated │ 81

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

shown in Table 23. Thus, an OVSAMPL setting of 8 afford

Comparator Oversampling

1 sample outside of the OV/UV condition before setting

an alert. It is recommended for higher noise immunity that

the OVSAMPL setting should be configured to 8 or higher

for comparator acquisition with oversampling. When the

ADC and comparator are simultaneously sampled, the

oversampling normally be set by the noise reduction

required for ADC measurements.

To effectively mitigate high frequency noise from affect-

ing the comparator measurement, the output can be

oversampled using the OVSAMPL bits in the SCANCTRL

register. The accumulated oversamples are digitally aver-

aged from the comparator output to gauge if a valid OV,

UV condition is present. An OV, UV condition require the

comparator readings to meet or exceed the threshold

listed in the table below for an alert to be generated as

Table 23. Comparator Faults for Alerts vs. Oversampling

OVSAMPL

COMPARATOR FAULTS FOR ALERT

1

4

1

8

2

16

32

64

128

3

5

10

20

Note: The comparator acquisition can be performed using the cell input path (C ) or the switch input path (SW ) as configured

n

by the ALTMUXSEL bit. In the event that the comparator acquisition is performed on the switch input path, it is recommended to

increase the oversampling to account for the lessened noise attenuation from the inputs due to the higher lowpass cutoff frequency.

Oversampling Watchdog Timeout

Table 24. Watchdog-Timeout Duration

OVSAMPL

0b000

SAMPLES

THEORETICAL RESOLUTION

ACQUISITION WATCHDOG TIMEOUT

1

4

12 bits

13 bits

14 bits

750μs

3ms

0b001

0b010

8

6ms

0b011

16

32

64

128

12ms

24ms

48ms

96ms

0b100

0b101

0b110

Note 1: When AUTOBALSWDIS=1, the watchdog timeout duration is extended by SWDLY or CELLDLY (depending on ALTMUXSEL).

Note 2: When AUXTIME is > 0, the timeout duration is extended by AUXTIME.

Maxim Integrated │ 82

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The FOSR settings of 0b01, 0b10 or 0b11 enables a

100Hz and 120Hz Filtering

notch filter at a frequency of 50Hz, 60Hz, 100Hz, or

120Hz. This mode can be particularly useful for accurate

voltage detection during vehicle charging where noise

from the power mains effect the voltage seen by the bat-

tery pack. To enable proper filtering for 50Hz or 100Hz,

the FOSR must be set to 0b01. For 60Hz or 120Hz filter-

ing, the FOSR must be set to either 0b10 or 0b11.

There are two types of scan configurations in which

oversampling frequency can be utilized, each providing a

different benefit to the system performance.

The first configuration is entered through FOSR = 0b00,

which performs the acquisition with minimal time delay

between measurement cycles to recharge the HV charge

pump. The FOSR=0b00 mode yields the highest number

of measurements per sample period allowing for higher

oversampling rates and further noise reduction. The total

acquisition time is proportional to the number of oversam-

ples configured by OVSAMPL and the type and number

of enabled channels.

Note: When configuring the FOSR the acquisition period

automatically be preconifgured to 625us for 50Hz/100Hz

and 520μs for 60Hz/120Hz.

Table 25. FOSR Notch-Filter Setting

REJECTION FREQUENCY (Hz)

FOSR

0x1

OVSAMPL

0x4

50

60

0x2 or 0x3

0x1

0x4

100

120

None

0x4 or 0x3

don't care

0x2 or 0x3

0x0

Note: The typical notch-filter responses are shown for both 100Hz (Figure 31) and 120Hz (Figure 32), respectively.

100Hz FOSRREJECTION vs. FREQUENCY

120Hz FOSRREJECTION vs. FREQUENCY

-20

-25

-30

-35

-40

-45

-50

-30

-35

-40

-45

-50

FOSR = 0X3

OVSAMPL = 0X3

FOSR = 0X1

OVSAMPL = 0X3

110

115

120

FREQUENCY (Hz)

125

130

90

95

100

FREQUENCY (Hz)

105

110

Figure 31. 100Hz Notch Filter

Figure 32. 120Hz Notch Filter

Maxim Integrated │ 83

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

If double-buffer mode is enabled (DBLBUFEN = 1), the

ALU registers are cleared but the data registers remain

Acquisition Watchdog Timeout

If the acquisition does not finish within a predetermined

time interval, the SCANTIMEOUT bit is set, the ADC logic

is reset, the ALU registers are cleared, and the measure-

ment data registers are also cleared. The acquisition

watchdog timeout interval depends on the oversampling

configuration as shown in Table 24.

unchanged as these are known good values previously

stored. Once a move operation is evoked (SCAN = 1),

the previously cleared ALU data is moved from the ALU

registers to the data registers and the data registers now

show as cleared. Refer to the Double Buffer section for

detailed information on the data control in mode.

STANDBY MODE

NO

COMPARE MEASUREMENTS

TO THRESHOLDS AND

UPDATE ALERTS

SCAN = 1?

YES

LATCH ACQUISITION

CONFIGURATION;

DISABLE

YES

DBLBUFEN = 1?

HV CHARGE PUMP

NO

SET WATCHDOG

TIMEOUT PERIOD

MOVE ALU DATA

TO DATA REGISTERS;

SET DATARDY=1

YES

SET SCANDONE

DBLBUFEN = 1?

MOVE ALU DATA

TO DATA REGISTERS;

SET DATARDY = 1

NO

ENABLE

HV CHARGE PUMP

CLEAR ALL INTERNAL

ALU REGISTERS

STANDBY MODE

PERFORM

SCAN MEASUREMENTS

ENABLE

HV CHARGE PUMP

NO

ALL SAMPLES

DONE?

YES

Figure 33. Acquisition-Mode Flowchart

Maxim Integrated │ 84

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

● Calibration

● IIR Filter

Data Control

Acquisition Data Transfer and Control

● Single-Buffer Data Transfer

The ADC data flow, Figure 34, can be directed through

multiple data processing paths until it reaches the register

space(CELLnREG,AUXnREG,BLOCKREG,DIAG1REG,

DIAG2REG, TOTALREG, and MINMAXCELL) depending

on the enabled configuration. The following sections detail

the data flow through:

● Double-Buffer Data Transfer

● Cell balancing with Embedded Measurements

ALU REGISTERS

USER REGISTER MAP

14

ALU1

ADC IN +

CELL1REG

12

ADC

14

ADC IN -

ALU2

CELL2REG

12

CALIBRATION

12

ADCTEST1A[11:0]

12

ADCTEST1B[11:0]

ADCTEST2A[11:0]

ADCTEST2B[11:0]

12

14

ADCCALEN

ALU14

CELL14REG

FILTER REGISTERS

RDFILT

ADC_CHOP

OVSAMP_EVEN_ODD

ADCTSTEN

ALU1_IIR

USER INTERFACE

COMMUNICATION

ALU2_IIR

IIR

ALU14_IIR

Figure 34. Data-Flow Diagram

Maxim Integrated │ 85

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Calibration Data Control

Filter Description

The ADC data is either directly output to the ALU or acted

upon by the Calibration block depending on the state

of the ADCCALEN bit. See the Calibration sections for

details on the configuration and application of calibration.

The IIR filter is implemented per the following transfer

function, Figure 35:

Equation 1:

Y(n) = FC*X(n) + (1-FC)*Y(n-1)

IIR Filter

FC is a 3-bit user-programmable filter coefficient. The

default value of 0b010 has a weight of 3/8.

To augment the accuracy performance over multiple

measurement cycles, the user can enable the embed-

ded IIR filter. The filter acts upon all enabled CELLn and

VBLOCK inputs according to the user defined settings in

the MEASUREEN1 register. The TOTAL register does not

have a unique IIR filter, but is instead directly computed

from the sum of the IIR data registers as selected through

RDFILT.

The detailed filter coefficient settings are defined in the

IIRFC register. The smaller that coefficient is, the more

the history represented by Y(n-1) outputs in Equation 1. It

is a trade-off between response times to change in input

value versus the noise attenuation.

The filter can be turned off by setting the filter coef-

ficient to 1 (IIRFC=0b111). The filter can be temporarily

bypassed by setting AMENDFILT=0; this is useful when

performing periodic safety and diagnostic checks, as the

filtered main measurement results be preserved within the

filter memory registers. Both filtered and raw result data

can be read back using the RDFILT option.

Additionally, when oversampling is enabled, the system

response of the measurement data is the combination of

the IIR filter and oversampling noise reduction.

Although the IIR filter can be updated dynamically on

any individual acquisition through AMENDFILT, it is rec-

ommended to always allow non-diagnostic acquisitions

into the IIR filter. Using the IIR filter leads to the greatest

benefit in noise reduction with the external hardware filter

combined with the digital filtering.

X(n)

Diagnostics (including BALSWDIAG results) or higher

noise data from ALTMUXSEL=1 should not be processed

within the IIR as this corrupt the desired measure-

ment result. This involves (but is not limited to) con-

figuration with the diagnostic current sources (CTSTCFG,

MUXDIAGEN).

INTERNAL REGISTER

COMBINATIONAL LOGIC

Y(n)

Y(n-1)

Note: IIR filtering is always applied to the measurement

cycle during automatic cell balancing. In the event the

IIRFC=111b (off) in automatic Cell-Balancing modes, the

IIR filter is internally forced to 000b (1/8). All other selection

of IIRFC are valid.

USER REGISTER

Figure 35. IIR Filter Algorithm

Maxim Integrated │ 86

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(ex. 0V to 100mV Unipolar Cell transition) to 12-bit and

Filter Response

14-bit accuracy. Note: This settling time can be sig-

nificantly shortened after power-up, or when operating

mode changes require large step responses by using the

MEASUREEN2:SCANIIRINIT or BALCTRL:CBIIRINIT ini-

tialization options, which accelerate settling by loading the

next acquired sample into the filter's accumulated result

memory.

The IIR Filter provides a means to improve measure-

ment noise rejection at a cost of increased settling time.

This tradeoff can be managed by selecting the proper

IIR Filter Coefficient for the application. [[IIR 100mV

Scale Step Response Settling]] shows the number of

samples taken by the IIR Filter to settle a full-scale step

Table 26. IIR 100mV Step Response Settling

IIRFC SETTING:

IIR FILTER COEFFICIENT (FC):

12-BIT SETTLING (# SAMPLES):

14-BIT SETTLING (# SAMPLES):

0b000

1/8

0b001

1/4

0b010

3/8

0b011

0b100

0b101

0b110

0b111

1/2

7

5/8

5

3/4

4

7/8

3

1

33

16

10

44

21

13

9

6

5

3

IIR FILTER RESPONSE – 100mV STEP

FC = 1/8

FC = 1/4

FC = 3/8

FC = 1/2

FC = 5/8

FC = 3/4

FC = 7/8

FC = 1

Figure 36. 100mV IIR Step Response

Maxim Integrated │ 87

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

If DBLBUFEN=x and SCAN=0, the ALU results are load-

IIR Data Control

ed into the IIR during the requested data move sequence

if DATARDY=0.

The control of ADC data into and around the IIR filter is

performed using dedicated register bits (AMDENDFILT,

RDFILT, ALRTFILT) in the SCANCTRL register. The fol-

lowing sections detail this operation.

Table 27 shows the interactions that can occur between

the IIR Data Control Setting:

AMENDFILT and RDFILT

ALRTFILTSEL

The AMENDFILT bit directs the ALU data into the IIR for

filtering operations or around the IIR filter to the output

data registers (CELLn and BLOCKREG).

When IIR filter operation is enabled, there are two pos-

sible data sources for user access, the raw sequencer

outputs (oversampling still applies), or the IIR filtered

outputs. The Alert Filtering Selection bit (ALRTFILTSEL)

is used to select one of these outputs to generate the

relevant alerts.

When the AMENDFILT bit is deasserted, the ADC acquisi-

tion in the ALU is not transferred into the IIR accumulator

at the end of the scan sequence. This setting should be

used for diagnostic operations which disrupt the input data

or for operations which utilize a different measurement

path, as both operations would corrupt the normal data.

Examples of measurement modes which disrupt the input

data are when the cell test current sources or HVMUX

test current sources are enabled using the CTSTEN bit

and MUXDIAGEN bits respectively. Alternatively, when

AMENDFILT is asserted, the ADC acquisition in the ALU

is automatically scaled and transferred into the IIR accu-

mulator at the end of the scan sequence.

When ALRTFILTSEL=0, the raw sequencer outputs are

used. This data source is used to assert all related alert bit

assertions, calculate MINMAXCELL and TOTAL registers,

and cell mismatch MSMTCH checks.

When ALRTFILTSEL=1, the IIR filtered data is used. This

IIR data is used to assert all related alert bit assertions,

calculate MINMAXCELL and TOTAL registers, and cell

mismatch MSMTCH checks.

Regardless of the ALRTFILTSEL settling, DIAG1 and

DIAG2 register always come from the unfiltered sequenc-

er outputs.

The RDFILT bit determines if IIR filtered data or normal

acquisition data is read from the output data registers is

issued (CELLn and BLOCKREG). See the Single-Buffer

Mode and Double-Buffer Mode sections for details on

how the RDFILT affects data transfer.

IIR Initialization

When IIR operation is engaged, the data to be oper-

ated upon initially is controlled by the Sequencer IIR

Initialization Request bit (SCANIIRINIT).

Note: If DBLBUFEN=0 and SCAN=1, the ALU results

are loaded into the IIR automatically at the end of the

requested measurement sequence.

By default, SCANIIRINIT=0, IIR filter is in continuation

mode. In Continuation mode, the current value in the IIR

accumulators is kept (presumably from previous cell mea-

surements) and sequencer measurements are amended

normally.

If DBLBUFEN=1 and SCAN=1, the ALU results are

loaded into the IIR automatically at the beginning of the

following sequence.

Table 27. IIR Data-Control Settings

AMENDFILT

RDFILT

USAGE

0

IIR Filter Disabled

Potential Stale-Data Fetch

0

1

IIR is not updated but IIR results read.

Note: This operation is not recommended.

Reads Current Unﬁltered Acquisition Data:

IIR is updated but current acquisition read.

See the Out-of-Scan Data Transfer section for information on reading both ﬁltered and

unﬁltered results

1

0

1

IIR Filter Updated and IIR Filter Read

Maxim Integrated │ 88

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

When SCANIIRINIT=1, IIR filter is in initialization mode. In Initialization mode, the IIR accumulators be reinitialized to the

first measurement taken, and further cell-balancing measurements are amended normally.

Single-Buﬀer Mode

Single-buffer Mode (Figure 37) is activated when DBLBUFEN=0. In this mode data is moved to the CELLnREG,

AUXnREG, BLOCKREG, DIAG1REG, DIAG2REG, TOTALREG, and MINMAXCELL registers at the end of the scan

indicated by SCANDONE=1 and DATARDY=1.

SINGLE-BUFFER DATA TRANSFER: DBLBUFEN= 0 , RDFILT= 0

SCAN=1

SCANDONE=1

SCAN=1

SCANDONE=1

TIME

SCAN SEQUENCE # 1

IDLE

SCAN SEQUENCE # 2

IDLE

ALU DATA

MEASUREMENT RESULTS

TRANSFERED

MEASUREMENT RESULTS

TRANSFERED

DATA REGISTER

MEASUREMENT RESULTS FROM SCAN #2

MEASUREMENT RESULTS FROM SCAN #1

SINGLE-BUFFER DATA TRANSFER: DBLBUFEN=0, RDFILT=1

SCAN=1

SCANDONE=1

SCAN=1

SCANDONE=1

TIME

SCAN SEQUENCE # 1

IDLE

SCAN SEQUENCE # 2

IDLE

IIR DATA (POST FILTERING)

MEASUREMENT RESULTS

TRANSFERED

MEASUREMENT RESULTS

TRANSFERED

DATA REGISTER

MEASUREMENT RESULTS FROM SCAN #2

MEASUREMENT RESULTS FROM SCAN #1

Figure 37. Single-Buffer Data Transfer

Maxim Integrated │ 89

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Double-Buﬀer Mode

With DBLBUFEN = 1, the Double Buffer Mode, Figure 38, is activated. In this mode data is moved to the CELLnREG,

AUXnREG, BLOCKREG, DIAG1REG, DIAG2REG, TOTALREG, and MINMAXCELL registers at the start of the next scan

when SCAN = 1 and is indicated by DATARDY = 1. This allows the host to read data from the last scan while the cur-

rent scan is in progress. In the event that a final measurement is requested prior to a sleep or shutdown event, the host

would need to issue another SCAN request to force the data transfer from the last acquisition or move the data through

the Out-of-Scan data transfer method.

DOUBLE-BUFFER DATA TRANSFER: DBLBUFEN=1, RDFILT=0

SCAN=1

SCANDONE=1

SCAN=1

SCANDONE=1

SCAN=1

SCANDONE=1

TIME

SCAN SEQUENCE # 1

IDLE

SCAN SEQUENCE # 2

IDLE

SCAN SEQUENCE # 3

ALU DATA

MEASUREMENT RESULTS

TRANSFERED

MEASUREMENT RESULTS

TRANSFERED

DATA REGISTER

MEASUREMENT RESULTS FROM SCAN #1

MEASUREMENT RESULTS FROM SCAN #2

DOUBLE-BUFFER DATA TRANSFER: DBLBUFEN=1, RDFILT=1

SCAN=1

SCANDONE=1

SCAN=1

SCANDONE=1

SCAN=1

SCANDONE=1

TIME

SCAN SEQUENCE # 1

IDLE

SCAN SEQUENCE # 2

IDLE

SCAN SEQUENCE # 3

IIR DATA (POST FILTERING)

MEASUREMENT RESULTS

TRANSFERED

MEASUREMENT RESULTS

TRANSFERED

DATA REGISTER

MEASUREMENT RESULTS FROM SCAN #1

MEASUREMENT RESULTS FROM SCAN #2

Figure 38. Double-Buffer Data Transfer

Maxim Integrated │ 90

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Upon writing CBSCAN (and after any auto cell-balancing

Out-of-Scan Data Transfer

measurement operation in complete), all enabled con-

version parameters are updated in the CELLnREG,

AUXnREG, BLOCKREG, DIAG1REG, DIAG2REG,

TOTALREG, and MINMAXCELL output registers. See the

Cell Balancing section for further detail.

Out-of-Scan data transfer occurs in the period after a scan

is complete, indicated by SCANDONE=1, and before a

new scan request, SCAN=1, is issued by the host. Since

data exists in both the ALU and IIR accumulator but only

one set is transferred to the data registers depending on

the RDFILT setting, this procedure allows access to the

other set of data that was not transferred to the data reg-

isters. By setting DATARDY=0, RDFILT=0 and SCAN=0,

data from the ALU is transferred to the data registers. By

setting DATARDY=0, RDFILT=1 and SCAN=0, data from

the IIR accumulator is transferred to the data registers.

Measurement Alerts

After the acquisition, the ALU compares the enabled

measurement data to the enabled OV/UV thresholds

for both measurement paths (ADC and Comparator) as

shown in Table 28. If outside of the configured threshold,

the associated alert bit is set during data transfer into the

ALU or IIR ALU blocks. In the event that calibration is

enabled using the ADCCALEN bit, the digital correction is

performed prior to the alert generation. This ensures that

the alert is generated from the correct accuracy results.

IfanOut-of-ScandatatransferisissuedtheMINMAXCELL,

TOTAL, and MSMTCH registers are not updated when

changing RDFILT and SCAN=0. Additionally, Out-of-

Scan alert processing not be updated when changing

ALRTFILTSEL and SCAN=0. If updated data process-

ing is required a new acquisition (SCAN=1) must be

requested.

Note: The ALRTFILTSEL bit for the IIR data control deter-

mine if the alerts be generated upon filtered or unfiltered

data.

Cell Balancing with

The data control settings impact the management of alert

signaling. The aforementioned alert handling details the

Single Buffer Mode data control. Since Double Buffered

Mode allow for simultaneous data offload and acquisi-

tion, it is recommended to read alert status after the

SCANDONE for the current acquisition and prior to initiat-

ing the next acquisition.

Embedded-Measurement Data Control

The data control for cell balancing with embedded

measurements is controlled by the CBSCAN bit in the

BALDATA register. This bit acts as a strobe, and the

CBSCAN bit content is automatically cleared, reading

back a logic zero when polled.

Table 28. Measurement Alerts

CONDITION OR

DESCRIPTION

SIGNAL PATH

ALERT BIT

LOCATION

STATUS1,

ALRTSUM,

ALRTOVCELL

RESULT

ALRTCELLOVST,

ALRTADCOVST,

ALRTOVn

V

- V

> V

Cn

Cn-1 OVTHSET

Cell overvoltage (OV)

ADC

for POLARITYn=0

ALRTCELLOVST,

ALRTADCOVST,

ALRTCOMPOVn

STATUS1,

ALRTSUM,

ALRTCOMPOVREG

Cell overvoltage (OV)

Cell undervoltage (UV)

COMP

ADC

V

- V

> V

< V

Cn

Cn-1

COMPOVTH

ALRTCELLUVST,

ALRTADCUVST,

ALRTUVn

STATUS1,

ALRTSUM,

ALRTUVCELL

Cn

Cn-1

UVTHSET

for POLARITYn=0

ALRTCELLUVST,

ALRTADCUVST,

ALRTCOMPUVn

STATUS1,

ALRTSUM,

ALRTCOMPUVREG

COMP

V

- V

< V

Cn

Cn-1

COMPUVTH

ALRTCELLOVST,

ALRTADCOVST,

ALRTOVn

STATUS1,

ALRTSUM,

ALRTOVCELL

Bipolar cell/bus-bar

overvoltage (OV)

V

- V

> V

Cn

Cn-1

BIPOVTHSET

ADC ONLY

for POLARITYn=1

Maxim Integrated │ 91

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 28. Measurement Alerts (continued)

CONDITION OR

DESCRIPTION

SIGNAL PATH

ALERT BIT

LOCATION

STATUS1,

ALRTSUM,

ALRTUVCELL

RESULT

ALRTCELLUVST,

ALRTADCUVST,

ALRTUVn

Bipolar Cell/Bus-bar

undervoltage (UV)

V

- V

< V

Cn

Cn-1 BIPUVTHSET

ADC Only

for POLARITYn=1

Block overvoltage (OV)

ADC Only

V

> V

< V

- V

ALRTBLKOV

ALRTBLKUV

ALRTMSMTCH

STATUS1

BLK

MAX

BLKOVTHSET

Block undervoltage

(UV)

BLKUVTHSET

Cell Mismatch

> V

MSMTCH

MIN

n where V

Unipolar if MINMAXPOL=0

else Bipolar

= V

MIN

CELLn

Cell with minimum

voltage

ADC Only

None

MINMAXCELL

n where V

Unipolar if MINMAXPOL=0

else Bipolar

= V

MAX

CELLn

Cell with maximum

voltage

ADC Only

ADC

None

MINMAXCELL

TOTAL

Σ V

for n=1 to

CELLn

Total of all Cell voltages

TOPCELL1/2

ALRTAUXOVST,

ALRTADCAUXOVST,

ALRTAUXOVn

STATUS1,

ALRTSUM,

ALRTAUXOV

AUXINn overvoltage

(undertemperature)

V

> (V

or

AUXINn

AUXAOVTHSET

AUXROVTHSET

)

ALRTAUXOVST,

ALRTCOMPAUXOVST, ALRTSUM,

ALRTCOMPAUCOVn

STATUS1,

AUXINn overvoltage

(undertemperature)

V

OR V

> (V

AUXINn

COMPAUXROVTH

COMP

ADC

)

COMPAUXAOVTH

ALRTCOMPAUXOV

ALRTAUXUVST,

ALRTADCAUXUVST,

ALRTAUXUVn

STATUS1,

ALRTSUM,

ALRTAUXUV

AUXINn undervoltage

(overtemperature)

V

< (V

AUXINn

AUXRUVTHSET

OR V

)

AUXAUVTHSET

ALRTAUXUVST,

ALRTCOMPAUXUVST, ALRTSUM,

ALRTCOMPAUCUVn ALRTCOMPAUXUV

STATUS1,

AUXINn undervoltage

(overtemperature)

V

OR V

< (V

AUXINn

COMPAUXRUVTH

COMP

)

COMPAUXAUVTH

Table 29. Set- and Clear-Threshold Selection

OVERVOLTAGE

THRESHOLD

UNDERVOLTAGE

THRESHOLD

DESCRIPTION

SIGNAL PATH

OV HYSTERESIS

UV HYSTERESIS

Cell

ADC

COMP

ADC

OVTHSET

UVTHSET

COMPUVTH

BIPUVTHSET

BLKUVTHSET

OVTHCLR

Not Applicable

BIPOVTHCLR

BLKOVTHCLR

UVTHCLR

COMPOVTH

BIPOVTHSET

BLKOVTHSET

Not Applicable

BIPUVTHCLR

BLKUVTHCLR

Bus bar

Block

ADC

Maxim Integrated │ 92

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

set threshold to full-scale, or setting the undervoltage set

Voltage Alerts

threshold to zero-scale, effectively disables voltage alerts

independent of the ALRTOVEN and ALRTUVEN.

The ALRTOVEN and ALRTUVEN registers are config-

ured to enable voltage alerts for the CELL and Block

inputs. These alerts have programmable OV and UV set

thresholds as well as programmable OV and UV clear

thresholds allowing for programmable hysteresis in both

OV or UV measurements as mentioned in below Table 29.

This is beneficial for the programming of alert detection in

lithium ion cells where the different characteristics at fully

charged and discharged states.

Alert conditions for the individual ADC Cell inputs are sum-

marized using the ALRTADCOVST and ALRTADCUVST

bits in the ALRTSUM register and occur when any alert

bit is set in the ALRTOVCELL or ALRTUVCELL reg-

isters, respectively. Similarly, alert conditions for the

individual Comparator Cell inputs are set using the

ALRTCOMPOVST and ALRTCOMPUVST bits in the

ALRTSUM register when any alert bit is set in the

ALRTCOMPOVREG or ALRTCOMPUVREG registers,

respectively. To ease identification of any OV or UV

alerts, both ADC summary alerts and Comparator sum-

mary alerts are further logically OR'ed and summarized

in the ALRTCELLOVST and ALRTCELLUVST bits in

the STATUS1. This enables the alert information to get

propagate using the hardware alert interface or the data

check byte.

Overvoltage alerts in the ALRTOVCELL or

ALRTCOMPOVREG registers are set when the CELLn

voltage exceeds the programmed threshold voltages

V

and V

respectively. Alternatively,

OVTHSET

COMPOVTH

undervoltage alerts in the ALRTUVCELL and

ALRTCOMPUVREG registers are set when the CELLn volt-

age exceeds the programmed threshold voltage V

UVTHSET

and V

respectively. It is important to note that

COMPUVTH

due to the different resolutions of the ADC and compara-

tor (described in the ADC Input Range and Comparator

Input Range sections) the user may experience a condition

where the alert for the ADC may be set while the alert for

the comparator my be cleared and vice versa.

Alert conditions for the Block input are directly sum-

marized using the ALRTBLKOVST and ALRTBLKUVST

bits in the STATUS1 register when the acquired BLOCK

voltage is over V

respectively.

or under V

BLKOVTHSET

BLKUVTHSET

Note: ADC alerts provide the most accurate indications

of the acquisition.

If an alert does not need to be propagated using the alert

interface or data check byte, these can be individually

masked. See the Alert interface for further details on the

masking.

Alerts are cleared when the cell voltage moves in the oppo-

site direction and crosses the OVTHCLR, COMPOVTH

and UVTHCLR, COMPUVTH thresholds.The voltage must

cross the threshold; if it is equal to a threshold, the alert

flag does not change. Therefore, setting the overvoltage

The cell and block voltage hysteresis diagram is as shown

in below Figure 39.

V

OVERVOLTAGE ALERT

SET

OVERVOLTAGE SET AND CLEAR

THRESHOLDS

POR DEFAULT VALUE (+5.0V)

OVERVOLTAGE SET THRESHOLD

(OVTHRSET)

OVERVOLTAGE CLEAR THRESHOLD

(OVTHRCLR)

OVERVOLTAGE

ALERT

CLEARED

CELL_N

VOLTAGE

UNDERVOLTAGE

ALERT

UNDERVOLTAGE CLEAR THRESHOLD

(UVTHCLR)

CLEARED

UNDERVOLTAGE SET THRESHOLD

(UVTHRSET)

UNDERVOLTAGE

ALERT

UNDERVOLTAGE SET AND CLEAR

THRESHOLDS

POR DEFAULT VALUE (+0.0V)

SET

T

Figure 39. Cell Voltage-Alert Thresholds

Maxim Integrated │ 93

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The measured values after the acquisition reads 2V, 2V,

Cell Mismatch

-1V, and 2.5V, respectively.

Enable the mismatch alert to signal when the mini-

mum and maximum cell voltages differ by more than a

specified voltage. The MSMTCHREG register sets the

The TOTALREG register reads:

TOTALREG = 2 + 2 -1 +2.5 = 5.5V

14-bit threshold (V

) for the mismatch alert,

MSMTCHREG

The MINCELL bitfields read CELL1 and the MAXCELL

register read CELL4.

ALRTMSMTCH. WheneverV

-V

>V

,

MAX MIN

MSMTCHREG

then ALRTMSMTCH = 1. The alert bit be cleared when a

new acquisition does not exceed the threshold condition.

To disable the alert, write 3FFFh to the MSMTCHREG

register bitfield (default value).

Temperature Alerts

The ALRTAUXOVEN and ALRTAUXUVEN registers are

configured to enable the temperature alerts for the

enabled AUXn inputs. Like the cell-voltage alerts, the

temperature alerts have programmable OV and UV set

thresholds, as well as programmable OV and UV clear

thresholds, to provide user-programmable hysteresis to

avoid unwanted alerts in the presence of measurement

noise, as shown in Table 30.

Cell Statistics

The cell numbers corresponding to the lowest and highest

enabled voltage measurements are stored in the MINCELL

and MAXCELL bitfields. When multiple cells have the same

minimum or same maximum voltage, only the lowest cell

position having that voltage is reported. For acquisitions

with no enabled cell inputs, the MINCELL and MAXCELL

bitfields, and the TOTALREG register are not updated.

Overvoltage alerts in the ALRTAUXOVEN or

ALRTCOMPAUXOV registers are set when the AUXn

voltage exceeds the programmed threshold volt-

The RDFILT bit determines the source data (filtered/unfil-

tered) used for the MINCELL and MAXCELL bitfields, and

the TOTALREG register.

ages of V

or V

, and

, respectively.

AUXAOVTHSET

AUXROVTHSET

V

or V

COMPAUXAOVTH

COMPAUXROVTH

The appropriate threshold used is determined by the

AUXREFSEL bits which can be different per channel.

Alternatively, undervoltage alerts in the ALRTAUXUVREG

and ALRTCOMPAUXUVREG registers are set when

the AUXn voltage exceeds the programmed thresh-

The MINMAXPOL bit ensures that only like measure-

ments are used for the statistical processing of MINCELL,

MAXCELL and ALRTMSMTCH. This ensures that bus bars

do not affect the cell statistics in mixed-mode acquisitions.

When MINMAXPOL = 0 only unipolar measurements are

used. When MINMAXPOL = 0b1, only bipolar mearure-

ments are used upon unipolar or bipolar measurements.

old voltage V

or V

, and

AUXUVTHSET

AUXRUVTHSET

V

or V

, respectively. It

COMPAUXRUVTH

COMPAUXAUVTH

is important to note that due to the different resolutions

of the ADC and comparator (described in the ADC Input

Range and Comparator Input Range sections), the user

may experience a condition where the alert for the ADC

is set, while the alert for the comparator is cleared, and

vice versa.

Note: For lithium-ion applications, MINMAXPOL should be

configured for unipolar statistics, while fuel-cell application

should be configured for bipolar statistics.

The sum of all enabled cell voltages, irrespective of the

POLARITY configuration, are stored in the TOTALREG

register as a 16-bit value.

Note: An OV alert for the ratiometric acquisition signal an

undertemperature (UT) event for the NTC measurement

and an UV alert signal an overtemperature (OT) event for

the NTC measurement.

Example:

Assume four cell inputs are enabled (CELL1, CELL2,

CELL3, and CELL4, where CELL1 and CELL2 are config-

ured as unipolar, CELL3 is bipolar, and CELL4 is unipolar.

Table 30. Temperature-Alert Threshold

OVERVOLTAGE

THRESHOLD/UNDER THRESHOLD/OVER

UNDERVOLTAGE

SIGNAL

HYSTERESIS

DESCRIPTION

TYPE

PATH

ADC

OV

UV

TEMPERATURE

AUXROVTH-

CLR

AUXINn

Ratio metric

Absolute

AUXROVTHSET

AUXRUVTHSET

AUXRUVTHCLR

AUXAUVTHCLR

AUXAOVTH-

CLR

AUXAOVTHSET

AUXAUVTHSET

AUXINn

COMP

Ratiometric

Absolute

COMPAUXROVTH

COMPAUXAOVTH

COMPAUXRUVTH

COMPAUXAUVTH

Not Applicable

Maxim Integrated │ 94

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Alerts are cleared when the cell voltage moves in the

opposite direction and crosses the AUXROVTHCLR,

AUXAOVTHCLR and AUXRUVTHCLR, AUXAUVTHCLR

thresholds. The voltage must cross the threshold; if it

is equal to a threshold, the alert flag does not change.

Therefore, setting the overvoltage set threshold to full-

scale, or setting the undervoltage set threshold to zero-

scale, effectively disables voltage alerts independent of

the ALRTAUXOVEN and ALRTAUXUVEN.

selected and started, the device remains in this mode until

a new value is written to CBMODE, or until a successful

exit criteria is achieved from all enabled conditions (UV

threshold, timer, and thermal).

To determine the current state of cell balancing, the

CBACTIVE bits can be polled using the BALCTRL,

BALSTAT or BALUVSTAT registers. The current timer

value can be read through CBTIMER, a 1Hz alive counter

can be read through CBCNTR. The timer units (i.e., sec-

ond, minute, hour) can be read through CBUINT. These

status registers are only cleared when CBMODE is writ-

ten to a new mode or disabled. The combination of these

bitfields allow for user verification that the cell balancing

machine is responsive, meanwhile an internal health

check is performed prior to verify a hardware integrity

prior to balancing. ALRTCBTIMEOUT notifies the user a

health check failure (if one is found).

Alert conditions for the individual ADC auxiliary inputs

are summarized using the ALRTADCAUXOVST and

ALRTADCAUXUVST bits in the ALRTSUM register and

occur when any alert bit is set in the ALRTAUXOV or

ALRTAUXUV bitfields, respectively.

Note: The ALRTSUM alert status does not specify the

auxiliary input measurement mode in AUXREFSEL, how-

ever, this can be determined from polling the alert channel

within ALRTAUXOV or ALRTAUXUV

Once a CBMODE mode is selected and started, the

device remains in this mode until a new value is written

to CBMODE. Note that all CBMODE active operations

automatically end due to either timer expiration(s), ther-

mal faults, and/or cell UV thresholds being met. In these

cases, the CBMODE is still engaged, although the bal-

ancing operation is ended (the status of the operation can

be checked by reading the BALSTAT and BALUVSTAT

registers).

Similarly, alert conditions for the individual comparator

auxiliary inputs are set using the ALRTCOMPAUXOV and

ALRTCOMPAUXUV bits in the ALRTSUM register when

any alert bit is set in the ALRTCOMPAUXOVSTREG or

ALRTCOMPAUXUVREG registers, respectively.

To ease identification of any OV or UV alerts, both ADC

summaryalertsandComparatorsummaryalertsarefurther

logically OR'ed and summarized in the ALRTAUXOVST

and ALRTAUXUVST bits in the STATUS1. This enables

the alert information to get propagated using the hard-

ware alert interface or the data check byte.

After cell balancing is initiated, write access to specific

cell-balancing registers is blocked; if a write to a blocked

register is attemped, it is ignored and the ALRTRJCT

flag set in the STATUS2 register. See Table 31 for spe-

cific register behavior. Note that blockage operations are

implemented at the register level.

Cell Balancing

Cell balancing can be performed using any combination

of the 14 internal cell-balancing switches according to the

programming of the enabled BALSWCTRL:BALSWEN

configuration and POLARITYCTRL configuration. Each

configured channel performs cell balancing according to

the configured operational mode, which includes manual

or automatic balancing-discharge control using a timer

and/or undervoltage threshold, as well as well as duty-

cycle configuration.

Notes: The CBRESTART is a strobe bit to manually

restart/refresh the watchdog timer during a cell-balancing

operation in manual mode. Although this can be written in

other balancing modes, no internal action is taken.

Writes to the BALSWEN bitfields during manual Cell-

Balancing mode are expected and supported.

Writes to BALAUTOUVTHR with CBUVMINCELL=1 are

rejected if a measurement scan is in progress (since

data from the last completed scan is used to populate

CBUVTHR).

Cell-Balancing Mode Conﬁgurations

Cell balancing is initiated using the CBMODE bits in

the BALCTRL register. This selection defines automatic

versus manual balancing control, channel timer configu-

ration, and timer resolution. Once a CBMODE mode is

Any value rewritten to CBMODE other than 000 (disable)

restarts the CBTIMER at zero and relaunches the request-

ed mode of operation.

Maxim Integrated │ 95

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 31. Cell-Balancing Register Write Behavior when Cell Balancing is Selected

AUTO (INDIVIDUAL OR

GROUP) MODE (1xx)

EMERGENCY-DISCHARGE

MODE (001)

MANUAL MODE (01x)

Data

Write

Data

Write

Data

Write

REGISTER

BITFIELD

ALRT-

RJCT

Status

ALRT-

RJCT

Status

ALRT-

RJCT

Status

applicable accepted

in this

mode?

applicable accepted

in this

mode?

applicable accepted

in this

mode?

in this

mode?

in this

mode?

in this

mode?

CBRESTART

BALSWEN

BALEXP1

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

BALSWCTRL

BALEXP1

1

—

1

BALEXP2-14 BALEXP2-14

Yes

—

Yes

—

CBUVTHR

No

BALAUTOU-

1

—

1

CBUVMIN-

VTHR

Yes

No

Yes

No

Yes

CELL

CBNTFYCFG

BALDLYCTRL

Yes

No

Yes

No

CBCALDLY

Notes: Writing 1 to CBRESTART after the cell-balancing

timer expiration has no effect. To perform another manual-

mode cell-balancing event, the user must issue a separate

write to the BALCTRL register.

Manual Mode

In manual mode, balance switches (BALSWn) are con-

trolled directly by BALSWEN[14:1] with a watchdog time-

out set by CBEXP1 as follows:

Manual balancing allows for adjacent balancing switches

to turn on simultaneously according to the application

requirement. Enabling adjacent balancing switches simul-

taneously under manual Cell-Balancing mode increases

the balancing current significantly, so care must be taken

not to exceed the device’s maximum operating conditions.

BALSWn = BALSWEN[n] & (CBTIMER ≤ CBEXP1) &

~(AUTOBALSWDIS & measurement in progress)

CBTIMER is incremented on a real-time basis, regard-

less of BALSWEN settings or suspensions for ADC or

CAL events. This means the watchdog timeout is set in

CBEXP1 once manual cell balancing is initiated.

AUTOBALSWDIS Feature

Manual cell-balancing operations can be temporarily sus-

pended during measurements using theAUTOBALSWDIS

feature.

Configuring AUTOBALSWDIS=1 automatically disables

the balancing switches (in manual Cell-Balancing modes

only) during measurements to eliminate the additional

voltage drop caused due to the cell-balancing application

circuit. This ultimately allows the system to achieve higher

accuracy cell measurements to help calculate higher

accuracy of state-of-charge (SOC).

In certain instances, as defined by the AUTOBALSWDIS

operation or other manual diagnostic operation, the user

may wish to have explicit control of the BALSWEN without

wanting to refresh the CBTIMER watchdog. In this case,

the user can configure CBEXP1=3FFh to disable the

timer. Thus, balancing will be controlled only using the

BALSWEN; this is also equivalent to the cell-balancing

behavior supported in Maxim legacy battery-management

devices.

Measurement settling-time control for cell measurement

(CELLDLY) and BALSW diagnostic/ALTMUX (SWDLY) is

configured in the BALSWDLY register. These delay regis-

ters provides programmable settling (wait) times from 0µs

up to 24.57ms, in steps of 96μs, between the time when

the acquisition is enabled and the start of actual measure-

ment to allow for the external application circuit to settle to

accurate voltages. In the BALSWDLY register, CELLDLY

is the upper 8-bit delay setting for cell-recovery time while

SWDLY is the lower-delay setting for certain diagnostics

CBRESTART is provided as a means to refresh the active

balancing switches or the watchdog timer during normal

BALSWn cycling operations. CBUVTHR exit settings are

ignored, measurements and calibrations operations are

requested through normal scan-control registers allowing

for simultaneous measurements and balancing.

Maxim Integrated │ 96

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

such as sense-wire open. When AUTOBALSWDIS=1

and ALTMUXSEL=0, CELLDLY is selected. When

AUTOBALSWDIS=1 and ALTMUXSEL=1, SWDLY is

selected. Hence, this feature can be used during normal

cell measurements as well as during diagnostic measure-

ments with two separate delay timers that can be inde-

pendently set. Any write to the BALSWDLY register be

ignored, signaled by ALRTRJCT, while a measurement

sequence or an automated Cell-Balancing mode is active.

Manual Cell-Balancing Mode with FlexPack

During manual cell balancing, the top two consecutive

cells should not be enabled for manual cell balancing. This

creates a situation where SW

, SW

,

TOPCELL1/2

TOPCELL1

and SW

could potentially all be 5V below the

TOPCELL2

TOPCELL1/2 cell input voltage. Although, the MAX17853

digital logic does not prevent users from using such a

configuration, ALRTHVUV is expected to trip and the

TOPCELL1/2 cell input measurements will not be valid.

Note: The appropriate delay time is dependent on the

application circuit and the level of accuracy required. For

the typical application circuit on the cell input, utilizing a

input filter network of 1kΩ and 0.1μF, it is recommended

to choose a settling time of 960μs to achieve calibrated

accuracy specified in the Electrical Characteristics table.

Auto-Individual Mode

Auto-individual mode performs cell balancing in a con-

trolled manner so that the cells can be individually dis-

charged for a duration and/or to a specific voltage level,

as required in the end application. The host initiates

an auto-individual mode by setting CBMODE to 0b100

(duration is seconds) or 0b101 (duration in minutes), con-

figuring CBEXPn to the desired value (where the LSB =

1 second or minute, respectively), and setting individual

BALSWENn bits, a group voltage target can also be set

using CBUVTHR.

Note: AUTOBALSWDIS affects cell-balancing switch

behavior in manual Cell-Balancing modes only.

Note: The cell-balancing timer incrementing/expiration

behavior is not affected by the AUTOBALSWDIS setting.

HOST

BALSWEN[n]

ONE ADC ACQUISTION

MEASUREMENT

AUTOBALSWDIS=11

AUTOBALSWDIS=1

BALSWN

Figure 40. Logic Diagram when Balancing Switches are Disabled

Maxim Integrated │ 97

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

t

4

1

2

3

BALSW ON

ACQUISITION

BALSW OFF

ACQUISITION

Figure 41. AUTOBALSWDIS Measurement Settling

In auto-individual mode, the balancing switches defined

by BALSWEN[n] are automatically controlled through

non-overlapping even/odd cycling in accordance with the

programmable timer duration (CBEXPn) and/or the under-

voltage threshold (CBUVTHR). The balancing switch duty

cycle can further be controlled using CBDUTY to pro-

grammatically set the average balancing current. This is

indicated below:

for 1 hour and the CBDUTY=100%, the associated timers

would be set accordingly and the operation would last

for ~2 hours (accounting for non-overlap timing). If the

CBDUTY is now set to 50% with the same timer settings,

the total operation time would extend to ~4 hours.

The read-only counter (CBCNTR) increments at a 1Hz

rate with periodic rollover at 0b11. The host can read this

counter periodically to confirm the auto-individual mode

is active.

Even Cells (2, 4, ... 14):

BALSWn = BALSWEN[n] & (CBTIMER ≤ CBEXPn)

& CBEVEN & ( ((CBMEASEN ==0b11) & (CELLn ≥

CBUVTHR)) | (CBMEASEN != 0b11))

SHDNL operation can be controlled by HOLDSHDNL,

preventing device shutdown during auto-individual mode

in case of an extended lapse in host communication.

Odd Cells (1, 3, ... 13):

Once initiated, auto-individual mode normally continues

to run until CBTIMER reaches max (CBEXPn) or all cells

reach the voltage CBUVTHR (whichever comes first,

depending on configuration settings), and at this point,

balancing-switch operations cease and CBACTIVE is set

to 0b10, indicating a normal exit condition. Cell balancing

checks that thermal, calibration, and watchdog faults apply

if enabled; if any of these conditions occur, switching activ-

ity is immediately halted and CBACTIVE is set to 0b11,

notifying the μC of the result. The cell balancing timer

(CBTIMER) continues to run until expiration (CBEXPn),

and HOLDSHDNL extensions are supported (if enabled).

This allows the μC to confirm the exit condition.

BALSWn = BALSWEN[n] & (CBTIMER ≤ CBEXPn)

& CBODD & ( ((CBMEASEN ==0b11) & (CELLn ≥

CBUVTHR)) | (CBMEASEN != 0b11))

CBUVTHR exit settings apply, and ADC measurement

and calibration operations can be performed if enabled to

support host-controller readback.

CBTIMER is incremented on a duty-cycled basis, indicat-

ing the time each channel is subject to discharge (i.e.,

one t

cycle out of each E/O/M discharge cycle). In

CBEO

real time, this means the discharge operation always runs

at least 2x the maximum value set in CBEXPn. As an

example, if both an even and odd cell must be balanced

Maxim Integrated │ 98

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

In Emergency-Discharge mode, all balance switches

Auto-Group Mode

(BALSWn) are enabled regardless of the BALSWEN[n]

settings, with a CBTIMER duration set by CBEXP1, and

governed by non-overlapping even/odd cycling, as follows:

The auto-group mode performs cell balancing in a con-

trolled manner so that the cells can be discharged as a

group for a duration and/or to a specific voltage level,

as required in the end application. The host initiates

auto-group mode by setting CBMODE to 0b110 (dura-

tion is seconds) or 0b111 (duration in minutes), configur-

ing CBEXP1 to the desired value (where the LSB = 1

second or minute, respectively), and setting individual

BALSWENn bits. A group voltage target can also be set

using CBUVTHR.

Even Cells (2, 4, ... 14):

BALSWn = (CBTIMER ≤ CBEXP1) & CBEVEN

Odd Cells (1, 3, ... 13):

BALSWn = (CBTIMER ≤ CBEXP1) & CBODD

CBUVTHR exit settings do not apply, but ADC measure-

ment and calibration operations can still be performed if

enabled to support host-controller readback.

In auto-group mode, the balancing switches defined by

BALSWEN[n] are automatically controlled through non-

overlapping even/odd cycling in accordance with the pro-

grammable timer duration (CBEXP1) and/or the under-

voltage threshold (CBUVTHR). The balancing-switch

duty cycle can further be controlled using CBDUTY to

programmatically set the average balancing current. This

is indicated as follows:

CBTIMER is incremented on a duty-cycled basis indicat-

ing the time each channel is subject to discharge (i.e.,

one t

cycle out of each E/O/M discharge cycle). In

CBEO

real time, this means the discharge operation always runs

at least 2x the maximum value set in CBEXP1. As an

example, if both an even and odd cells must be balanced

for 1hour and the CBDUTY=100% the associated timers

would be set to 0x3C and the operation would last for ~2

hours (accounting for non-overlap timing). If the CBDUTY

is now set to 50% with the same timer setting, the total

operation time would extend to ~4hours.

Even Cells (2, 4, ... 14):

BALSWn = BALSWEN[n] & (CBTIMER ≤ CBEXP1)

& CBEVEN & ( ((CBMEASEN ==0b11) & (CELLn ≥

CBUVTHR)) | (CBMEASEN != 0b11))

The read-only counter (CBCNTR) increments at a 1Hz

rate with periodic rollover at 0b11. The host can read this

counter periodically to confirm that Emergency-Discharge

mode is active.

Odd Cells (1, 3, ... 13):

BALSWn = BALSWEN[n] & (CBTIMER ≤ CBEXP1)

& CBODD & ( ((CBMEASEN ==0b11) & (CELLn ≥

CBUVTHR)) | (CBMEASEN != 0b11))

SHDNL operation can be controlled by HOLDSHDNL,

preventing device shutdown during Emergency-Discharge

mode due to the extended lapse in host communication.

Auto-group modes are identical to auto-individual modes

except all timer durations are checked against CBEXP1

(a single-expiration event).

Once initiated, Emergency-Discharge mode normally

continues to run until CBTIMER reaches CBEXP1. At this

point, balancing-switch operations cease and CBACTIVE is

setto0b10, indicatinganormalexitcondition. Cell-balancing

checks if thermal, calibration, and watchdog faults apply, if

enabled. If any of these conditions occur, switching activity

is immediately halted and CBACTIVE is set to 0b11,

notifying the μC of the result. The cell-balancing timer

(CBTIMER) continues to run until expiration (CBEXPn),

and HOLDSHDNL extensions are supported (if enabled).

This allows the μC to confirm the abnormal exit condition.

Emergency-Discharge Mode

Emergency-Discharge mode performs cell balancing in a

controlled manner so that the cells can be discharged in

the event of an emergency or battery end-of-life.

The host initiates the Emergency-Discharge mode by setting

CBMODE to 0b001, configures CBEXP1 to the desired value

(where the LSB = 1 hour). After Emergency-Discharge mode

is activated, battery cells are discharged until CBTIMER

expires or CBMODE is set to 0b000 (disabled).

Maxim Integrated │ 99

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Note: t

= 1/2 x timer resolution

Cell-Balancing Modes Summary

CBEO

Table 32 summarizes the Cell-Balancing modes sup-

ported by the MAX17853.

The measurement time (t

) includes the cell-

MEASUREMENT

balancing path recovery-delay selection (CELLDLY) and a

user-programmable delay determined by the external

application circuit, which is imposed after each pair of even/

odd discharge cycles. The other component to the mea-

surement time includes the physical time for ADC acquisi-

tion, as defined in the SCANCTRL register (OVSAMPL in

Cell-Balancing mode is non-programmable and fixed at 16

to ensure the highest accuracy measurements).

Auto-Even/Odd Cell Balancing

Auto-even/odd cell balancing controls the enabling of

adjacent balancing switches automatically with timing

resolution from 1s to 1hr depending on the CBMODE con-

figuration. This ensures that even or odd switches are not

enabled simultaneously, while balancing equally within

the balancing period. This allows the host to program the

BALSWEN bit once without having to adjust the balance

switches or timer period, which can be beneficial during

system low-power operational modes where the host

controller is asleep.

Note: CELLDLY is used in manual Cell-Balancing mode

whenusing AUTOBALSWDIS=0b1and ALTMUXSEL=0b0.

Also used in automated cell-balancing and discharge

modes after each pair of even/odd discharge cycles.

CBMODE=0x4, CBUVTHR=0x3FF

To prevent simultaneous channel conduction, a non-over-

=

lap period (t

1μs) is inserted between dis-

CMODE=5h, FLXPACK1/2=1, TOPCELL1/2=ODD

NONOVERLAP

abling one switch and enabling the adjacent switch. When

the UV threshold is disabled, the total cell-balancing period

Note: Figure 42 and Figure 43 are not drawn to exact

timescale; some sections have been exaggerated for

visibility.

is (t

+ t ) x 2. When the UV threshold is

NONOVERLAP

CBEO

enabled, the cell-balancing period is increased by the ADC

measurement time (t ). In this case, the

See the Cell-Balancing UV Detection section for further

details and recommendations for embedded measure-

ments during cell balancing.

MEASUREMENT

total cell-balancing period is (t

+ t ) x 2

NONOVERLAP

CBEO

+ t

.

MEASUREMENT

Table 32. Cell-Balancing Mode

RANGE OF CBEXPN[9:0]

TIMER

RESOLUTION

CBMODE[2:0]

DESCRIPTION

CBEXPN[9:0]

T

CBEO

MINIMUM

MAXIMUM

000b

001b

Cell Balancing Disabled

000h

—

Emergency/EOL

Discharge by Hour

001h to 3FFh

1hr

0.5min

—

1hr

1s

1022hrs

1022s

Manual-Cell Balancing

by Second

010b

011b

100b

101b

110b

111b

001h to 3FFh

1s

1min

1s

Manual-Cell Balancing

by Minute

—

1min

1s

1022mins

1022s

Auto-Individual Cell

Balancing by Second

0.5s

Auto-Individual Cell

Balancing by Minute

1min

1s

0.5min

0.5s

1min

1s

1022mins

1022s

Auto-Group Cell

Balancing by Second

Auto-Group Cell

Balancing by Minute

1min

0.5min

1min

1022mins

Note: t

CBEO

is the effective time that the even or odd switches are balanced within the timer resolutions.

Maxim Integrated │ 100

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

EVEN CELLS ENABLED

ODD CELLS ENABLED

0.5s

t

NONOVERLAP

t

NONOVERLAP

1s + (2 x t

)

NONOVERLAP

CELL BALANCING TIMER

INCREMENTED BASED ON

CBMODE AND CBDUTY

Figure 42. Auto Even/Odd Cell Balancing without UV Detection

ODD CELLS ENABLED

EVEN CELLS ENABLED

30.5µs

HVCP

RECOVERY

30s

CELLDLY

t

MEASUREMENT

t

NONOVERLAP

t

NONOVERLAP

1 min + 2 x t

+ CELLDLY + t

MEASUREMENT

NONOVERLAP

CELL BALANCING

TIMER INCREMENTED

BASED ON CBMODE

AND CBDUTY

Figure 43. Auto Even/Odd Cell Balancing with UV Detection, ADC with OVSAMPL

Maxim Integrated │ 101

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

When any CBEXPn is non-zero, the cell-balancing timer

Cell-Balancing Timer (CBTIMER)

runs and any requested measurement and calibra-

tion operations are performed until expiration, even if

BALSWEN[14:1]=000h (i.e., no balancing switches are

actually activated). This ensures that the μC can still

access the device to confirm balancing-operation prog-

ress and exit status.

Manual, Emergency Discharge, and Auto Group Mode

Timing: In manual, emergency discharge, and auto-group

modes, the CBEXP1 bitfield within the BALEXP1 register is

used as the cell-balancing timer duration setting. The dura-

tion can be configured from 1 to 1023 seconds, 1 to 1023

minutes, or 1 to 1023 hours depending on the CBMODE

setting (LSB = hour, minute, or second). A value of 0x3FF

allows the switches to be enabled indefinitely for CELLn if

BALSWENn is also enabled (CBTIMER mube active, and

rollover at 3FFh, but is not checked against CBEXP1). In

manual, emergency discharge, and auto- group modes,

the 10-bit timer (CBTIMER) counts up until it reaches the

duration set by BALEXP1. When the cell-balancing timer

expires, all cell-balancing switches are disabled.

If all 14 CBEXPn settings are 000h, no cell balancing

occurs for the switches.

General Timing and Safety Features (All Modes): For

safety concerns, all BALEXPn are defaulted to 0x000,

which ensures no cell balancing occurs without prior

configuration.

The CBTIMER runs to expiration, even if the active cell

balancing is halted due to UV- or thermal-exit conditions,

which that the μC can still access the part to confirm bal-

ancing-operation progress and exit status. If an extend-

ed SHDNL hold time is requested (HOLDSHDNL=1x),

CBTIMER reads back the governing CBEXP time for the

duration of the extended hold interval, allowing the μC to

confirm that the requested balancing operation has run to

completion.

When CBEXP1 is non-zero, the cell-balancing timer

(CBTIMER) runs and any requested measurement and

calibration operations are performed until expiration, even

if BALSWEN[14:1]=000h (i.e., no balancing switches are

actually activated), this ensures the μC can still access

the device to confirm balancing-operation progress and

exit status.

A value of CBEXP1=000h ensure no cell balancing occur.

CBRESTART Usage in Manual Mode

For safety concerns, all BALEXPn are defaulted to 0x000,

which ensures no cell balancing occurs without prior

configuration.

The CBRESTART bit within the BALSWCTRL register

must periodically be written to a 1 to restart the watchdog

timer and prevent the cell balancing switches from being

automatically disabled due to exiting Manual mode when

CBTIMER reaches CBEXP1. In the event that a host

fails to write the CBRESTART bit or forgets to disable the

cell balancing switches, the cell balancing watchdog can

automatically disable all cell balancing switches regard-

less of the BALSWEN configuration. The cell balancing

watchdog does not modify the contents of the BALSWEN

bits within the BALSWCTRL register.

Auto-Individual-Mode Timing: In auto-individual mode,

the CBEXPn bits within the BALEXPn registers are used

as individual cell-balancing duration times for each cor-

responding CELLn. Individual durations can be configured

from 1 to 1023 seconds, or 1 to 1023 minutes depending

on the CBMODE setting (LSB = minute, or second). A

value of 0x3FF allows the switches to be enabled indefi-

nitely for CELLn if BALSWENn is also enabled (CBTIMER

active and rollover at 3FFh, but is not checked against

CBEXPn). The 10-bit expiration timer (CBTIMER) counts

up until it reaches the maximum CBEXPn timeout value

in the register block (regardless of the BALSWENn set-

tings), governing the balancing operations of all balancing

switches. When an individual cell expiration time is reached

(determined by CBEXPn), the CELLn switch is disabled

going forward.

The CBRESTART bit is used in Manual Cell-Balancing

mode only. It provides a means to select new BALSW

settings and refresh the Watchdog timer with a single

command.

This bit is ignored and has no effect outside of an active

Manual Cell-Balancing operation. If a Manual operation

was selected and the timer is allowed to expire, the opera-

tion must be relaunched with a write to BALCTRL (i.e.,

CBRESTART will not reinitiate a Manual operation that

has allowed the CBTIMER to expire).

Maxim Integrated │ 102

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Emergency-Discharge Mode and CBDUTY Behavior

Notiﬁcation Alerts Using CBNTFYCFG

In Emergency-Discharge mode, he CBTIMER is incre-

mented on a duty-cycled basis, indicating the effective

time on each channel is subject to discharge. Since the

In automatic and discharge modes, the cell-balancing

notification alert (ALRTCBNTFY) can be issued to con-

firm normal progression of automated operations. The

frequency of issuance is 1 hour, 2 hours, or 4 hours, in

real time (i.e., not CBDUTY adjusted). Notification alerts

continue to be issued during HOLDSHDNL extension

periods.

active duty cycle within each 30s t

period is speci-

CBEO

fied by the CBDUTY register, the CBTIMER is increment-

ed at specified fractions of 30s (see Table 33).

For example, when CBDUTY is set to 1hr, CBTIMER is

incremented in 3.750s steps at the end of the E/O/M cycle.

Cell-Balancing Expiration Timer Summary

In summary, the implementation of the CBTIMER is

shown in Figure 44.

Table 33. Emergency-Discharge Mode

FUNCTION

REGISTER FIELD

CONFIGURATION

BEHAVIOR

Switches on for 6.25% for 30s (1.875s per 30s)

Switches on for 12.5% for 30s (3.750s per 30s)

…

0x0

0x1

…

Emergency-discharge

duty cycle

CBDUTY[3:0]

0xF

Switches on for 100% for 30s (less t

)

NONOVERLAP

Note: It is recommended to design the external balancing current at 100% duty-cycle operation to avoid potential thermal issues.

+0.5 x CBDUTY

TIMEOUT

CBTIMER

D

Q

1 SECOND

1 MINUTE

1 HOUR

=

CBEXPn

3FFh

CELLn TIMER EXPIRED

CBMODE

=

INDEFINITELY ENABLED

(HOLDS OUTPUT LOW, NEVER EXPIRED)

Figure 44. Cell-Balancing Expiration Timer

Note: The CELLn time-expired output feeds into the cell-balancing stop control logic.

Maxim Integrated │ 103

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

to the CBUVTHR in the BALAUTOUVTHR register. This

Cell-Balancing UV Detection

register allows for 14-bit values relating to a 305μV LSB.

Cell balancing to a UV threshold allows for all enabled cells

configured by BALSWEN to be individually balanced to a

specified and uniform voltage level, as shown in Figure 45.

When a cell reaches the UV threshold, the corresponding

balance switch is disabled and remains in an idle state until

reinitialized by the host.

Optionally, the MINCELL value from the prior ADC acqui-

sition can be used as the the desired threshold value.

When CBUVMINCELL is disabled, the value written to

CBUVTHR during a valid write to BALAUTOUVTHR be

loaded to CBUVTHR. When CBUVMINCELL is enabled

the current value in the CELL[n] register correspond-

ing to the MINCELL address be automatically loaded

to CBUVTHR during a valid write to BALAUTOUVTHR

(and the content in CBUVTHR during the write be

ignored). When the BALAUTOUVTHR register is read

back, the current value of CBUVTHR be provided, with

CBUVMINCELL indicating the means by which it was

selected.

Automated-cell balancing with CBUVTHR checking

is only supported for unipolar cell measurements in

locations with BALSWENn=0b1. The user must also

ensure CELLENn=0b1 and POLARITYn=0b0 to allow the

required measurement updates; if the measurement is not

supported, balancing of the cell automatically ends with a

CBUVSTATn=0b1 exit condition.

CBUVSTATn in the BALUVSTAT register indicates the

corresponding CELLn+1 result falls below the threshold

specified by CBUVTHR and that cell-balancing operations

on that cell have ended. CBUVSTAT[n] is only cleared

when CBMODE is written to 0b000 (disabled) or when a

new CBMODE operation is initiated through BALCTRL.

The HVMUX and ADC signal chain is used for the bal-

ancing measurement and threshold comparison. The

acquisition is determined by the channels enabled in the

BALSWEN bitfield as well as the parameters set in the

SCANCTRL register. The achievable accuracy of the UV

measurement will be determined by ADC accuracy speci-

fications in the electrical characteristics. For the highest

accuracy, calibration should be asserted prior to initiating

balancing.

Automated-cell balancing to a UV threshold is configured

by setting the CBMEASEN bits within the BALCTRL

register to 0b11. The UV threshold can be used indepen-

dently or along side the cell-balancing timer(s) (CBEXP1

or CBEXPn). In the case where a timer is programmed,

it serves as a redundant mechanism to ensure that a cell

is not over-discharged. When all cells have reached the

UV threshold, all cel-balancing switches will be disabled

but the cell-balancing timer runs until completion; this

ensures that the μC can still access the device to confirm

balancing-operation progress and exit status. To use a

defined UV threshold, the threshold level must be written

Note: CELL , CELL , CELL , and CELL are non-specif-

A

B

C

D

ic cells. CELL represents the cell with the lowest starting

A

voltage. CELL represents the cell with the highest starting

D

voltage. In this example, CBUVTHR is the UV threshold for

all cells and CBEXP1 is the cell-balancing expiration timer

for auto-group Cell-Balancing mode (CBMODE=0b11x).

The CELL UV-threshold crossings are inputs to the cell-

N

balancing stop control logic.

CBEXP1

START CELL

D

c

START CELL

B

A

CBUVTHR

CELL UV

A

CELL UV

B

CELL UV

C

CELL UV

D

TIME

Figure 45. Cell-Balancing UV-Threshold Crossing

Maxim Integrated │ 104

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the CBIIRINIT bit should be used to initialize the IIR with

Cell-Balancing Measurement

the first acquisition's measurements to avoid falsely exit-

ing the UV threshold due to the long settling response.

How the filter behaves upon entry into an automatic or

emergency-discharge Cell-Balancing mode thus depends

on the CBIIRINIT setting:

Embedded cell-balancing measurements only occur when

requested by CBMEASEN, as indicated in Table 34.

CBMEASEN selections are only functional in discharge

and automated Cell-Balancing modes; this setting is

ignored in all other modes.

In continuation mode (CBIIRINIT=0), the current value in

the IIR accumulators are kept (presumably from previous

cell measurements), and cell-balancing measurements

amended normally.

Measurements are taken using the ADC with a fixed

OVSAMPL=16x, SCANMODE='pyramid' to provide the

highest accuracy measurements. All other scan param-

eters will be set according the current SCANCTRL,

ACQCFG, DIAGCFG, and POLARITYCTRL registers. Any

attempt to overwrite the scan parameters during balancing

be ignored and an ALRTRJCT condition be issued.

In initialization mode (CBIIRINIT=1), the IIR accumulators

are reinitialized to the first measurement taken, and fur-

ther cell-balancing measurements are amended normally.

CBUVTHR checking will not be enabled after the 16th

measurement is taken (checking begins on the 17th mea-

surement) which gives the IIR time to settle.

Cell-Balancing IIR Filtering

In auto-discharge and automated Cell-Balancing modes,

the automated ADC measurements are processed

through each of the individual cellss' IIR filter. This filter

allows for more accurate measurements and provides

noise immunity to maintain robust balancing performance.

Cell-Balancing Calibration

In automated and discharge modes, after each pair of

even/odd cell-balancing periods, a supervisory ADC mea-

surement can be taken (and checked against CBUVTHR,

if enabled/applicable, see CBMEASEN). Due to the

expected temperature rise during cell balancing, it is rec-

ommended to allow automated-calibration sequences to

be interleaved with the measurement acquisitions. This

is done by programming the CBCALDLY to a non-zero

value, which signifies how many measurement cycles are

taken prior to a calibration being taken (see Table 35)

In these modes, the IIR filter maintains the setting con-

figured by the user, if enabled (IIRFC!=0b111). In the

event that the IIR is not used in the normal application

(IIRFC=0b111 = 8/8), the IIR filter will be enabled with

an equivalent IIRFC=0b000 = 1/8 for use in debouncing

measurements.

Additionally, if the IIR filter is not used in normal applica-

tions or has not been routinely updated using AMENDFILT,

Table 34. Cell-Balancing Measurement Enable

CBMEASEN[1:0]

DESCRIPTION

Provides the highest duty cycling by skipping all measurement operations. Only cell-balancing timer(s) are

used to terminate cell balancing normally.

0b0x

0b1x

0b11

Enables embedded measurements for manual UV monitoring or supervision by the host processor.

Enables embedded measurements and internal CBUVTHR checks in automated modes (checking is not

supported in Emergency-Discharge mode).

Table 35. Cell-Balancing Calibration Selection

ADCCALEN

CBCALDLY

RESULTING OPERATION

(APPLY CALIBRATION) (PERFORM CALIBRATION)

ADC results are post-processed based on calibration coeﬃcients

obtained periodically during the cell-balancing operation.

1 (ON)

Non-Zero (ON)

000 (OFF)

ADC results are post-processed based on calibration coeﬃcients

obtained prior to the cell-balancing operation.

Calibration is performed during the cell-balancing operation, but ADC

results are based on factory defaults (not recommended).

0 (OFF)

Non-Zero (ON)

000 (OFF)

ADC results are based on factory defaults.

Maxim Integrated │ 105

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The CBCALDLY settings are only functional if

CBMEASEN=0b1x (cell-balancing measurements are

requested); otherwise they are ignored.

If ALRTCAL is set and calibration is enabled

(ADCCALEN=1), the ALRTCBCAL bit will be set and

active cell-balancing operations immediately halted to

prevent balancing errors due to inaccurate measure-

ments. All subsequent measurements, calibration, and

switching cycles are skipped until the cell-balancing

duration expires, or is otherwise aborted/restarted. The

cell-balancing timer (CBTIMER) continues to run until the

governing CBEXP time is reached, and HOLDSHDNL

extensions still apply (if enabled), allowing the μC to con-

firm exit status. Note that once ALRTCBCAL is issued,

data in the CBUVSTAT bitfields and data fetched by

CBSCAN requests should be considered compromised.

A value of 0x00 (default) in the CBCALDLY bits within the

BALDLYCTRL register disables CAL operations (only ADC

measurement operations are performed).

If a non-zero value is selected, the first ADC measurement

(ADC) operation is replaced with an on-demand calibra-

tion (CAL) operation. From that point on, this selection

determines how often the ADC operation is automatically

replaced with a CAL operation (to address thermal drift

due to power dissipation during cell balancing). 0b001

means ADC and CAL alternate every other cycle. 0b010

means a CAL occurs once every four cycles. 0b111 (maxi-

mum setting) means a CAL occurs once every 32 cycles.

See Table 36 for a list of all possible settings .

If an ALRTCAL/ALRTCBCAL condition is issued, the

user can exit the cell-balancing operation, and attempt to

resolve the condition. If the condition cannot be resolved,

cell-balancing operations can be requested using factory-

calibration defaults by setting ADCCALEN=0.

Calibration Out-of-Range During Cell Balancing

After a measurement or calibration is completed, the cell

balancer checks the status of the ALRTCAL register bit to

see if calibration is enabled (ADCCALEN=1). If ALRTCAL

is set, it indicates that calibration is out-of-range, and that

calibrated ADC results could be corrupted as a result.

Transfer-Measurement Results Using CBSCAN

The CBSCAN bit in the BALDATA[7:0] register can initi-

ate a manual transfer of results from the IIR to the CELLn

data registers (RDFILT is ignored, and IIR data is always

transferred, since the IIR governs cell-balancing opera-

tions). CBSCAN supports the readback of measurement

results taken during automated and emergency-discharge

Cell-Balancing modes. If CBSCAN is issued during these

cell-balance measurements, the move will be executed

once the sequence is completed.

Table 36. Calibration Frequency

CBCALDLY

0b000

CALIBRATION FREQUENCY

Periodic Calibration Disabled

2 cycles

0b001

CBSCAN acts as a strobe bit and therefore does not need

to be cleared (self-clearing). Always reads logic zero.

0b010

4 cycles

0b011

8 cycles

CBSCAN is not valid outside an automated cell-balanc-

ing operation. If automated cell balancing is stopped, or

when manual balancing is operational, the measurement

scan bitfields in the SCANCTRL register must be used

for data control in the CELLn registers.

0b100

12 cycles

0b101

16 cycles

0b110

24 cycles

0b111

32 cycles

CYCLYE 1

CYCLE 2

CBCALDLY = 0b000

Figure 46. Cell Balancing with No Calibration

Maxim Integrated │ 106

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Cell Balancing with Calibration

Cycle#1

Figure 47. Cell Balancing with Calibration

Cell-Balancing Completion

Cycle#2

CBCALDLY = 0b010

CBACTIVE allows confirmation of cell-balancing opera-

tion status. A cell-balancing operation is considered com-

pleted normally if the CBTIMER expires (all CB modes), or

when all enabled cells reach the programmed CBUVTHR

limit (automatic modes only, if CBMEASEN=1b1). A cell-

balancing operation is considered completed abnormally in

the event of an ALRTCBCAL or ALRTCBTEMP condition.

In summary, after the host initializes the cell-balancing

operation, the operation is stopped by any of the following:

● Watchdog-timer expiration (CBTIMER=CBEXPn)

● Reaching the UV threshold (per cell in automatic

mode only, if CBMEASEN=0b11)

● Thermal-fault condition (automatic and discharge

Note: The thermal fault limits the temperature rise to a

safe level below the maximum junction temperature of the

device, as defined by the ALRTTEMP specification in the

Electrical Characteristics table. For applications requiring

maximum cell-balancing current, this can be disabled, but

the system should take caution to ensure that the device

is not damaged by exceeding the absolute maximum

rated junction temperature.

modes only, if CBTEMPEN=0b1)

● Calibration-fault condition (automatic and discharge

modes only, if ADCCALEN=0b1)

● Aborting the operation by changing CBMODE to

0b000 (disabled)

● Re-initiating an operation by changing CBMODE to a

value other than 0b000

Automatic SHDNL Control Using HOLDSHDNL

Manual cell-balancing-mode switch activity can be tempo-

rarily suspended for calibration or ADC measurements if

AUTOBALSWDIS=0b1.

To allow for timed balancing with no host interaction, the

SHDNL pin can be pulled up to V to keep SHDNL high

AA

while the timers or UV detection is running, by appro-

priately configuring the HOLDSHDNL bitfield within the

BALCTRL[15:8] register. When enabled and engaged,

In discharge, manual, and auto-group modes, the

CBTIMER is stopped when it reaches CBEXP1, regard-

less of BALSWEN settings.

this mode activates an internal diode pullup from the V

AA

pin to SHDNL. This keeps the device operational, even

if UART operation is suspended for long periods of time.

In auto-individual modes, the CBTIMER is stopped when

it reaches MAX(CBEXPn), regardless of BALSWENn

settings.

The HOLDSHDNL options have no effect in disabled or

manual modes.

Automatic and discharge modes are halted if temperature

exit is enabled (CBTEMPEN=0b1) and an overtempera-

ture fault occurs.

In mode 0b01, the pullup will be engaged for the selected

CBEXP1 interval for group operations, or the longest

CBEXPn time selected for individual operations, even

if switch activity is halted due to thermal protection

(ALRTCBTEMP), calibration issues (ALRTCBCAL), or

reaching the specified voltage target (CBUVTHR).

Automatic and discharge modes are halted if

(CBMEASEN=0b1x) and a calibration fault occurs.

All timed modes run CBTIMER for the full duration speci-

fied, even if actual cell-balancing operations are stopped

due to UV or thermal-exit conditions, allowing the μC to

confirm the exit status. Additional time for the μC to check

exit status can be afforded using HOLDSHDNL options.

Maxim Integrated │ 107

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

MANUAL CELL-BALANCING

MODES

AUTOBALSWDIS

MEASUREMENT IN

PROGRESS

(TIMER NOT EXPIRED) &&

(UV THRESHOLD NOT CROSSED) &&

(THERMAL ALERT NOT TRIPPED) &&

(ADC NOT MEASURING)

TIMER ENABLED

CELLN TIMER EXPIRED

AUTOMATIC MODE ENABLED

UV THRESHOLD ENABLED

CELLn UV THRESHOLD CROSSED

BALSWN

BALSWEN[n]

(CELL-BALANCING THERMAL-EXIT ENABLE)

CBTEMPEN

(THERMAL ALERT TRIPPED)

ALRTTEMP

ENABLE CELLn BALANCING SWITCH IFF

ABOVE LOGIC IS TRUE && BALSWENN = 1

Figure 48. Cell-Balancing Stop Control

In mode 0b10, the pullup will be engaged for the selected

CBEXP1 interval for group operations, or the longest

CBEXPn time selected for individual operations, even

if switch activity is halted due to thermal protection

(ALRTCBTEMP), calibration issues (ALRTCBCAL), or

reaching the specified voltage target (CBUVTHR). After

CBTIMER expires, HOLDSHDNL continues to be held for

the larger of 5 minutes or 6.25% of the relevant CBEXPn

interval. If CBEXPn timing is disabled/infinite (3FFh),

SHDNL is held until removed by a write to BALCTRL.

V

AA

ENABLE SHDNL PULLUP

SHDNL

In mode 0b11, the pullup will be engaged until removed

by a write to BALCTRL.

1nF

10MΩ

(C

)

SHDNL

If HOLDSHDNL=0b1x, CBTIMER reads back the gov-

erning CBEXP time for the duration of the extended

hold interval, allowing the μC to confirm the requested

balancing operation has run to completion. In modes

HOLSDSHDNL=0b1x, the hold behavior can be removed

after operations are completed and the exit status has

been confirmed by writing CBMODE to disabled, allowing

the device to power down.

Figure 49. SHDNL Pullup Control

Maxim Integrated │ 108

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Cell-Balancing Switches

Example: Autonomous-Cell Balancing by Time

The cell-balancing current is limited by the external bal-

ancing resistance, R , and the internal balancing-

Autonomous-cell balancing can be commanded within

the MAX17853 to enable balancing while the host micro-

controller enters a sleep state. The following procedure

illustrates how autonomous-cell balancing is invoked with

the primary stop mechanism as a timer:

BALANCE

switch resistance (R ). See Figure 50. Cell-balancing

SW

switches are internally controlled with even/odd switching

sequences in auto/manual modes, or independently in

Emergency-Discharge mode. Fault detection is described

in the Diagnostics section.

1) Host calculates SOC for each of the individual cells.

2) Host determines which cells to balance and the

associated balancing time.

Cell-Balancing Current

The cell-balancing current is limited by package power

dissipation, average die temperature, average duty cycle,

and the number of switches conducting current at any

one time. The system designer must carefully control

the device power dissipation by selecting a balancing

3) Host programs balancing channels using

BALSWEN[13:0].

4) Host programs eﬀective balancing current.

Eﬀective balancing current = V

/(2 x

CELLn

R

) x CBDUTY[7:4]

BALANCE

current resistance (R

) to ensure the die and

BALANCE

package temperature are below the absolute maximum

package rating and neither the device thermal-shutdown

threshold or the ADC measurement accuracy is impacted.

The maximum per-switch balancing current for seven

switches concurrently enabled are shown in Figure 51 for

an assumed 10-year device lifetime.

5) Host programs CBEXP1–CBEXP14 based on the

eﬀective balancing current and SOC.

6) Host programs HOLDSHDNL to determine shutdown

behavior at completion of cell balancing.

7) Host initiates balancing using CBMODE

"auto-individual cell balancing by second" or

"auto-individual cell balancing by minute."

TO CELL

N+1

SENSE

WIRE

C(N)

TO HVMUX

R

FILTER

C

FILTER

R

BALANCE

TO ALTMUX

BALSWN

HV

SW(N)

BALANCIN

G SWITCH

(N)

CELL N

R

BALFILTER

R

BALANCE

SW(N-1)

TO ALTMUX

TO HVMUX

SENSE

WIRE

C(N-1)

AGND

R

FILTER

C

FILTER

TO CELL N-1

Figure 50. Internal Cell-Balancing Switches

Maxim Integrated │ 109

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Figure 51. Typical Balancing-Current Performance

5) Host programs CBEXP1–CBEXP14 based on the

Example: Autonomous-Cell Balancing

with Programmable UV Threshold

eﬀective balancing current and balancing time

calculation.

Autonomous-cell balancing controlled through program-

mable UV thresholds can be commanded within the

MAX17853 to enable balancing while the host micro-

controller enters a sleep state. The following procedure

illustrates how balancing is invoked, with the primary stop

mechanism configured as a voltage measurement and

a secondary stop mechanism as a programmable timer.

6) Host programs CBUVTHR or CBUVMINCELL to

program the UV measurement stop threshold.

7) Host programs CBMEASEN as "embedded ADC/

CAL measurements enabled, CBUVTHR checking

enabled."

8) Host programs CBCALDLY to force measurement

calibration to account for temperature rise from

balancing

1) Host calculates SOC for each of the individual cells.

2) Host determines which cells to balance and the

associated balancing time:

Calibration choice should be chosen based on the

thermal time constant of the board.

Timer is a secondary stop mechanism and should

have additional margin applied to not interact with

primary UV measurement stop threshold.

9) Host programs HOLDSHDNL shutdown behavior at

completion of cell balancing

3) Host programs balancing channels using

BALSWEN[13:0].

10) Host initiates balancing using CBMODE as

"auto-individual cell balancing by second" or

"auto-individual cell balancing by minute."

4) Host programs eﬀective balancing current:

Eﬀective balancing current = V

/(2 x

CELLn

R

) x CBDUTY[7:4]

BALANCE

Maxim Integrated │ 110

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Interface

Interface Options

The MAX17853 supports two different interfaces to con-

trol the data-acquisition system. The applied interface is

configured using the UARTSEL pin. Drive this pin exter-

ALERTIN

RXU

TXU

nally by applying a pullup resistor to V to enable UART,

AA

MAX1785x

or a pulldown resistor to AGND to enable SPI. This inter-

face flexibility allows one device to serve multiple battery

applications for high-voltage and low-voltage systems, but

it cannot dynamically change between them both.

ALERTOUT

RXL

TXL

UART Interface

ISOLATION

ALERTIN

The Battery-Management UART Protocol allows up to 32

devices to be independently addressed in a daisy-chain

fashion, as shown in Figure 52. The host initiates all com-

munication with the daisy-chained devices through a UART

interface such as the MAX17841B. The UART can be

configured to support a variety of flexible implementations

depending on the application requirement. The configura-

tions, as defined using UARTCFG, are shown in Table 37:

RXU

TXU

RXL

MAX1785x

ALERTOUT

ISOLATION

TXL

Single-UART Interface with External Loopback

When UARTCFG is configured for single-UART with

external loopback, the data flow is always unidirectional

from the host, up the daisy-chain (Up path), and then

loops back down the daisy-chain (Down path) to the host,

as shown in Figure 52.

ISOLATION

In the Up path, each device first receives data at its lower

Rx port and immediately retransmits data from its upper Tx

port to the lower Rx port of the next device. The last device

uses an external loopback-differential cable to transfer

data from its upper Tx port directly into its upper Rx port,

then immediately retransmits the data from its lower Tx

port to the upper Rx port of the next down-stack device.

The Down path then acts as a pass through, buffering and

retransmitting the data. It does not act on any commands

in this configuration.

MAX17841

MICROPROCESSOR/MICROCONTROLLER

The external loopback has two advantages, it is quicker

to determine device count for applications where the host

does not assume what the device count is, and it helps

to match the supply current of the last device to that of

the other daisy-chained devices (because the hardware

configuration is identical).

Figure 52. Single UART with External Loopback

Table 37. UART Configurations

UARTCFG

0b00

UART CONFIGURATION

Single-UART Interface with External Loopback

Single-UART Interface with Internal Loopback

Single-UART Interface with Diﬀerential Alert Interface

Dual-UART Interface

UART UP PATH

Active

UART DOWN PATH

Inactive (Buﬀered/Pass Through)

Diﬀerential Alert

0b01

Active

0b10

Active

0b11

Active

Maxim Integrated │ 111

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Single UART with Internal Loopback

Single UART with internal loopback (UARTCFG=0b01)

routes the upper-port transmit data internally to the upper-

port receiver. This can be used to configure the top device

in the daisy-chain to prevent the need for external com-

ponents and wire connections. Additionally, this mode is

useful to diagnose the location of any daisy-chain signal

breaks. This is done by enabling the internal-loopback

mode on the first device, checking communication, then

moving the loopback mode to the next device and con-

tinuing up the stack until communication is lost.

ALERTIN

RXU

TXU

MAX1785x

ALERTOUT

RXL

TXL

Changing the UART configuration to single UART with

internal loopback immediately changes that device's

upper-port configuration so the signal is routed internally

from the upper transmitter to the upper receiver, while

external signals present on the upper-port receivers' input

pins are ignored; therefore, when UARTCFG is written

to 0b01, the WRITE command forwarded in the Up path

is interrupted in the down-stack direction, interrupting its

return to the host. To verify if the operation was success-

ful, issue this command twice. If the MAX17841B inter-

face is used, its receive buffer should be cleared before

changing UARTCFG, and cleared again after changing

the loopback configuration because the communication

was interrupted.

ALERTIN

RXU

TXU

RXL

MAX1785x

ALERTOUT

TXL

ISOLATION

Dual-UART Interface

If the end application requires higher data throughput

or a redundant communication path for safety, a dual-

UART-interface configuration can be utilized by writing

UARTCFG=0b11. When configured, the Down path acts

as an independent UART path that enables simultaneous

read processing from both UART paths. This essentially

doubles the effective interface rate to ~4Mbps. In the event

of a broken interface wire, the independent UART paths

allow uninterrupted access to all devices in the daisy-chain

by dynamically changing the master interface with no loss

of functionality.

MAX17841

MICROPROCESSOR/MICROCONTROLLER

Note: For this configuration to be utilized, both hardware

and software configurations should match.

Figure 53. Single UART with Differential Alert Interface

Maxim Integrated │ 112

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

By default, the Down-path UART operates as a slave

device and as such, has no response to a WRITE or

WRITEALL command. The slave interface only responds

to the READ, READALL, and READBLOCK commands. If

a WRITE command is issued on the slave UART, the write

is ignored and passed through to the next device in the

daisy-chain, eventually returning to the MAX17841. Each

device in the daisy-chain asserts its ALRTDUALUART bit in

the STATUS2 register to indicate that a valid WRITE com-

mand was received but not acted upon. This bit remains

set until cleared by the master interface.

ALERTIN

RXU

TXU

MAX1785x

ALERTOUT

RXL

TXL

Configuration of the master is performed using

the UPHOST or DOWNHOST commands; iden-

tification of the master is performed by reading the

UARTHOST bit. See the Battery-Management UART

Protocol Commands section.

ALERTIN

RXU

TXU

RXL

MAX1785x

ALERTOUT

TXL

Dual-UART Master Conﬁguration

ISOLATION

If the upstream UART path cannot communicate due to

a failure condition, the downstream UART path can reini-

tialize itself as the master through a DOWNHOST UART

command packet issued by the host. This allows the

downstream path to have full read and write capability. The

upstream path then hands over master functionality and

configures itself as a slave. If the upstream path regains

functionality, it is able to only issue READ commands,

unless it reinitializes itself as the master using the UPHOST

command.

MAX17841

MICROPROCESSOR/MICROCONTROLLER

If an interface is reinitialized, the host should poll the

UARTHOST bit to ensure that all devices within the daisy-

chain are configured to the same master interface.

Note: The UPHOST command is only valid on the

upstream UART and the DOWNHOST command is only

valid on the downstream UART. If an UPHOST command

Figure 54. Dual-UART Interface

Maxim Integrated │ 113

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

is issued on the downstream UART, no action is taken

and the ALRTDUALUART bit will be set.

propagates through the last device in the daisy-chain. See

Figure 55 and Figure 56 for an example of the timing con-

siderations. The master UART path will not prevent this

interaction and should be handled by the host.

Dual-UART Master/Slave Interaction

The upstream and downstream UART timing should be

synchronized by the host controller to avoid potentially

reading data from the prior acquisition. This may occur

when the master issues a WRITE command and the slave

attempts to read the data before the entire data packet

Similarly, the UPHOST and DOWNHOST commands

should not be sent simultaneously to avoid an unknown

state to the host controller. The host controller will not

be able to diagnose the incorrect state by reading the

t

ACQUISITION_DEVIC

E1

t

ACQUISITION_DEVICE

N

WRITEALL SCAN = 1

RECEIVED AT DEVICE 1

WRITEALL SCAN = 1

RECEIVED AT DEVICE 2

WRITEALL SCAN = 1

RECEIVED AT DEVICE N

t

PROP

t

N

PROP x

t

PROP

READALL: CH1

ISSUED AT UP PATH

READALL: CH2

ISSUED AT DOWN PATH

READALL: CH3

ISSUED AT UP PATH

READALL: CH4

ISSUED AT DOWN PATH

Figure 55. Dual-UART Master/Slave Interaction (Timing Considerations)

READALL CH 1

WRITEALL

ST

ND

TH

ST

(1 DAISY-CHAIN)

(2 DAISY-CHAIN)

(N DAISY-CHAIN)

(1 DAISY-CHAIN)

ND

TH

(2 DAISY-CHAIN)

(N DAISY-CHAIN)

MASTER

UART

T

1

T

0

t

PROP

T

PROP

T

PROP

SLAVE

UART

T

2

t

HOST_DELAY

t

PROP

READALL CH 3

READALL CH 2

READALL CHANNEL 2

ST

ND

(1 DAISY-CHAIN)

(2 DAISY-CHAIN)

TH

(N DEVICE

Figure 56. Dual-UART Command Timing

Maxim Integrated │ 114

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

UARTHOST bit, or by invalid commands signified by the

ALRTDUALUART bit.

provides a balanced signal (50% duty cycle) that ensures

charge neutrality on the isolation capacitors.

UART Ports

UART Transmitter

Two UART ports are utilized, a lower port (RXL/TXL) and

an upper port (RXU/TXU). Each port consists of a differ-

ential line driver and differential line receiver. DC-blocking

capacitors or transformers can be used to isolate daisy-

chained devices operating at different common-mode

voltages. During communication, the character encoding

When no data is being transmitted by the UART, the

differential outputs must be driven to a common level

to maintain a neutral charge difference between the

AC-coupling capacitors or to avoid saturation of the

isolation transformers. In the default idle mode (low-Z),

the transmitter drives both outputs to a logic-low level

to balance the charge on the capacitors; this also works

well with transformer coupling. The high-Z idle mode

(TXLIDLEHIZ, TXUIDLEHIZ=0b1) places the TXn pins

in a high-Z state during time periods where the UART

isinactive, which can be desirable to minimize the effects

of charging and discharging the isolation capacitors. The

idle mode for the upper and lower ports can be controlled

independently through the TXUIDLEHIZ and TXLIDLEHIZ

configuration bits.

V

, V

DDL2 DDL3

TX[U,L]IDLEHIZ

(UART STATE = IDLE?)

DRIVE HIGH

DRIVE LOW

UART Receiver

TX[U,L][P,N]

The UART receiver has a wide common-mode input

range to tolerate harsh EMC conditions. It can operate in

differential mode or single-ended mode (see Table 38). By

default, the UART receivers are configured for differential

mode. In single-ended mode, the RXP input is grounded

and the RXN input receives inverse data, as described in

the Applications Information section (see Figure 106). In

single-ended mode, the receiver input threshold is nega-

ESD CLAMP

GNDL2, GNDL3

Figure 57. UART Transmitter

tive, so a zero differential voltage (V

, V

RXP RXN

= 0V) is

30kΩ

4pF

HIGH COMPARATOR

V

/60

DDL

1.18MΩ

RXP

41.6kΩ

ZERO-CROSSING

COMPARATOR

VCM = V /3

DDL

GNDL

DIGITAL CORE

41.6kΩ

LOW COMPARATOR

1.18MΩ

RXN

V /60

DDL

4pF

30kΩ

Figure 58. UART Receiver

Maxim Integrated │ 115

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

considered to be a logic one and a negative differential

voltage (V high), a logic zero.

in Figure 59. V

SHDNL

charge pump then self-regulates to the V

can maintain V

SHDNL

durations. In the event coummication is haulted, the SHDNL

pin voltage falls, with a 10ms time constant (assuming only

a 1nF capacitor).

reaches 1.8V in 200μs (typ). The

and

even with the UART idle for long

RXN

SHDNLIMIT

SHDNL Charge Pump

The SHNDL input can be driven externally or can be con-

trolled using UART communication only. Using a differential

UART configuration, the signaling on the lower-port receiver

drives an internal charge pump that charges up the external

1nF capacitor connected to the SHDNL input, as shown

DCIN

C40

15pF

C42

2nF, 600V

R40

4.7kΩ

RXLP/RXUP

RXLN/RXUN

FROM

DEVICE(N-1)

TRANSMITTER

CIRCUIT

TO RECEIVER

C43 2nF

600V

R41

4.7kΩ

C41

15pF

R43

100kΩ

R42

100kΩ

GNDL

SHDNL

C44 1nF

(CSHDNL)

FORCEPOR

10MΩ

Figure 59. SHDNL Charge Pump

Maxim Integrated │ 116

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Note: Both upper and lower UART Rx ports are enabled

with charge pumps, allowing for communication on either

the Up or Down path to initialize the device.

ALRTCOMMSEL1 (for the lower port) in the FMEA1

register are set after the STATUS1:ALRTRST has

been cleared

● ALRTCOMMSEU2 (for the upper port) and

ALRTCOMMSEL2 (for the lower port) in the FMEA1

register are set before the STATUS1:ALRTRST has

been cleared

UART Rx Modes

During the first preamble received after a reset, the

receiver automatically detects if the received signal is

single-ended; if valid, the receiver is appropriately con-

figured in single-ended mode. To be detected, the device

must be reset for any change in the receiver hardware

configuration. Device reset is signaled to the host through

the ALRTRST status bit. In normal operation, this bit is

cleared after the first HELLOALL command.

See Table 38 for a list of the conditions under which

ALRTCOMMSEU1 and ALRTCOMMSEL1 are set. If the

RXP input is open circuit, the Rx-mode detection places

the UART in single-ended mode so the port can still oper-

ate despite reduced noise immunity. The host can diag-

nose this condition by checking the ALRTCOMMSELn

and ALRTCOMMSEUn bits. Any other faults result in

communication errors.

Receiver mode is indicated using the following bits:

● ALRTCOMMSEU1 (for the upper port) and

Table 38. UART Rx Modes (Post ALRTRST Being Cleared)

STATUS1:ALRTRST

RXP

Connected to data Connected to inverse data

Grounded Connected to inverse data

RXN

ALRTCOMMSEX1

Rx MODE

x

0

1

Diﬀerential mode (normal)

Single-ended mode (normal)

0

Single-ended mode

(low noise immunity)

0

Open circuit (fault) Connected to inverse data

Connected to data Open-circuit (fault)

1

Diﬀerential mode

(communication errors)

x

0

1

Don't care

—

Table 39. UART Rx Modes (Prior to ALRTRST Being Cleared)

STATUS1:ALRTRST

RXP

Connected to data Connected to inverse data

Grounded Connected to inverse data

RXN

ALRTCOMMSEX2

Rx MODE

x

0

1

Diﬀerential mode (normal)

Single-ended mode (normal)

1

Single-ended mode

(low noise immunity)

1

Open circuit (fault) Connected to inverse data

Connected to data Open circuit (fault)

1

Diﬀerential mode

(communication errors)

x

0

Don't care

—

Note: ALRTCOMMSEU1 and ALRTCOMMSEL1 both read 0b0 if STATUS1:ALRTRST=0b1.

ALRTCOMMSEU2 and ALRTCOMMSEL2 both read 0b0 if STATUS1:ALRTRST=0b0.

Maxim Integrated │ 117

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 39 lists conditions under which ALRTCOMMSEU2

and ALRTCOMMSEL2 are set.

incoming Up-path signal. With this adaptive transmit tim-

ing, the interface between a conventional UART node and

a Maxim proprietary battery-monitoring-system node has a

tolerance for baud-rate mismatch much higher than that of

the conventional receiver port alone, providing a high level

of timing margin for direct-connection applications.

Baud-Rate Detection

The UART can operate at a baud rate of 2Mbps, 1Mbps,

or 0.5Mbps. The baud rate is controlled by the host and

is automatically detected by the device when the first

preamble character is received after reset. If the host

changes the baud rate, it must issue a reset and resend a

minimum of 2 x n preambles at the new baud rate (where

n = number of devices). The 2 x n preambles are neces-

sary because the transmitter for the upper port does not

transmit data until the lower-port receiver has detected

the baud rate; likewise, the transmitter on the lower port

does not transmit data until the upper-port receiver has

detected the baud rate. A simple way to do this is for the

host to start transmitting preambles and stop when a pre-

amble has been received back at the host Rx port.

Battery-Management UART Protocol

The Maxim Battery-Management UART Protocol uses the

following features to maximize the integrity of its commu-

nications:

● All transmitted Manchester-encoded data bytes, where

each data bit is transmitted twice with the second bit

inverted (G.E. Thomas convention)

● Every transmitted character contains 12 bits that

include a start bit, a parity bit, and two stop bits

● Read/write packets contain a CRC-8 packet-error

checking (PEC) byte

Sending 2 x n preambles completes baud detection on all

n devices in the chain. To receive a preamble back at the

host Rx port, (2 x n) + 1 preambles must be sent.

● Each packet is framed by a preamble character and a

stop character

● Read packets contain a data-check byte to verify the

Note: Baud rate for dual-UART configuration is determined

during the initialization sequence of either the Up path or

Down path. Both paths operate at the same communica-

tion rate.

integrity of the transmission

The protocol is also designed to minimize power con-

sumption by allowing slave devices to shut down if the

UART is idle for a specified period of time. The host must

periodically transmit data to prevent shutdown, unless the

SHDNL input is driven externally.

Tx Adaptive Mode for Single-Ended Mode

To overcome the error-tolerance limitation when con-

necting a MAX17853 to a conventional UART port, an

adaptive transmit-timing feature has been added. The

feature works by monitoring the location of the incoming

Manchester transitions at the RXL port, with respect to the

local clock, to calculate a correction factor. This correc-

tion factor is then applied to the TXL port so the outgoing

Down-path signal has similar timing characteristics to the

Command Packet

A command packet is defined as a sequence of UART

characters originating at the host. Each packet starts with

a preamble character, followed by data characters, and

ending with a stop character, as shown in Figure 60. After

IDLE

PREAMBLE

MESSAGE

STOP

TXP-TXN

Figure 60. Command Packet

Maxim Integrated │ 118

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

sending a packet, the host either goes into idle mode or

sends another packet.

Data Characters

Each data character contains a single-nibble (4-bit) pay-

load, so two characters must be transmitted for each

byte of data. All data is transmitted least-significant bit,

least-significant nibble, and least-significant byte first.

See Table 40, and Figure 62 for an example. The data

itself is Manchester encoded, which means that each data

bit is followed by its complement. If the UART detects a

Manchester-encoding error in any received data charac-

ter, it sets the ALRTMANUP or ALRTMANDN bit in the

STATUS2 register. All single-UART configurations set

Preamble Character

The preamble is a framing character that signals the

beginning of a command packet. It is transmitted as an

unencoded 15h, with a logic-one parity bit and a balanced

duty cycle. If any bit(s) other than the stop bits deviate

from the unique preamble sequence, the character is not

interpreted as a valid preamble, but rather as a data char-

acter. See Figure 61 for an example.

OPTIONAL IDLE

S

1

0

1

0

1

0

E=1

P

IDLE DISABLE

IDLE ENABLE

Figure 61. Preamble Character

DATA NIBBLE = 0H

0

OPTIONAL IDLE

S

0

1

0

1

0

1

0

1

E=0

P

IDLE DISABLE

IDLE ENABLE

DATA NIBBLE = AH

0

1

0

1

OPTIONAL IDLE

S

0

1

0

1

0

E=0

P

IDLE DISABLE

IDLE ENABLE

Figure 62. Data Characters

Maxim Integrated │ 119

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the ALRTMANUP bit. In a dual-UART configuration, a

Manchester error in the Up path sets the ALRTMANUP,

and a Manchester error in the Down path sets the

ALRTMANDN.

is always transmitted as a logic zero. If the UART detects

a parity error in any received data character, it sets the

ALRTPARUP or ALRTPARDN bit in the STATUS2 regis-

ter. All single-UART configurations set the ALRTPARUP

bit. In a dual-UART configuration, a parity error in the Up

path sets ALRTPARUP and a parity error in the Down

path sets ALRTPARDN.

The parity is even, meaning the parity bit’s value should

always result in an even number of logic-one bits in the

character. Given the data is Manchester encoded and

there are two stop bits, the parity bit for data characters

Stop Character

Table 40. Data Character Description

BIT

1

NAME

Start

SYMBOL

DESCRIPTION

First bit in character, always logic zero

Least signiﬁcant bit of data nibble (true)

Least signiﬁcant bit of data nibble (inverted)

Data bit 1 (true)

S

2

Data0

Data0/

Data1

Data1/

Data2

Data2/

Data3

Data3/

Parity

Stop

3

4

5

Data bit 1 (inverted)

6

Data bit 2 (true)

7

Data bit 2 (inverted)

8

Most signiﬁcant bit of data nibble (true)

Most signiﬁcant bit of data nibble (inverted)

Always logic zero (even parity)

Always logic one

9

10

11

12

E

P

Stop

Last bit in character, always logic one

OPTIONAL IDLE

S

0

1

0

1

0

1

0

E=1

P

IDLE DISABLE

IDLE ENABLE

Figure 63. Stop Character

Maxim Integrated │ 120

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The stop character is a framing character that signals the

end of a command packet (see Figure 63). It is transmitted

as an unencoded 54h, with a logic-one parity bit and a bal-

anced duty cycle.

packet and remains in idle mode until either the next

command packet is sent or it goes into keep-alive mode,

sending periodic stop characters to prevent the daisy-

chained device(s) from going into shutdown.

UART Idle Mode

UART Communication Mode

In the low-Z (default) idle mode, the transmitter outputs

are both driven to 0V, as shown in Figure 64. In the high-

Z idle mode, the transmitter outputs are not driven by the

UART. The MAX17841B interface automatically places its

transmitter in idle mode immediately after each command

When transitioning from idle mode to communication

mode, the TXP pin must be pulled high (logic one) prior

to signaling the start bit (logic zero), as shown in Figure

64. The duration of the logic one is minimized to maintain

a balanced duty cycle while still meeting the timing speci-

fication. When transitioning from the stop bit back to idle

mode, the delay, if any, is also minimized.

IDLE

PREAMBLE

IDLE

TXNP

TXNN

T_STSU

TXNP-TXNN

Figure 64. Communication Mode

Table 41. Data Types

DATA TYPE

DESCRIPTION

Command byte

Register address

Register data

A byte deﬁning the command packet type, generally either a READ or a WRITE

A byte deﬁning the register address to be read from or written to

Register data bytes being read from or written to

Data-check byte

An error and alert-status byte sent and returned with all reads

Packet-error checking byte A packet-rrror checking (PEC) byte sent and returned with every packet except HELLOALL

Alive-counter

Fill byte

A byte functioning as a device counter on all reads and writes, if ALIVECNTEN=1

Bytes transmitted in READALL and READBLOCK command packets (for clocking purposes only)

Maxim Integrated │ 121

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

device address is encoded in the command byte. The

device ignores those commands containing a device

address other than its own.

Data Types

The Battery-Management UART Protocol employs several

different data types, as described in Table 41.

Register Addresses

Command Bytes

All register addresses are single-byte quantities and are

defined in the Register Map. In general, if the register

or device address in a received command is not a valid

address for the device, the device ignores the read or

write and simply passes through the packet to the next

device.

The Battery-Management UART Protocol supports eight

command types, summarized in Table 42.

Command-Byte Encoding

Command-byte encoding is described in Table 43. For

READDEVICE and WRITEDEVICE commands, the

Table 42. Command Packet Types

DATA-

CHECK

ALIVE-

COUNTER

PACKET SIZE

(CHARACTERS)

COMMAND

DESCRIPTION

PEC

Writes a unique device address to each device in the

daisy-chain. Required for system initialization.

HELLOALL

WRITEALL

No

8

Writes a speciﬁc register in all devices.

No

Yes

14

WRITEDEVICE Writes a speciﬁc register in a single device.

READALL

Reads a speciﬁc register from all devices.

Reads a speciﬁc register from a single device.

Reads a set of registers from a single device.

Yes

12 + (4z)

16

READDEVICE

READBLOCK

14 + (4* BS)

Makes the Up path the master in a dual-UART

conﬁguration. Sets bitﬁeld UARTHOST=0b1.

UPHOST

No

Yes

No

10

Makes the Down path the master in a dual-UART

conﬁguration. Sets bitﬁeld UARTHOST=0b0.

DOWNHOST

Note: z = Total number of devices, ALIVECNTEN=1, packet size includes framing characters.

*Block size[4:0] = 1–32, which is the number of registers read.

Table 43. Battery-Management Protocol (Command-Byte Encoding)

COMMAND

HELLOALL

BYTE*

57h

21h

04h

02h

05h

03h

06h

09h

08h

7

0

6

1

5

0

4

1

3

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ALERTPACKET

WRITEDEVICE

WRITEALL

0

1

0

DA4

0

DA3

0

DA2

0

DA1

0

DA0

0

READDEVICE

READALL

DA4

0

DAe

0

DA2

0

DA1

0

DA0

0

READBLOCK

DOWNHOST

UPHOST

BS4

0

BSe

0

BS2

0

BS1

0

BS0

1

0

1

*Assumes DA[4:0]=0x00 where DA[4:0] is the device address in the ADDRESS register.

BS[4:0] = Block size (1–32).

Maxim Integrated │ 122

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

indicates a POR condition, and thus cannot be masked.

Register Data

STATUS1,5:ALRTPEC is not included intentionally in the

data-check byte.

All registers are 16-bit words (2 data bytes) and are

defined in the Register Map.

PEC Byte

Data-Check Byte

The PEC byte is a CRC-8 packet error check (PEC)

sent by the host with all READ and WRITE commands.

If any device receives an invalid PEC byte, it sets the

ALRTPECUP, or ALRTPECDN bit in the STATUS2 regis-

ter, and also the ALRTPEC bit in the STATUS1 register.

All single-UART configurations set the ALRTPECUP bit.

In a dual-UART configuration, a PEC error in the Up path

sets ALRTPECUP, and a PEC error in the Down path sets

the ALRTPECDN. During any write transaction, a device

does not execute the WRITE command internally unless

the received PEC matches the expected calculated value.

For READ commands, the device must return its own cal-

culated PEC byte based on the returned data. The host

should verify that the received PEC byte matches the cal-

culated value and if an error is indicated, the data should

be discarded. See the Applications Information section for

details on the PEC calculation.

The host uses the returned data-check byte to promptly

determine if any communication errors occurred during

the packet transmission and to check if alert flags are

set in any devices, as shown in Table 44. Individual alert

conditions can be masked out of the data-check byte

using settings in ALRTIRQEN; however, the underlying

alert information will not always be available for readback

in the STATUS1 register. The data-check byte is returned

by the READALL, READDEVICE, and READBLOCK

commands. For READDEVICE, the data-check byte is

updated only by the addressed device.

The data-check byte that is sent by the host is a seed

value normally set to 00h although non-zero values and

can be used as a diagnostic. Each device logically ORs

the received data-check byte with its own status and trans-

mits it to the next device. A PEC error detected by any

device sets the appropriate ALRTPECUP or ALRTPECDN

in the STATUS2 register, and thus, the ALRTPEC rollup

bit in the STATUS1 register. Also, the device sets the PEC

error bit in the data-check byte within the associated path's

command packet, as described below.

Alive-Counter Byte

The alive-counter byte is the last data byte of the

command packets (except HELLOALL, UPHOST, and

DOWNHOST) if the ALIVECNTEN bit is set in the

DEVCFG1 register. The host typically transmits the alive-

counter seed value as 00h but any value is permitted.

For WRITEALL or READALL commands, each device

retransmits the alive-counter incremented by one. For

WRITEDEVICE or READDEVICE commands, only the

Note: STATUS1,15:ALRTSCAN is a procedural notifica-

tion bit and is not included intentionally in the data-check

byte. It is available for inclusion in theAlert interface to sup-

port interrupt-driven applications. STATUS1,14:ALRTRST

Table 44. Data-Check Byte

BIT

7

NAME

DESCRIPTION

PEC ERROR

ALRTFMEA

PEC error detected during the current transaction on the Up/Down path issuing this bit.

(ALRTFMEA1 & FMEA1ALRTEN) or (ALRTFMEA2 & FMEA2ALRTEN)

6

ALRTRST or (ALRTMSMTCH & MSMTCHALRTEN) or (ALRTBLKOVST & BLKOVALRTEN)

or (ALRTBLKUVST & BLKUVALRTEN) or

(ALRTINTRFC & INTRFCALRTEN) or (ALRTCAL & CALALRTEN) or

(ALRTCBAL & CBALALRTEN)

5

ALRTSTATUS

4

3

2

1

0

AUXOV (UT)

AUXUV (OT)

CELLOV

(ALRTAUXOVST & AUXOVSTALRTEN)

(ALRTAUXUVST & AUXUVSTALRTEN)

(ALRTCELLOVST & CELLOVSTALRTEN)

(ALRTCELLUVST & CELLUVSTALRTEN)

0

CELLUV

RESERVED

Maxim Integrated │ 123

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

addressed device increments it. The alive-counter is not

used in the HELLOALL, UPHOST, and DOWNHOST

commands. If the alive-counter reaches FFh, the next

device increments it to 00h.

propagate to the next device until it returns to the host, at

which point the host is able to determine the total number

of devices in the daisy-chain for subsequent READALL,

READDEVICE, READBLOCK commands.

Since the alive-counter comes after the PEC byte, an

incorrect PEC value will not affect the incrementing of

the alive-counter byte. Also, the PEC calculation does

not include the alive-counter byte. The host should verify

that the alive-counter equals the original seed value + the

number of devices, considering that if the alive-counter

reaches FFh, the next device increments it to 00h.

HELLOALL Operation in Dual-UART Conﬁguration

By default, dual-UART operation is configured with the

primary communication path being the Up path (refer to

the UARTCFG and UARTHOST bits in the DEVCFG1

register for details about defaults and possible configu-

rations), where the Up path is defined as transmission

from the TXU port to the RXL port. The DA[4:0] bits in the

HELLOALL command packet are incremented as they

progress up the daisy-chain. Thus, when the HELLOALL

is received by the host microcontroller, the DA[4:0] value

returned is one greater than the address assigned to the

top device.

Fill Bytes

In the READALL command, the host sends two fill bytes

for each device in the daisy-chain. The fill bytes are the

locations within the packet that are used by the device to

place the read data. The fill-byte values transmitted by the

MAX17841B interface alternate between C2h and D3h.

As the command packet propagates through the device,

the device overwrites the appropriate fill bytes with the

register data. The device uses the ADDRESS register to

determine which specific fill bytes in the packet to over-

write. For a READBLOCK command, the number of fill

bytes sent is equal to the read-data block size.

It is recommended that the host seeds the initial address

of the Up path at a value of 0x00. This configuration

applies to the first address of the daisy-chain at the same

value of the default condition of the bottom address (BA

bits in the ADDRESS register). Thus, it is not necessary

to write the bottom address BA[4:0] to all the devices. The

host microcontroller should never set the bottom address

at a value that would result in the device address exceed-

ing 0x1F

For a READDEVICE command, only two fill bytes are

required since only one device responds (returning two

data bytes). Also, fill bytes are not required for WRITE

commands because the data received is exactly the same

as the data retransmitted.

Note: The device address is only stored and incremented

in the Up path, and then passes through the Down

path, leaving the device address unaffected. As such,

if the hardware is configured as a single daisy-chain

and the UART is looped back using the Down path, the

UARTHOST configuration prevents the Down path from

changing the device address already determined.

Battery-Management UART

Protocol Commands

HELLOALL Command

The HELLOALL command initializes the daisy-chain

device addresses after a POR. The device addresses are

stored in the DA[4:0] bits of the ADDRESS register with

the highest address being 0x1F. Thus, a maximum of 32

devices can be addressed.

The HELLOALL command packet can also be applied

through the Down path, where the Down path is defined

as transmission from the TXL port to the RXU port. For

proper operation, the host microcontroller must first send

the DOWNHOST command through the Down path prior

to sending the HELLOALL.

The device address bits (DA[4:0]) in the HELLOALL com-

mand packet are seeded by the host microcontroller. The

command proceeds to the first device of the daisy-chain

and is stored in that device's DA bits of the ADDRESS reg-

ister. The first device then increments or decrements the

HELLOALL command-packet bitfield DA[4:0] according to

the UARTHOST configuration settling (see the HELLOALL

Operation in Dual-UART Configuration section). Thus,

the initial seeded value corresponds to the first device's

address in the daisy-chain. The command continues to

The device address in the HELLOALL command packet

is decremented as it progresses down the daisy-chain.

Thus, the address of the top daisy-chain (first device in

the Down path) will be the value that is seeded in the

DA[4:0] bits of the HELLOALL command packet. This top

daisy-chain device proceeds to decrement the DA[4:0]

and propagates the value down the daisy-chain. When

the HELLOALL is received by the host microcontroller,

the DA[4:0] value returned is one less than the address

Maxim Integrated │ 124

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

assigned to the bottom device. The host microcontroller

should never set the top address at a value which would

result in a DA[4:0] decremented below 0x0.

Note: The device address is only stored and decremented

in the Down path and passes through the Up path leaving

the device address unaffected (I.e., HELLOALL sent in the

Up path with UARTHOST=1'b0).

After the HELLOALL is processed, the TA bits (Top

Address bits) in the ADDRESS register must be set to the

initial DA[4:0] seeded value.

HELLOALL Operation In a

Single-UART Conﬁguraiton

In a single-UART configuration the HELLOALL is pro-

cessed the same as in the dual-UART Up path.

It is recommended that the host seeds the initial address

of the Down path at a value equal to the number of

devices in the daisy-chain, such that the bottom address

is 0x00. This configuration ensures that whether the

HELLOALL is sent through the Up path or Down path,

the device address remains the same, which is ideal for

consistency with the addressing of the READDEVICE,

and READALL commands.

Special considerations exist if the host desires to use

internal loopback instead of external loopback. The first

HELLOALL command is not returned to the host because

the internal loopback (UARTCFG) for the top device has

not yet been written. If the number of devices is known

to the host, the host can use a WRITEDEVICE to set the

internal loopback bit on the last device and then verify

with a READALL. If the number of devices is unknown,

the internal loopback bit must be set on the first device,

verified and then cleared. It can then be set on the second

device and verified, and so on incrementally until there is

no response (end of stack). With the number of devices

known, the loopback bit can be reset on the top device

and all ADDRESS registers verified.

Table 45. HELLOALL Command Packet

HELLOALL

Preamble

57h

00h

HELLOALL Address Lock

{0b000,DA[4:0]}

Stop

When a device receives a valid HELLOALL command, it

clears the ADDRUNLOCK bit of the ADDRESS register.

When this bit is 0, HELLOALL commands are ignored to

Table 46. HELLOALL Up-Path Sequencing

HELLOALL UP-PATH SEQUENCING (z = TOTAL NUMBER OF DEVICES)

DEVICE (n) RXL DEVICE (n) TXU

Preamble Preamble

HOST TX

HOST Rx

Preamble

57h

Preamble

57h

00h

{0b000,DA[4:0]}

Stop

{0b000,DA[4:0]+n-1}

Stop

{0b000,DA[4:0]+n}

Stop

{0b000,DA[4:0]+z}

Stop

Table 47. HELLOALL Down-Path Sequencing

HELLOALL SEQUENCING (z = TOTAL NUMBER OF DEVICES)

DEVICE (n) RXU DEVICE (n) TXL

Preamble Preamble

HOST Tx

HOST Rx

Preamble

57h

Preamble

57h

00h

{0b000,ADDR[4:0]}

Stop

{0b000,ADDR[4:0]-(n-1)}

Stop

{0b000,ADDR[4:0]-n}

Stop

{0b000,ADDR[4:0]-z}

Stop

Maxim Integrated │ 125

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

prevent inadvertently changing any device address. To

reconfigure the device address, the ADDRUNLOCK bit

must first be set to 1, or a POR event must occur. After

configuring the device addresses, they should be verified

using the READALL command.

PEC byte, it sets the ALRTPECUP or ALRTPECDN bit in

the STATUS2 register, and also the ALRTPEC bit in the

STATUS1 register. All single-UART configurations set the

ALRTPECUP bit. In a dual-UART configuration, a PEC

error in the Up path sets ALRTPECUP, and a PEC error

in the Down path sets the ALRTPECDN.

WRITEALL Command

WRITEDEVICE Command

The WRITEALL command writes a 16-bit value to a

specified register in all daisy-chain devices. Since most

configuration information is common to all the devices,

this command allows faster setup than individually writing

to each device. If the register address is not valid for the

device, the command is ignored. The command sequence

is shown in Table 48.

The WRITEDEVICE command writes a 16-bit value to

the specified register in the addressed device only. If the

register address is not valid for the device, the command

is ignored. The command sequence is shown in Table 49.

The register value is written immediately after the valid

PEC byte is received or, if NOPEC is set, after the last

byte received. If the received PEC byte does not match

the internal calculation, the command is not executed, but

is still forwarded to the next device. The PEC is calculated

from the first 4 bytes of the command starting after the

preamble. If the addressed device receives an invalid

PEC byte, it sets the ALRTPECUP, or ALRTPECDN bit in

The register value is written immediately after the valid

PEC byte is received or, if NOPEC is set, after the last

byte received. If the received PEC byte does not match

the internal calculation, the command is not executed,

but is still forwarded to the next device. The PEC is

calculated from the first 4 bytes of the command start-

ing after the preamble. If any device receives an invalid

Table 48. WRITEALL Sequencing (Unchanged by Daisy-Chain)

DEVICE(n) RXL (UP PATH)

OR RXU (DOWN PATH)

DEVICE(n) TXU (UP PATH)

OR TXL (DOWN PATH)

HOST Tx

HOST Rx

Preamble

02h

Preamble

02h

Preamble

02h

Preamble

02h

[REG ADDR]

[DATA LSB]

[DATA MSB]

[PEC]

[REG ADDR]

[DATA LSB]

[DATA MSB]

[PEC]

[REG ADDR]

[DATA LSB]

[DATA MSB]

[PEC]

[DATA LSB]

[DATA MSB]

[PEC]

[ALIVE]*

Stop

[ALIVE]*

Stop

[ALIVE]*

Stop

*If alive-counter mode is enabled.

Table 49. WRITEDEVICE Sequencing (Unchanged by Daisy-Chain)

DEVICE RXL (UP PATH)

OR RXU (DOWN PATH)

DEVICE TXU (UP PATH)

OR TXL (DOWN PATH)

HOST Tx

HOST Rx

Preamble

{(DA[4:0]),0b100}

[REG ADDR]

[DATA LSB]

[DATA MSB]

[PEC]

{(DA[4:0]),0b100}

[REG ADDR]

[DATA LSB]

{(DA[4:0]),0b100}

[REG ADDR]

[DATA LSB]

[DATA MSB]

[PEC]

{(DA[4:0]),0b100}

[REG ADDR]

[DATA LSB]

[DATA MSB]

[PEC]

[DATA MSB]

[PEC]

[ALIVE]*

Stop

*If alive-counter mode is enabled.

Maxim Integrated │ 126

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the STATUS2 register, and also the ALRTPEC bit in the

STATUS1 register. All single-UART configurations set the

ALRTPECUP bit. In a dual-UART configuration, a PEC

error in the Up path sets ALRTPECUP, and a PEC error

in the Down path sets the ALRTPECDN. A PEC error can

only occur in the addressed device.

bit in the STATUS2 register, and also the ALRTPEC bit in

the STATUS1 register. All single-UART configurations set

the ALRTPECUP bit. In a dual-UART configuration, a PEC

error in the Up path sets ALRTPECUP, and a PEC error

in the Down path sets ALRTPECDN; however, the com-

mand proceeds to the next device in the daisy-chain. A

Manchester error immediately switches the data propaga-

tion from read mode to write (pass-through) mode, ensur-

ing that the Manchester error is propagated through the

daisy-chain and back to the host.

READALL Command

The READALL command returns register data from the

specified register for all daisy-chained devices. The data

for the first device (connected to the host) is returned last.

The command sequence is shown in Table 50 and Table

51. If the received PEC byte does not match the calculated

value, the UART sets the ALRTPECUP, or ALRTPECDN

The fill-byte values transmitted by the MAX17841B inter-

face alternate between C2h and D3h, as shown. As the

packet propagates through the device, the device retrans-

Table 50. READALL Command Sequencing In Single-UART or

Dual-UART Up Path (z = Number of Devices)

DEVICE(n)

HOST Tx

HOST Rx

RXL

TXU

Preamble

03h

Preamble

03h

Preamble

03h

[REG ADDR]

[DC] = 0x00

[PEC]

[REG ADDR]

[DATA ADDR]

[REG ADDR]

[DATA LSB(n-1)]

[DATA LSB(n)]

[DATA LSB(z)] = [DATA LSB(TA)]

[DATA MSB(z)] = [DATA MSB(TA)]

[DATA LSB(z-1)] = [DATA LSB(TA-1)]

[DATA MSB(z-1)] =[DATA MSB(TA-1)]

[DATA MSB(n-1)]

[DATA MSB(n)]

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

[FD(2) C2h]

[FD(2) D3h]

...

[DATA LSB(1)] = [DATA LSB(BA)] [DATA LSB(1)] = [DATA LSB(BA)] ...

[DATA MSB(1)] = [DATA MSB(BA)] [DATA MSB(1)] = [DATA MSB(BA)] ...

[DC]

...

[PEC]

...

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

...

[ALIVE]*

...

[FD(1) C2h]

[FD(1) D3h]

...

[DATA LSB(1)] = [DATA LSB(BA)]

...

[DATA MSB(1)] = [DATA MSB(BA)]

...

[DC]

[FD(z) C2h]

[FD(z) D3h]

Stop

[FD(z-n) C2h]

[FD(z-n) D3h]

Stop

[FD(z-n-1) C2h]

[FD(z-n-1) D3h]

Stop

[PEC]

[ALIVE]*

Stop

12+(4 x z) characters 12+(4 x z) characters

12+(4 x z) characters

*If alive-counter mode is enabled.

Maxim Integrated │ 127

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 51. READALL Command Sequencing In Dual-UART Down Path

(z = Number of Devices)

DEVICE(n)

HOST Tx

HOST Rx

RXU

TXL

Preamble

03h

Preamble

03h

Preamble

03h

Preamble

03h

[REG ADDR]

[DATA ADDR]

[REG ADDR]

[DATA LSB(z)] = [DATA

LSB(BA)]

[DC] = 0x00

[DATA LSB(n-1)]

[DATA LSB(n)]

[DATA MSB(z)] = [DATA

MSB(BA)]

[PEC]

[DATA MSB(n-1)]

[DATA MSB(n)]

[DATA LSB(z-1)] = [DATA

LSB(BA +1)]

[ALIVE]*

...

[DATA MSB(z-1)] = [DATA

MSB(BA +1)]

[FD(1) C2h]

[FD(1) D3h]

[FD(2) C2h]

[DATA LSB(1)]= [DATA

LSB(TA)]

[DATA LSB(1)]= [DATA

LSB(TA)]

...

[DATA MSB(1)] =[DATA

MSB(TA)]

[DATA MSB(1)] =[DATA

MSB(TA)]

[FD(2) D3h]

[DC]

...

[PEC]

[ALIVE]*

[FD(1) C2h]

[ALIVE]*

[FD(1) C2h]

[DATA LSB(1)] = [DATA

LSB(TA)]

...

[FD(1) D3h]

...

[FD(1) D3h]

...

[DATA MSB(1)] =[DATA

MSB(TA)]

...

[DC]

[FD(z) C2h]

[FD(z-n) C2h]

[FD(z-n) D3h]

Stop

[FD(z-n-1) C2h]

[FD(z-n-1) D3h]

Stop

[PEC]

[FD(z) D3h]

[ALIVE]*

Stop

12+(4 x z) characters

*If alive-counter mode is enabled.

12+(4 x z) characters

Maxim Integrated │ 128

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

mits it in the order shown in the sequencing table (device

TXU column). The device knows which bytes to overwrite

since its ADDRESS register contains the top, and bottom

device addresses, and its own device address; therefore,

it knows where in the data stream it belongs.

If the register address is not valid for the device, the com-

mand is ignored. The command sequence is shown in

Table 52 and Table 53.

The command packet is forwarded up the daisy-chain

until it reaches the addressed device. The addressed

device overwrites the received fill bytes with the two

bytes of register data and forwards the packet to the

next device. The alive-counter byte (if enabled) is only

READDEVICE Command

The READDEVICE command returns a 16-bit word read

from the specified register in the addressed device only.

Table 52. READDEVICE Sequencing In Single-UART or Dual-UART Up Path

DEVICE

RXL

DEVICE

TXU

HOST Tx

HOST Rx

Preamble

{DA[4:0], 0b101}

[REG ADDR]

[DC]

{DA[4:0], 0b101}

[REG ADDR]

[DC]

{DA[4:0], 0b101}

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

{DA[4:0], 0b101}

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

[PEC]

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

Stop

[FD(1) C2h]

[FD(1) D3h]

Stop

[PEC]

[ALIVE]*

Stop

16 characters

*If alive-counter mode is enabled

16 characters

Table 53. READDEVICE Sequencing In Dual-UART Down Path

DEVICE

RXU

DEVICE

TXL

HOST Tx

HOST Rx

Preamble

{DA[4:0], 0b101}

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

{DA[4:0], 0b101}

[REG ADDR]

[DC]

{DA[4:0], 0b101}

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

[REG ADDR]

[DC]

[PEC]

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

Stop

[PEC]

[FD(1) D3h]

[ALIVE]*

Stop

16 characters

*If alive-counter mode is enabled.

16 characters

Maxim Integrated │ 129

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

incremented by the addressed device. A Manchester error

immediately switches the data propagation from read

mode to write (pass-through) mode, ensuring that the

Manchester error is propagated through the daisy-chain

and back to the host.

for the device, it returns 0 for any invalid addresses. If the

Device Address is not valid, the command be ignored.

The command sequences for a block size of 1 and for

a block size of 2 are shown in Table 54 and Table 55 for

a block size of 1 and Table 56 and Table 57 for a block

size of 2. The command packet is forwarded up the

daisy-chain until it reaches the addressed device. The

addressed device overwrites the received fill bytes with

the 2 bytes of register data (from a single device) and

forwards the packet to the next device. The alive-counter

READBLOCK Command

The READBLOCK command returns a 18-byte read

from the specified register for a Block size of 1 in the

addressed device only. If the register address is not valid

Table 54. READBLOCK Sequencing In Single-UART or Dual-UART Up Path (Block Size = 1)

DEVICE

RXL

DEVICE

TXU

HOST Tx

HOST Rx

Preamble

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

[PEC]

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

Stop

[FD(1) C2h]

[FD(1) D3h]

Stop

[PEC]

[ALIVE]*

Stop

18 characters

*If alive-counter mode is enabled.

18 characters

Table 55. READBLOCK Sequencing In Single-UART or Dual-UART Up Path (Block Size = 1)

DEVICE

RXL

DEVICE

TXU

HOST TX

HOST RX

Preamble

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA0 LSB]

[DAT0 MSB]

[DATA1 LSB]

[DATA1 MSB]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA0 LSB]

[DATA0 MSB]

[DATA1 LSB]

[DATA1 MSB]

[DC]

[PEC]

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

[FD(1) C2h]

[FD(1) D3h]

Stop

[FD(1) C2h]

[FD(1) D3h]

[FD(1) C2h]

[FD(1) D3h]

Stop

[PEC]

[ALIVE]*

Stop

22 characters

*If alive-counter mode is enabled.

22 characters

Maxim Integrated │ 130

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 56. READBLOCK Sequencing In Dual-UART Down Path (Block Size = 2)

DEVICE

RXU

DEVICE

TXL

HOST Tx

HOST Rx

Preamble

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA LSB]

[DATA MSB]

[DC]

[PEC]

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

Stop

[FD(1) C2h]

[FD(1) D3h]

Stop

[PEC]

[ALIVE]*

Stop

18 characters

*If alive-counter mode is enabled.

18 characters

Table 57. READBLOCK Sequencing In Single-UART or Dual-UART Down Path (Block

Size = 2)

DEVICE

RXU

DEVICE

TXL

HOST Tx

HOST Rx

Preamble

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA0 LSB]

[DAT0 MSB]

[DATA1 LSB]

[DATA1 MSB]

[DC]

{BS[4:0], 3b110}

[DEVICE ADDR]

[REG ADDR]

[DATA0 LSB]

[DATA0 MSB]

[DATA1 LSB]

[DATA1 MSB]

[DC]

[PEC]

[ALIVE]*

[FD(1) C2h]

[FD(1) D3h]

[FD(1) C2h]

[FD(1) D3h]

Stop

[FD(1) C2h]

[FD(1) D3h]

[FD(1) C2h]

[FD(1) D3h]

Stop

[PEC]

[ALIVE]*

Stop

22 characters

*If alive-counter mode is enabled.

22 characters

Maxim Integrated │ 131

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

byte (if enabled) is only incremented by the addressed

device. A Manchester error immediately switches the

data propagation from read mode to write (pass through)

mode, ensuring that the Manchester error is propagated

through the daisy-chain and back to the host.

Note: The DOWNHOST command is relevant only when

the device is configured in dual-UART mode. Sending the

DOWNHOST command outside of a dual-UART configu-

ration will not have any effect on the device; the command

is passed through, unchanging the DEVCOUNT.

DOWNHOST Command

UPHOST Command

Only one of the DUALUART paths (Up path or Down

Path) can be granted WRITE access through using the

UPHOST or DOWNHOST commands, however, both

paths have read access. The path that holds the WRITE

access is specified using the UARTHOST register bit.

By default only the Up path has the WRITE access

(UARTHOST=1b1). See Table 58.

Only one of the dual-UART paths (Up path or Down

path) can be granted WRITE access through using

the UPHOST or DOWNHOST commands; however,

both paths have read access. The path that holds the

write access is specified using the UARTHOST regis-

ter bit. By default, only the Up path has write access

(UARTHOST=1b1). See Table 59.

The DOWNHOST command is used when WRITE access

is required to be passed from the Up path (UARTHOST =

1b1) to the Down path (UARTHOST=1b1). Alternatively,

the UPHOST command is used when WRITE access is

required to be passed from the Down path to the Up path.

The UPHOST command is detailed in a different section.

The UPHOST command is used when write access needs

to be passed from the Down path (UARTHOST=1b1)

to the Up path (UARTHOST=1b1). Alternatively, the

DOWNHOST command is used when write access needs

to be passed from the Up path to the Down path. See the

DOWNHOST Command section for further detail.

When the DOWNHOST command is sent, each device

modifies the UARTHOST bit in the DEVCFG1 register

to change master control, as well as increments the

DEVCOUNT variable as it sends the command to the

next device downstream in the chain. The final value of

DEVCOUNT received by the host should be equal to the

initial DEVCOUNT + total number of devices in the chain.

If the DOWNHOST command is sent on the Up path, the

command passes through the device unmodified, leaving

the UARTHOST unchanged; the ALRTDUALUART bit is

also set in the STATUS2 register, signifying that an invalid

command was received. Additionally, If the DOWNHOST

command is sent on the Down path while the Down

path is designated as the master, the command passes

through the device unmodified, leaving the UARTHOST

unchanged with the Down path indication.

When the UPHOST command is sent, each device

modifies the UARTHOST bit in the DEVCFG1 register

to change master control, as well as increments the

DEVCOUNT variable as it sends the command to the

next device upstream in the chain. The final value of

DEVCOUNT received by the host should be equal to the

initial DEVCOUNT + total number of devices in the chain.

If the UPHOST command is sent on the Down path, the

command passes through the device unmodified, leaving

the UARTHOST unchanged; the ALRTDUALUART bit

will also be set in the STATUS2 register, signifying that

an invalid command was received. Additionally, If the

UPHOST command is sent on the Up path while the Up

path is designated as the master, the command passes

through the device unmodified, leaving the UARTHOST

unchanged with the Up path indication.

Table 58. DOWNHOST Sequencing (z = Total Number of Devices)

HOST Tx

DEVICE (n) RXU

Preamble

DEVICE (n) TXL

Preamble

HOST Rx

Preamble

09h

Preamble

09h

00h

{0b000,DEVCOUNT[4:0]}

Stop

{0b000,DEVCOUNT[4:0]+n-1}

Stop

{0b000,DEVCOUNT[4:0]+n}

Stop

{0b000,DEVCOUNT[4:0]+z}

Stop

Maxim Integrated │ 132

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 59. UPHOST Sequencing (z = total number of devices)

HOST Tx

DEVICE (n) RXL

DEVICE (n) TXU

HOST Rx

Preamble

08h

Preamble

08h

00h

{0b000,DEVCOUNT[4:0]}

Stop

{0b000,DEVCOUNT[4:0]+n-1}

Stop

{0b000,DEVCOUNT[4:0]+n}

Stop

{0b000,DEVCOUNT[4:0]+z}

Stop

Note: The DOWNHOST command is relevant only when

the device is configured in dual-UART mode. Sending the

DOWNHOST command outside of a dual-UART configu-

ration will not have any effect on the device; the command

is passed through unchanging the DEVCOUNT.

Table 60. ALERTPACKET Sequencing

ALERT PACKET

Preamble

Command Byte (0x21)

Module Alert Location 1 {(DA[4:7]), (DA[0:3])}

Module Alert Location 2 {(DA[12:15]),(DA[8:11])}

Module Alert Location 3 {(DA[20:23]),(DA[16:19])}

Module Alert Location 4 {(DA[28:31]),(DA[24:27])}

[STATUS LSB]

ALERTPACKET Command

The MAX17853 supports the transmission of an ALERT

packet from either the host microcontroller or SPI to

UART bridge. This packet contains the alert command

byte, daisy-chain module alert data-address location

(DA[4:0]), and alert status byte, as well as the PEC byte

of the protected data (see Table 60).

[STATUS MSB]

[PEC]

The module alert location is a 32-bit value split into four

transmission data packets, where each bit represents the

device address (DA[4:0]), defined by the HELLOALL com-

mand. The alert status is the 16-bit output of the STATUS1

register, subject to masking through ALRTIRQEN, as

Stop

Maxim Integrated │ 133

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

described in the following sections. As the data passes

through the daisy-chain, the module alert location con-

tains a unique identifier; the STATUS output will be logi-

cally OR'ed to communicate the alert type. This creates

a method to quickly assess the module status and health

with little host interaction.

CSB line held low will accept SCLK SPI transactions to

the slave devices are defined by SCLK rising edges. The

start of the transaction is defined by the SCLK rising edge,

following the CSB falling edge (subject to t

and

CSH0

t

timing criteria). Transactions including a number of

CSS0

SCLK rising edges not equal to 32 will not be qualified for

execution (also based on t , t , and t timing

CSA CSH1

CSQ

SPI Interface

criteria). Qualified transactions will be executed on the

rising edge of CSB. To abort a transaction sequence, the

rise of CSB must precede a qualified (32nd) rising edge

When a single device is used in a single battery-pack

application with no daisy-chain, the host can use the

SPI interface to communicate with the device. The host

should set UARTSEL low. When UARTSEL is set high,

the device uses the UART interface to communicate with

the microprocessor.

of SCLK (meeting the t

timing requirement). Note:

CSA

An aborted command will result in the issuance of an SPI

CLK Error.

The SDI line should be hooked up to a master-out/slave-

in (MOSI) port and distributed to all slave devices. SDI

data is latched into the selected slave device on SCLK

Overview

The MAX17853 SPI interface is SPI/QSPI™/Microwire/

DSP compatible, ensuring compatible operation with

standard microcontrollers (µCs) from a variety of manu-

facturers.

rising edges, subject to setup and hold criteria (t , t ).

DS DH

The SDI content of the SPI transaction consists of 4 bytes

for qualified transactions.

The SDO line should be hooked up to a master-in/slave-

out (MISO) port and distributed to all slave devices. SDO

is actively driven by the selected slave device when CSB

The µC always operates as the master and is able to initi-

ate read and write transactions to individual slave devices

selected by a specific CSB connection. The operation

and timing criteria of the SPI interface is shown in Figure

65. The MAX17853 will be programmed by a qualified

32-cycle SPI instruction framed by a CSB low interval.

falls (t

timing applies), initially presenting the MSB

DOE

of the output data (the SPI_CRC_ERR bit for all trans-

actions). Following the initial SCLK rising edge, SDO is

updated in response to SCLK falling edges, conforming

The SCLK line should be driven by the master and dis-

tributed to all slave devices. Only the slave device with its

to hold and transition time criteria (t

t

), allowing

DOH, DOT

DI31

DI30

DI29

DI28

DI27

DI26

DI25

DI24

DI23

DI22

DI1

DI0

DI31*

1*

SDI

SCLK

CSB

t

DS

DH

CP

1

2

3

4

5

6

7

8

9

10

31

32

t

CSQ

CSH0

CSS0

CH

CL

CSH1

t

CSA

t

DOZ

CSPW

DOE

DOT

DOH

HIGH-Z

DO31

DO30

DO29

DO28

DO27

DO26

DO25

DO24

DO23

DO22

DO1

DO0

DO31*

SDO

t

TO

Figure 65. SPI Timing Diagram

QSPI is a trademark of Motorola, Inc.

Maxim Integrated │ 134

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the µC to latch the data on SCLK rising edges. When CSB

is high, the SDO line is high-impedance, allowing other

slave devices to access the SDO bus.

ing its unique CSB port low. Note that each slave device

on the interface requires a dedicated CSB line from the

master. The SCLK, SDI, and SDO lines are common to

all devices. A total of (3+N) lines is required for an inter-

face supporting N slave devices. Transaction qualification

criteria remain in effect; in write mode, the device will

only execute instructions exactly 32 bits in length. In read

mode, return the requested data through SDO during the

read-mode transaction. A standard connection example is

shown in Figure 66.

Transactions lasting longer than the timeout interval (t ),

TO

measured from CSB falling edge to CSB rising edge qre

not qualified or executed.

System-Level Connection

Following the previous guidelines, the SPI interface

allows multiple devices to share the SPI interface with the

active device for the transaction being selected, by pull-

MAXxxxx DevN

µC SPI MASTER

CSBN

CSB

SCLK

SDI

CSB2

CSB1

SCLK

MOSI

MISO

SDO

MAXxxxx Dev2

CSB

SCLK

SDI

SDO

MAXxxxx Dev1

CSB

SCLK

SDI

SDO

Figure 66. SPI Device Connection

CSB

1

8

9

16

17

24

DI8

25

DI7

32

SCLK

SDI

X

DI31 DI30 DI29 DI28 DI27 DI26 DI25 DI24 DI23 DI22 DI21 DI20 DI19 DIN18 DI17 DI16 DI15 DI14 DI13 DI12 DI11 DI10 DI9

DI6

DI5

DI4

DI3

DI2

DI1

DI0

X

DO23

DO15

DO7

DO31 DO30 DO29 DO28 DO27 DO26 DO25 DO24

DO22 DO21 DO20 DO19 DO18 DO17 DO16

DO14 DO13 DO12 DO11 DO10 DO9 DO8

DO6 DO5 DO4 DO3 DO2 DO1 DO0

SDO

CPOL = 0 CPHA = 0 TRANSACTION ALIGNMENT

CSB

SCLK

SDI

1

8

9

16

17

24

DI8

25

32

X

DI31 DI30 DI29 DI28 DI27 DI26 DI25 DI24 DI23 DI22 DI21 DI20 DI19 DIN18 DI17 DI16 DI15 DI14 DI13 DI12 DI11 DI10 DI9

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

DO0

X

DO23

DO15

DO7

DO31

DO30 DO29 DO28 DO27 DO26 DO25 DO24

DO22 DO21 DO20 DO19 DO18 DO17 DO16

DO14 DO13 DO12 DO11 DO10 DO9 DO8

DO6 DO5 DO4 DO3 DO2 DO1

SDO

CPOL = 1 CPHA = 1 TRANSACTION ALIGNMENT

Figure 67. SPI Supported Transaction Alignments

Maxim Integrated │ 135

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

exactly what data was sent to the device during the trans-

Supported Transaction Alignments

action.

The MAX17853 is capable of supporting SPI transactions

with masters using either (CPOL=0 and CPHA=0) or

(CPOL=1 and CPHA=1). Examples of these transactions

are shown in Figure 67.

The MAX17853 will only accept and execute qualified SPI

transactions based on the 32 bits of SDI data received

and several interface integrity checks. Details of write-

mode transactions are explained below and summarized

in Figure 68.

Safety Pulup/Pulldown Resistors

To guard against broken SPI interface connections, the

MAX17853 includes internal safety terminations on all

SPI interface input ports. SCLK and SDI have internal

SPI Write-Mode Input Data Format

During write-mode transactions, the MAX17853 accepts

qualified instructions through the SDI input, described

as follows. If more than 32 SCLK cycles are provided in

the transaction, the device ignores the excess data pro-

vided during the remaining clock cycles, the transaction is

ignored, and an SPI clock error issued.

pulldowns to GND. CSB has an internal pulup to V

.

DDL3

All safety resistors are 100kΩ (nom).

The internal safety resistors can be individually enabled

or disabled using DEVCFG1 register bits (SFTYSCLK,

SFTYSDI, SFTYCSB) with a high state (default) to indi-

cate the safety termination is enabled/engaged and a low

state to indicate it is disengaged. This allows the user to

eliminate loading currents when the safety resistors are

not needed. Note pulup resistors still have a resistor and

An SPI error due to frame length sets the ALRTINTRFC

and ALRTSPI bits in the STATUS1 and STATUS2 regis-

ters, respectively, as well as the CLK_ERR diagnostic bit

(DO[28]) present in every SPI frame.

diode connection to V

even if disengaged (limiting

+ 0.3V to avoid conduction).

DDL3

Write Bit — R/WB = 0 (DI[31])

CSB voltage to V

DDL3

Write-mode transactions are identified by R/WB = 0 in

MSB position of the 32-bit data frame

SPI Transactions

SPI Write-Mode Transcations

Address — A[7:0] (DI[30:23])

A properly constructed write-mode transaction is made up

of a 32-bit data frame. Each SDI data frame from the mas-

ter contains a R/WB=0 bit, an 8-bit command/address, a

3-bit CRC covering the command/address, 2 bytes of input

data, a confirmation of the R/WB=0 bit, and a 3-bit CRC

covering the input data.

Write-mode transactions allow new information to be writ-

ten to internal configuration/command registers within the

device. The register address to be written is indicated by

A[7:0] within the data frame.

Address Cyclic-Redundancy Check — CRCA[2:0]

(DI[22:20])

During a write-mode transaction, the MAX17853 outputs

data on the SDO line confirming device status, as well

as the command/address and input data received. Each

SDO data frame from the slave contains 5 bits of status

information protected by a 3-bit CRC followed by a 24-bit

direct readback of the command/address and input data

received during the transaction. Note that while the 24-bit

readback is not CRC protected, the transaction can be

verified with 100% confidence since the master knows

Write-mode command/address data transactions are

protected by a 3-bit CRC with polynomial 0x5 (x +x+1). A

3

total of 9 bits are protected, yielding a Hamming distance

of 2 (HD = 2). The CRCA check is calculated over the fol-

lowing bits: R/WB + A[7:0] (i.e., positions DI[31:23]), con-

firming the integrity of the incoming command. The mas-

ter must embed the correct CRCA value within each data

frame in positions DI[22:20] for the transaction to qualify

for execution. The receiving slave will only accept/execute

CSB

1

8

9

16

17

24

25

32

SCLK

SDI

X

WB

A7

A6

A5

A4

A3

A2

A1

A0 CRCA2 CRCA1 CRCA0 D_IN15 D_IN14 D_IN13 D_IN12 D_IN11 D_IN10 D_IN

9

D_IN

8

D_IN

7

D_IN

6

D_IN

5

D_IN

4

D_IN

3

D_IN

2

D_IN

1

D_IN

0

WB’ CRCD2 CRCD1 CRCD0

X

CRC_ RW_ TO_ CLK_

ERR ERR ERR ERR

ALERT CRCS2 CRCS1 CRCS0 A7'

A6'

A5'

A4'

A3'

A2'

A1'

A0' D_IN15' D_IN14' D_IN13' D_IN12' D_IN11' D_IN10' D_IN9' D_IN8' D_IN7' D_IN6' D_IN5' D_IN4' D_IN3' D_IN2' D_IN1' D_IN0'

SDO

Figure 68. SPI Write-Mode Transaction Format

Maxim Integrated │ 136

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the transaction if the CRCA check is passed; otherwise,

the transaction is ignored and an SPI CRC error issued.

Status Cyclic-Redundancy Check — CRCS[2:0]

(DO[26:24])

During write-mode transactions, the MAX17853 outputs

status CRC data protecting the status information pro-

vided through SDO. Since the CRCS[2:0] information is

identical for both read- and write-mode transactions, the

definition of these bits is described in a common section

that follows.

SPI errors caused by CRCA failures set the ALRTPEC bit

in the STATUS1 register, as well as the CRC_ERR diag-

nostic bit (DO[31]) present in every SPI frame.

Input Data — DIN[15:0] (DI[19:4])

These 2 bytes of input data in the 32-bit data frame repre-

sent data that will be written to the requested register, or

describes internal operations to be executed.

Address Conﬁrmation — A‘[7:0] (DO[23:16])

During write-mode transactions, the MAX17853 relays the

incoming address (A[7:0]) data received through SDI in

positions DO[23:16] through SDO. This behavior allows

the master complete confirmation that what was sent

through the SPI interface was accurately received by the

device; as such, the write-mode confirmation data is not

covered by a CRC. If any error is detected, the master

should react accordingly, knowing that the flawed trans-

action may have been rejected if an SPI error condition

was detected and/or the CRCA check on the incoming

transaction did not pass.

Repeated-Write Bit — R/WB‘ = 0 (DI3)

Write-mode transactions are confirmed by a repeated R/

WB = 0 in position DI[3] of the bit data frame. If the data

in positions DI[31] and DI[3] do not match, the transaction

is ignored and an SPI RW error issued.

SPI errors caused by R/WB and R/WB' mismatches set

the ALERTINTRFC and ALRTSPI bits in the STATUS1

and STATUS2 registers, respectively, as well as the RW_

ERR diagnostic bit (DO[30]) present in every SPI frame.

Input Data Cyclic-Redundancy

Check — CRCD[2:0] (DI[2:0])

Input Data Conﬁrmation — DIN‘[7:0] (DO[15:0])

During write-mode transactions, the MAX17853 relays the

incoming input data (DIN[7:0]) received through the SDI in

positions DO[15:0] through SDO. This behavior allows the

master complete confirmation that what was sent through

the SPI interface was accurately received by the device;

as such, the write-mode confirmation data is not covered

by a CRC. If any error is detected, the master should react

accordingly, knowing that the flawed transaction may

have been rejected if an SPI error condition was detected

and/or the CRCD check on the incoming transaction did

not pass.

Write-mode input data transactions are protected by a

3-bit CRC with polynomial 0x5 (x +x+1). A total of 16

bits are protected, yielding a Hamming distance of 2 (HD

= 2). The CRCD check is calculated over the following

3

bits: D [15:0] (i.e., positions DI[19:4]). The master must

IN

embed the correct CRCD value within each data frame in

positions DI[2:0] for the transaction to qualify for execu-

tion. The slave only accepts/executes the transaction if

the CRCD is passed; otherwise, the transaction is ignored

and an SPI CRC error issued.

SPI errors caused by CRCD failures set the ALRTPEC bit

in the STATUS1 register, as well as the CRC_ERR diag-

nostic bit (DO[31]) present in every SPI frame.

SPI Write-Mode Qualiﬁcation Checks

To qualify for write-mode execution, the following condi-

tions must be met:

● SPI transaction must be exactly 32 bits in length

(with no CLK_ERR recorded)

● CRCA address CRC check must pass (with no CRC_

ERR recorded)

● CRCD input data CRC check must pass (with no

CRC_ERR recorded)

SPI Write-Mode Output Data Format

During write-mode transactions, the MAX17853 outputs

data through the SDO line confirming both device status

and the received instructions, as described below. If more

than 32 SCLK cycles are provided in the transaction,

the device will output zeros for the remaining cycles, the

transaction will be ignored and an SPI clock error issued.

● R/WB must match R/WB’ (i.e., DI[31] = DI[3] (with no

RW_ERR recorded)

Status Information — STAT[4:0] (DO[31:27])

● SPI transaction must be completed within the timeout

During write-mode transactions, the MAX17853 outputs

status data through the SDO line confirming current device

status. Since the STAT[4:0] information is identical for both

read- and write-mode transactions, the definition of these

bits is described in a common section that follows.

interval (t , with no TO_ERR recorded)

TO

If the SPI transaction is qualified, the instruction will be

executed, and the requested internal register contents

updated, or the requested action performed.

Maxim Integrated │ 137

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

If the SPI write transaction is not qualified, the instruction

is not executed, and the appropriate SPI error diagnostic

bits will be set. The SPI error diagnostic bits are returned in

response to later read- and write-mode transactions, notify-

ing the µC that the SPI interface may be compromised.

ters, respectively, as well as the CLK_ERR diagnostic bit

(DO28) present in every SPI frame.

Read Bit — R/WB = 1 (DI[31]):

Read-mode transactions are identified by R/WB =1 in the

MSB position of the 32-bit data frame.

SPI Read-Mode Transactions

Address — A[7:0] (DI[30:23])

A properly constructed read-mode transaction is made up

of a 32-bit data frame. Each SDI data frame from the mas-

ter contains a R/WB=1 bit, an 8-bit requested address, a

3-bit CRC covering the address, two bytes of input data =

0000\h, a confirmation of the R/WB=1 bit, and a 3-bit CRC

covering the input data.

Read-mode transactions fetch the information from the

register requested by the address byte (A[7:0]). If the

CRCA check fails, indicating a problem with the transac-

tion or interface, the MAX17853 still reads back the data

requested by A[7:0]. This may not be what the master

intended, and the master will be notified of this through the

read-mode confirmation bit (ROK, see following sections).

Note that reading from a reserved address results in a

During a read-mode transaction, the MAX17853 outputs

data on the SDO line confirming device status, and pro-

viding the data requested with full CRC protection. Each

SDO data frame from the slave device contains 5 bits of

status information protected by a 3-bit CRC, four ones

(indicating a read operation is pending), followed by 16

bits of output data, and finally, a read-mode confirmation

bit and a 3-bit CRC protecting the output data.

read-back value of D [15:0] = 0000\h.

OUT

Address Cyclic Redundancy Check — CRCA[2:0]

(DI[22:20])

Read-mode command/address data transactions are

3

protected by a 3-bit CRC with polynomial 0x5 (x +x+1). A

total of 9 bits are protected, yielding a Hamming distance

of 2 (HD=2). The CRCA check is calculated over the fol-

lowing bits: R/WB + A[7:0] (i.e., positions DI[31:23]), con-

firming the integrity of the incoming command. The mas-

ter must embed the correct CRCA value within each data

frame in positions DI[22:20] for the transaction to qualify

for execution. The receiving slave device will only accept/

execute the transaction if the CRCA is passed; otherwis,

the transaction is ignored and an SPI CRC error issued.

The MAX17853 will only accept and execute qualified SPI

transactions, based on the 32 bits of SDI data received,

and several interface integrity checks. Details of read-

mode transactions are explained in following sections and

summarized in Figure 69.

SPI Read-Mode Input-Data Format

During read-mode transactions, the MAX17853 accepts

qualified instructions through the SDI inputs, as described

below. If more than 32 SCLK cycles are provided in the

transaction, the device ignores the excess data provided

during the remaining clock cycles, the transaction will be

ignored, and an SPI Clock error issued.

SPI errors caused by CRCA failures set the ALRTPEC bit

in the STATUS1 register, as well as the CRC_ERR diag-

nostic bit (DO[31]) present in every SPI frame.

An SPI error due to frame length sets the ALRTINTRFC

and ALRTSPI bits in the STATUS1 and STATUS2 regis-

CSB

1

8

9

16

17

24

25

32

R’ CRCD2 CRCD1 CRCD0

ROK CRCO2CRCO1CRCO0

SCLK

SDI

X

R

A7

A6

A5

A4

A3

A2

A1

A0 CRCA2 CRCA1 CRCA0 D_IN15 D_IN14 D_IN13 D_IN12 D_IN11 D_IN10 D_IN

9

D_IN

8

D_IN

7

D_IN

6

D_IN

5

D_IN

4

D_IN

3

D_IN

2

D_IN

1

D_IN

0

X

CRC_ RW_ TO_ CLK_

ERR ERR ERR ERR

ALERT CRCS2 CRCS1 CRCS0 (R)

(R)

(R) D_OUT15 D_OUT14 D_OUT13 D_OUT12 D_OUT11 D_OUT10 D_OUT

9

D_OUT

8

D_OUT

7

D_OUT

6

D_OUT

5

D_OUT

4

D_OUT3 D_OUT2 D_OUT1 D_OUT0

SDO

Figure 69. SPI Read-Mode Transaction Format

Maxim Integrated │ 138

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Input Data — DIN[15:0] (DI[19:4])

Status Cyclic-Redundancy Check — CRCS[2:0]

(DO[26:24])

These 2 bytes of input data in the 32-bit data frame must

be set to zero (0000h); otherwise, the transaction is

ignored and an SPI error issued.

During read-mode transactions, the MAX17853 outputs

status CRC data, protecting the status information pro-

vided through SDO. Since the CRCS[2:0] information is

identical for both read- and write-mode transactions, the

definition of these bits is described in a common section

that follows.

SPI errors generated by read transactions with non-zero

input data set the ALERTINTRFC and ALRTSPI bits in

the STATUS1 and STATUS2 registers, respectively, as

well as the RW_ERR diagnostic bit (DO[30]) present in

every SPI frame.

Read Conﬁrmation Bits — F\h (DO[23:20])

During read-mode transactions, the MAX17853 relays

four ones in the DO[23:20] position, indicating the R/

WB bit received was a one and a read-mode transaction

has been requested. Since all addresses above 0x98

are reserved, seeing all ones in this position during a

WRITEMODE command indicates an interface or pro-

tocol fault. Likewise, seeing anything but all ones in this

position during a read-mode command indicates the R/

WB was not received or the interface is compromised. If

either error is detected, the master should react accord-

ingly, knowing that the flawed transaction may have been

rejected if an SPI error and/or CRC checks on the incom-

ing transaction did not pass.

Repeated-Read Bit — R/WB‘ = 1 (DI[3])

Read-mode transactions are confirmed by a repeated

R/WB=1 in position DI[3] of the bit data frame. If the data

in positions DI[31] and DI[3] do not match, the transaction

is ignored and an SPI RW error issued.

SPI errors caused by R/WB and R/WB' mismatches set

the ALERTINTRFC and ALRTSPI bits in the STATUS1

and STATUS2 registers, respectively, as well as the RW_

ERR diagnostic bit (DO[30]) present in every SPI frame.

Input-Data Cyclic-Redundancy Check – CRCD[2:0]

(DI[2:0])

Read-mode input-data transactions are protected by a

3

3-bit CRC with polynomial 0x5 (x +x+1). A total of 16

Output Data — DOUT[15:0] (DO[19:4])

bits are protected, yielding a Hamming distance of 2 (HD

= 2). The CRCD check is calculated over the following

During read-mode transactions, the MAX17853 relays the

requested output data (D

through SDO.

[15:0]) in positions DO[19:4]

OUT

bits: D [15:0] (i.e., positions DI[19:4]). The master must

IN

embed the correct CRCD value within each data frame in

positions DI[2:0] for the transaction to qualify for execu-

tion. The slave will only accept/execute the transaction if

the CRCD is passed; otherwise, the transaction is ignored

and an SPI CRC error issued.

Read OK Bit — ROK (DO[3])

During read-mode transactions, the MAX17853 relays a

1 in the DO3 position, indicating a read-mode transaction

is in progress and the CRCA check has passed. This,

combined with the read-confirmation bits in positions

DO[23:20] allows the master to confirm the data received

matches the address requested.

SPI errors caused by CRCD failures set the ALRTPEC bit

in the STATUS1 register, as well as the CRC_ERR diag-

nostic bit (DO[31]) present in every SPI frame.

Output-Data Cyclic-Redundancy Check —

CRCO[2:0] (DO[2:0])

SPI Read-Mode Output-Data Format

During read-mode transactions, the MAX17853 outputs

data through the SDO line, confirming device status and

the requested output data, described as follows. If more

than 32 SCLK cycles are provided in the transaction, the

device outputs zeros for the remaining cycles, the trans-

action is ignored, and an SPI clock error issued.

Read-mode output data transmissions are protected by a

3

3-bit CRC with polynomial 0x5 (x + x + 1). A total of 16

bits are protected, yielding a Hamming distance of 2 (HD

= 2). The CRC check is calculated over the following bits:

D

[15:0] (i.e., positions DO[19:4]). The MAX17853 will

OUT

embed the correct CRC value within each data frame in

positions DO[2:0] for the transaction to be qualified by the

master. The master should only accept the output data

as valid if the CRCO check passed; otherwise, the data

should be considered compromised.

Status Information – STAT[4:0] (DO[31:27])

During read-mode transactions, the MAX17853 output

status data through the SDO line confirming current

device status. Since the STAT[4:0] information is identical

for both read and write-mode transactions, the definition

of these bits is described in a common section below.

Maxim Integrated │ 139

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

transaction was rejected due to one or more of the

SPI Read-Mode Qualiﬁcation Checks

following errors:

• Repeated R/WB mismatch, R/WB ≠ R/WB’

(i.e., DI[31]≠DI[3], protocol error)

To qualify for read-mode execution, the following condi-

tions must be met:

● SPI transaction must be exactly 32 bits in length

(with no CLK_ERR recorded)

● CRCA address CRC check must pass (with no

CRC_ERR recorded)

● CRCD input data CRC check must pass (with no

CRC_ERR recorded)

• D [15:0]≠0000\h for any read-mode transaction

IN

(protocol error)

●

SPI TO_ERR (STAT2) Indicates a previous

transaction was rejected due to a timeout violation

SPI CLK_ERR (STAT1) Indicates a previous

transaction was rejected due to one or more of the

following conditions:

● R/WB must match R/WB’ (i.e., DI[31] = DI[3] (with no

RW_ERR recorded)

● D [15:0] must match the required value of 0000\h

IN

• Number of SCLK cycles was not exactly 32

(ALRTSCLKERR)

• 16MHz HF OSC is halted or drifting severely

(ALRTOSC3)

(with no RW_ERR recorded)

● SPI transaction must be completed within the timeout

interval, t

(with no TO_ERR recorded)

TO

Since the full SPI transaction cannot be fully qualified until

it is completed, the MAX17853 responds to all read-mode

transactions as received, providing the requested output

data within the frame, based on the received value of

A[7:0]; however, if the command in its entirety is found to

fail any qualification check, the command will be rejected,

which means any clear-on-read behaviors expected will

not be executed internally.

• Expected transfer to the internal memory bus has

failed (ALRTINTBUS)

●

ALERT (STAT0) Indicates one or more alert

conditions exist in the STATUS or FMEA registers

If multiple SPI Protocol errors occur during a single trans-

action, only the first error will be reported in the follow-

ing order of precedence: CLK_ERR (ALRTSCLKERR),

CRC_ERR, RW_ERR. SPI Timeout Errors, TO_ERR,

and Internal Clock Errors, CLK_ERR (ALRTOSC3 and

ALRTINTBUS) Can be reported with other errors occurring

in the same transaction. This is done to aid identification

of root cause. For example, a malformed transaction 33

SCLK cycles in length would fail the clock check, but may

also fail CRC and address checks since the data is also

likely misaligned as a result. In such a case, only the CLK_

ERR SPI diagnostic bit would be set, due to precedence.

In addition, if the SPI write transaction is not qualified, the

appropriate SPI error diagnostic bits will be set. The SPI

error diagnostic bits will be returned in response to later

read- and write-mode transactions, notifying the µC that

the SPI interface may have been compromised.

General-Transaction Information (SPI)

The following sections describe behaviors common to

both read- and write-mode transactions.

All SPI diagnostic bits are "Write 0 to Clear," meaning

once asserted, they continue to read back as high until

the content is cleared by writing 1'b0 to the particular

status register bit: ALRTSPI ( clear CRC_ERR, RW_ERR,

and TO_ERR), component bits in STATUS2 clear indi-

vidual components of CLK_ERR. The MAX17853 keeps

a cumulative list of all SPI failure types observed dur-

ing failed transactions until the readback is performed.

Note: The SPI CRC_ERR condition is reported using

the dedicated STATUS1:ALRTPEC bit (read only), but is

cleared using the STATUS2:ALRTSPI (i.e., the CRC_ERR

condition is not reported in ALRTSPI). To clear ALRTPEC,

it may be necessary to write ALRTSPI to zero even if it is

already zero (if no other SPI errors are reported).

Status and Status CRC Output Data

The MAX17853 provides status (STAT[4:0]) and status

CRC (CRCS[2:0]) data through SDO during the MSByte

of each SPI transaction. The content is identical for both

read- and write-mode transactions (defined as follows):

Status Information — STAT[4:0] (DO[31:27])

The MAX17853 provide the following SPI error diag-

nostic bits and alerts during both read- and write-mode

transactions.

●

SPI CRC_ERR (STAT4) Indicates a previous

transaction was rejected due to a CRC failure for

checks CRCA or CRCD.

●

SPI RW_ERR (STAT3) Indicates a previous

Maxim Integrated │ 140

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

All device STATUS alert bits remain asserted (and thus

the ALERT interface remains asserted), until the content

is cleared by the proper operations. See STATUS register

definitions for specific details.

in the SPI ALERT bit; it is available for inclusion in the

ALERT Interface, to support interrupt-driven applications.

Status Cyclic Redundancy Check — CRCS[2:0]

(DO[26:24])

Note that transactions processed after any SPI diag-

nostic or device alert bit are set and remain high will be

qualified and executed/accepted as defined under normal

operation—a previous/uncleared error condition does not

prevent further transactions from being executed.

Status output-data content is protected by a 3-bit CRC

with polynomial 0x5 (x +x+1). A total of 5 bits are pro-

3

tected, yielding a Hamming distance of 2 (HD=2, meaning

the CRC will reliably catch transactions with 2-bit errors

or less). The CRCS check is calculated over the following

bits: STAT[4:0] (i.e., positions DO[31:27]). The MAX17853

embeds the correct CRCS value within each data frame

in positions DO[26:24] for the transaction to be qualified

by the master. The master should only accept the status

data as valid if the CRCS check is passed; otherwise, the

data should be considered compromised.

SPI ALERT Bit-Masking Operations

Assertion of the SPI ALERT Status bit (STAT0, DO27) is

based on the contents of the STATUS1 register. Individual

alert conditions can be masked out of the SPI Alert bit

using settings in ALRTIRQEN; however, the underlying

alert information will always be available for readback in

the STATUS1 register.

SPI CRC Calculations

All SPI CRC calculations use the same polynomial and

CRC calculation method. CRC operations on incoming

SDI data streams (CRCA and CRCD) are performed

by the MAX17853 and require the host to compute the

required CRC Remainders for inclusion in the SDI input

data stream. CRC operations on outgoing SDO data

streams (CRCS and CRCO) are performed by the host,

based on CRC Remainders supplied by the MAX17853.

To support SPI CRC computations and checking, the host

must implement a CRC-3 encoding and decoding algo-

rithm based on the following polynomial (0x5):

SPI ALERT =

ALRTRST or (ALRTMSMTCH & MSMTCHALRTEN) or

(ALRTCELLOVST & CELLOVSTALRTEN) or

(ALRTCELLUVST & CELLUVSTALRTEN) or

(ALRTBLKOVST & BLKOVALRTEN) or (ALRTBLKUVST

& BLKUVALRTEN) or

(ALRTAUXOVST & AUXOVSTALRTEN) or

(ALRTAUXUVST & AUXUVSTALRTEN) or

(ALERTPEC & PECALRTEN) or (ALRTINTRFC &

INTRFCALRTEN) or

3

1

P x = x + x +1

( )

(ALRTCAL & CALALRTEN) or (ALRTCBAL &

CBALALRTEN) or

This polynomial is capable of protecting the covered SPI

content with a Hamming distance of two, meaning any

combination of 2 bits of error or less is guaranteed to be

identified. If more than 2 bits of error are encountered,

(ALRTFMEA1 & FMEA1ALRTEN) or (ALRTFMEA2 &

FMEA2ALRTEN)

Note: STATUS1:ALRTRST indicates a POR condition,

and thus cannot be masked. STATUS1:ALRTSCAN is a

procedural notification bit and is intentionally not included

Table 61. SPI CRC Operation Summary

CRCN

OPERATION

R/W

TRANSACTION

COVERED

DATA

POSITION

TRANSACTION

BIT MASK

CRCN

REMAINDER

CRCN

POSITION

Address (CRCA)

Input Data (CRCD)

Status (CRCS)

Read and Write

Read only

R/WB + A[7:0]

DI[31:23]

DI[19:4]

0xFF80_0000

0x000F_FFF0

0xF800_0000

0x000F_FFF0

CRCA[2:0]

CRCD[2:0]

CRCS[2:0]

CRCO[2:0]

DI[22:20]

DI[2:0]

D

[15:0]

IN

STAT[5:0]

D [15:0]

OUT

DO[31:27]

DO[19:4]

DO[26:24]

DO[2:0]

Output Data (CRCO)

Maxim Integrated │ 141

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIT 0

BIT 1

BIT 2

INPUT DATA BITSTREAM (MSB FIRST)

Figure 70. SPI CRC Calculation

the SPI CRC operation very likely identify the problem,

though this cannot be mathematically guaranteed.

is successful, and the transaction accepted and executed

by the MAX17853. If there is a mismatch, the MAX17853

will reject the transaction and issue the SPI CRC_ERR

status bit and STATUS1:ALRTPEC flag, notifying the host

of the issue, so the transaction can be resent.

The list of CRCn operations and the effective bit-transac-

tion masking operations are shown in Table 61. A hardware

implementation of the CRC calculation is shown in Figure

70. The CRC Engine shown would be implemented within

both MAX17853 and the host. Be sure to note the ordering

of the bits within the Remainder, as shown in the figure (i.e.

BIT[2:0] = CRCn[2:0]). All SPI CRC calculations are per-

formed by supplying the MSB first, in the order presented

in the SPI transaction.

For outgoing SDO data streams, the MAX17853 first

clears the CRC Engine and then provides the covered bits

within the outgoing data stream into the the CRC Engine,

MSB first. The host should perform the same operation

in parallel. After the final bit of data is processed (in this

case, the LSB of the outgoing data stream is applied

to the Engine), the Engine is stopped and the CRCn

Remainder is known. The CRCn Remainder, as calcu-

lated by the MAX17853 using its copy of the CRC Engine,

then follows within the SPI transaction (also MSB first), for

comparison against the CRC Remainder as calculated by

the host. At this point, there are two equivalent ways the

host can complete the CRCn operation to establish the

validity of the received data:

For incoming SDI data streams, the MAX17853 will first

clear the CRC Engine and then provide the covered bits

within the incoming data stream into the the CRC Engine,

MSB first. The host should perform the same operation

in parallel. After the final bit of data is processed (in this

case, the LSB of the incoming data stream is applied to the

Engine), the Engine is stopped and the CRCn Remainder

is known. The CRCn Remainder, as calculated by the

host using its copy of the CRC Engine then follows within

the SPI transaction (also MSB first), and is internally

compared against the CRC Remainder as calculated by

the MAX17853. If the CRCn Remainder received from

the host matches the CRC Remainder calculated by the

device for the incoming data stream, the CRC operation

● Direct Comparison Method: The host stops the CRC

Engine once the data LSB is applied and compares

the resulting CRCn Remainder to the Remainder sup-

plied by the MAX17853 (again, MSB first). If the two

Remainders match, the data is accepted as valid, other-

wise it should be rejected. This is the method employed

by the MAX17853 internally, as described above.

Maxim Integrated │ 142

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

● Zero Remainder Method: The host continues CRC Engine computations after the data LSB is applied by appending

the received Remainder to the end of the data stream, MSB first (i.e., in the order received during the SPI transac-

tion). Once the LSB of the Remainder arrives at the input of the CRC Engine, if the resulting CRC Remainder=0h,

the data is accepted as valid; otherwise, it should be rejected.

SPI CRC Pseudocode Example

Function SPI_CRC_Calculation(Data, CRC)

{

//Data - the incoming data [MSB:LSB] for which CRC needs to be calculated

//CRC - the calculated CRC that be returned by the function

//Calculate length of incoming data

//Data length is 5 for Status (CRCS), 9 for Address (CRCA), and 16 for

Data (CRCD and CRCO)

DataLength = Length(Data)

//CRC polynomial = x^3 + x + 1

POLY = 4'hB //Polynomial = 4'b1011

//Append Data with 3 zeros for 3 bit CRC

DataCalc = {Data, 3'b000}

//Append zeros to POLY such that it is of the same length as DataCalc

PolyZeros = {{(DataLength + 3 - 4) 1'b0}} //Data Calc length = DataLength

+ 3

//Since POLY = 4bits, subtract 4

PolyCalc = {POLY, PolyZeros}

//Append Zeros to POLY

For Counter = (DataLength+3) to 4

MSB to LSB of Data

//Counter decremented from

(

//Check MSB of DataCalc

//If DataCalc[Counter] = 1'b1, bitwise XOR PolyCalc with DataCalc, and

store result in DataCalc

//If DataCalc[Counter] = 1'b0, skip the XOR operation

//Circular Shift PolyCalc right by 1 bit every iteration.

if(DataCalc[Counter] == 1'b1) Then

DataCalc = DataCalc XOR PolyCalc

End If

Maxim Integrated │ 143

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

PolyCalc

=

{PolyCalc[0],

ally met, the transaction not be qualified or executed, and

the TO_ERR diagnostic bit be set.

PolyCalc[Length[PolyCalc-1

: 1]} //Circular Shift Right

PolyCalc by 1 bit

In order to resolve a timed-out transaction and move for-

ward with subsequent transactions, the timed-out trans-

action needs to be terminated by bringing CSB high. It is

not necessary to complete the transaction by supplying

32 clocks; though if this is not done, the SPI CLK_ERR

condition will be reported in addition to the TO_ERR

condition. New transactions can then begin, initiated by

pulling CSB low.

)

Return

DataCalc[3:1]

//3

LSBs of DataCalc give the 3

bit CRC}

SPI Timeout Behavior

All SPI transactions are timed by an internal 16MHz

oscillator and are measured from the falling edge of CSB

initiating a transaction to the rising edge of CSB terminat-

Alert Interface

The alert interface communicates the presence of a fault

condition generated from the logical OR of the STATUS1

register, which flags any error within safety-critical func-

tionality: voltage measurements, temperature measure-

ments, interface-communication robustness, calibration,

as well as other internal hardware diagnostics. Because

the safety consideration per platform may differ, each of

the associated alerts can be masked to provide individu-

alized control. Additionally, the interface may be actively

driven without the need of an actual alert condition to

validate the functionality when commanded. This is done

using the ALRTUSER bit in the FMEA2 register

ing a transaction. If the time out interval (t ) is exceeded

TO

by a transaction, the transaction be timed-out and not be

qualified or executed.

If a transaction is paused/interrupted for any reason

(defined by a cessation of SCLK activity), and later

resumed under the same CSB low interval, the SPI

interface continue to accept input data through SDI and

relay the expected output data through SDO, as would

normally be expected for the remainder of the transaction.

However, even if all other qualification criteria are eventu-

Table 62. Alert-Interface Configuration in UART Mode

UARTCFG

UART CONFIGURATION

UART UP PATH

UART DOWN PATH

SINGLE ENDED ALERT

Single-UART interface with

External Loopback

Inactive (Buﬀered/Pass

Through)

0b00

Active

ALERTEN conﬁgured

Single-UART interface with

Internal Loopback

Inactive (Buﬀered/Pass

Through)

0b01

Active

ALERTEN conﬁgured

Disabled

(except in ALRTDCTSTEN

mode)

Single-UART interface with

Diﬀerential Alert Interface

0b10

0b11

Active

Diﬀerential Alert

Dual-UART interface

Active

ALERTEN conﬁgured

Maxim Integrated │ 144

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

By default, the alert interface is a single-ended, unidirec-

tional interface using the ALERTIN and ALERTOUT pins.

The ALERTIN pin is configured as a single-ended UART

receiver with RXP grounded (see the UART Receiver sec-

tion for details). The ALERTOUT pin uses a single-UART

transmitter as its output driver. If UARTSEL=0 (SPI inter-

face), ALERTOUT becomes a DC active-low output that

can be configured for open-drain (wired-OR) or CMOS

operation. For UARTSEL=1 (UART interface), ALERTOUT

is an AC CMOS output (see full details that follow).

of a fault, where the single-ended configuration allows for

full UART flexibility and the need for a different isolation

component (opto-isolators).

If the Hardware Alert interface is disabled, no alerts

can be communicated through the hardware-interface

options. The ALERTIN pin remain a high-impedance input

and will not respond to any input. Table 63 describes the

configuration of the alert output drivers for both single-

ended or differential alerts.

Note: Although the Hardware Alert interface can be dis-

abled, the user still has the option to validate alerts by

reading the STATUS registers, as well as the communica-

tion of the UART data-check byte or SPI Alert status bit.

Alternatively, a differential alert interface can be config-

ured using the UARTCFG bits, as discussed in the UART

Interface section and shown in Figure 53. The Differential

Alert interface allows for robust low-cost configurations

using capacitive isolation to communicate the presence

Table 63. Alert Output Driver Configuration

ALERTOUT

ACTIVE/ASSERTED

ALERTOUT INACTIVE/

DEASSERTED OR ALERTEN=0

UARTSEL

UARTCFG

SPIDRVINT

SPI (Pulldown)

Don't Care

0 (Open Drain)

1 (CMOS)

0

Hi-Z

1

GND (TXLIDLEHIZ=0)

Hi-Z (TXLIDLEHIZ=1)

UART (Pullup)

0b00, 0b01, 0b11

Don't Care

AC Active

0b10

(Diﬀerential)

GND (TXLIDLEHIZ=0)

Hi-Z (TXLIDLEHIZ=1)

GND (TXLIDLEHIZ=0)

Hi-Z (TXLIDLEHIZ=1)

UART (Pullup)

ALERTDCTSTEN=1

Don't Care

0

1

FAULT (OV/UV/OT/UT, etc.)

ALRTOUT

1µs

V

DDL

t

PDF

PDR

ALRTIN 0V

FAULT (OV/UV/OT/UT, etc.)

ALRTOUT

V

DDL

V

DDL

ALRTIN

1µs

t

PDR

t

DELAY

Figure 71. UART-Mode Alert-Detection Timing Diagram

Maxim Integrated │ 145

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(ALRTAUXOVST & AUXOVSTALRTEN) or

(ALRTAUXUVST & AUXUVSTALRTEN) or

UART-Mode Alert Detection (UARTSEL=1'b1)

This alert interface outputs a 2MHz continuous square

wave with 50% duty cycle in the presence of a fault

condition. The fault output persists for the duration of the

fault and is updated at the rate determined by the scan

mode. For a valid alert command to be recognized by the

ALERTIN pin, the signal must be valid for 25μs and at

the desired frequency. If the duration is shorter than the

allocated time, or at a different frequency, this will not be

recognized as a fault and the signal will not be propagated

to the host. See Figure 71 for a timing diagram.

(ALERTPEC & PECALRTEN) or (ALRTINTRFC &

INTRFCALRTEN) or

(ALRTCAL & CALALRTEN) or (ALRTCBAL &

CBALALRTEN) or

(ALRTFMEA1 & FMEA1ALRTEN) or (ALRTFMEA2 &

FMEA2ALRTEN)

Note: ALRTRST indicates a POR condition, and thus can-

not be masked.

In the absence of an alert, the output status depends on

TXLIDLEHIZ-TXLIDLEHIZ=1'b1, with ALERTOUT driven

Hi-Z, and TXLIDLEHIZ=1'b0, with ALERTOUT driven low.

Alert Packet Status Masking

The UART Alert packet content is based on the con-

tents of the STATUS1 register. Individual alert conditions

can be masked out of the Alert packet using settings in

ALRTIRQEN register; however, the underlying alert infor-

mation always be available for read back in the STATUS1

register. The masking operations for each STATUS1 bits

is detailed below:

SPI Mode Alert Operation (UARTSEL=1'b0)

When configured to communicate through the SPI inter-

face (UARTSE=0), the ALERTOUT driver is reconfigured

as an open-drain output or a CMOS output, depending

on the SPIDRVINT selection. If an alert is present, the

ALERTOUT output is driven active low. This is done to

minimize power consumption of the application when

configured as an open-drain output. If no ALERT condi-

tion is present, ALERTOUT is driven high (CMOS mode)

or pulled high through an external connection to a pulup

resistor for the open-drain configuration.

ALRT_PKT_STAT[15] = 0

ALRT_PKT_STAT[14] = ALRTRST

ALRT_PKT_STAT[13] = (ALRTMSMTCH &

MSMTCHALRTEN)

ALRT_PKT_STAT[12] = (ALRTCELLOVST &

CELLOVSTALRTEN)

The open-drain configuration allows for the ALERTOUT

signal to be logically OR'ed with any other signals at the

application level to drive a host-controller interrupt.

ALRT_PKT_STAT[11] = (ALRTCELLUVST &

CELLUVSTALRTEN)

ALRT_PKT_STAT[10] = (ALRTBLKOVST &

BLKOVALRTEN)

Note: If an open-drain configuration, the voltage should

not exceed V

.

DDL2

ALRT_PKT_STAT[9] = (ALRTBLKUVST &

BLKUVALRTEN)

In SPI mode, there are no daisy-chain devices, so any

signal on the ALERTIN input is ignored.

ALRT_PKT_STAT[8] = (ALRTAUXOVST &

AUXOVSTALRTEN)

Alert Interface Masking Operations

The Alert interface activity is based on the contents of

the STATUS1 register. Individual alert conditions can

be masked out of the Alert Interface using settings in

ALRTIRQEN; however, the underlying alert information

will always be available for readback in the STATUS1

register.

ALRT_PKT_STAT[7] = (ALRTAUXUVST &

AUXUVSTALRTEN)

ALRT_PKT_STAT[6] = 0

ALRT_PKT_STAT[5] = (ALRTPEC & PECALRTEN)

ALRT_PKT_STAT[4] = (ALRTINTRFC &

INTRFCALRTEN)

Active =

(ALRTSCAN & SCANALRTEN) or ALRTRST or

(ALRTMSMTCH & MSMTCHALRTEN) or

(ALRTCELLOVST & CELLOVSTALRTEN) or

(ALRTCELLUVST & CELLUVSTALRTEN) or

(ALRTBLKOVST & BLKOVALRTEN) or (ALRTBLKUVST

& BLKUVALRTEN) or

Maxim Integrated │ 146

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ALRT_PKT_STAT[3] = (ALRTCAL & CALALRTEN)

ALRT_PKT_STAT[2] = (ALRTCBAL & CBALALRTEN)

ALRT_PKT_STAT[1] = (ALRTFMEA1 & FMEA1ALRTEN)

ALRT_PKT_STAT[0] = (ALRTFMEA2 & FMEA2ALRTEN)

Alert-Masking TOPCELL1/2

If the battery stack contains less than 14 cells and the

Flexible Pack configuration is not enabled, the lowest

order inputs (e.g., C1 and C0) should be utilized first

and connected to the lowest common-mode signals. Any

unused cell inputs should be shorted together and unused

switch inputs should be shorted together. The TOPCELL1

and TOPCELL2 registers mask all ALRTBALSW diagnos-

tics from being reported.

Note: STATUS1[15]:ALRTSCAN is a procedural notifi-

cation bit and is intentionally not included in the UART

Alert packet; it is available for inclusion in the Alert

interface, to support interrupt-driven applications.

STATUS1[14]:ALRTRST indicates a POR condition, and

thus cannot be masked.

All selections are supported for this function; if TOPCELL2

is not equal to TOPCELL1, no alerts are masked.

Table 64. Low-Voltage Regulator Operating Characteristics

INPUT: DCIN

Input Voltage: 9V to 65V

Output:

Output Voltage: 3.3V

Disable:

V

AA

V

< 0.6V or T

> 145°C

SHNDL

DIE

Table 65. Low-Voltage Regulator Diagnostic

FAULT

CONDITION

ALERT

LOCATION

V

undervoltage

V

< 2.95V

ALRTRST

STATUS1

AA

R_DCIN

DCIN

LINEAR

REGULATOR

ENABLE

VAA

THERMAL

SHUTDOWN

TO SHDNL

CHARGE

PUMP

SHDNL/

+

-

INTERNAL

POR\

C_SHDNL

C_VAA

C_DIN

3.0V

AGND

Figure 72. Low-Voltage Regulator and Thermal-Shutdown Circuit

Maxim Integrated │ 147

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

replenished prior to the next measurement cycle. See

Figure 73 for an example of an HV charge pump.

Low-Voltage Regulator

An internal linear regulator supplies low-voltage power

(V ) for the ADC and digital logic. The regulator is

Note: The charge pump is operational during AUXTIME,

CELLDLY, and SWDLY settling periods greater than 30μs,

which is considered a worst-settling delay for the SWn

input.

AA

disabled when SHDNL is active-low or when the die tem-

perature (T ) exceeds 145°C. Once V decays below

DIE

AA

2.95V (typ), an internal power-on reset (POR) will be gen-

erated, as summarized in Table 64 and shown in Figure

72. This POR event can be detected with the ALRTRST

bit, as shown in Table 65. After a thermal shutdown, the

Outside of an acquisition, the charge pump is clocked at

32kHz.

An undervoltage comparator detects if V

drops

HV-DCIN

regulator will not be enabled until T

hysteresis.

< 130°C due to

DIE

below V

. If an undervoltage is detected, the

HVUV

ALRTHVUV bitfield is set. Assertion of the ALRTHVUV bit

is gated untilALRTRST is cleared for the first time following

power-up.

HV Charge Pump

The high-voltage multiplexers must be powered by a

supply higher than any monitored voltage. As such, an

internal charge pump draws power from the DCIN pin

An overvoltage comparator disables the charge pump

when V - V

exceeds V . This condition is indi-

HVOV

HV

DCIN

to provide a high-voltage supply (V ) that is regulated

HV

cated by the ALRTHVOV bit in the FMEA1 register; the

ALRTHVOV alert does not necessarily indicate a condi-

tion that affects measurement accuracy. HV charge-pump

diagnostics are summarized in Table 66.

to V

regulation (V

+ V

. When the charge pump achieves

), charge pumping stops until the

DCIN

HV-DCIN

voltage drops by 20mV. The charge pump is automatically

disabled during shutdown.

If V

drops too low relative to the top-cell inputs, there

HV

During the measurement cycle for ADC, comparator,

ADC+COMP, and calibration, the charge pumping is

paused to eliminate any potential impact of the charge-

pump noise within the measurements. The charge pump

then become active, operating on an 83kHz clock, during

an inter-charge time (defined as the time between con-

secutive scan sequences), which lasts for 57μs on the

ADC, comparator, and ADC+COMP. During calibration,

the inter-charge time is reduced to 21μs. The inter-charge

is insufficient headroom to guarantee that the HVMUX

switch resistance is sufficiently low, or enough head-

room exists for the LSAMP1 and LSAMP2 inputs for an

accurate acquisition of the channel. Headroom alerts are

indicated with the ALRTHVDRM bit in the FMEA1 register.

The HV undervoltage and HV headroom-alert functions can

be verified by disabling the HV charge pump (HVCPDIS=1)

and allowing V

to decay while in acquisition mode.

HV

time ensures that the charge on the C

capacitor is

HV

Table 66. HV Charge-Pump Diagnostics

FAULT

CONDITION

ALERT BIT

ALRTHVUV

LOCATION

FMEA1:ALRTHVUV

FMEA1:ALRTHVOV

FMEA1:ALRTHVHDRM

V

undervoltage

overvoltage

low headroom

V

- V

< V

HV

DCIN

HVUV

> V

ALRTHVOV

DCIN

HVOV

< V

(min)

ALRTHVHDRM

TOPCELL1/2

HVHDRM

Table 67ꢀ Oscillator Diagnostics

FAULT

CONDITION

ALERT BIT

LOCATION

31.129kHz > f

34.406kHz

>

osc_32k

32.768kHz oscillator

ALRTOSC1

FMEA1[15]

31.129kHz > f

34.406kHz

>

osc_32k

32.768kHz oscillator

16MHz oscillator

ALRTOSC2

ALRTOSC3

FMEA1[14]

STATUS2[5]

15MHz > f

> 17MHz

osc_16M

Maxim Integrated │ 148

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

+

-

HVOV

To ALRTHVOV

To ALRTHVUV

-

+

V

HVUV

HVOV

+

-

+

-

20mV

Hyst.

HV

R

HV

C

HV

CPP

INTERNAL POR/

CP_CLK

V

HV-DCIN

SWITCH

LOGIC

+

-

R

DCIN

DISABLE

DCIN

CPN

HVOV

C

CP

DEVCFG2:HVCPDIS

+

C

DCIN

I

SINK

AGND

Figure 73. HV Charge Pump

Maxim Integrated │ 149

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

response such as a communication error, or are detect-

able through a built-in diagnostic. Analyzing the effect of

pin faults is referred to as a pin FMEA. Contact Maxim

Applications to obtain pin FMEA results.

Oscillators

Two factory-trimmed oscillators provide all timing require-

ments: a 16MHz oscillator for the UART and control logic, a

32.768kHz oscillator for the HV charge pump and timers. A

special diagnostic counter, clocked by the 16MHz signal, is

employed to check the 32kHz oscillator. Every two periods

of the 32kHz clock, the counter is sampled. If the count

varies more than 5% from the expected value, the

ALRTOSC1 bit is set (see Table 67). A redundant alert bit,

ALRTOSC2 bit, increases the integrity level. If the 16MHz

oscillator varies by more than 5%, for UART part, commu-

nication errors may be indicated. For SPI configuration, the

ALRTOSC3 bit is set as shown in Table 67.

ALERTOUT Pin-to-Pin Short Diagnostic

The UART Alert DC Diagnostic test is used to test the

ALERTOUT pin for shorts to AUXIN0/GPIO0 pins. When

UARTSEL=0b1 (UART mode), this test is enabled by set-

ting the ALERTDCTSTEN bit to 0b1.

When the DC Diagnostic test is enabled, the ALERTOUT

pin is driven low if an Alert condition is present, and driven

high otherwise. The ALRTUSER bitfield can be written to

exercise ALRTOUT in either direction. Neighboring pins

such as AUXIN0/GPIO0 can be monitored directly or in

diagnostic modes to detect a fault.

Diagnostics

Built-in diagnostics support ISO 26262 (ASIL) require-

ments by detecting specific fault conditions (see Table 68).

The device automatically performs some of the diagnostics

while the host performs others during initialization (e.g., at

key-on) or periodically during operation, as required by the

application. Diagnostics performed automatically by the

device are previously described in the relevant functional

sections. A description of the diagnostics requiring specific

configurations is provided in this section.

This function works in all UARTCFG modes, including

the differential alert, which does not normally use the

ALERTOUT pin. This setting has no impact in SPI mode

(UARTSEL=0), the same functionality can be realized

using SPIDRVINIT and ALRTUSER.

CELL Pin Open Diagnositics

If an input of the MAX17853 is disconnected from the cell

input through any combination of mechanical failures, the

position of the failure can be detected by performing cell

open diagnostics. It is recommended that comparator

Note: Pin faults such as an open pin or adjacent pins

shorted to each other must be detectable. Pin faults do

not result in device damage but have a specific device

Table 68. Summary of Built-In Diagnostics

DIAGNOSTICS PERFORMED AUTOMATICALLY BY DEVICE WITH NO HOST INTERVENTION

Fault

undervoltage

Diagnostic Procedure

Output

V

Continuous voltage comparison

Voltage comparison (updated during measurement)

Continuous frequency comparison

Communication error checking

Verify RX mode after POR

ALRTRST

AA

VHV undervoltage

VHV overvoltage

ALRTHVUV

ALRTHVOV

VHV low headroom

32kHz oscillator fault

16MHz oscillator fault

Communication fault

RX pin open/short

ALRTHVHDRM

ALRTOSC1, ALRTOSC2

ALRTMAN, ALRTPAR, ALRTOSC3

ALRTPEC, ALRTMAN, ALRTPAR

ALRTCOMMSEUn/ALRTCOMMSELn

ALRTVDDLx

VDDLx pin open/short

GNDLx pin open/short

Die overtemperature

Continuous voltage comparison

Temperature comparison

ALRTGNDLx

ALRTTEMP

Accuracy comparison -updated after oversampled

acquisition

Measurement accuracy

Flex Pack fault

ALRTCOMPACCOV/ALRTCOMPACCUV

ALRTDCINMUX

Continuous fault checking of Flexible Pack operation

Maxim Integrated │ 150

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 68. Summary of Built-In Diagnostics (continued)

DIAGNOSTICS PERFORMED DURING ACQUISITION MODE AS SELECTED BY DIAGSEL OR

SCACFG (BALSW DIAGNOSTICS)

DIAGSEL[3:0] or

FAULT

DIAGNOSTIC PROCEDURE

OUTPUT

SCANCFG

Die Temperature (PTAT)

Diagnostic

Die Temp (PTAT) fault

DIAGSEL1/2 = 1h

DIAGSEL1/2[15:0] = PTAT voltage

V

Voltage fault

V

Veriﬁcation

DIAGSEL1/2 = 2h

DIAGSEL1/2 = 3h

DIAGSEL1/2 = 4h

DIAGSEL1/2[15:0] = V voltage

AA

Reference Voltage fault

ALTREF Veriﬁcation

DIAGSEL1/2[15:0] = ALTREF voltage

Comp Cell Signal Path fault Comp Signal Path Veriﬁcation

DIAGSEL1/2[15:0] = COMP error voltage

DIAGSEL1/2[15:0] = Calibration voltage

(6/13)

Cell Gain Calibration fault

Cell Gain Calibration Veriﬁcation

Oﬀset Calibration Veriﬁcation

DIAGSEL1/2 = 5h

DIAGSEL1/2 = 6h

DIAGSEL1/2[15:0] = Calibration Oﬀset

Voltage (0V)

Oﬀset Calibration fault

DAC bit stuck high

DAC bit stuck low

DAC 3/4 Scale

DAC 1/4 Scale

DIAGSEL1/2 = 7h

DIAGSEL1/2 = 8h

DIAGSEL1/2[15:0] = DAC Code 1772d

DIAGSEL1/2[15:0] = DAC Code 591d

NTC(THRM) Oﬀset

Calibration Fault

NTC(THRM) Oﬀset Calibration

Veriﬁcation

DIAGSEL1/2[15:0] = Calibration oﬀset

error with THRM

DIAGSEL1/2 = 9h

DIAGSEL1/2= Ah

ADC bit stuck high

Zero-Scale ADC diagnostic

Full-Scale ADC diagnostic

LSAMP oﬀset diagnostic

BALSW diagnostic mode

DIAGSEL1/2[15:0] = ADC zero scale

ADC bit stuck low

DIAGSEL1/2 = Bh DIAGSEL1/2[15:0] = ADC full scale

LSAMP Oﬀset too high

Balancing switch short

Balancing switch open

Odd Cell sense-wire open

Even Cell sense-wire open

DIAGSEL1/2 = Ch DIAGSEL1/2[15:0] (LSAMP oﬀset voltage)

SCANCFG = 4h

SCANCFG = 5h

SCANCFG = 6h

SCANCFG = 7h

ALRTBALSW, FMEA1:ALRTBALSWSUM

Procedural Diagnostics: Contact Maxim Applications for the complete listing of procedural diagnostics found in the safety manual.

measurements be used for quick identification against the

default threshold setting, COMPOPNTH. If measurement

is below the set threshold, the corresponding CELL alerts

are flagged in ALRTCOMPOV.

The die-temperature measurement allows the host to

compute the device temperature (T ) as it relates to

DIE

the acquisition accuracy, and allows the device to auto-

matically shut itself down when T

> 145°C. The mea-

DIE

surement employs a source where voltage (V

), is

PTAT

Enable this diagnostic by setting CELLOPNDIAGSEL=1

and performing a comparator scan (SCANCFG=0b010).

Only unipolar measurements are allowed for this diagnos-

tic; if a cell position is set as bipolar, the corresponding

cell is skipped and an alert flag is not set for that bipolar

cell. Normally in open-diagnostic modes, pulldown cur-

rent sources are enabled on all measured channels using

CTSTEN for required cells. Various current configuration

settings are available for the user and can be configured

using the DIAGCFG:CTSTDAC bit field.

proportional to absolute temperature (PTAT), as shown in

Figure 74. The V measurement is enabled by setting

PTAT

DIAGSEL1[3:0] or DIAGSEL2[3:0] to 0b0001, with the

14-bit measurement stored in DIAG1=DIAG1REG[15:2]

or DIAG2=DIAG2REG[15:2], respectively. The die-tem-

perature measurement requires a settling time of 39μs

from the start of the measurement cycle until the diagnos-

tic conversion. As long as two or more cell measurements

are enabled, there will be sufficient settling time for this

Die-Temperature Measurement

Maxim Integrated │ 151

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

measurement. See the various acquisition timing sections

for more details.

V

= (DIAG2/16384d) x V

PTAT REF

Where V

= 2.3077V. The measured voltage can be

REF

The PTAT voltage is computed as follows:

converted into °C as follows:

Equations 2:

Equation 3:

V

PTAT

= (DIAG1/16384d) x V

or

T

(in °C) = (V

/A

) + T

- 273°C

OS_PTAT

REF

DIE

PTAT V_PTAT

ALRTTEMP

REF

1.230V

+

-

ADC IN +

ADC IN -

LV

MUX

ADC

V

PTAT

AGND

Figure 74. Die-Temperature Measurement

Maxim Integrated │ 152

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

See the Electrical Characteristics table for A

and

V

Diagnostic Measurement

V_PTAT

AA

The V

T

values.

OS_PTAT

diagnostic measurement (DIAGSEL1 or

AA

DIAGSEL2=0b0010) verifies that V

is within specifica-

AA

Die-Temperature Alert

The die temperature is continuously monitored in 1ms

intervals to detect if T > T . When die temper-

ature is greater, the ALRTTEMP bit in the FMEA2 register

is asserted. The only exception is ALRTTEMP monitoring

is temporarily disabled when the die-temperature mea-

surement is requested by configuring DIAGSEL1[3:0] or

DIAGSEL2[3:0]=1h. The signal path for die-temperature

alert and measurement is shown in Figure 74.

tion. This diagnostic measures V

while using V

as

REF

AA

the ADC reference. Signal path for the V diagnostics is

shown in Figure 75

AA

DIE

ALRTTEMP

The voltage into the ADC is computed from the result in

the DIAG1REG (or DIAG2REG) register, as follows.

Equation 4:

(6/13) x V

= (DIAG1REG[15:2]/16384) x V

AA

REF

V

can be calculated as follows.

AA

If ALRTTEMP is set, the host should consider the possibil-

ity that the acquisition does not meet the expected accu-

racy specification, or the die-temperature measurement

itself may be inaccurate due to insufficient settling time

(< two cell measurements enabled).

Equation 5:

V

= (6/13) x V

x 16384/DIAG[15:2]

AA

REF

V

AA

THRM

G = 6/13

+

LSAMP

-

ADC IN +

ADC IN -

LVMUX

ADC

DIGITAL

CONTROL

V

DIAGNOSTIC

REF

AA

AGND

Figure 75. V

Diagnostic

AA

Maxim Integrated │ 153

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

where V

= 2.3077V

ALTREF Diagnostic Measurement

REF

The ALTREF diagnostic measurement (DIAGSEL1 or

DIAGSEL2=0b0011) checks the primary voltage reference

of the ADC by measuring the alternate reference voltage

The result for V should fall within the range provided in

AA

the Electrical Characteristics table for V

.

AA

For ADCCALEN=1, the 14-bit ADC measurement that

passes the diagnostic ranges from 0x1576 to 0x13E4,

based on the Electrical Characteristics specs.

(V

ALTREF

) while using V

as the ADC reference. The

REF

result is available in the DIAG1REG (or DIAG2REG) reg-

ister. The ALTREF voltage is computed from the result in

the DIAG register as follows.

For ADCCALEN=0, the 14-bit ADC measurement that

passes the diagnostic ranges from 0x1592 to 0x13CA

based on the Electrical Characteristics specs.

Equation 6:

V

x (6/13) = (DIAG[15:2]/16384) x V

REF

ALTREF

Note: With any sampled measurement, the signal-chain

noise performance must be considered within the mea-

surement result. For consistent measurement perfor-

Because V

/(6/13) should nominally equal 5V,

REF

V

can be determined as follows.

ALTREF

mance, is recommended to average V within multiple

system-measurement cycles to mitigate the variation

seen by noise.

AA

Equation 7:

V

= (DIAG[15:2]/16384) x 5V

ALTREF

REF

THRM

G=6/13

+

LSAMP

ADC IN +

-

LV

MUX

ADC

ADC IN -

REFDIAG

ALTREF

UNIPOLAR MODE SET FOR

REFDIAG MEASUREMENT

AGND

Figure 76. ALTREF Diagnostic

Maxim Integrated │ 154

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

During ALTREF diagnostic measurements, the ADC is

automatically set to unipolar mode. The signal path for

ALTREF diagnostic is shown in Figure 76.

● Comparator-thresholds calibration

● Increased comparator performance for improved

specification beyond that described in the Electrical

Characteristics specs

Since 1.23V < V

< 1.254V and V

= 1.242V

ALTREF

(nom), the expected range for DIAG[15:2] is shown below.

The functionality of the comparator signal-conditioning

path (shown in Figure 77) can be measured using

DIAGSEL1=0b0100 or DIAGSEL2=0b0100 in the

DIAGCFG register. This configuration applies an input

For ADCCALEN=1, the 14-bit ADC measurement that

passes the diagnostic ranges from 0x0FFA to 0xFD5.

For ADCCALEN=0, the 14-bit ADC measurement that

passes the diagnostic ranges from 0x1024 to 0xFAE.

of V

= 2.3077V to LSAMP2, while the DAC is pro-

REF

grammed to 0x1D8 (DAC reference of 2.3077V). The

LSAMP2 path is gained up by 6 and compared against

the DAC output gained by a factor of 13. The output of the

comparator preamp is routed to the ADC input where it is

effectively measured. The result of the ADC measurement

will be presented in corresponding DIAG1REG[15:2] or

DIAG2REG[15:2] registers.

Note: With any sampled measurement, the signal-chain

noise performance must be considered within the mea-

surement result. For consistent measurement perfor-

mance, it is recommended to average V

within

ALTREF

multiple system-measurement cycles to mitigate the

variation seen by noise.

Comparator Signal-Path Diagnostic Measurement

Note: It is recommended to run the comparator signal-

path diagnostic with an OVSAMPL=16.

The comparator signal conditioning path can be measured

by the ADC, which allows for the following capabilities:

●

Comparator-functionality verification against specification

REFBUF

2.3077

REFBUF

2.3077V

ADC

COMPARATOR SIGNAL

PATH DIAGNOSTIC

DIGITAL

CONTROL

+

LSAMP2

-

PREAMP

A=6

+

-

COMP

A=13

10-BIT DAC

0x1D8

Figure 77. Comparator Signal Path to ADC

Maxim Integrated │ 155

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Comparator functionality is verified by comparing the

DIAG register outputs against the ranges shown in table

shown below:

Equation 10:

2

V

= ε

+ 0.004

COMP_CELLPATH

OS_COMP_EFFECTIVE

In addition to verifying functionality against the specifica-

tion, the DIAGn register output can be used to calculate

the error of the comparator-cell signal path, as shown in

the following equation.

For example, if the DIAG1 register output reads 0x1FEC

(0d7996) then the following adjustments can be applied.

Equations 11:

Equation 8:

1

0d7996 − 0d8224





ε

=

×

COMP_CELLPATH







13

0d16384







DIAG1REG15 : 2 − 0d8224

1

[

]

ε

=

×

× 5V





COMP_CELLPATH

×5V = −5.35mV

13

0d16384





The error can then be used by the user to man-

ually adjust the comparator OV and UV thresholds

(COMPOVTH, COMPUVTH, COMPACCOVTHREG,

COMPACCUVTHREG) to ensure that the thresholds are

applied to the true comparator performance.

COMPOVTH

= COMPOVTH

+

Adjusted

Desired

Round( − 5.35mV ×1023 / 5)

COMPOVTH

= COMPOVTH

−1

Adjusted

Desired

Equations 9:

COMPOVTH

= COMPOVTH

+

Adjusted

Desired

COMPOVTH

= COMPOVTH

+

Adjusted

Desired

Round( − 5.35mV ×1023/5)

Round (ε

×1023/5)

COMP_CELLPATH

COMPOVTH = COMPOVTH

−1

COMPUVTH

= COMPUVTH

Desired

Adjusted

Desired

Adjusted

Comparator-Accuracy Diagnostic

Round(ε

×1023/5)

COMP_CELLPATH

The COMPACCEN bit in the ACQCFG register is used

to test the accuracy of the comparator and is evalu-

ated at the end of a measurement sequence for con-

figurations that use the comparator (SCANCFG=001b

or 010b in the SCANCTRL register) during scans. When

Note: the above threshold corrections cannot be applied

to the AUX measurements since the correction includes

LSAMP2 errors.

The computed error value also allows the user to specify

improvement in the comparator accuracy beyond what

that described in the Electrical Characteristics specs.

COMPACCEN=1, V

= 2.3077V is configured as the

REF

Table 69. Comparator Signal-Path Diagnostic Verification Ranges

UPPER DIAGNOSTIC RANGE

LOWER DIAGNOSTIC RANGE

ADCALEN=1

ADCALEN=0

0x2480

0x24A0

0x1BC0

0x1BA0

Maxim Integrated │ 156

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

REFBUF

2.3077V

REFBUF

2.3077V

ADC

DIGITAL

CONTROL

+

LSAMP2

-

PREAMP

A=6

+

-

COMP

A=13

COMPACCOVTH

COMPACCUVTH

10-BIT DAC

COMPARATOR ACCURACY

PATH

Figure 78. Comparator Accuracy Diagnostic Path

Maxim Integrated │ 157

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

input to the LSAMP2; the 10-bit DAC uses values from the

COMPACCOVTH and COMPACCUVTH registers.

If COMPACCUVTH=D8h, the comparator may not set the

ALRTCOMPACCUV bit (not expected to be set for the

ideal case).

An overvoltage alert is issued by setting the

ALRTCOMPACCOV bit in the FMEA2 register if the

threshold value in COMPACCOVTH is violated.

Comparator Accuracy diagnostic-signal path is shown in

Figure 78.

If COMPACCOVTH=1D8h, the comparator may set the

ALRTCOMPACCOV bit (expected to be set for the ideal

case).

To eliminate a false alert, the user should adjust

COMPACCOVTH and COMPACCUVTH by ±5 DAC

codes.

An undervoltage alert is issued by setting the

ALRTCOMPACCUV bit in the FMEA2 register if the

threshold value in COMPACCUVTH is violated.

See the Comparator Signal Path Diagnostic Measurement

section for details on setting these thresholds.

Comparator Accuracy diagnostics procedure, requested

by setting COMPACCEN=1, is run only once at the end of

INPUT

CHANNEL

CELL OV QUALIFICATION

CELL UV QUALIFICATION

AUX OV/UV QUAL

TIME

T₀

Figure 79. Comparator Accuracy End of Scan Measurement

Maxim Integrated │ 158

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the last oversample of the SCAN measurement request,

as shown in Figure 79.

each of the SCANMODE configurations utilized by the

application to validate calibration.

The diagnostic is performed by multiplexing V

into the

REF

Cell Gain-Calibration-Diagnostic Measurement

LSAMP1 inputs, as shown in Figure 80. The OVSAMPL

bitfield used during this diagnostic acquisition must be

minimally configured to an oversample of 16, which

ensures proper accuracy performance.

The cell gain-calibration diagnostic verifies that on-

demand calibration is functioning correctly and the ADC

and LSAMP1 are operating within the specification

described by the Electrical Characteristics table. This

diagnostic is run by setting the DIAGSEL1=0b0101 or

DIAGSEL2=0b0101 in the DIAGCFG register in accor-

dance with the SCANMODE setting. Thus, if SCANMODE

is configured for Pyramid mode operation when this

diagnostic is run, the sampling will occur as two conver-

sion phases and effectively chop the offset. Similarly,

if SCANMODE is configured for Ramp mode operation

when this diagnostic is run, only a single conversion

phase is implemented. This diagnostic must be run for

The expected result is 6/13 of full-scale (0x1D8A) volt-

age and can be read from the DIAG1REG[15:2] or

DIAG2REG[15:2] registers. To allow 14-bit ADC measure-

ments should extend from 0x1D7D to 0x1D97.

Note: This diagnostic should not be run without enabling

calibration.

Oﬀset-Calibration Diagnostic

The offset-calibration diagnostic is run by setting

DIAGSEL1=0b0110 or DIAGSEL2=0b0110 in the

REF

HVMUX BUS

THRM

G = 6/13

+

LSAMP

-

ADC IN +

LVMUX

ADC

DIGITAL

CONTROL

ADC IN -

CELL CAL DIAGNOSTIC

REF

UNIPOLAR MODE SELECTED

AGND

Figure 80. Cell Gain Calibration-Diagnostic Measurement

Maxim Integrated │ 159

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

DIAGCFG register. This diagnostic verifies that on-

demand calibration is functioning correctly and operating

within the Electrical Characteristics table specs.

during this diagnostic acquisition must be minimally con-

figured to an oversample of 16 to ensure proper accuracy

performance.The expected result is 0V (0x2000) and can

be read from the DIAG1REG[15:2] or DIAG2REG[15:2]

registers.

This diagnostic is configured differently depending on the

SCANMODE setting in the SCANCTRL register. When con-

figured in Pyramid mode (SCANMODE=0), the diagnostic

is performed by shorting the ADC inputs and performing

an acquisition with the ADC polarity overridden in bipolar

mode. When configured in Ramp mode (SCANMODE=1),

the diagnostic is performed by shorting the LSAMP1 inputs

to ground and performing an unchopped acquisition with

the ADC polarity overridden in bipolar mode. For both

SCANMODE configurations, the OVSAMPL bitfield used

For Pyramid mode, the 14-bit ADC measurement bound

that passes this diagnostic ranges from 1FF3h to 200dh.

For Ramp mode, the 14-bit ADC measurement bound that

passes this diagnostic ranges from 1FEAh to 2011h.

The signal path is shown in Figure 81.

Note: This diagnostic should not be run without enabling

calibration.

REF

THRM

ADC IN +

ADC

DIGITAL

CONTROL

ADC IN -

BIPOLAR MODE SELECTED

OFFSET CAL DIAGNOSTIC

AGND

Figure 81. Offset-Calibration Diagnostic

Figure 82. THRM Offset-Calibration Diagnostic

Maxim Integrated │ 160

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

measurement exceeds the valid range for V , as

OS_LSAMP

THRM Oﬀset-Calibration Diagnostic

specified in the Electrical Characteristics table, the chop-

ping function may not be able to cancel out all the offset

error, and acquisition accuracy could be degraded accord-

ingly. Signal path for this diagnostic is shown in Figure 83.

The THRM offset-calibration diagnostic is run by set-

ting the DIAGSEL1=0b1001 or DIAGSEL2=0b1001 in

the DIAGCFG register. The diagnostic verifies that on-

demand calibration for the THRM case is functioning

correctly and the ADC is operating within the specifica-

tion described in the Electrical Characteristics table.

This is performed by shorting the ADC inputs to ground

with ADC reference connected to THRM, and perform-

ing an acquisition with a recommendation of minimum

16x oversample (OVSAMPL=0b011) in bipolar mode. If

ADCCALEN=1, appropriate calibration coefficients are

applied to the diagnostic result. The signal path can be

seen in Figure 82.

The LSAMPoffset is computed from the result in the DIAG1

or DIAG2 as follows: LSAMP Offset = (|DIAGn[15:2] -

2000h|/16384d) x 5V.

For ADCCALEN=0, the 14-bit ADC measurement bound

that passes this diagnostic ranges from 1D59 to 22A9h.

For ADCCALEN=1, the 14-bit ADC measurement bound

that passes this diagnostic ranges from 1D70h to 228Fh.

The validity of measurements through LSAMP is further

confirmed by the ALTREF and V diagnostics, and com-

AA

The expected result is 0V or DIAG1/2[15:2]=2000h (nom).

For ADCCALEN=1, the 14-bit ADC measurement bound

that passes this diagnostic ranges from 1FF8h to 2003h.

parison of the VBLK measurement to the sum of the cell

measurements.

Zero-Scale ADC Diagnostic Measurement

For ADCCALEN=0, the 14-bit ADC measurement bound

that passes this diagnostic ranges from 1FB0h to 204Fh.

Stuck ADC output bits can be verified with a combina-

tion of the zero-scale and full-scale diagnostics. The

zero-scale ADC diagnostic measurement (DIAGSEL1 or

DIAGSEL2=0b1010) verifies that the ADC conversion

LSAMP Oﬀset-Diagnostic Measurement

The LSAMP diagnostic measurement (DIAGSEL1 or

DIAGSEL2=0b1100) measures the level-shift amplifier

offset by shorting the LSAMP inputs during the diagnostic

portion of the acquisition. The result is available in the

DIAG1REG or DIAG2REG registers after an acquisition.

For this measurement, the ADC polarity is automatically

set to bipolar mode to allow accurate measurement of volt-

ages near zero. This measurement eliminates the chop-

ping phase to preserve the offset error. If the diagnostic

results in 000h (12-bit) when its input is at -V in bipolar

AA

mode (for an input ≤ -2.5V, DIAG1/2[13:0]=0000h). For

this measurement, the ADC is automatically set to bipolar

mode. Signal path for this diagnostic is shown in Figure 84

If the user is looking for a quick combination of ADC zero

scale and full scale to detect if the ADC is stuck at some

value, this can be performed as part of end of scan by

G = 6/13

+

ADC IN +

LVMUX

FROM HVMux

LSAMP

ADC

ADC IN -

-

BIPOLAR ADC MODE

SET FOR AMPDIAG MEASUREMENT

Figure 83. LSAMP Offset Diagnostic

Maxim Integrated │ 161

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

REF

THRM

V

AA

ADC IN +

LV

MUX

ADC

ADC IN -

AGND

ADC AUTOMATICALLY

IN BIPOLAR MODE

AGND

Figure 84. ADC Zero-Scale Diagnostic

REF

THRM

V

AA

ADC IN +

LV

MUX

ADC

ADC IN -

AGND

ADC AUTOMATICALLY IN

BIPOLAR MODE

AGND

Figure 85. Full-Scale ADC Diagnostic Measurement

Maxim Integrated │ 162

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

configuring ADCZSFZEN=1 and then requesting a SCAN.

See the the various acquisition timing sections for details

on insertion into the scan and timing.

DAC 1/4 Scale Diagnostic

The DAC 1/4 scale diagnostic can be requested by setting

DIAGSEL1 or DIAGSEL2=0x1000. This configures the

internal DAC used to set the comparator thresholds to 1/4

Full-Scale ADC Diagnostic Measurement

of full scale (V ) or 0x100. The DAC voltage is muxlti-

REF

Stuck ADC output bits can be verified with a combina-

tion of the zero-scale and full-scale diagnostics. The

full- scale ADC diagnostic measurement (DIAGSEL1 or

DIAGSEL2=0b1011) verifies that the ADC conversion

plexed to the ADC and then compared against the bounds

shown in Figure 86.

The nominal DAC and ADC voltages are:

results in FFFh (12-bit) when its input is at V in bipolar

V

= 256/1023 x 2.3077 = 0.5775V

AA

DAC

ADC

mode (since for an input ≥ 2.5V, DIAG1/2[13:0]=3FFCh).

For this measurement, the ADC is automatically set to

bipolar mode. Signal path for this diagnostic is shown in

Figure 85.

= 0.5775/2.3077 x 16384 = 4100 = 0x1004

For ADCCALEN=1, the 14-bit ADC measurement bounds

for passing this diagnostic range from 0x0FD0 to 0x1040.

For ADCCALEN=0, the 14-bit ADC measurement bounds

for passing this diagnostic range from 0x0FA0 to 0x1060.

If the user is looking for a quick combination of ADC zero

scale and full scale to detect if the ADC is stuck at some

value, this can be performed as part of end of scan by

configuring ADCZSFZEN=1 and requesting a SCAN. See

the the various acquisition timing sections for details on

insertion into the scan and timing.

This can be used in conjunction with the DAC 3/4 scale

diagnostic to ensure there are no stuck bits that may

cause errors with the comparator threshold settings.

REFBUF

2.3077V

REFBUF

2.3077V

DIGITAL

0x100

CONTROL

ADC

10-BIT DAC

0x2FF

Figure 86. DAC 1/4 and 3/4 Diagnostic

Maxim Integrated │ 163

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

● Even sense wire open (SCANCFG[2:0]=0b111)

DAC 3/4 Scale Diagnostic

The DAC 3/4 scale diagnostic can be requested by set-

ting DIAGSEL1 or DIAGSEL2=0x0111. This configures

the internal DAC used to set the comparator thresholds to

Enabling any of these modes automatically configures

several acquisition settings (e.g., enables the ALTMUX

measurement path). The host must initiate the acquisi-

tion but the diagnostic mode automatically compares the

measurements to the specific thresholds, as configured

through BALSHRTTHR, BALLOWTHR, or BALHIGHTHR

threshold registers and sets any corresponding alerts

in the ALRTBALSW register field. The host presets the

thresholds, as determined by the minimum and maximum

3/4 of full scale (V ) or 2FFh. The DAC voltage is multi-

REF

plexed to the ADC and then compared against the bounds

shown below.

The nominal DAC and ADC voltages are:

V

= 767/1023*2.3077 = 1.73V

DAC

= 1.73/2.3077 x 16384 = = 2FFAh

resistance of the switch (R ) specified in the Electrical

ADC

SW

Characteristics table and the intended cell-balancing

current.

For ADCCALEN=1, the 14-bit ADC measurement bounds

for passing this diagnostic range from 2F80h to 3070h.

At the start of a new scan request, the Balance-Switch

Fault-Alert Register (ALRTBALSW[13:0]) is cleared

if balancing-switch diagnostic mode is requested

(SCANCFG=0b100, 0b101, 0b110, or 0b111). The result

from the current balancing-switch diagnostic is written to

ALRTBALSW[13:0] at the end of scan (SCANDONE=1).

The previous result persists in ALRTBALSW until a new

scan is requested, with balancing-switch diagnostic mode

enabled.

For ADCCALEN=0, the 14-bit ADC measurement bounds

for passing this diagnostic range from 2F70h to 3080h.

This be used in conjunction with the DAC 1/4 scale diag-

nostic to ensure there are no stuck bits that may cause

errors with the comparator-threshold settings.

BALSW Diagnostics

Four balancing switch diagnostic modes are available to

facilitate the following diagnostics:

Table 70 describes which Balance Switch Diagnostic Alert

Thresholds contribute to ALRTBALSW in each of the four

modes.

● Balancing switch shorted (SCANCFG[2:0]=0b100)

● Balancing switch open (SCANCFG[2:0]=0b101)

● Odd sense wire open (SCANCFG[2:0]=0b110)

Table 70. BALSW Diagnostic

MODE

SCANCFG[2:0]

THRESHOLD

BALSHRTTHR

FAULT CONDITION

Data < BALSHRTTHR

Balancing Switch Short

0b100

Data < BALLOWTHR, or

Data > BALHIGHTHR

Balancing Switch Open

Cell Sense Open Odds

Cell Sense Open Evens

0b101

0b110

0b111

BALLOWTHR, BALHIGHTHR

Data < BALLOWTHR, or

Data > BALHIGHTHR

Data < BALLOWTHR, or

Data > BALHIGHTHR

Maxim Integrated │ 164

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The summary status bitfield ALRTBALSWSUM is updated

at the end of scan when a balancing switch diagnostic

mode is enabled. ALRTBALSWSUM is a bit-wise logical

OR of ALRTBALSW[13:0].

ALRTBALSW[13:0] alerts are resolved (by subsequent

scan) or by writing to logic zero.

Note: In balancing switch diagnostic mode, the ALRTOV,

ALRTUV, and ALRTMSMTCH alerts are not updated

because these are only applicable during normal cell

measurements.

ALRTBALSW is a bitwise alert status for all the 14

channels/switches, the alert masking depend on the

TOPCELL1 and TOPCELL2 settings. The user should

pay attention that if TOPCELL1 != TOPCELL2 then none

of the alerts are masked. If TOPCELL1 = TOPCELL2

all the alerts above TOPCELL1/2 positions are masked.

These conditions apply for all the four BALSW diagnostic

SCAN requests.

BALSW Short Diagnostic

A short-circuit fault in the balancing path could be a short

between SWn and SWn-1 as shown in Figure 87 or that

a balancing FET is stuck in the conducting state. In the

short circuit state, the voltage between SWn and SWn-1

(switch voltage) is less than the voltage between Cn and

Cn-1 (cell voltage).

The balancing switch diagnostic summary sta-

tus ALRTBALSWSUM can be cleared if all enabled

Table 71. BALSW-Short Diagnostics Operation

BALSW

V

FAULT INDICATED?

POSSIBLE FAULT CONDITION

SWn

> V

< V

No

None

BALSHRTTHR

Oﬀ

Yes

Short circuit or leakage current

C(n)

To HVMux

To ALTMux

BALSWn

HV

SW(n)

BALANCIN

G SWITCH

(n)

SHORT

CIRCUIT

SW(n-1)

To ALTMux

To HVMux

C(n-1)

AGND

Figure 87. Balancing Switch Short

Maxim Integrated │ 165

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

When enabled, the balancing switch short diagnostic mode (SCANCFG[2:0] = 0b100) functions as follows:

MAX1785X FULLY

FUNCTIONAL AND

INITIALIZED

ENSURE BALSHRTTHR

SET TO DESIRED

VALUE

SET SCANCFG TO

0B100

WAIT 100μs

START ADC

MEASUREMENT

ALRTFMEA1

YES

SCANDONE = 1

DATACHECK BIT

SHOWS RESULT

NO

CLEAR SACNCFG AND

SCANDONE

BALSW SHORT-CIRCUIT

CHECK INVALID

CHECK ALRTBALSW OR

CELLN REGISTERS FOR

DETAILED RESULT

BALSW SHORT-CIRCUIT

CHECK DONE

Figure 88. BALSW Short-Diagnostic Chart

Maxim Integrated │ 166

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

● Disables the balancing switches automatically

See Figure 87 for an example of a BALSW short.

● Configures the acquisition using ALTMUX path auto-

The BALSW Short diagnostic procedural flow chart is

shown in Figure 88.

matically

● Host initiates the acquisition on selected Unipolar

The BALSW Short diagnostic automatically overrides the

configuration settings during the measurements scan

(see Table 72).

Cells only (~POLARITYn & CELLENn)

● Compares the measurement to the threshold value

BALSHRTTHR automatically (for Unipolar Cells only,

i.e. POLARITYn=0, see Table 71)

BALSW Open Diagnostic

The BALSW open diagnostic (SCANCFG[2:0]=0b101)

verifies that each enabled balancing switch is conducting

(not open) as follows:

● If outside the threshold, sets the corresponding flag

in ALRTBALSW automatically

For the best sensitivity to leakage current, set the thresh-

old value based on the minimum cell voltage minus a

small noise margin (100mV) then update the threshold

value periodically or every time a measurement is taken

depending on how fast the cell voltages are expected to

change.

● Configures acquisition for bipolar mode (for measuring

voltages near zero) automatically

● Configures acquisition for ALTMUX path automatically

● Configures acquisition to measure switch voltages

for any switches enabled by BALSWENn automati-

cally on all unipolar cell positions (~POLARITYn &

BALSW Short decision is as shown in Table 71.

Table 72. BALSW Short Diagnostic Auto-Configuration

CONFIGURATION BITS

MEASUREEN1[15:14]

MEASUREEN1[13:0]

MEASUREEN2[5:0]

BALSWEN[13:0]

AUTOMATIC SETTING

0b00

PURPOSE

Disable VBLK measurements

(~POLARITYn & CELLENn)

Enable only selected Unipolar Cell measurements

Disable AUXn measurements

0b000000

0x0000

0x0

Disable all balancing switches

DIAGSEL1/2

Disable all diagnositics

SCANCTRL:ALTMUXSEL

SCANCTRL:OVSAMPL

1

Enable ALTMUX measurement path

Oversample rates conﬁgured to 1

0x0

Table 73. BALSW Open-Diagnostic Operation

BALSW

V

FAULT INDICATED?

POSSIBLE FAULT CONDITION

SWn

> V

Yes

Switch open circuit, or overcurrent

BALHIGHTHR

BALLOWTHR

BALHIGHTHR

On

No

None

< V

Yes

Path open circuit, or short circuit

BALLOWTHR

Table 74. BALSW Open-Diagnostic Auto-Configuration

CONFIGURATION BITS

MEASUREEN1[15:14]

MEASUREEN1[13:0]

MEASUREEN2[5:0]

AUTOMATIC SETTING

PURPOSE

0b00

Disable VBLK measurements

BALSWENn & ~POLARITYn

Measure only active unipolar switch positions

Disable AUXn measurements

0b000000

DIAGSEL1/2

0x0

1

Disable all diagnostics

SCANCTRL:ALTMUXSEL

SCANCTRL:OVSAMPL

Enable ALTMUX measurement path

Conﬁgure oversample rate to 1

0x0

Maxim Integrated │ 167

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALSWENn). Note: it is not necessary for the device

to be in an active manual cell-balancing operation,

only that BALSWEN will be conﬁgured as desired.

Set the thresholds by taking into account the minimum

and maximum R of the switch itself, as specified in the

Electrical Characteristics table and the balancing current

SW

for the application.

● Host initiates acquisition

BALSW Open Diagnostics operation decision is as shown

in Table 73.

● Compares each measurement to the threshold value

BALLOWTHR and BALHIGHTHR automatically (see

Table 73)

The BALSW Open Diagnostic procedural flow chart is

shown in Figure 89.

● If outside the threshold, sets the corresponding flag

in ALRTBALSW automatically

MAX1785X FULLY

FUNCTIONAL AND

INITIALIZED

MAX1785X FULLY

FUNCTIONAL AND

INITIALIZED

ENSURE BALLOWTHR

AND BALHIGHTHR SET

TO DESIRED VALUE

ENSURE BALLOWTHR

AND BALHIGHTHR SET

TO DESIRED VALUE

0B110 FOR ODD SWITCHES

SET SCANCFG

0B111 FOR EVEN SWITCHES

SET SCANCFG TO

0B101

WAIT 100μs

START ADC

MEASUREMENT

START ADC

MEASUREMENT

ALRTFMEA1

DATACHECK BIT

SHOWS RESULT

YES

SCANDONE

= 1?

ALRTFMEA1

DATACHECK BIT

SHOWS RESULT

YES

SCANDONE

= 1?

NO

CLEAR SCANCFG AND

SCANDONE

BALSW OPEN CHECK

INVALID

CLEAR SCANCFG AND

SCANDONE

BALSW CONDUCTING

CHECK INVALID

CHECK ALRTBALSW OR

CELLN REGISTERS FOR

DETAILED RESULT

CHECK ALRTBALSW OR

CELLN REGISTERS FOR

DETAILED RESULT

BALSW CELL SENSE

CHECK DONE

BALSW CONDUCTING

CHECK DONE

Figure 89. BALSW Open Diagnostic

Figure 90. Sense-Wire Open-Diagnostic Flow

Maxim Integrated │ 168

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The BALSW Short Diagnostic automatically overrides

the configuration settings during the measurements scan

(see Table 74).

If enabled, the sense-wire open diagnostic modes detect

if a cell sense wire is disconnected as follows:

● Configures acquisition for bipolar mode

Even/Odd Sense-Wire Open Diagnostics

Table 75. Sense-Wire Open-Diagnostic Automatic Configuration Overrides

CONFIGURATION

BIT(S)

CONFIGURATION

TASK

STATE

Enable odd switches

Enable even switches

Switch positions with POLARITYn=1 (bipolar/bus bar)

and those above TOPCELL1/2 are masked/disabled.

1555h (SCANCFG[2:0]=0b110) or

2AAAh (SCANCFG[2:0]=0b111)

BALSWEN[13:0]

MEASUREEN1[15:14]

MEASUREEN1[13:0]

0b00

Disable VBLK measurements

BALSWEN[13:0] is set as per automatic overrides shown above.

Measure only active switch positions per automatic BALSWEN

overrides and unipolar positions.

(BALSWENn & ~POLARITYn)

MEASUREEN2[5:0]

DIAGSEL1/2

0b000000

Disable AUXn measurements

Disable all diagnostics

0x0

1

SCANCTRL:ALTMUXSEL

SCANCTRL:OVSAMPL

Enable ALTMUX measurement path

Oversample conﬁgured to 1

0x0

To Cell 5

TO CELL 5

R

FILTER

R

FILTER

SENSE

WIRE

SENSE

WIRE

4.0*V(CELL)

C(4)

To HVMux

~2X

LOWER

V4 APPEARS AS

~ V(CELL5)/2 + V(CELL4) + V(CELL3)/2

TO ALTMUX

C

R

C

FILTER

~3.5*V(CELL)

R

FILTER

~4.5*V(CELL)

BALANCE

SW(4)

V4 APPEARS REDUCED:

BALLOWTHR < V4 < BALHIGHTHR

To ALTMux

BALSW4

HV

To ALTMux

BALSW4

HV

(BUT IS NOT MEASURED)

CELL 4

CELL 3

CELL 2

C

CELL 4

C

BALFILTER

ON

OFF

BALANCIN

G SWITCH

4

BALANCIN

G SWITCH

4

SW4 & SW3

Pulled closer

R

FILTER

SENSE

WIRE

SENSE

WIRE

3.0*V(CELL)

C(3)

To HVMux

To ALTMux

~2X

To HVMux

To ALTMux

LOWER

V3 APPEARS AS

~ V(CELL4)/2 + V(CELL3) + V(CELL2)/2

TO ALTMUX

R

BALANCE

R

C

FILTER

~3.5*V(CELL)

BALANCE

~2.5*V(CELL)

C

FILTER

SW(3)

V3 APPEARS REDUCED:

BALLOWTHR < V3 < BALHIGHTHR

SW(3)

(BUT IS NOT MEASURED)

BALSW3

HV

BALSW3

HV

C

CELL 3

C

BALFILTER

OFF

ON

Detect breaks

in dashed-line paths.

BALANCIN

G SWITCH

3

BALANCIN

G SWITCH

3

SW3 & SW2

PULLED CLOSER

R

FILTER

SENSE

WIRE

SENSE

WIRE

2.0*V(CELL)

R

2.0*V(CELL)

FILTER

C(2)

To HVMux

~2X

To HVMux

LOWER

V2 APPEARS AS

~ V(CELL3)/2 + V(CELL2) + V(CELL1)/2

TO ALTMUX

R

BALANCE

R

C

FILTER

~1.5*V(CELL)

BALANCE

FILTER

~2.5*V(CELL)

SW(2)

V2 APPEARS REDUCED:

BALLOWTHR < V2 < BALHIGHTHR

To ALTMux

BALSW2

To ALTMux

BALSW2

HV

(BUT IS NOT MEASURED)

CELL 2

C

HV

BALFILTER

ON

C

OFF

BALFILTER

BALANCIN

G SWITCH

2

BALANCIN

G SWITCH

2

SW2 & SW1

Pulled closer

R

FILTER

SENSE

WIRE

SENSE

WIRE

R

FILTER

1.0*V(CELL)

C(1)

To HVMux

To ALTMux

To HVMux

To ALTMux

~1.5X (END CASE)

LOWER

V1 APPEARS AS

~ V(CELL2)/2 + V(CELL1)

TO ALTMUX

BALANCE

~1.5*V(CELL)

R

C

FILTER

BALANCE

~0.5*V(CELL)

C

FILTER

SW(1)

V1 APPEARS REDUCED:

BALLOWTHR < V1 < BALHIGHTHR

To Cell 1

TO CELL 1

(BUT IS NOT MEASURED)

AGND

EVEN SENSE-WIRE OPEN DIAGNOSTIC:

ODD SENSE-WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH NO BROKEN SENSE WIRES

Figure 91. Cell Sense-Wire Open-Diagnostic Operations (Normal Operation)

Maxim Integrated │ 169

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

(for measuring voltages near zero) automatically

● Closes nonadjacent switches (even or odd)

automatically

● Configures acquisition to use ALTMUX path

automatically

● Host waits 100μs for settling and then initiates the

acquisition

● Compares the result to the BALHIGHTHR and

BALLOWTHR registers automatically

● If outside thresholds, sets flags in ALRTBALSW

automatically

Examples of normal and faulty operations are shown

in Figure 92, Figure 93, Figure 94, and Figure 95

for examples with and without bus bars (identified by

POLARITYn=1). By examining the combined reported

results from even and odd runs, the location and type of

fault can be determined. Figure 90 shows the procedure

performed by the MAX17853 during an open sense-wire

diagnostic.

TO CELL 5

SENSE

WIRE

SENSE

WIRE

3.0*V(CELL)

C(4)

~1.5X

To HVMux

LOWER

R

FILTER

C

FILTER

V4 APPEARS AS

~ V(CELL5)/2 + V(CELL4) + 0

TO ALTMUX

R

~2.5*V(CELL)

R

BALANCE

~3.5*V(CELL)

SW(4)

V4 APPEARS REDUCED:

BALLOWTHR < V4 < BALHIGHTHR

To ALTMux

BALSW4

To ALTMux

BALSW4

HV

(BUT IS NOT MEASURED)

HV

CELL 4

ON

CELL 4

OFF

R

BALFILTER

R

BALFILTER

BALANCING

SWITCH 4

BALANCING

SWITCH 4

SW4 & SW3

PULLED CLOSER

SENSE

WIRE

SENSE

WIRE

2.0*V(CELL)

C(3)

~1X

To HVMux

0V

C

FILTER

V3 APPEARS AS

~ V(CELL4)/2 + 0 + V(CELL2)/2

TO ALTMUX

V3 IS NEAR-ZERO

V3 < BALLOWTHR

(BUT IS NOT MEASURED)

~2.5*V(CELL)

2.0*V(CELL)

SW(3)

To ALTMux

BALSW3

To ALTMux

BALSW3

HV

(BUT IS NOT MEASURED)

BUSBAR

3

BUSBAR

3

HV

OFF

Rbalfilter

R

BALFILTER

OFF

(POLARITY[3] = 1)

BALANCING

SWITCH 3

BALANCING

SWITCH 3

C3, SW3

≈ C2, SW2

C3, SW3

≈ C2, SW2

SENSE

WIRE

SENSE

WIRE

2.0*V(CELL)

C(2)

~1.5X

To HVMux

LOWER

V2 APPEARS AS

~ 0 + V(CELL2) + V(CELL1)/2

TO ALTMUX

C

FILTER

~1.5*V(CELL)

2.0*V(CELL)

SW(2)

V2 APPEARS REDUCED:

BALLOWTHR < V2 < BALHIGHTHR

To ALTMux

BALSW2

HV ON

To ALTMux

BALSW2

(BUT IS NOT MEASURED)

CELL 2

HV

OFF

R

BALFILTER

R

BALFILTER

BALANCIN

G SWITCH 2

BALANCING

SWITCH 2

SW2 & SW1

PULLED CLOSER

SENSE

WIRE

SENSE

WIRE

1.0*V(CELL)

C(1)

To HVMux

To ALTMux

To HVMux

To ALTMux

~1.5X (END CASE)

LOWER

C

FILTER

V1 APPEARS AS

~ V(CELL2)/2 + V(CELL1)

TO ALTMUX

~1.5*V(CELL)

~0.5*V(CELL)

SW(1)

V1 APPEARS REDUCED:

BALLOWTHR < V1 < BALHIGHTHR

TO CELL 1

(BUT IS NOT MEASURED)

AGND

EVEN SENSE WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH BUS BAR

ODD SENSE WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH BUS BAR

Figure 92. Cell Sense-Wire Open-Diagnostic Operations (Normal Operation, Including Bus Bars)

Maxim Integrated │ 170

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

TO CELL 5

SENSE

WIRE

SENSE

WIRE

4.0*V(Cell)

C(4)

~2.5X

ZERO

To HVMux

R

FILTER

R

FILTER

C

FILTER

V4 APPEARS AS

~ V(CELL5)/2 + V(CELL4) + V(CELL3)

TO ALTMUX

V4 APPEARS

NEAR-ZERO TO ALTMUX:

V4 < BALLOWTHR,

4.0*V(Cell)

R

BALANCE

R

BALANCE

~4.5*V(Cell)

SW(4)

To ALTMux

BALSW4

To ALTMux

BALSW4

(BUT IS NOT MEASURED)

SO ALRTBALSW[4] IS ISSUED

HV

CELL 4

OFF

CELL 4

CELL 3

CELL 2

ON

R

BALFILTER

R

BALFILTER

BALANCING

SWITCH 4

BALANCING

SWITCH 4

C3/SW3

PULLED TO

C4/SW4

3.0*V(CELL) OR

4.0*V(CELL)

DEPENDING ON

BREAK LOCATION

SENSE

WIRE

BREAK

SENSE

WIRE

BREAK

2.0*V(CELL)

DEPENDING ON

BREAK LOCATION

C(3)

ZERO

~2.5X

To HVMux

R

FILTER

C

FILTER

V3 APPEARS

NEAR-ZERO TO ALTMUX:

V3 < BALLOWTHR

V3 APPEARS AS

~ V(CELL4) + V(CELL3) + V(CELL2)/2

TO ALTMUX

~4.0*V(Cell)

R

BALANCE

R

BALANCE

2.0*V(Cell)

SW(3)

To ALTMux

BALSW3

To ALTMux

BALSW3

SO ALRTBALSW[3] IS ISSUED

(BUT IS NOT MEASURED)

BREAKS IN

THESE

LOCATIONS

YIELD SIMILAR

RESULTS VIA

ALTMUX,

BUT WILL NOT

IMPACT HVMUX.

BREAKS IN

THESE

LOCATIONS

YIELD SIMILAR

RESULTS VIA

ALTMUX,

BUT WILL NOT

IMPACT HVMUX.

CELL 3

HV

ON

HV

OFF

R

BALFILTER

R

BALFILTER

BALANCING

SWITCH 3

BALANCING

SWITCH 3

C3/SW3

PULLED TO

C2/SW2

SENSE

WIRE

SENSE

WIRE

2.0*V(Cell)

C(2)

~1.5X

To HVMux

LOWER

R

FILTER

C

FILTER

V2 APPEARS AS

~ 0 + V(CELL2) + V(CELL1)/2

TO ALTMUX

~1.5*V(Cell)

R

BALANCE

2.0*V(Cell)

R

BALANCE

SW(2)

V2 APPEARS REDUCED,

BALLOWTHR < V2 < BALHIGHTHR

To ALTMux

BALSW2

To ALTMux

BALSW2

HV ON

2X

(BUT IS NOT MEASURED)

CELL 2

HV

OFF

R

BALFILTER

BALANCING

SWITCH 2

BALANCING

SWITCH 2

SW2 & SW1

PULLED CLOSER

SENSE

WIRE

SENSE

WIRE

1.0*V(Cell)

C(1)

To HVMux

To ALTMux

To HVMux

To ALTMux

~1.5X (END CASE)

LOWER

R

FILTER

C

FILTER

V1 APPEARS AS

~ V(CELL2)/2 + V(CELL1)

TO ALTMUX

~1.5*V(Cell)

R

BALANCE

~0.5*V(Cell)

R

BALANCE

SW(1)

V1 APPEARS REDUCED:

BALLOWTHR < V1 < BALHIGHTHR

TO CELL 1

(BUT IS NOT MEASURED)

AGND

ODD SENSE WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH BROKEN SENSE WIRE 3

EVEN SENSE WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH BROKEN SENSE WIRE 3

ALRTBALSW[3] ISSUED DUE TO BALLOWTHR VIOLATION.

ALRTBALSW[4] ISSUED DUE TO BALLOWTHR VIOLATION.

Figure 93. Cell Sense-Wire Open-Diagnostic Operations (Example with Odd Sense-Wire Fault)

TO CELL 5

SENSE

TO CELL 5

SENSE

4.0*V(Cell)

WIRE

4.0*V(Cell)

WIRE

C(4)

~1.5X

To HVMux

LOWER

R

FILTER

C

FILTER

V4 APPEARS AS

~ V(CELL5)/2 + V(CELL4) + 0

TO ALTMUX

~3.5*V(Cell)

R

BALANCE

~4.5*V(Cell)

BALANCE

SW(4)

V4 APPEARS REDUCED:

BALLOWTHR < V4 < BALHIGHTHR

To ALTMux

BALSW4

To ALTMux

BALSW4

(BUT IS NOT MEASURED)

CELL 4

CELL 3

CELL 2

HV

CELL 4

CELL 3

CELL 2

OFF

ON

R

BALFILTER

BALANCIN

G SWITCH

4

BALANCING

SWITCH 4

SW4 & SW3

PULLED CLOSER

SENSE

WIRE

SENSE

WIRE

3.0*V(Cell)

C(3)

~2.5X

ZERO

To HVMux

C

FILTER

V3 APPEARS

NEAR-ZERO TO ALTMUX:

V3 < BALLOWTHR

V3 APPEARS AS

~ V(CELL4)/2 + V(CELL3) + V(CELL2)

TO ALTMUX

~3.5*V(Cell)

SW(3)

To ALTMux

BALSW3

To ALTMux

BALSW3

SO ALRTBALSW[3] IS ISSUED

(BUT IS NOT MEASURED)

HV

ON

HV

OFF

R

BALFILTER

BALANCIN

G SWITCH

3

BALANCING

SWITCH 3

C2/SW2

PULLED TO

C3/SW3

2.0*V(CELL) OR

3.0*V(CELL)

DEPENDING ON

BREAK LOCATION

2.0*V(CELL) OR

SENSE

WIRE

BREAK

SENSE

WIRE

BREAK

1.0*V(CELL)

DEPENDING ON

BREAK LOCATION

C(2)

~2.5X

ZERO

To HVMux

V2 APPEARS AS

~ V(CELL3) + V(CELL2) + V(CELL1)/2

TO ALTMUX

C

FILTER

V2 APPEARS

NEAR-ZERO TO ALTMUX:

V2 < BALLOWTHR

1.0*V(Cell)

3.0*V(Cell)

SW(2)

To ALTMux

BALSW2

To ALTMux

BALSW2

HV ON

(BUT IS NOT MEASURED)

SO ALRTBALSW[2] IS ISSUED

BREAKS IN

THESE

LOCATIONS

BREAKS IN

THESE

LOCATIONS

HV

OFF

R

BALFILTER

YIELD SIMILAR

RESULTS VIA

ALTMUX,

BUT WILL NOT

IMPACT HVMUX.

YIELD SIMILAR

RESULTS VIA

ALTMUX,

BUT WILL NOT

IMPACT HVMUX.

BALANCIN

G SWITCH

2

BALANCING

SWITCH 2

C2/SW2

PULLED TO

C1/SW1

SENSE

WIRE

SENSE

WIRE

1.0*V(Cell)

C(1)

To HVMux

To ALTMux

To HVMux

To ALTMux

~1X (End Case)

LOWER

R

FILTER

C

FILTER

V1 APPEARS AS

~ 0 + V(CELL1)

TO ALTMUX

1.0*V(Cell)

R

~0.5*V(Cell)

R

BALANCE

SW(1)

V1 APPEARS REDUCED:

BALLOWTHR < V1 < BALHIGHTHR

TO CELL 1

(BUT IS NOT MEASURED)

AGND

ODD SENSE WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH BROKEN SENSE WIRE 2

EVEN SENSE WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH BROKEN SENSE WIRE 2

ALRTBALSW[3] ISSUED DUE TO BALLOWTHR VIOLATION.

ALRTBALSW[2] ISSUED DUE TO BALLOWTHR VIOLATION.

Figure 94. Cell Sense-Wire Open-Diagnostic Operations (Example with Even Sense-Wire Fault)

Maxim Integrated │ 171

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 75 lists the configuration-setting overrides the

MAX17853 temporarily enforces during an open sense-

wire diagnostic-measurement scan.

Examples of Normal Sense-Wire Operation

Figure 91 shows the electrical behavior during both odd

and even sense-wire open diagnostics when no sense

wires are open or compromised.

These overrides are only active during the scan; normal

configured operation is restored at the end of the scan.

Table 76. Odd Sense-Wire Open-Measurement Results for Broken Sense Wires

SENSE-WIRE OPEN-FAULT LOCATION

SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 SW13 SW14

Cell1 LO

Cell2 NM

Cell3 OK

Cell4 NM

Cell5 OK

Cell6 NM

Cell7 OK

Cell8 NM

Cell9 OK

Cell10 NM

Cell11 OK

Cell12 NM

Cell13 OK

Cell14 NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

Cell

Measurement

Note: OK = No error detected; LO = BALLOWTHR violation; NM = Not Measured; Maximum result is 2.5V.

Table 77. Even Sense-Wire Open-Measurement Results for Broken Sense Wires

SENSE-WIRE OPEN-FAULT LOCATION

SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 SW13 SW14

Cell1 NM

Cell2 OK

Cell3 NM

Cell4 OK

Cell5 NM

Cell6 OK

Cell7 NM

Cell8 OK

Cell9 NM

Cell10 OK

Cell11 NM

Cell12 OK

Cell13 NM

Cell14 OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

OK

NM

LO

Cell

Measurement

Note: OK = No error detected; LO = BALLOWTHR violation; NM = Not measured; Maximum result is 2.5V.

Maxim Integrated │ 172

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Figure 92 shows the electrical behavior during both odd

and even sense-wire open diagnostics when no sense

wires are open or compromised, with bus bars included.

Figure 94 and Figure 95 show examples of how broken

sense wires are detected and diagnosed using combina-

tions of odd and even sense-wire open diagnostics.

Figure 94 shows the electrical behavior during both odd

and even sense-wire open diagnostic sequences when a

sense-wire in an even position is broken. The alerts that

are issued as a result of the fault are also shown.

Examples of Broken Sense-Wire Fault Detection

Figure 93 shows the electrical behavior during both odd

and even sense-wire open diagnostic sequences when a

sense-wire in an odd position is broken. The alerts that

are issued as a result of the fault are also shown.

Sense-Wire Open-Fault-Detection Results

Table 78. Odd and Even Sense-Wire Open-Measurement Results Overlay for Broken

Sense Wires

SENSE-WIRE OPEN-FAULT LOCATION

SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 SW13 SW14

Cell1 LO

Cell2 OK

Cell3 OK

Cell4 OK

Cell5 OK

Cell6 OK

Cell7 OK

Cell8 OK

Cell9 OK

Cell10 OK

Cell11 OK

Cell12 OK

Cell13 OK

Cell14 OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

OK

LO

Cell

Measurement

Note: OK = No Error Detected; LO = BALLOWTHR Violation; Maximum result is 2.5V

Maxim Integrated │ 173

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

TO CELL 5

SENSE

WIRE

SENSE

WIRE

4.0*V(Cell)

C(4)

<2X

To HVMux

LOWER

R

FILTER

C

FILTER

V4 APPEARS AS

~ V(CELL5)/2 + V(CELL4) + V(CELL3)/2

TO ALTMUX

~3.5*V(Cell)

R

BALANCE

~4.5*V(Cell)

BALANCE

SW(4)

V4 APPEARS REDUCED:

BALLOWTHR < V4 < BALHIGHTHR

To ALTMux

BALSW4

To ALTMux

BALSW4

(BUT IS NOT MEASURED)

HV

CELL 4

CELL 3

CELL 2

OFF

CELL 4

ON

R

BALFILTER

BALANCING

SWITCH 4

BALANCING

SWITCH 4

SW4 & SW3

PULLED CLOSER

SENSE

WIRE

SENSE

WIRE

3.0*V(Cell)

C(3)

<2X

To HVMux

LOWER

C

FILTER

V3 APPEARS AS

~ V(CELL4)/2 + V(CELL3) + V(CELL2)/2

TO ALTMUX

V3 APPEARS ONLY PARTIALLY REDUCED:

V3 > BALHIGHTHR

SO ALRTBALSW[3] IS ISSUED

~3.5*V(Cell)

<3.0*V(Cell)

SW(3)

To ALTMux

BALSW3

To ALTMux

BALSW3

(BUT IS NOT MEASURED)

R

BALFILTE

HV

ON

CELL 3

HV

OFF

R

BALFILER

BALANCING

SWITCH 3

BALANCING

SWITCH 3

TOO MUCH IR DROP

ACROSS BALSW3

SENSE

WIRE

SENSE

WIRE

2.0*V(Cell)

C(2)

<2X

To HVMux

LOWER

V2 APPEARS AS

~ V(CELL3)/2 + V(CELL2) + V(CELL1)/2

TO ALTMUX

C

FILTER

<2.0*V(Cell)

V2 APPEARS ONLY PARTIALLY REDUCED:

V2 > BALHIGHTHR

SO ALRTBALSW[2] IS ISSUED

>2.0*V(Cell)

SW(2)

To ALTMux

BALSW2

To ALTMux

BALSW2

HV ON

(BUT IS NOT MEASURED)

Rbalfilter

HV

OFF

CELL 2

R

BALFILTER

BALANCING

SWITCH 2

BALANCING

SWITCH 2

TOO MUCH IR DROP

ACROSS BALSW2

SENSE

WIRE

SENSE

WIRE

1.0*V(Cell)

C(1)

To HVMux

To ALTMux

To HVMux

To ALTMux

<1.5X (End Case)

LOWER

C

FILTER

V1 APPEARS AS

~ V(CELL2)/2 + V(CELL1)

TO ALTMUX

>1.0*V(Cell)

~0.5*V(Cell)

SW(1)

V1 APPEARS REDUCED:

BALLOWTHR < V1 < BALHIGHTHR

TO CELL 1

(BUT IS NOT MEASURED)

AGND

ODD SENSE WIRE OPEN DIAGNOSTIC:

EVEN SENSE WIRE OPEN DIAGNOSTIC:

EXAMPLE WITH HIGH IMPEDANCE SWITCH OR INTERNAL LINE BREAK 3

ALRTBALSW[3] ISSUED DUE TO BALHIGHTHR VIOLATION.

EXAMPLE WITH HIGH IMPEDANCE SWITCH OR INTERNAL LINE BREAK 2

ALRTBALSW[2] ISSUED DUE TO BALHIGHTHR VIOLATION.

Figure 95. Cell Sense-Wire Open-Diagnostic Operations (Example with Broken BALSW or Internal Trace)

Table 79. Odd and Even Sense-Wire Open-Measurement Results Overlay for Broken

Sense Wires

SWITCH OR TRACE FAULT LOCATION (BALSW)

1

2

3

4

5

6

7

8

9

10

OK

HI

11

12

OK

HI

13

OK

HI

14

OK

HI

Cell1

Cell2

Cell3

Cell4

Cell5

Cell6

Cell7

Cell8

Cell9

HI

OK

HI

OK

HI

OK

HI

OK

HI

OK

HI

OK

HI

OK

HI

OK

HI

OK

HI

OK

Cell

Measurement

OK

Cell10 OK

Cell11 OK

Cell12 OK

Cell13 OK

Cell14 OK

OK

Note: OK = No error detected, LO = BALLOWTHR violation, Maximum result is 2.5V

Maxim Integrated │ 174

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Table 76 shows the measurement alerts that correspond

to a break in each sense-wire position during an odd

sense-wire open diagnostic. When combined with the

results from an even sense-wire open diagnostic, the

exact location of the sense-wire fault can be determined.

Register Map

MAX17853 User Register Map

Register Map Usage Guidelines

The register map (RMap) for the MAX17853 is detailed

in the following sections. General-usage guidelines per-

taining to the entire RMap are outlined here, detailing

the expected usage of the RMap, including how various

protocol and access issues are handled.

Table 77 shows the measurement alerts that correspond

to a break in each sense-wire position during an oven

sense-wire open diagnostic. When combined with the

results from an odd sense-wire open diagnostic, the exact

location of the sense-wire fault can be determined.

Interface Protocol Errors

When combined together, the two diagnostics can identify

the exact location of a broken sense wire. The combined

diagnostic results are shown in Table 78.

For read and write transactions to be accepted, all inter-

face-protocol expectations must be met. If protocol errors

occur, they are reported through alerts in the STATUS1

and STATUS2 registers, notifying the user of the issue

observed. If a protocol error occurs, none of the behaviors

listed below apply, because the transaction will be reject-

ed, even if the transaction addresses a Reserved register

address. See the UART and SPI Interface descriptions for

complete details on expected interface protocols.

Examples of Broken Internal Switch and

Trace-Fault Detection

Figure 95 shows the electrical behavior during both odd

and even sense-wire open-diagnostic sequences when

there is a fault in an internal switch or connection. The

alerts that are issued as a result of the fault are also

shown.

Reserved Registers

Figure 96 shows examples of how broken-sense wires

are detected and diagnosed using combinations of odd

and even sense-wire open diagnostics.

All user-accessible registers are contained in the address

space between 0x00 and 0x98. Any address/register in

this space not specifically listed in the RMap should be

treated as Reserved; for the MAX17853, the following

addresses within the user address space are reserved:

0x2C, 0x2D, 0x2E, 0x2F, 0x46, and 0x84 through 0x8B.

The address space 0x99 to 0xFF is also reserved for

Maxim Use Only.

Broken-Switch Fault-Detection Results

When combined together, the two diagnostics can cover

and identify the exact location of a faulty switch or inter-

nal trace. The combined diagnostic results are shown in

Table 79. Notice that unlike a broken sense wire, only a

single ALRTBALSW alert is issued for faults of this type.

If an otherwise valid attempt to read or write to a reserved

register address occurs (with no protocol or CRC/PEC

errors), no errors are issued for the SPI/UART transaction.

No data written to a reserved register address are internally

stored, and reserved registers always read back all zeros.

If a UART block readback request includes any reserved

register addresses, the addresses will be included in the

readback data, with all zeros returned; no addresses are

skipped during UART block readback transactions. Users

should normally avoid writing to reserved registers, as the

MAX17853 will not respond to such transactions.

ADC End-of-Scan Diagnostics

This diagnostic is performed at the end of a measurement-

sequence that is configured to use the ADC (SCANCFG

= 0b000 or 0b001) when ADCZSFSEN=1. The ADC mea-

surements are taken in bipolar mode.

For full-scale diagnostic: ADC

= V

and ADC

=

IN

REF

V

AA

.

If the result from the ADC is less than FFFh (12-bit result),

an alert is issued by setting the ALRTADCFS bit in the

FMEA2 register.

Unused Bitﬁelds

Within the user-accessible registers, there are many

unused bitfields, denoted by a dash (-) in the RMap.

During read and write transactions, PEC and CRC checks

apply to all 16 bits of data, including any unused bitfields.

No data written to an unused bitfield is internally stored,

and unused bitfields always read back all zeros.

Maxim Integrated │ 175

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

that follow. These behaviors ensure that register content

Reserved Bitﬁelds

currently in use by any requested internal process is not

subject to alteration while in use. In general, the register

blocks are organized and defined to provide maximum

transaction efficiency, while also ensuring the ultimate

level of safety.

Within the RMap, there are two reserved bitfields,

DEVCFG1RSRV (1 bit) and DEVCFG2RSRV (4 bits);

these are reserved for future use. During read and write

transactions, PEC and CRC checks apply to all 16 bits

of data, including any reserved bitfields. Data written to

a reserved bitfield will be internally stored (though the

settings of these bitfields have no effect on internal opera-

tions), and the reserved bitfields always read back their

current settings.

If a valid write transaction to a blocked (busy) register

occurs, the transaction is rejected and the ALRTRJCT bit

set, indicating the write was ignored since that register

was currently being used by an ongoing internal opera-

tion. In general, user software should be written to avoid

modifying register content that is currently in use, instead

confirming that the internal process has completed before

any modifications are written to the MAX17853.

Register Blocks and Transaction-Reject Behavior

The RMap is organized into several register blocks. Each

register block is subject to specific transaction-rejection

behaviors, as detailed in the register block descriptions

ADDRESS

NAME

MSB

LSB

STATUS Registers

VERSION[15:8]

MOD[11:4]

VER[3:0]

0x00

VERSION[7:0]

ADDRESS[15:8]

ADDRESS[7:0]

STATUS1[15:8]

MOD[3:0]

ADDRUN-

LOCK

BA[4:0]

TA[4:3]

0x01

TA[2:0]

DA[4:0]

ALRT- ALRTCEL- ALRTCEL- ALRT-

ALRT-

ALR-

ALRTSCAN ALRTRST

MSMTCH LOVST

LUVST BLKOVST BLKUVST TAUXOVST

0x02

ALRTAUX-

UVST

ALRTIN-

ALRTPEC

ALRT-

CBAL

ALRT-

FMEA2

ALRT-

FMEA1

STATUS1[7:0]

STATUS2[15:8]

STATUS2[7:0]

–

ALRTCAL

TRFC

ALRTPE- ALRTP-

ALRT-

MANDN

ALRTPA-

RUP

ALRT-

PARDN ALUART

ALRTDU-

–

CUP

ECDN

MANUP

0x03

0x04

ALRTSCLK-

ERR

ALR-

TOSC3

ALRTINT-

BUS

ALRTSPI

–

ALRTRJCT

ALRTCB- ALRTCB- ALRTCB-

ALRT-

CBNTFY

ALRTCB-

DONE

STATUS3[15:8]

STATUS3[7:0]

–

TIMEOUT TEMP

CAL

–

ALRT-

COM-

MSEU1

ALRT-

COM-

MSEL1

ALRT-

COM-

MSEL2

ALR-

TOSC1

ALR-

TOSC2

ALRCOM-

MSEU2

ALRT-

VDDL3

ALRT-

VDDL2

FMEA1[15:8]

FMEA1[7:0]

FMEA2[15:8]

FMEA2[7:0]

0x05

0x06

ALRT-

BALS-

WSUM

ALRT-

VDDL1

ALRT-

GNDL3

ALRT-

GNDL2

ALRT-

GNDL1

ALRTH- ALRTHVH- ALRTH-

VUV

DRM

VOV

ALRTAUX-

PRTCT-

SUM

ALRTUS- ALRTD-

ALRT- ALRTSCAN-

TEMP

–

ER

CINMUX

TIMEOUT

ALRT-

COMPAC- COMPAC-

COV CUV

ALRT-

ALRTAD- ALRTAD-

–

CZS

CFS

Maxim Integrated │ 176

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

LSB

ALRT-

COM-

POVST

ALRT-

COMPU-

VST

ALRTAD-

CAUXU-

VST

ALRTAD-

COVST

ALRTAD-

CUVST

ALRTAD- ALRTCOM-

CAUXOVST PAUXOVST

COM-

PAUXU-

VST

ALRTSUM[15:8]

0x07

ALRT-

CALO-

SADC

ALRT-

CALOSR

STHRM

ALRTCAL- ALRTCAL-

GAINP GAINR

ALRTSUM[7:0]

–

CALO-

ALRTOVCELL[15:8]

ALRTOVCELL[7:0]

ALRTUVCELL[15:8]

ALRTUVCELL[7:0]

MINMAXCELL[15:8]

MINMAXCELL[7:0]

ALRTOV[14:9]

0x08

0x09

0x0A

ALRTOV[8:1]

ALRTUV[14:9]

ALRTUV[8:1]

–

MAXCELL[3:0]

MINCELL[3:0]

ALRTAUXPRTC-

TREG[15:8]

–

0x0B

ALRTAUXPRTCTREG[7:0]

ALRTAUXOVREG[15:8]

ALRTAUXOVREG[7:0]

ALRTAUXUVREG[15:8]

ALRTAUXUVREG[7:0]

ALRTCOMPOVREG[15:8]

ALRTCOMPOVREG[7:0]

ALRTCOMPUVREG[15:8]

ALRTCOMPUVREG[7:0]

–

ALRTAUXPRTCT[5:4]

ALRTAUXPRTCT[3:0]

–

0x0C

0x0D

0x0E

0x0F

ALRTAUXOV[5:4]

ALRTAUXOV[3:0]

–

ALRTAUXUV[5:4]

ALRTAUXUV[3:0]

ALRTCOMPOV[14:9]

ALRTCOMPOV[8:1]

ALRTCOMPUV[14:9]

ALRTCOMPUV[8:1]

–

ALRTCOM-

PAUXOVREG[15:8]

–

0x10

0x11

ALRTCOM-

PAUXOVREG[7:0]

ALRTCOM-

PAUXOV[5:4]

–

ALRTCOMPAUXOV[3:0]

ALRTCOMPAUXUVREG[15:8]

–

ALRTCOMPAUX-

UV[5:4]

ALRTCOMPAUXUVREG[7:0]

ALRTCOMPAUXUV[3:0]

ALRTBALSWREG[15:8]

ALRTBALSWREG[7:0]

SWACTION[15:8]

ALRTBALSW[13:8]

ALRTBALSW[7:0]

0x12

0x13

–

SWACTION[7:0]

–

SWPOR

GENERAL CONFIGURATION Registers

TXUIDLE- TXLIDLE-

ALIVECNT-

EN

UAR-

THOST

DEVCFG1[15:8]

UARTCFG[1:0]

ADAPTTXEN[1:0]

DEVCF-

HIZ

0x14

0x15

SPI-

DEVCFG1[7:0]

DEVCFG2[15:8]

DEVCFG2[7:0]

SFTYCSB SFTYSCLK SFTYSDI

IIRFC[2:0]

NOPEC ALERTEN DBLBUFEN

DRVINT G1RSRV

–

DEVCFG2RSRV[3:0]

SCANTO-

FORCE- ALERT-

POR DCTSTEN

–

HVCPDIS

–

SPITODIS

CBTODIS

DIS

Maxim Integrated │ 177

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

LSB

AUXGPIOCFG[15:8]

AUXGPIOCFG[7:0]

GPIOCFG[15:8]

–

GPIOEN[5:4]

GPIODIR[5:4]

GPIODRV[5:4]

GPIORD[5:4]

GPIOEN[3:0]

GPIODIR[3:0]

GPIODRV[3:0]

GPIORD[3:0]

0x16

0x17

GPIOCFG[7:0]

FLXPCK- FLXPCK- FLXPCK-

EN2 EN1 SCAN

TOPCELL2[3:0]

PACKCFG[15:8]

PACKCFG[7:0]

–

TOPBLOCK[3:0]

TOPCELL1[3:0]

0x18

ALERT CONFIGURATION Registers

CEL-

LOVST-

ALRTEN ALRTEN

CEL-

LUVST-

SCAN-

ALRTEN

MSMTCH-

ALRTEN

BLKOVST- BLKUVST- AUXOVST-

ALRTEN ALRTEN ALRTEN

ALRTIRQEN[15:8]

ALRTIRQEN[7:0]

–

0x19

AUXUVST-

ALRTEN

PEC-

INTRFC- CAL-

ALRTEN ALRTEN ALRTEN ALRTEN 2ALRTEN 1ALRTEN

CBAL-

FMEA-

BLKOV-

ALRTEN

ALRTOVEN[15:8]

ALRTOVEN[7:0]

ALRTUVEN[15:8]

–

OVALRTEN[14:9]

OVALRTEN[8:1]

0x1A

0x1B

BLKUV-

ALRTEN

–

UVALRTEN[14:9]

ALRTUVEN[7:0]

UVALRTEN[8:1]

ALRTAUXOVEN[15:8]

ALRTAUXOVEN[7:0]

ALRTAUXUVEN[15:8]

ALRTAUXUVEN[7:0]

ALRTCALTST[15:8]

–

0x1C

0x1D

AUXOVALRTEN[5:4]

AUXOVALRTEN[3:0]

–

AUXUVALRTEN[5:4]

AUXUVALRTEN[3:0]

–

CALO-

SADC-

ALRTFRC

CALO- CALGAIN- CALGAIN-

0x1E

CALOSR-

ALRTFRC

ALRTCALTST[7:0]

–

STHRM- PALRT-

RALRT-

FRC

ALRTFRC

FRC

THRESHOLD Registers

OVTHCLRREG[15:8]

0x1F

OVTHCLR[13:6]

OVTHCLR[5:0]

OVTHSET[13:6]

OVTHSET[5:0]

UVTHCLR[13:6]

UVTHCLR[5:0]

UVTHSET[13:6]

UVTHSET[5:0]

MSMTCH[13:6]

MSMTCH[5:0]

BIPOVTHCLR[13:6]

BIPOVTHCLR[5:0]

BIPOVTHSET[13:6]

BIPOVTHSET[5:0]

OVTHCLRREG[7:0]

–

OVTHSETREG[15:8]

0x20

OVTHSETREG[7:0]

UVTHCLRREG[15:8]

0x21

UVTHCLRREG[7:0]

UVTHSETREG[15:8]

0x22

UVTHSETREG[7:0]

MSMTCHREG[15:8]

(0x23)

MSMTCHREG[7:0]

BIPOVTHCLRREG[15:8]

0x24

BIPOVTHCLRREG[7:0]

BIPOVTHSETREG[15:8]

0x25

BIPOVTHSETREG[7:0]

Maxim Integrated │ 178

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

LSB

BIPUVTHCLRREG[15:8]

BIPUVTHCLRREG[7:0]

BIPUVTHSETREG[15:8]

BIPUVTHSETREG[7:0]

BLKOVTHCLRREG[15:8]

BLKOVTHCLRREG[7:0]

BLKOVTHSETREG[15:8]

BLKOVTHSETREG[7:0]

BLKUVTHCLRREG[15:8]

BLKUVTHCLRREG[7:0]

BLKUVTHSETREG[15:8]

BLKUVTHSETREG[7:0]

AUXROVTHCLRREG[15:8]

AUXROVTHCLRREG[7:0]

AUXROVTHSETREG[15:8]

AUXROVTHSETREG[7:0]

AUXRUVTHCLRREG[15:8]

AUXRUVTHCLRREG[7:0]

AUXRUVTHSETREG[15:8]

AUXRUVTHSETREG[7:0]

AUXAOVTHCLRREG[15:8]

AUXAOVTHCLRREG[7:0]

AUXAOVTHSETREG[15:8]

AUXAOVTHSETREG[7:0]

AUXAUVTHCLRREG[15:8]

AUXAUVTHCLRREG[7:0]

AUXAUVTHSETREG[15:8]

AUXAUVTHSETREG[7:0]

COMPOVTHREG[15:8]

COMPOVTHREG[7:0]

BIPUVTHCLR[13:6]

0x26

0x27

0x28

0x29

0x2A

0x2B

0x30

0x31

0x32

0x33

0x34

(0x35)

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

BIPUVTHCLR[5:0]

BIPUVTHSET[13:6]

BIPUVTHSET[5:0]

BLKOVTHCLR[13:6]

BLKOVTHCLR[5:0]

BLKOVTHSET[13:6]

BLKOVTHSET[5:0]

BLKUVTHCLR[13:6]

BLKUVTHCLR[5:0]

BLKUVTHSET[13:6]

BLKUVTHSET[5:0]

AUXROVTHCLR[13:6]

AUXROVTHCLR[5:0]

AUXROVTHSET[13:6]

AUXROVTHSET[5:0]

AUXRUVTHCLR[13:6]

AUXRUVTHCLR[5:0]

AUXRUVTHSET[13:6]

AUXRUVTHSET[5:0]

AUXAOVTHCLR[13:6]

AUXAOVTHCLR[5:0]

AUXAOVTHSET[13:6]

AUXAOVTHSET[5:0]

AUXAUVTHCLR[13:6]

AUXAUVTHCLR[5:0]

AUXAUVTHSET[13:6]

AUXAUVTHSET[5:0]

COMPOVTH[9:2]

–

COMPOVTH[1:0]

COMPUVTH[1:0]

–

COMPUVTHREG[15:8]

COMPUVTHREG[7:0]

COMPUVTH[9:2]

–

COMPAUXROVTHREG[15:8]

COMPAUXROVTH[9:2]

COMPAUXROVTHREG[7:0] COMPAUXROVTH[1:0]

COMPAUXRUVTHREG[15:8]

–

COMPAUXRUVTH[9:2]

COMPAUXRUVTHREG[7:0] COMPAUXRUVTH[1:0]

COMPAUXAOVTHREG[15:8]

–

COMPAUXAOVTH[9:2]

COMPAUXAOVTHREG[7:0] COMPAUXAOVTH[1:0]

COMPAUXAUVTHREG[15:8]

–

COMPAUXAUVTH[9:2]

COMPAUXAUVTHREG[7:0] COMPAUXAUVTH[1:0]

–

Maxim Integrated │ 179

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

LSB

DIAGNOSTIC THRESHOLD Registers

COMPOPNTHREG[15:8]

COMPOPNTH[9:2]

0x3E

COMPOPNTHREG[7:0]

COMPOPNTH[1:0]

–

COMPAUXROPNTHREG[15:8]

COMPAUXROPNTH[9:2]

0x3F

0x40

0x41

0x42

0x43

(0x44)

0x45

COMPAUXROPNTHREG[7:0] COMPAUXROPNTH[1:0]

COMPAUXAOPNTHREG[15:8]

–

COMPAUXAOPNTH[9:2]

COMPAUXAOPNTHREG[7:0] COMPAUXAOPNTH[1:0]

COMPACCOVTHREG[15:8]

–

COMPACCOVTH[9:2]

COMPACCOVTHREG[7:0]

COMPACCUVTHREG[15:8]

COMPACCUVTHREG[7:0]

BALSHRTTHRREG[15:8]

BALSHRTTHRREG[7:0]

BALLOWTHRREG[15:8]

BALLOWTHRREG[7:0]

BALHIGHTHRREG[15:8]

BALHIGHTHRREG[7:0]

COMPACCOVTH[1:0]

–

COMPACCUVTH[9:2]

COMPACCUVTH[1:0]

–

BALSHRTTHR[13:6]

BALSHRTTHR[5:0]

BALLOWTHR[13:6]

BALLOWTHR[5:0]

BALHIGHTHR[13:6]

BALHIGHTHR[5:0]

CELL DATA Registers

CELL1REG[15:8]

0x47

CELL1[13:6]

CELL1REG[7:0]

CELL1[5:0]

CELL2[5:0]

CELL3[5:0]

CELL4[5:0]

CELL5[5:0]

CELL6[5:0]

CELL7[5:0]

CELL8[5:0]

CELL9[5:0]

–

CELL2REG[15:8]

0x48

CELL2[13:6]

CELL3[13:6]

CELL4[13:6]

CELL5[13:6]

CELL6[13:6]

CELL7[13:6]

CELL8[13:6]

CELL9[13:6]

CELL2REG[7:0]

CELL3REG[15:8]

0x49

CELL3REG[7:0]

CELL4REG[15:8]

0x4A

CELL4REG[7:0]

CELL5REG[15:8]

0x4B

CELL5REG[7:0]

CELL6REG[15:8]

0x4C

CELL6REG[7:0]

CELL7REG[15:8]

(0x4D)

CELL7REG[7:0]

CELL8REG[15:8]

0x4E

CELL8REG[7:0]

CELL9REG[15:8]

0x4F

CELL9REG[7:0]

CELL10REG[15:8]

0x50

CELL10[13:6]

CELL10[5:0]

CELL11[13:6]

CELL11[5:0]

CELL10REG[7:0]

CELL11REG[15:8]

0x51

CELL11REG[7:0]

Maxim Integrated │ 180

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

LSB

CELL12REG[15:8]

CELL12REG[7:0]

CELL13REG[15:8]

CELL13REG[7:0]

CELL14REG[15:8]

CELL14REG[7:0]

BLOCKREG[15:8]

BLOCKREG[7:0]

CELL12[13:6]

0x52

0x53

0x54

0x55

CELL12[5:0]

CELL13[13:6]

CELL13[5:0]

CELL14[13:6]

CELL14[5:0]

VBLOCK[13:6]

VBLOCK[5:0]

–

TOTAL DIAG AUX DATA Registers

TOTALREG[15:8]

0x56

TOTAL[15:8]

TOTALREG[7:0]

TOTAL[7:0]

DIAG1[13:6]

DIAG1REG[15:8]

0x57

DIAG1REG[7:0]

DIAG1[5:0]

DIAG2[5:0]

AUX0[5:0]

AUX1[5:0]

AUX2[5:0]

AUX3[5:0]

AUX4[5:0]

AUX5[5:0]

–

DIAG2REG[15:8]

0x58

DIAG2[13:6]

AUX0[13:6]

AUX1[13:6]

AUX2[13:6]

AUX3[13:6]

AUX4[13:6]

AUX5[13:6]

DIAG2REG[7:0]

AUX0REG[15:8]

0x59

AUX0REG[7:0]

AUX1REG[15:8]

0x5A

AUX1REG[7:0]

AUX2REG[15:8]

0x5B

AUX2REG[7:0]

AUX3REG[15:8]

0x5C

AUX3REG[7:0]

AUX4REG[15:8]

0x5D

AUX4REG[7:0]

AUX5REG[15:8]

0x5E

AUX5REG[7:0]

SCAN SETTINGS Registers

MINMAX-

POL

POLARITYCTRL[15:8]

–

POLARITY[14:9]

POLARITY[8:1]

0x5F

POLARITYCTRL[7:0]

AUXREFCTRL[15:8]

AUXREFCTRL[7:0]

AUXTIMEREG[15:8]

AUXTIMEREG[7:0]

–

0x60

0x61

AUXREFSEL[5:4]

AUXREFSEL[3:0]

AUXTIME[9:8]

–

AUXTIME[7:0]

ADCZSF-

SEN

ADC-

CALEN

COMPAC-

CEN

ACQCFG[15:8]

FOSR[1:0]

THRMMODE[1:0]

–

0x62

0x63

ACQCFG[7:0]

–

BALSWDLY[15:8]

BALSWDLY[7:0]

CELLDLY[7:0]

SWDLY[7:0]

Maxim Integrated │ 181

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

LSB

SCAN CONTROL Registers

MEASUREEN1[15:8]

0x64

–

BLOCKEN

CELLEN[14:9]

CELLEN[8:1]

MEASUREEN1[7:0]

SCANI-

IRINIT

MEASUREEN2[15:8]

–

0x65

MEASUREEN2[7:0]

–

AUXEN[5:4]

AUTO-

DATARDY BALSW-

DIS

AUXEN[3:0]

SCAN- SCANTIME-

DONE

ALRTFILT- AMEND-

SCAN-

CFG[2]

SCANCTRL[15:8]

RDFILT

OUT

SEL

FILT

0x66

ALTMUX- SCAN-

SEL MODE

SCANCTRL[7:0]

SCANCFG[1:0]

OVSAMPL[2:0]

SCAN

DIAGNOSTIC SETTINGS Registers

ADCT-

STEN

ADCTEST1AREG[15:8]

–

ADCTEST1A[11:8]

0x67

ADCTEST1AREG[7:0]

ADCTEST1BREG[15:8]

ADCTEST1BREG[7:0]

ADCTEST2AREG[15:8]

ADCTEST2AREG[7:0]

ADCTEST2BREG[15:8]

ADCTEST2BREG[7:0]

ADCTEST1A[7:0]

–

ADCTEST1B[11:8]

ADCTEST2A[11:8]

ADCTEST2B[11:8]

0x68

0x69

0x6A

ADCTEST1B[7:0]

–

ADCTEST2A[7:0]

–

ADCTEST2B[7:0]

DIAGNOSTIC CONTROL Registers

MUXDIAG-MUXDIAG- MUXDIA-

DIAGCFG[15:8]

CTSTDAC[3:0]

DIAGSEL2[3:0]

CTSTSRC

BUS

PAIR

GEN

0x6B

DIAGCFG[7:0]

DIAGSEL1[3:0]

CEL-

CTSTCFG[15:8]

LOPNDI-

AGSEL

CTSTEN[14:8]

CTSTEN[7:0]

0x6C

CTSTCFG[7:0]

AUXTSTCFG[15:8]

AUXTSTCFG[7:0]

DIAGGENCFG[15:8]

DIAGGENCFG[7:0]

–

0x6D

0x6E

AUXTSTEN[5:4]

–

AUXTSTEN[3:0]

AUXDIAGSEL[2:0]

–

CELL-BALANCING Registers

CBRE-

START

BALSWCTRL[15:8]

–

BALSWEN[14:9]

BALSWEN[8:1]

0x6F

BALSWCTRL[7:0]

BALEXP1[15:8]

0x70

–

CBEXP1[9:8]

CBEXP2[9:8]

BALEXP1[7:0]

CBEXP1[7:0]

BALEXP2[15:8]

0x71

–

BALEXP2[7:0]

CBEXP2[7:0]

Maxim Integrated │ 182

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

LSB

BALEXP3[15:8]

BALEXP3[7:0]

–

CBEXP3[9:8]

CBEXP4[9:8]

CBEXP5[9:8]

CBEXP6[9:8]

CBEXP7[9:8]

CBEXP8[9:8]

CBEXP9[9:8]

CBEXP10[9:8]

CBEXP11[9:8]

CBEXP12[9:8]

CBEXP13[9:8]

CBEXP14[9:8]

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

CBEXP3[7:0]

BALEXP4[15:8]

BALEXP4[7:0]

–

CBEXP4[7:0]

BALEXP5[15:8]

BALEXP5[7:0]

–

CBEXP5[7:0]

BALEXP6[15:8]

BALEXP6[7:0]

–

CBEXP6[7:0]

BALEXP7[15:8]

BALEXP7[7:0]

–

CBEXP7[7:0]

BALEXP8[15:8]

BALEXP8[7:0]

–

CBEXP8[7:0]

BALEXP9[15:8]

BALEXP9[7:0]

–

CBEXP9[7:0]

BALEXP10[15:8]

BALEXP10[7:0]

BALEXP11[15:8]

BALEXP11[7:0]

BALEXP12[15:8]

BALEXP12[7:0]

BALEXP13[15:8]

BALEXP13[7:0]

BALEXP14[15:8]

BALEXP14[7:0]

BALAUTOUVTHR[15:8]

–

CBEXP10[7:0]

–

CBEXP11[7:0]

–

CBEXP12[7:0]

–

CBEXP13[7:0]

–

CBEXP14[7:0]

CBUVTHR[13:6]

0x7E

0x7F

0x80

CBUVMIN-

CELL

CBNTFYCFG[1:0]

CBCALDLY[2:0]

CBIIRINIT HOLDSHDNL[1:0]

BALAUTOUVTHR[7:0]

CBUVTHR[5:0]

–

BALDLYCTRL[15:8]

BALDLYCTRL[7:0]

BALCTRL[15:8]

–

CBACTIVE[1:0]

CBDUTY[3:0]

CBACTIVE_M1[1:0] CBUNIT[1:0]

CBMODE[2:0]

CBDONE- CBTEM-

ALRTEN PEN

CBCNTR[1:0]

CBTIMER[7:0]

CBUVSTAT[14:9]

CBUVSTAT[8:1]

BALCTRL[7:0]

CBMEASEN[1:0]

CBTIMER[9:8]

BALSTAT[15:8]

BALSTAT[7:0]

0x81

0x82

BALUVSTAT[15:8]

BALUVSTAT[7:0]

CBACTIVE_M2[1:0]

Maxim Integrated │ 183

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADDRESS

NAME

MSB

CBACTIVE_M3[1:0]

LSB

DATAR-

DY_M

BALDATA[15:8]

–

0x83

BALDATA[7:0]

–

CBSCAN

ROM SUPPORT Registers

ID1[15:8]

0x8C

DEVID[15:8]

DEVID[7:0]

DEVID[31:24]

DEVID[23:16]

OTP2[15:8]

OTP2[7:0]

ID1[7:0]

ID2[15:8]

0x8D

ID2[7:0]

OTP2[15:8]

0x8E

OTP2[7:0]

OTP3[15:8]

0x8F

OTP3[15:8]

OTP3[7:0]

OTP4[15:8]

0x90

OTP4[15:8]

OTP4[7:0]

OTP5[15:8]

0x91

OTP5[15:8]

OTP5[7:0]

OTP6[15:8]

0x92

OTP6[15:8]

OTP6[7:0]

OTP7[15:8]

0x93

OTP7[15:8]

OTP7[7:0]

OTP8[15:8]

0x94

OTP8[15:8]

OTP8[7:0]

OTP9[15:8]

0x95

OTP9[15:8]

OTP9[7:0]

OTP10[15:8]

0x96

OTP10[15:8]

OTP10[7:0]

OTP11[15:8]

OTP11[7:0]

ROMCRC[7:0]

OTP12[7:0]

OTP10[7:0]

OTP11[15:8]

0x97

OTP11[7:0]

OTP12[15:8]

0x98

OTP12[7:0]

Maxim Integrated │ 184

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Register Details

VERSION (0ꢀ00)

VERSION is a read-only-accessible register that returns information on the device.

BIT

Field

15

14

13

12

11

10

9

1

8

0

MOD[11:4]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

MOD[3:0]

VER[3:0]

0x05

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Device Model Number:

0x853 = MAX17853

Read only.

MOD

VER

15:4

Si Version:

0x05

3:0

Read only.

ADDRESS (0ꢀ01)

ADDRESS is a read-/write-accessible register that sets the first, last, and device address used by a device in a UART

chain (UARTSEL = 1).

This register has no effect on a device operating in SPI mode (UARTSEL = 0).

BIT

15

14

13

12

11

10

9

8

ADDRUN-

LOCK

Field

BA[4:0]

TA[4:3]

Reset

0b1

0b0_0000

Write, Read, Ext

0b0_0000

Write, Read,

Ext

Access Type

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

TA[2:0]

DA[4:0]

Reset

0b0_0000

Write, Read, Ext

0b0_0000

Write, Read, Ext

Access Type

Maxim Integrated │ 185

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

UART Device Address Unlock:

0 = Normal operation (following HELLOALL)

1 = Disable write-protection of device address DA[4:0], allowing resends of

HELLOALL to reassign device addresses without POR (also POR default).

Cleared only by HELLOALL command (writes to zero are ignored).

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

ADDRUNLOCK

15

Note: This bit should normally be written to zero when populating BA and

TA content, it should only be necessary to set this bit if the user believes the

original DA content populated by the HELLOALL command is corrupted.

Bottom-Device Address in a UART Chain:

Address of the device at the bottom of the daisy-chain.

If the host sends an initial address other than 0x00 in the HELLOALL

command through the UART Up path (assign/increment), the host must write

that bottom address (as well as the expected top address) to all devices in the

daisy-chain with a WRITEALL command to this bitﬁeld.

READALL commands and Alert Packets require that BA[4:0], TA[4:0], and

DA[4:0] must be correct for the data-check and PEC features to function as

intended.

BA

14:10

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

Top-Device Address in a UART Chain:

Address of the device connected to the top of the daisy-chain.

If the host sends an initial address in the HELLOALL command through the

UART DOWN path (assign/decrement), then the host must write that top

address (as well as the expected bottom address) to all devices in the daisy-

chain with a WRITEALL command to this bitﬁeld.

TA

9:5

READALL commands and Alert Packets require that BA[4:0], TA[4:0], and

DA[4:0] must be correct for the data-check and PEC features to function as

intended.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

Device Address:

Device address written only by the HELLOALL command as it propagates

through the daisy-chain. If HELLOALL is issued through the UART Up path,

this bitﬁeld is accepted and automatically incremented by each device. If

HELLOALL is issued through the UART DOWN path, this bitﬁeld is accepted

and automatically decremented by each device.

The host must choose an initial (bottom) address 0x00 or greater and ensure

the resulting top address not exceed the maximum address of 0x1F during the

propagation of the HELLOALL command through the Up path. Likewise, the

host must choose an initial (top) address (0x1F or lower) and ensure that the

resulting bottom address is 0x00 or greater after propagation of the

HELLOALL command through the DOWN path.

DA

4:0

Writing has no eﬀect, only a HELLOALL command executed while

ADDRUNLOCK = 1 updates this content.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

Maxim Integrated │ 186

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

STATUS1 (0ꢀ02)

STATUS1 is a read-/write-accessible register that relates the current status of the device. STATUS1 also contains

summary information on STATUS2, STATUS3, and FMEA registers, and other selected registers, indicating if additional

readback checks are required.

BIT

15

14

ALRTRST

0b1

13

12

11

10

9

8

ALRT-

MSMTCH

ALRTCEL-

LOVST

ALRTCEL-

LUVST

ALRT-

BLKOVST

ALRTBLKU-

VST

ALR-

TAUXOVST

Field

ALRTSCAN

0b0

Reset

0b0

Write 0 to

Clear, Read

Access Type

Read Only

BIT

7

6

5

4

3

2

1

0

ALRTAUXU-

VST

ALRTIN-

TRFC

ALRT-

FMEA2

ALRT-

FMEA1

Field

–

ALRTPEC

ALRTCAL

ALRTCBAL

Reset

0b0

–

0b0

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Scan-Done Alert:

0 = No measurement requested or measurement in progress (default)

1 = Measurement complete

Cleared if SCANCRTL:SCANDONE is removed.

Read only.

ALRTSCAN

ALRTRST

15

Reset Alert:

Indicates if a power-on-reset (POR) event occurred.

UART users should clear this alert after power on and after a successful

HELLOALL transaction to detect future resets.

SPI users should clear this alert immediately after power on to detect future

resets.

14

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Cell-Voltage-Mismatch Alert:

Indicates V

- V

> V

threshold.

MAX

MIN

MSMTCH

To aid diagnosis, read MINMAXCELL for detailed information on which chan-

nels are involved.

Cleared at next acquisition if the condition is false.

Read only.

ALRTMSMTCH

13

12

Cell-Overvoltage Status-Summary Alert:

Bit-wise logical OR of ALRTOV[14:1] and ALRTCOMPOV[14:1].

To aid diagnosis, read ALRTSUM for information on whether the ADC,

comparator, or both circuits detected the fault.

ALRTCELLOVST

Cleared on next acquisition, if all enabled overvoltage conditions are resolved.

Read only.

Maxim Integrated │ 187

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Undervoltage Status-Summary Alert:

Bit-wise logical OR of ALRTUV[14:1] and ALRTCOMPUV[14:1].

To aid diagnosis, read ALRTSUM for information on whether the ADC,

comparator, or both circuits detected the fault.

ALRTCELLUVST

11

Cleared on next acquisition, if all enabled undervoltage conditions are resolved.

Read only.

Block-Overvoltage Status Alert:

Indicates if the latest block-voltage measurement exceeded the threshold set

by BLKOVTHSET.

Cleared on next Block-voltage acquisition, if condition is resolved.

Read only.

ALRTBLKOVST

ALRTBLKUVST

10

9

Block-Undervoltage Status Alert:

Indicates if the latest block-voltage measurement was below the threshold set

by BLKUVTHSET.

Cleared on next block-voltage acquisition, if condition is resolved.

Read only.

Auxiliary-Overvoltage (Cold) Status-Summary Alert:

Logical OR of ALRTAUXOV[5:0] and ALRTCOMPAUXOV[5:0] auxiliary alerts.

To aid diagnosis, read ALRTSUM for information on whether the ADC,

comparator, or both circuits detected the fault.

Cleared on next acquisition, if all enabled overvoltage conditions are resolved.

Read only.

ALRTAUXOVST

ALRTAUXUVST

8

7

Auxiliary-Undervoltage (Hot) Status-Summary Alert:

Logical OR of ALRTAUXUV[5:0] and ALRTCOMPAUXUV[5:0] auxiliary alerts.

To aid diagnosis, read ALRTSUM for information on whether the ADC,

comparator, or both circuits detected the fault.

Cleared on next acquisition, if all enabled undervoltage conditions are resolved.

Read only.

Packet-Error Check (PEC) Alert:

Indicates a received UART/SPI character/transaction contained a PEC/CRC

error and was ignored as a result. Logical OR of (ALRTPECUP, ALRTPECDN,

SPICRCERR).

Cleared if component alerts are resolved in STATUS2:ALRTPECUP/DN

(UART), or STATUS2:ALRTSPI (SPI). See component bitﬁeld descriptions for

details.

ALRTPEC

5

Note: In UARTSEL = 0 (SPI mode), the SPICRCERR bit only appears in the

SPI transaction as STAT4 (DO[31]), it does not activate STATUS2:ALRTSPI,

though it is cleared by writing STATUS2:ALRTSPI to zero.

Read only.

Maxim Integrated │ 188

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Interface-Speciﬁc Error Alert:

Indicates that an error speciﬁc to the selected interface (UART or SPI user

interface) has occurred.

For UART operation, this is the bitwise OR of ALRTMANUP/DN,

ALRTPARUP/DN, ALRTDUALART, and ALRTRJCT.

For SPI operation, this is the bitwise OR of ALRTSPI, ALRTSCLKERR,

ALRTOSC3, ALRTINTBUS, and ALRTRJCT.

ALRTINTRFC

4

ALRTPEC is common to both UART and SPI interfaces and holds a dedi-

cated position in the status registers (assertion of ALRTPEC not does assert

ALRTINTRFC).

If this alert bit is set, the speciﬁc error(s) can be read and cleared using the

STATUS2 register.

Calibration-Fault Alert:

Logical OR of all calibration alerts (ALRTCALOSADC, ALRTCALOSR,

ALERTCALOSTHRM, ALRTCALGAINP, and ALRTCALGAINR).

Cleared if component alerts are resolved in ALRTSUM. See ALRTSUM and

ALRTIRQEN for details.

ALRTCAL

3

Read only.

Note: If a calibration error occurs during an automated cell balancing or

discharge operation, the operation ends and issues CBACTIVE = 11 and

ALRTCBCAL, notifying the user of the termination.

Cell-Balancing Status Alert:

0 = Cell balancing inactive/normal

1 = Cell balancing complete/fault

Logical OR of all enabled/unmasked cell-balancing alerts (ALRTCBTIMEOUT,

ALRTCBTEMP, ALRTCBCAL, ALRTCBNTFY, and ALRTCBDONE).

Cleared if component alerts are resolved in STATUS3. See STATUS3 and

ALRTIRQEN for details.

ALRTCBAL

2

Read only.

FMEA2 Condition Summary Alert:

Bit-wise logical OR of FMEA2[15:0].

Read only.

ALRTFMEA2

ALRTFMEA1

1

0

FMEA1 Condition Summary Alert:

Bit-wise logical OR of FMEA1[15:0].

Read only.

Maxim Integrated │ 189

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

STATUS2 (0ꢀ03)

STATUS2 is a read-/write-accessible register that contains summary information on alerts related to interface and

communication faults.

BIT

15

14

13

12

11

10

9

8

–

ALRTPE-

CUP

ALRTP-

ECDN

ALRTMAN-

UP

ALRT-

MANDN

ALRTPA-

RUP

ALRT-

PARDN

ALRTDU-

ALUART

Field

Reset

0b0

Write 0 to

Access Type

Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read

BIT

Field

7

6

5

4

3

–

2

–

1

–

0

ALRTSCLK-

ERR

ALRTINT-

BUS

ALRTSPI

0b0

ALRTOSC3

0b0

ALRTRJCT

0b0

Reset

0b0

Write, Read, Write, Read, Write, Read, Write, Read,

Ext Ext Ext Ext

Write 0 to

Clear, Read

Access Type

BITFIELD

BITS

DESCRIPTION

UART Up-Interface PEC Alert:

Indicates that a character/transaction recieved by the UART Up interface

contained a PEC error and was ignored as a result.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

ALRTPECUP

15

Applies only to parts operating using the UART interface (UARTSEL = 1).

PEC is not used in SPI mode (SPI CRC checking is reported and managed

directly through ALRTPEC and ALRTSPI, respectively).

UART Down-Interface PEC Alert:

Indicates that a character/transaction recieved by the UART Down interface

contained a PEC error and was ignored as a result.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Applies only to parts operating using the dual-UART interface (UARTSEL = 1,

UARTCFG = 11); not used in SPI mode.

ALRTPECDN

ALRTMANUP

ALRTMANDN

14

13

12

UART Up-Interface Manchester-Encoding Error:

Indicates that a character received by the UART Up interface (through RXL)

contained a Manchester error.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Applies only to parts operating using the UART interface (UARTSEL = 1).

Manchester encoding is not used in SPI mode.

UART Down-Interface Manchester-Encoding Error:

Indicates that a character received by the UART down interface (through

RXU) contained a Manchester error.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Applies only to parts operating using the dual-UART interface (UARTSEL = 1,

UARTCFG = 11). Manchester encoding is not used in SPI mode.

Maxim Integrated │ 190

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

UART Up-Interface Parity Error:

Indicates that a character received by the UART Up interface (through RXL)

contained a parity error.

ALRTPARUP

11

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Applies only to parts operating using the UART interface (UARTSEL = 1). Par-

ity checking is not used in SPI mode.

UART Down-Interface Parity Error:

Indicates that a character received by the UART Down interface (through

RXU) contained a parity error.

ALRTPARDN

10

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Applies only to parts operating using the dual-UART interface (UARTSEL = 1,

UARTCFG = 11). Parity checking is not used in SPI mode.

Dual-UART Fault Alert:

0 = No dual-UART fault detected

1 = Invalid dual-UART command received

ALRTDUALUART indicates that one or more of the following conditions

occurred:

A WRITEDEVICE or WRITEALL command sent through a path not conﬁgured

as host was ignored (only the host path accepts writes).

An UPHOST command was issued and ignored on the downstream UART

path.

ALRTDUALUART

9

A DOWNHOST command was issued and ignored on the upstream UART

path.

These conditions are checked only when UARTCFG = DUAL (11).

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

SPI Error Summary Alert:

Indicates that one or more of the following SPI transaction errors have

occured: R/WB ! = R/WB’ (i.e., DI[31] ! = DI[3], RW_ERR)D [15:0] ! =

IN

0x0000 in read mode (RW_ERR) transaction timeout (TO_ERR). Specific

error-condition breakouts are reported as STAT[4:0] (DO[31:27]) as part of all

SPI transactions.

All existing SPI CRC_ERR, RW_ERR, and TO_ERR, alerts be cleared by

writing this bit to logic zero. Writing to a logic one has no eﬀect.

Applies only to parts operating using the SPI interface (UARTSEL = 0).

Note: The SPI CRC_ERR condition is reported using the dedicated

STATUS1:ALRTPEC bit (read only), but is cleared using this bitﬁeld (i.e., the

CRC_ERR condition is not reported in ALRTSPI). To clear ALRTPEC, it is

necessary to write ALRTSPI to zero even if it is already zero (if no other SPI

errors are reported). SPI clock issues covered by SPI CLK_ERR are broken

out, reported, and cleared individually (see ALRTSCLKERR, ALRTOSC3, and

ALRTINTBUS for details).

ALRTSPI

7

Maxim Integrated │ 191

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

SPI SCLK-Error Alert:

Indicates that an SPI transaction was received that was not exactly 32 SCLK

cycles in length.

This error condition is one of three reported as STAT1 (DO28) as part of all

SPI transactions.

ALRTSCLKERR

6

Cleared by writing this bit to logic zero.

Writing to a logic one has no eﬀect.

Applies only to parts operating using the SPI interface (UARTSEL = 0).

16MHz Oscilator-Fault Alert:

Indicates that the 16MHz oscillator frequency is not within ±5% of its expected

value when measured against the 32kHz oscillator. The status is updated every

two cycles (32kHz). Required/supported only in SPI mode (UARTSEL = 0).

While it is possible for the SPI interface to continue to function under drift-alert

conditions, it does not function if the 16MHz oscillator is dead or extremely fast/

slow.

ALRTOSC3

5

This error condition is one of three reported as STAT1 (DO28) as part of all

SPI transactions.

Cleared only by writing to logic zero if the condition has been resolved.

Writing to a logic one has no eﬀect.

SPI Internal Bus-Transaction Failure:

Indicates that an SPI read or write transaction was not correctly passed

across the internal memory bus. This can happen if the 16MHz oscillator

(or branch) clocking the internal bus is dead, intermittent, or severely out of

its speciﬁed frequency range. May be accompanied by ALRTOSC1, 2, or 3

alerts.

ALRTINTBUS

4

This error condition is one of three reported as STAT1 (DO28) as part of all

SPI transactions.

Cleared by writing this bit to logic zero.

Writing to a logic one has no eﬀect.

Applies only to parts operating using the SPI interface (UARTSEL = 0).

Maxim Integrated │ 192

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Protected Command-Rejection Alert:

0 = Normal operation

1 = Invalid command rejected during an active scan or cell-balancing operation.

ALRTRJCT is issued when an invalid write to a protected register is received

during an active/gating scan or cell-balancing operation. The invalid command

should be ignored.

ALRTRJCT

0

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

STATUS3 (0ꢀ04)

STATUS3 is a read-/write-accessible register that contains summary information on alerts related to automated cell-

balancing operations.

BIT

15

14

13

12

11

10

9

–

8

–

ALRTCB-

TIMEOUT

ALRTCB-

TEMP

ALRTCB-

CAL

ALRT-

CBNTFY

ALRTCB-

DONE

Field

–

Reset

0b0

–

Write 0 to

Access Type

–

Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read

BIT

Field

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Timeout Alert:

0 = Cell balancing disabled or in progress

1 = Cell-balancing operation halted due to a timeout fault

ALRTCBTIMEOUT is issued when a discharge, or automated cell-balancing

operation is halted due to an internal logic fault condition triggering the watch-

dog timer.

ALRTCBTIMEOUT

15

This alert is automatically enabled if CBTODIS = 0.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Cell-Balancing Thermal Alert:

0 = Cell balancing disabled or in progress

1 = Cell-balancing operation halted due to a thermal fault

ALRTCBTEMP is issued when a manual, discharge, or automated cell-

balancing operation is halted due to a thermal-fault condition.

This alert is automatically enabled if CBTEMPEN = 1.

Cleared only by writing to logic zero after the automated cell-balancing

operation that generated the alert has been completed or otherwise ended.

Writing to a logic one has no eﬀect.

ALRTCBTEMP

14

Maxim Integrated │ 193

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Calibration Alert:

0 = Cell balancing disabled or in progress

1 = Cell-balancing operation halted due to a calibration fault

ALRTCBCAL is issued when a discharge, or automated cell-balancing

operation is halted due to an embedded calibration fault condition.

Cleared only by writing to logic zero after the automated cell-balancing

operation that generated the alert has been completed or otherwise ended.

Writing to a logic one has no eﬀect.

ALRTCBCAL

13

Cell-Balancing Notiﬁcation Alert:

0 = No cell-balancing progression notiﬁcation present

1 = Cell-balancing progression notiﬁcation

ALRTCBNTFY is periodically issued during discharge and automated cell-

balancing operations to conﬁrm normal progression of the operation.

This alert is enabled and conﬁgured by CBNTFYCFG.

Cleared only by writing to logic zero.

ALRTCBNTFY

12

Writing to a logic one has no eﬀect.

Cell-Balancing-Complete Alert:

0 = Cell balancing disabled or in progress

1 = Cell-balancing operation complete

ALRTCBDONE is issued when a manual, discharge, or automated cell-

balancing operation completes due to a normal timed or undervoltage exit

condition.

ALRTCBDONE

11

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

FMEA1 (0ꢀ05)

FMEA1 is a read-/write-accessible register that relates current information on possible fault conditions.

BIT

15

14

13

12

11

10

9

8

ALRTCOM- ALRTCOM- ALRTCOM- ALRTCOM-

ALRTVD-

DL3

ALRTVD-

DL2

Field

ALRTOSC1 ALRTOSC2

MSEU1

0b0

MSEL1

0b0

MSEU2

0b0

MSEL2

0b0

Reset

0b0

Write 0 to

Clear, Read Clear, Read

Write 0 to

Clear, Read Clear, Read

Write 0 to

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

0

ALRTVD-

DL1

ALRT-

GNDL3

ALRT-

GNDL2

ALRT-

GNDL1

ALRTHVH-

DRM

ALRTBALS-

WSUM

ALRTHVUV

ALRTHVOV

Reset

0b0

Write 0 to

Write, Read,

Ext

Access Type

Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read

Maxim Integrated │ 194

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

32kHz Oscilator-Fault Alert:

Indicates that the 32kHz frequency is not within ±5% of its expected value

when measured against the 16MHz oscillator. The status is updated every two

cycles (32kHz).

ALRTOSC1

15

Cleared only by writing to logic zero if the condition has been resolved.

Writing to a logic one has no eﬀect.

32kHz Oscilator-Fault Alert (Redundant):

Identical to ALRTOSC1 (redundant alert with independent latch).

Cleared only by writing to logic zero if the condition has been resolved.

Writing to a logic one has no eﬀect.

ALRTOSC2

14

13

UART Upper-Port Single-Ended Alert:

Indicates that the UART has placed the upper-port receiver in single-ended

mode based on the ﬁrst preamble received after POR.

This bit is not set until the ALRTRST bit is cleared.

Read only.

ALRTCOMMSEU1

UART Lower-Port Single-Ended Alert:

Indicates that the UART has placed the lower-port receiver in single-ended

mode based on the ﬁrst preamble received after POR.

This bit is not set until the ALRTRST bit is cleared.

Read only.

ALRTCOMMSEL1

12

UART Upper-Port Single-Ended Redundant Alert:

Same as ALRTCOMMSEU1 (redundant alert) except that it sets before

ALRTRST is cleared.

ALRTCOMMSEU2

ALRTCOMMSEL2

11

10

Read only.

UART Lower-Port Single-Ended Redundant Alert:

Same as ALRTCOMMSEL1 (redundant alert) except that it sets before

ALRTRST is cleared.

Read only.

V

Fault Alert:

DDL3

Indicates V

< V

. This bit is not set until the ALRTRST bit is

DDL3

VDDL_OC

ALRTVDDL3

ALRTVDDL2

ALRTVDDL1

ALRTGNDL3

9

8

7

6

cleared.

Cleared only by writing to logic zero if condition is resolved.

Writing to a logic one has no eﬀect.

V

Fault Alert:

DDL2

Indicates V

cleared.

< V

. This bit is not set until the ALRTRST bit is

DDL2

VDDL_OC

Cleared only by writing to logic zero if condition is resolved.

Writing to a logic one has no eﬀect.

V

Fault Alert:

DDL1

Indicates V

cleared.

< V

. This bit is not set until the ALRTRST bit is

DDL1

VDDL_OC

Cleared only by writing to logic zero if condition is resolved.

Writing to a logic one has no eﬀect.

GNDL3 Fault Alert:

Indicates an open-circuit on the GNDL3 pin. This bit is not set until the

ALRTRST bit is cleared.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

Maxim Integrated │ 195

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

GNDL2 Fault Alert:

Indicates an open-circuit on the GNDL2 pin. This bit is not set until the

ALRTRST bit is cleared.

ALRTGNDL2

5

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

GNDL1 Fault Alert:

Indicates an open-circuit on the GNDL1 pin. This bit is not set until the

ALRTRST bit is cleared.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

ALRTGNDL1

ALRTHVUV

4

3

2

HV-Undervoltage Fault Alert:

Indicates V

< V

. This bit is not set until the ALRTRST bit is cleared.

HV

HVUV

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

HV-Headroom Fault Alert:

Indicates that V

- V

was too low during the acquisition for an

HV

TOPCELL1/2

ALRTHVHDRM

accurate measurement. Checked only during measurement activity.

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

HV-Overvoltage Fault Alert:

Indicates that V

is cleared.

Cleared only by writing to logic zero.

- V

> V

. This bit is not set until the ALRTRST bit

HV

DCIN

HVOV

ALRTHVOV

1

0

Writing to a logic one has no eﬀect.

Balance-Switch Fault-Alert Summary:

Bit-wise logical OR of ALRTBALSW[13:0].

Updated at the end of a BALSWDIAG scan.

Cleared if all enabled ALRTBALSW alerts are resolved or by writing to logic

zero.

ALRTBALSWSUM

Writing to a logic one has no eﬀect.

FMEA2 (0ꢀ06)

FMEA1 is a read-/write-accessible register that relates current information on possible fault conditions.

BIT

Field

Reset

15

ALRTUSER

0b0

14

13

12

ALRTTEMP

0b0

11

10

9

–

8

–

ALRTDCIN- ALRTAUX-

ALRTSCAN-

TIMEOUT

–

MUX

0b0

PRTCTSUM

0b0

–

Write 0 to

Clear, Read

Write 0 to

Clear, Read

Access Type Write, Read

Read Only

–

BIT

Field

Reset

7

–

6

–

5

–

4

–

3

2

1

0

ALRTAD-

CZS

ALRTAD-

CFS

ALRTCOM- ALRTCOM-

PACCOV

PACCUV

0b0

Maxim Integrated │ 196

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Write 0 to

Access Type

BITFIELD

–

Clear, Read Clear, Read Clear, Read Clear, Read

BITS

DESCRIPTION

User-Deﬁned Alert (Diagnostic):

Used to test the alert interface. Asserted by writing to logic one. The resulting

alert is relayed through the alert interface/UART DCByte/SPI ALERT bit and

can be read back using the FMEA2 command.

ALRTUSER

15

Cleared by writing to logic zero (default).

DCIN MUX-Fault Alert:

0 = No DCINMUX fault detected (default)

1 = DCINMUX fault detected

A high condition indicates the enabled DCINMUX is not functioning properly

in a Flex Pack application. Connections will be made by diodes; performance

may be impacted and/or other related faults issued.

This alert is enabled if the DCINMUX is enabled (FLXPACKEN = 1), after

STATUS1:ALRTRST has been cleared. The PACKCFG register makes

selections on which SW[n] input is used for the DCIN supply and which C[n] is

used for the VBLK measurements in Flex Pack applications.

Cleared only by writing to logic zero if condition has been resolved.

Writing to a logic one has no eﬀect.

ALRTDCINMUX

14

Auxiliary-Protection Fault-Alert Summary:

Logical OR of all enabled ALRTAUXPRTCT bits, indicating one or more

AUXINn inputs is in a fault mode with input protection engaged. These alerts

are enabled for all AUXn/GPIOn pins currently conﬁgured as AUXINn inputs.

This bit is only cleared when the ALRTAUXPRTCT register is cleared (see the

ALRTAUXPRTCT register for speciﬁc details).

ALRTAUXPRTCTSUM

13

12

11

Read only.

Die Overtemperature-Fault Alert:

Indicates that T

> 115°C (120°C typical).

DIE

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

If a thermal alert occurs during an automated cell-balancing or discharge

operation, the operation ends and issues CBACTIVE = 11 and ALRTCBTEMP,

notifying the user of the termination.

ALRTTEMP

Scan-Timeout Alert:

0 = Scan not requested or progressing normally (default)

1 = Scan operation halted due to timeout fault

ALRTSCANTIMEOUT is a copy of SCANTIMEOUT.

This alert is automatically enabled if SCANTODIS = 0.

Cleared only by writing SCANCTRL:SCANTIMEOUT to zero.

Read only.

ALRTSCANTIMEOUT

Maxim Integrated │ 197

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

ADC Zero-Scale BIST Alert:

0 = ADC zero-scale BIST passed

1 = ADC zero-scale BIST failed

Reports the result of the ADC zero-scale BIST measurement performed

during the last acquisition. Tests the SAR ADC DAC, comparator, and logic

components. Enabled using ADCZSFSEN.

Cleared only by writing to logic zero.

ALRTADCZS

3

Writing to a logic one has no eﬀect.

Note: If detailed results are desired, use the zero-scale ADC detailed

diagnostic.

ADC Full-Scale BIST Alert:

0 = ADC full-scale BIST passed

1 = ADC full-scale BIST failed

Reports the result of the ADC full-scale BIST measurement performed during

the last acquisition. Tests the SAR ADC DAC, comparator, and logic

components. Enabled using ADCZSFSEN.

Cleared only by writing to logic zero.

ALRTADCFS

2

Writing to a logic one has no eﬀect.

Note: If detailed results are desired, use the full-scale ADC diagnostic.

End-of-Sequence Comparator-Accuracy Diagnostic Overvoltage Alert:

0 = Comparator accuracy OV test passed

1 = Comparator accuracy OV test failed

ALRTCOMPACCOV

1

0

Result of the end-of-sequence comparator-accuracy overvoltage diagnostic if

enabled (SCANCFG = 001 or 010, and COMPACCEN = 1).

Cleared only by writing to logic zero.

Writing to a logic one has no eﬀect.

End-of-Sequence Comparator-Accuracy Diagnostic Undervoltage Alert:

0 = Comparator accuracy UV test passed

1 = Comparator accuracy UV test failed

Result of the end-of-sequence comparator-accuracy undervoltage diagnostic

if enabled (SCANCFG = 001 or 010, and COMPACCEN = 1).

Cleared only by writing to logic zero.

ALRTCOMPACCUV

Writing to a logic one has no eﬀect.

ALRTSUM (0ꢀ07)

ALRTSUM is a read-accessible register that relates added detailed information on the current status of the device,

breaking out several summary bits in STATUS1.

BIT

15

14

13

12

11

10

9

8

ALRTAD-

COVST

ALRTCOM-

POVST

ALRTAD-

CUVST

ALRTCOM-

PUVST

ALRTAD-

ALRTCOM-

ALRTAD-

ALRTCOM-

Field

CAUXOVST PAUXOVST CAUXUVST PAUXUVST

Reset

0b0

Access Type

Read Only

BIT

7

6

5

4

3

2

1

0

ALRTCALO-

SADC

ALRT-

CALOSR

ALRTCALO- ALRTCAL-

STHRM GAINP

ALRTCAL-

GAINR

Field

–

Maxim Integrated │ 198

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Reset

–

0b0

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell ADC-Overvoltage-Alert Status Summary:

Bit-wise logical OR of ALRTOV[14:1], based on ADC measurements.

ALRTADCOVST

15

Cleared on next acquisition; if all enabled, overvoltage conditions are

resolved.

Read only.

Comparator Cell-Overvoltage-Alert Status Summary:

Bit-wise logical OR of ALRTCOMPOV[14:1], based on redundant comparator

monitoring.

Cleared on next acquisition, if all enabled overvoltage conditions are resolved.

Read only.

ALRTCOMPOVST

ALRTADCUVST

14

13

12

11

10

9

Cell ADC-Undervoltage-Alert Status Summary:

Bit-wise logical OR of ALRTUV[14:1], based on ADC measurements.

Cleared on next acquisition, if all enabled undervoltage conditions are resolved.

Read only.

Comparator Cell-Undervoltage-Alert Status Summary:

Bit-wise logical OR of ALRTCOMPUV[14:1], based on redundant comparator

monitoring.

Cleared on next acquisition, if all enabled undervoltage conditions are resolved.

Read only.

ALRTCOMPUVST

ALRTADCAUXOVST

Auxiliary ADC-Overvoltage (Cold)-Alert Status Summary:

Logical OR of ALRTAUXOV[5:0], based on ADC measurements.

Cleared on next acquisition, if all enabled overvoltage conditions are resolved.

Read only.

Comparator Auxiliary-Overvoltage (Cold)-Alert Status Summary:

Logical OR of ALRTCOMPAUXOV[5:0], based on redundant comparator

monitoring.

Cleared on next acquisition, if all enabled overvoltage conditions are resolved.

Read only.

ALRTCOMPAUXOVST

ALRTADCAUXUVST

ALRTCOMPAUXUVST

Auxiliary ADC-Undervoltage (Hot) Alert:

Logical OR of ALRTAUXUV[5:0], based on ADC measurements.

Cleared on next acquisition, if all enabled undervoltage conditions are resolved.

Read only.

Comparator Auxiliary-Undervoltage (Hot)-Alert Status Summary:

Logical OR of ALRTCOMPAUXUV[5:0], based on redundant comparator

monitoring.

8

Cleared on next acquisition, if all enabled undervoltage conditions are resolved.

Read only.

ADC Oﬀset-Calibration Alert:

0 = ADC oﬀset calibration valid

1 = ADC oﬀset calibration fault

ALRTCALOSADC indicates the ADC oﬀset-calibration operation returned a

result outside expected boundaries.

Cleared when a later calibration operation or write to CALOSADC returns an

expected result.

ALRTCALOSADC

4

Read only.

Maxim Integrated │ 199

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Ramp LSA + ADC Oﬀset-Calibration Alert:

0 = LSA + ADC oﬀset calibration valid

1 = LSA + ADC oﬀset calibration fault

ALRTCALOSR indicates the LSA + ADC oﬀset-calibration operation returned

a result outside expected boundaries.

ALRTCALOSR

3

Cleared when a later calibration operation or write to CALOSR returns an

expected result.

Read only.

ADC Ratiometric Oﬀset-Calibration Alert:

0 = Ratiometric ADC oﬀset calibration valid

1 = Ratiometric ADC oﬀset calibration fault

ALRTCALOSTHRM indicates the ratiometric ADC oﬀset-calibration operation

returned a result outside expected boundaries.

Cleared when a later calibration operation or write to CALOSTHRM returns an

expected result.

ALRTCALOSTHRM

2

1

0

Read only.

Pyramid Gain-Calibration Alert:

0 = Pyramid gain calibration valid

1 = Pyramid calibration fault

ALRTCALGAINP indicates the gain-calibration operation returned a result

outside expected boundaries.

Cleared when a later calibration operation or write to CALGAINP returns an

expected result.

Read only.

ALRTCALGAINP

Ramp Gain-Calibration Alert:

0 = Ramp gain-calibration valid

1 = Ramp-calibration fault

ALRTCALGAINR indicates the gain-calibration operation returned a result

outside expected boundaries.

ALRTCALGAINR

Cleared when a later calibration operation or write to CALGAINR returns an

expected result.

Read only.

ALRTOVCELL (0ꢀ08)

ALRTOVCELL is a read-accessible register that relates current information on cell overvoltage-fault alerts based on

ADC measurements.

BIT

Field

15

–

14

–

13

12

11

10

9

8

ALRTOV[14:9]

Reset

–

0x0000

Access Type

–

Read Only

BIT

Field

7

6

5

4

3

2

1

0

ALRTOV[8:1]

Reset

0x0000

Access Type

Read Only

Maxim Integrated │ 200

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell Overvoltage-Fault Alert:

ALRTOV[n] indicates V

> V

(OVTHSET threshold for POLARITY = 0,

CELLN

OV

ALRTOV

13:0

BIPOVTHSET for POLARITY = 1); evaluated/enabled if OVALRTEN[n] = 1.

Cleared on next acquisition, if the overvoltage condition is resolved.

Read only.

ALRTUVCELL (0ꢀ09)

ALRTOVCELL is a read-accessible register that relates current information on cell undervoltage-fault alerts based on

ADC measurements.

BIT

Field

15

–

14

–

13

12

11

10

9

8

ALRTUV[14:9]

Reset

–

0x0000

Access Type

–

Read Only

BIT

Field

7

6

5

4

3

2

1

0

ALRTUV[8:1]

Reset

0x0000

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell Undervoltage-Fault Alert:

ALRTOV[n] indicates V < V

(UVTHSET threshold for POLARITY = 0,

UV

CELLN

ALRTUV

13:0

BIPUVTHSET for POLARITY = 1); evaluated/enabled if UVALRTEN[n] = 1.

Cleared on next acquisition if the undervoltage condition is resolved.

Read only.

MINMAXCELL (0ꢀ0A)

MINMAX is a read-accessible register that relates the cell locations with the highest and lowest values measured.

BIT

Field

15

–

14

–

13

–

12

–

11

10

9

8

0

MAXCELL[3:0]

Reset

–

0x0

Access Type

–

Read Only

BIT

Field

7

–

6

–

5

–

4

–

3

2

1

MINCELL[3:0]

0x0

Reset

Access Type

Read Only

Maxim Integrated │ 201

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Maximum-Voltage Cell:

Cell number [14:1] of the maximum voltage enabled/observed (for all

CELLENn = 1) in the last scan (SCAN = 1) based on ALU/IIR data as selected

by RDFILT. This bitﬁeld is not updated for data requests made with SCAN = 0.

If multiple cells have the same maximum value, this ﬁeld contains the lowest

cell number reporting that result.

MAXCELL

11:8

Note: This operation works on unipolar or bipolar measurement sets, as

selected by MINMAXPOL. If MINMAXPOL is set so no measurements in the

scan meet the criteria (e.g., MINMAXPOL = 1 (bipolar), but POLARITY[14:1] =

0000h), a result of Fh be returned (indicating no valid result was found).

Read only.

Minimum-Voltage Cell:

Cell number [14:1] of the minimum-cell voltage enabled/observed (for all

CELLENn = 1) in the last scan (SCAN = 1) based on ALU/IIR data as selected

by RDFILT. This bitﬁeld is not updated for data requests made with SCAN = 0.

If multiple cells have the same minimum value, this ﬁeld contains the lowest

cell number reporting that result.

MINCELL

3:0

Note: This operation works on unipolar or bipolar measurement sets, as

selected by MINMAXPOL. If MINMAXPOL is set so no measurements in the

scan meet the criteria (e.g., MINMAXPOL = 1 (bipolar), but POLARITY[14:1] =

0000h), a result of Fh is returned (indicating no valid result was found).

Read only.

ALRTAUXPRTCTREG (0ꢀ0B)

ALRTAUXPRTCT is a read-accessible register that relates current information on auxiliary input-protection fault alerts.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

ALRTAUXPRTCT[5:4]

0x00

ALRTAUXPRTCT[3:0]

0x00

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Maxim Integrated │ 202

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Auxiliary-Protection Fault Alert:

ALRTAUXPRTCT[n] indicates V

> V ; the alert is evaluated/enabled on

AA

AUXINn

each AUXn/GPIOn pin conﬁgured as an auxiliary input (see AUXGPIOCFG).

Once the fault condition is detected on a pin, the AUXINn input switch is disabled to

protect internal circuitry. AUXINn measurements and alerts for that pin will be invalid

until proper operating conditions are restored.

ALRTAUXPRTCT

5:4

Cleared only if the condition is resolved upon a retry, or if the aﬀected pin is no longer

conﬁgured as an auxiliary input (disabling the protection circuit). To retry auxiliary

operation and clear the fault condition, rewrite the desired conﬁguration to the

AUXGPIOCFG register (it is not necessary to toggle the conﬁguration).

Read only.

Auxiliary-Protection Fault Alert:

ALRTAUXPRTCT[n] indicates V

> V ; the alert is evaluated/enabled on

AA

AUX[n]

each AUXn/GPIOn pin conﬁgured as an auxiliary input (see AUXGPIOCFG).

Once the fault condition is detected on a pin, the AUX[n] input switch is disabled to

protect internal circuitry. AUX[n] measurements and alerts for that pin will be invalid

until proper operating conditions are restored.

ALRTAUXPRTCT

3:0

Cleared only if the condition is resolved upon a retry, or if the aﬀected pin is no longer

conﬁgured as an auxiliary input (disabling the protection circuit). To retry auxiliary

operation and clear the fault condition, rewrite the desired conﬁguration to the

AUXGPIOCFG register (it is not necessary to toggle the conﬁguration).

Read only.

ALRTAUXOVREG (0ꢀ0C)

ALRTAUXOV is a read-accessible register that relates current information on auxiliary-overvoltage (cold)-fault alerts.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

ALRTAUXOV[5:4]

0x0

ALRTAUXOV[3:0]

0x0

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Maxim Integrated │ 203

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Auxiliary-Overvoltage (Cold)-Fault Alert:

ALRTAUXOV[n] indicates V

AUXOVALRTEN[n] = 1.

Cleared on next acquisition, if the overvoltage condition is resolved.

Read only.

> V

; evaluated/enabled if

AUXINn

AUXOVTHSET

ALRTAUXOV

5:4

3:0

AuxiliaryOvervoltage (Cold)-Fault Alert:

ALRTAUXOV[n] indicates V

AUXOVALRTEN[n] = 1.

> V

; evaluated/enabled if

AUXINn

AUXOVTHSET

Cleared on next acquisition, if the overvoltage condition is resolved.

Read only.

ALRTAUXUVREG (0ꢀ0D)

ALRTAUXUV is a read-accessible register that relates current information on auxiliary undervoltage fault (hot) alerts.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

ALRTAUXUV[5:4]

0x0

ALRTAUXUV[3:0]

0x0

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary-Undervoltage (Hot)-Fault Alert:

ALRTAUXUV[n] indicates V

AUXUVALRTEN[n] = 1.

Cleared on next acquisition, if the undervoltage condition is resolved.

Read only.

< V

; evaluated/enabled if

AUXINn

AUXUVTHSET

ALRTAUXUV

5:4

Auxiliary-Undervoltage (Hot)-Fault Alert:

ALRTAUXUV[n] indicates V

AUXUVALRTEN[n] = 1.

< V

; evaluated/enabled if

AUXINn

AUXUVTHSET

3:0

Cleared on next acquisition, if the undervoltage condition is resolved.

Read only..

Maxim Integrated │ 204

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ALRTCOMPOVREG (0ꢀ0E)

ALRTCOMPOV is a read-accessible register that relates current information on cell overvoltage-fault alerts based on

the redundant comparator.

BIT

Field

15

–

14

–

13

12

11

10

9

8

ALRTCOMPOV[14:9]

0x0000

Reset

–

Access Type

–

Read Only

BIT

Field

7

6

5

4

3

2

1

0

ALRTCOMPOV[8:1]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell Overvoltage-Fault Comparator Alert:

ALRTCOMPOV[n] indicates V > V

(comparator overvoltage

COMPOVTH

CELL[n]

ALRTCOMPOV

13:0

threshold); evaluated/enabled if OVALRTEN[n] = 1.

Cleared on next comparator acquisition, if the overvoltage condition is resolved.

Read only.

ALRTCOMPUVREG (0ꢀ0F)

ALRTCOMPUV is a read-accessible register that relates current information on cell undervoltage-fault alerts based on

the redundant comparator.

BIT

Field

15

–

14

–

13

12

11

10

9

8

ALRTCOMPUV[14:9]

0x0000

Reset

–

Access Type

–

Read Only

BIT

Field

7

6

5

4

3

2

1

0

ALRTCOMPUV[8:1]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell Undervoltage-Fault Comparator Alert:

ALRTCOMPUV[n] indicates V < V

(comparator undervoltage

COMPUVTH

CELL[n]

ALRTCOMPUV

13:0

threshold); evaluated/enabled if UVALRTEN[n] = 1.

Cleared on next comparator acquisition, if the undervoltage condition is resolved.

Read only.

ALRTCOMPAUXOVREG (0ꢀ10)

ALRTCOMPAUXOV is a read-accessible register that relates current information on auxiliary overvoltage-fault (cold)

alerts based on the redundant comparator.

Maxim Integrated │ 205

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

ALRTCOMPAUXOV[5:4]

ALRTCOMPAUXOV[3:0]

Reset

0x0

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary Overvoltage (Cold) Fault Comparator Alert:

ALRTCOMPAUXOV[n] indicates V > V

(comparator over-

COMPOVTH

AUXINn

ALRTCOMPAUXOV

5:4

voltage threshold, cold); evaluated/enabled if AUXOVALRTEN[n] = 1.

Cleared on next comparator acquisition, if the overvoltage condition is resolved.

Read only.

Auxiliary Overvoltage (Cold) Fault Comparator Alert:

ALRTCOMPAUXOV[n] indicates V

> V

(comparator over-

AUXINn

COMPOVTH

ALRTCOMPAUXOV

3:0

voltage threshold, cold); evaluated/enabled if AUXOVALRTEN[n] = 1.

Cleared on next comparator acquisition, if the overvoltage condition is resolved.

Read only.

ALRTCOMPAUXUVREG (0ꢀ11)

ALRTCOMPAUXUV is a read-accessible register that relates current information on auxiliary undervoltage-fault (hot)

alerts based on the redundant comparator.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

ALRTCOMPAUXUV[5:4]

ALRTCOMPAUXUV[3:0]

Reset

0x0

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary Undervoltage (Hot)-Fault Comparator Alert:

ALRTCOMPAUXUV[n] indicates V < V

(comparator under-

COMPUVTH

AUXINn

ALRTCOMPAUXUV

5:4

voltage threshold, hot); evaluated/enabled if AUXUVALRTEN[n] = 1.

Cleared on next acquisition, if the undervoltage condition is resolved.

Read only.

Auxiliary Undervoltage (Hot)-Fault Comparator Alert:

ALRTCOMPAUXUV[n] indicates V

< V

(comparator under-

AUXINn

COMPUVTH

3:0

voltage threshold, hot); evaluated/enabled if AUXUVALRTEN[n] = 1.

Cleared on next acquisition, if the undervoltage condition is resolved.

Read only.

Maxim Integrated │ 206

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ALRTBALSWREG (0ꢀ12)

ALRTBALSW is a read-accessible register that relates current summary information on balance-switch fault alerts.

BIT

Field

15

–

14

–

13

12

11

10

9

8

ALRTBALSW[13:8]

0x0000

Reset

–

Access Type

–

Read Only

BIT

Field

7

6

5

4

3

2

1

0

ALRTBALSW[7:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Balance-Switch Fault Alert:

ALRTBALSW[n] indicates the corresponding measurement result fails the

threshold speciﬁed by the balance-switch diagnostic modes (SCANCFG = 100

through 111).

Testing and faults above the TOPCELL1/2 position are automatically masked

out of this register (see PACKCFG:TOPCELL1&2 for complete details).

Cleared on next acquisition if the condition is resolved.

Read only.

ALRTBALSW

13:0

SWACTION (0ꢀ13)

SWACTION is a read-/write-accessible register that contains bits allowing software exit and reset requests. These

requests are not recommended for general use, but may be of use in case of error.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

SWPOR

0b0

Reset

Write, Read,

Pulse

Access Type

–

Maxim Integrated │ 207

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Software POR Request:

0 = Normal operation (default, no eﬀect)

1 = Initiates software POR event

Always reads logic zero.

SWPOR

0

DEVCFG1 (0ꢀ14)

DEVCNFG1 is a read-/write-accessible register that governs the configuration of the device-interface operation.

BIT

15

14

13

12

11

10

9

8

TXUIDLE-

HIZ

TXLIDLE-

HIZ

ALIVECNT-

EN

Field

UARTCFG[1:0]

ADAPTTXEN[1:0]

0b00

UARTHOST

0b1

Reset

0b11

0b0

Write, Read, Write, Read,

Write, Read,

Ext

Access Type

Write, Read, Ext

Read Only

Ext

BIT

Field

7

6

5

4

3

2

1

0

DEVCF-

G1RSRV

SFTYCSB

SFTYSCLK

SFTYSDI

SPIDRVINT

NOPEC

ALERTEN

DBLBUFEN

0b0

Reset

0b0

Write, Read, Write, Read, Write, Read, Write, Read,

Ext Ext Ext Ext

Write, Read, Write, Read,

Ext Ext

Access Type

Write, Read

Maxim Integrated │ 208

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

UART Interface Conﬁguration:

00 = Single-UART interface with external loopback

01 = Single-UART interface with internal loopback

10 = Single-UART interface with diﬀerential-alert interface

11 = Dual-UART Interface (default)

Single-UART options with Loopback (modes 0x): The UART Up path is

used for read and write commands and the down path is used as a return

(pass-through) path. If an internal loopback path is desired, the internal shunt

should only be engaged on the last device in the chain using mode 01. Alert

interface is single-ended (using the ALERTIN and ALERTOUT pins) since the

down path is engaged for UART communications.

Single-UART with Diﬀerential Alert Interface (mode 10): The UART Up

path is used for read and write commands with a direct wire return path from

the last device in the chain to the μC. The down path is used as a diﬀerential-

alert path. The single-ended alert-interface path is disabled (the ALERTOUT

port idle HIZ, and the ALERTIN port are disabled).

UARTCFG

15:14

Dual-UART interface: Both the up and down interfaces are used for UART

communication. Only the host path (selected using UPHOST or DOWNHOST

commands, and indicated by HOSTUART) accepts write commands, while

both paths can accept read commands. Alert interface is single-ended (using

the ALERTIN and ALERTOUT pins) since the down path is engaged for UART

communications.

For all the above options, the UART Up path uses the RXL→TXU ports, and

the UART down path uses the TXL→RXU ports.

These bits have no eﬀect if UARTSEL is set low (SPI interface enabled).

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

Note: The device hardware must be preconﬁgured to support the correct

operational mode. The device powers up in the dual-UART mode to ensure

any hardware conﬁguration can conﬁgure the device. If the incorrect operating

mode is conﬁgured, the UART master should cease communications (and

possibly issue a FORCEPOR) to reset the device to default status through

SHDNL assertion.

UART Upper-TX-Idle Mode Selection:

0 = TXU drivers idle in logic zero (default)

1 = TXU drivers idle in High-Z

TXUIDLEHIZ

TXLIDLEHIZ

13

12

Leave in default state for normal operation.

This bit has no eﬀect if UARTSEL is set low.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

UART Lower-TX-Idle Mode Selection:

0 = TXL drivers idle in logic zero (default)

1 = TXL drivers idle in High-Z

Leave in default state for normal operation.

This bit has no eﬀect if UARTSEL is set low.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

Maxim Integrated │ 209

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

UART Adaptive-Transmission Enable:

00 = Adaptive transmission oﬀ (default)

01 = Enable Up path adaptive transmission on TXU

10 = Enable Down path adaptive transmission on TXL

11 = Unsupported (adaptive transmission oﬀ)

Selections should only be made on device(s) at the end of up/down path(s)

that transmit directly to the μC/μP.

This bit has no eﬀect if UARTSEL is set low.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

ADAPTTXEN

ALIVECNTEN

UARTHOST

11:10

Enable UART-Interface Alive-Counter:

0 = Do not send alive-counter byte (default)

1 = Enables inclusion of alive-counter byte at end of all write and read pack-

ets.

9

8

UART Host-Mode Indicator Bit:

0 = UART down path is host

1 = UART Up path is host (default)

Indicates which UART path is currently conﬁgured as the host. Down-host

mode is only accessible if UARTCFG = DUAL (11). The host mode is selected

using UPHOST and DOWNHOST commands.

This bit has no meaning if UARTSEL is set low, and always reads back one.

Read only.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

SPI CSB Safety-Pullup Enable:

0 = CSB pulup disabled (default)

1 = CSB pulup enabled

SFTYCSB

SFTYSCLK

SFTYSDI

7

6

5

Determines if 100kΩ safety pulup to V

is enabled on the CSB interface

DDL2

input pin. This bit has no eﬀect if UARTSEL is set high.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

SPI SCLK Safety-Pulldown Enable:

0 = SCLK pulldown disabled (default)

1 = SCLK pulldown enabled

Determines if 100kΩ safety pulldown to GND is enabled on the SCLK

interface input pin.

This bit has no eﬀect if UARTSEL is set high.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

SPI SDI Safety-Pulldown Enable:

0 = SDI pulldown disabled (default)

1 = SDI pulldown enabled

Determines if 100kΩ safety pulldown to GND2/3 is enabled on the SDI interface

input pin. This bit has no eﬀect if UARTSEL is set high.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

Maxim Integrated │ 210

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

SPI IRQB Output Drive Mode:

0 = Open-drain nMOS (default)

1 = CMOS drive

SPIDRVINT

4

Determines drive mode for SPI IRQB function on ALERTOUT pin. This bit has

no eﬀect if UARTSEL is set high.

This bitﬁeld is unaﬀected in the event of a software POR (SWPOR) request by

the host.

Reserved:

Reads back the value written.

DEVCFG1RSRV

NOPEC

3

2

UART/SPI PEC/CRC Disable:

0 = PEC/CRC enabled (default)

1 = PEC/CRC disabled

Determines if packet-error checking is enforced using the UART interface and

if cyclic-redundancy checking is enforced using the SPI interface.

If this bit is set, the PEC characters should be omitted from the UART packet/

command (UARTSEL = 1), and the incoming CRC bits ignored during SPI

transactions (UARTSEL = 0).

Alert-Interface Enable:

0 = Alert interface is disabled (default)

1 = Alert interface enabled

If disabled, the following conventions apply:

If UARTSEL = 1 and UARTCFG = 0x or 11 (single-ended alert), the ALER-

TOUT port idles Hi-Z and the ALERTIN port is disabled/ignored.

If UARTSEL = 1 and UARTCFG = 10 (diﬀerential alert), the UART Down path

idle as set by TXLIDLEHIZ.

If UARTSEL = 0 (SPI), the ALRTOUT pin idles high with drive determined by

SPIDRVINT. The ALERTIN pin will be disabled/ignored in SPI mode (no shoot

through current result if the pin is not connected).

ALERTEN

1

This bit is unaﬀected in the event of SWPOR(Soft POR) request by host.

If enabled, the following conventions apply:

If UARTSEL = 1, the device initiates alerts based on STATUS1 content, as

well as passes through any alerts received from/to the daisy-chain.

If UARTSEL = 0 (SPI), the device generates active-low alerts based on

STATUS1 content with drive determined by SPIDRVINT. The ALERTIN pin will

be disabled and ignored in SPI mode (no shoot-through current results if the

pin is not connected).

Double-Buﬀer Mode Enable:

0 = Normal operation (default)

1 = Double-buﬀered operation

Enables the double-buﬀer mode.

This mode automatically transfers data from the ALU/IIR to the data registers

at the start of the next acquisition, instead of at the end of an acquisition.

Note: This mode may be used so the host can start a second acquisition and

then begin reading the data from the ﬁrst acquisition (during the second ac-

quisition). This works even if the ﬁrst data-read transactions take longer than

the second acquisition to complete; simply hold oﬀ on a third acquisition until

the ﬁrst acquisition's data is retrieved. Launching a third acquisition moves the

data from the second acquisition to the data registers for readback during the

third acquisition, and so forth.

DBLBUFEN

0

Maxim Integrated │ 211

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

DEVCFG2 (0ꢀ15)

DEVCNFG2 is a read-/write-accessible register that governs the configuration of the device filtering, several top-level

diagnostic modes, and timeout monitors.

BIT

Field

15

14

13

12

–

11

10

9

8

IIRFC[2:0]

0b010

DEVCFG2RSRV[3:0]

0b0000

Reset

–

Access Type

Write, Read

–

Write, Read

BIT

7

6

5

4

3

2

1

0

FORCE-

POR

ALERTDCT-

STEN

SCANTO-

DIS

Field

–

HVCPDIS

0b0

–

SPITODIS

0b0

CBTODIS

0b0

Reset

–

0b0

–

0b0

Access Type

Write, Read Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

IIR Filter Coeﬃcient Selection:

000 = 0.125

001 = 0.250

010 = 0.375 (default)

011 = 0.500

100 = 0.625

101 = 0.750

IIRFC

15:13

110 = 0.875

111 = 1.000 (ﬁlter oﬀ)

This setting determines the weight of the current measurement result vs.

the previously accumulated results in the IIR ﬁlter. A setting of 1.0 eﬀectively

disables the ﬁlter.

Reserved:

Reads back the value written.

DEVCFG2RSRV

HVCPDIS

11:8

6

HV Charge Pump Disable:

0 = Normal Operation (default)

1 = Disable HV Charge Pump

Used for ALRTHVUV diagnostic. If the HV charge pump is disabled in normal

operation, measurement errors result due to V

undervoltage condition.

HV

Force POR Event:

0 = Normal Operation (default)

1 = Enables hard POR by pulling down SHDNL internally. If cleared before the

POR occurs, the active pulldown on SHDNL be removed.

Note: This bit is used to accelerate a complete POR event issued by SHDNL

falling. In UART applications, it is possible continued UART activity ﬁght or

overcome the SHDNL pulldown. For best results, cease UART communica-

tions when using this mode.

FORCEPOR

5

Maxim Integrated │ 212

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

UART Alert DC Diagnostic Test Enable:

0 = UART Alert DC Testing Disabled (Default)

1 = UART Alert DC Testing Enabled

Used to place the ALRTOUT pin in a DC diagnostic mode for use in testing for

shorts to GPIO/AUX0.

If Enabled while UARTSEL = 1, the ALRTOUT pin be driven low if an Alert

condition is present, and driven high otherwise. ALRTUSER can be written to

exercise ALRTOUT in either direction. Neighboring pins such as AUX/GPIO[0]

can be monitored directly or in diagnostic modes to detect a fault.

This function works in all UARTCFG modes, including 10 (Diﬀerential Alert),

that do not normally use the ALRTOUT pin.

ALERTDCTSTEN

4

This setting has no impact in SPI mode (UARTSEL = 0), the same functional-

ity can be realized using SPIDRVINIT and ALRTUSER.

SPI Time Out Disable:

0 = SPI Time Out Enabled (default)

1 = SPI Time Out Disabled

SPITODIS

2

Determines if SPI time out monitor function is enabled. This bit has no eﬀect if

UARTSEL is set high.

Scan Time Out Disable:

0 = Normal Operation (default)

1 = Disables the acquisition watchdog but does not clear the SCANTIMEOUT

ﬂag in the SCANCTRL register if it is set.

SCANTODIS

CBTODIS

1

0

Cell-Balancing Timeout Disable:

0 = Normal Operation (default)

1 = Disables the cell balancing watchdog but does not clear the ALRTCB-

TIMEOUT ﬂag in the STATUS3 register if it was previously set.

AUXGPIOCFG (0ꢀ16)

AUXGPIOCFG is a read-/write-accessible register that governs the configuration of the AUX/GPIO multifunction pins.

BIT

Field

15

–

14

–

13

12

11

10

GPIOEN[3:0]

0xF

Write, Read, Ext

9

8

0

GPIOEN[5:4]

Reset

–

0x3

Access Type

–

Write, Read, Ext

BIT

Field

7

–

6

–

5

4

3

2

1

GPIODIR[5:4]

GPIODIR[3:0]

Reset

0x0

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Digital GPIO Mode Enable:

0 = Analog Input (AUX) Mode (High-Z)

1 = Digital GPIO Mode (default)

GPIOEN

13:12

GPIOEN[n] conﬁgures the corresponding AUX/GPIO[n] pin for operation in the

selected mode.

Maxim Integrated │ 213

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Digital GPIO Mode Enable

0 = Analog Input (AUX) Mode (High-Z)

1 = Digital GPIO Mode (default)

GPIOEN

11:8

GPIOEN[n] conﬁgures the corresponding AUX/GPIO[n] pin for operation in the

selected mode.

Digital GPIO Direction Selection

0 = Digital Input Mode (High-Z, default)

1 = Digital Output Mode

GPIODIR[n] conﬁgures the direction of the corresponding AUX/GPIO[n] pin.

This setting is only applicable if GPIOEN[n] = 1 (Digital GPIO Mode enabled).

In digital input mode (GPIOEN = 1 and GPIODIR = 0), a 2MΩ pulldown

GPIODIR

5:4

(R

) be enabled to prevent the GPIO input from ﬂoating.

GPIO

In digital output mode (GPIOEN = 1 and GPIODIR = 1, the GPIO input cir-

cuitry continue to operate, allowing direct observation of the port status.

Digital GPIO Direction Selection

0 = Digital Input Mode (High-Z, default)

1 = Digital Output Mode

GPIODIR[n] conﬁgures the direction of the corresponding AUX/GPIO[n] pin.

This setting is only applicable if GPIOEN[n] = 1 (Digital GPIO Mode enabled).

In digital input mode (GPIOEN = 1 and GPIODIR = 0), a 2MΩ pulldown

GPIODIR

3:0

(R

) be enabled to prevent the GPIO input from ﬂoating.

GPIO

In digital output mode (GPIOEN = 1 and GPIODIR = 1), the GPIO input

circuitry continue to operate, allowing direct observation of the port status.

GPIOCFG (0ꢀ17)

GPIO is a read-/write-accessible register that governs the output state of GPIO outputs and reads back the input state

of GPIO inputs.

Maxim Integrated │ 214

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIT

Field

15

–

14

–

13

12

11

10

9

8

0

GPIODRV[5:4]

GPIODRV[3:0]

Reset

–

0x0

0b0

Access Type

–

Write, Read, Ext

BIT

Field

7

–

6

–

5

4

3

2

1

GPIORD[5:4]

0x0

GPIORD[3:0]

0x0

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Digital GPIO Output State

0 = Output Logic Zero (default)

1 = Output Logic One

GPIODRV

13:12

GPIODRV[n] sets the output logic state direction of the corresponding AUX/

GPIO[n] pin.

This setting is only applicable if GPIOEN[n] = 1 and GPIODIR[n] = 1 (Digital

GPIO Output Mode enabled).

Digital GPIO Output State

0 = Output Logic Zero (default)

1 = Output Logic One

GPIODRV

11:8

GPIODRV[n] sets the output logic state direction of the corresponding AUX/

GPIO[n] pin.

This setting is only applicable if GPIOEN[n] = 1 and GPIODIR[n] = 1 (Digital

GPIO Output Mode enabled).

Digital GPIO Input State Indicator

0 = Logic Zero (default)

1 = Logic One

GPIORD[n] indicates the current logic state of each active GPIO[n] input buf-

fer.

GPIORD

5:4

Data is only relevant if GPIOEN[n] = 1 (all Digital GPIO pins are monitored in

Input or Output mode), otherwise zero be read back.

For UART, the logic state is sampled at the end of the parity bit of the register

address byte during a read transaction. For SPI, the logic state is sampled in

response to the 9th SCLK rising edge during a read transaction.

Read only.

Digital GPIO Input State Indicator

0 = Logic Zero (default)

1 = Logic One

GPIORD[n] indicates the current logic state of each active GPIO[n] input buf-

fer.

GPIORD

3:0

Data is only relevant if GPIOEN[n] = 1 (all Digital GPIO pins are monitored in

Input or Output mode), otherwise zero be read back.

For UART, the logic state is sampled at the end of the parity bit of the register

address byte during a read transaction. For SPI, the logic state is sampled in

response to the 9th SCLK rising edge during a read transaction.

Read only.

Maxim Integrated │ 215

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

PACKCFG (0ꢀ18)

PCKCFG is a read-/write-accessible register that configures the part such that the top most cell and block used in the

application is known. Details of Flex Pack applications are also configured within this register.

BIT

Field

Reset

15

14

13

12

11

10

9

8

FLXPCK-

EN2

FLXPCK-

EN1

FLXPCK-

SCAN

–

TOPBLOCK[3:0]

0b1

–

0xF

Access Type Write, Read Write, Read Write, Read

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

TOPCELL2[3:0]

0xF

TOPCELL1[3:0]

0xF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Flex Pack Enable 2

0 = Flex Pack functions disabled

1 = Flex Pack selection of top cell and top block enabled (default)

Indicates the ﬂexible-pack support is engaged (DCINMUX and VBLKMUX),

selecting the internal power and block-routing path when the DCIN pin is not

supplied externally.

This selection is protected by a redundant bitﬁeld. FLXPCKEN1 &

FLXPCKEN2 must agree, resulting in a valid internal FLXPCKEN1/2 selec-

tion. If the two bitﬁelds do not agree, the internal FLXPCKEN1/2 selection be

mapped to 1 (enabled, default) and DCINMUX selection be mapped to the

OFF position.

FLXPCKEN2

15

SWn selection is determined by TOPCELL1/2 (based on TOPCELL1&2). Valid

selections range from Cell 8 (0x8) to Cell 14 (0xE).

If an unsupported selection (0x0 to 0x7, 0xF) is made in TOPCELL1/2, the

DCINMUX selection switches are disabled, but the DCINMUX common switch

is enabled (this is the default condition). In this condition, DCIN is initially

pulled to a diode below the highest SWn input and there is no interference if

DCIN is externally supplied.

Block selection is determined by TOPBLOCK. Valid cell selections range from

Cell 8 (0x8) to Cell 14 (0xE).

If an unsupported selection (0x0~0x7, 0xF) is made in TOPBLOCK, the VBLK

port is selected.

Flex Pack Enable 1 (Redundant Bitﬁeld)

0 = Flex Pack functions disabled

FLXPCKEN1

14

1 = Flex Pack selection of top cell and top block enabled (default)

See FLXPCKEN2 for complete details on operation and redundant bitﬁeld

checking.

Maxim Integrated │ 216

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Flex Pack Scan Conﬁguration

0 = Flex Pack ALTMUX scan unmodiﬁed

1 = Flex Pack ALTMUX scan modiﬁed with additional 30μs delay before acqui-

sition of TOPCELL1/2 (default)

FLEXPCKSCAN conﬁgure the measurement sequence such that for any scan

with ALTMUXSEL = 1, there be 30μs delay prior to sampling the TOPCELL1/2

voltage regardless of SCANMODE. This delay aﬀords the SW[TOPCELL1/2]

input time to settle for an accurate diagnostic measurement when DCIN load-

ing is temporarily suspended in Flex Pack conﬁgurations.

Impacts scan sequences where FLXPCKEN = 1 and TOPCELL1/2 are set

to a supported value (0x8 to 0xE), and ALTMUXSEL = 1 (eﬀective value).

Ignored otherwise.

FLXPCKSCAN

13

Top-Block Selection:

Conﬁgures the top block position if a selection other than the VBLK pin is

chosen. Used to properly determine the connection point for the VBLOCK

resistive divider.

TOPBLOCK

11:8

TOPBLOCK[3:0] selects the Cn pin to be connected to the VBLOCK resistive

divider. 0xF (default) selects the VBLK pin. Selections 0x0–0x7 are not sup-

ported and be mapped to 0xF (VBLK, default).

TOPBLOCK may diﬀer from TOPCELL1/2 if there are Bus Bars installed in

channels above the top cell. TOPBLOCK is ignored if FLXPCKEN = 0.

Top-Cell Selection 2:

Conﬁgures the top cell position if less than 14 channels are used. Used to

properly mask the ALRTBALSW diagnostic alerts (always) and to make DCIN-

MUX selections when FLXPCKEN = 1.

This selection is protected by a redundant bitﬁeld. TOPCELL1 and TOPCELL2

must agree, resulting in a valid internal TOPCELL1/2 selection. If the two

bitﬁelds do not agree, no ALRTBALSW alerts are masked, and the internal

DCINMUX selection be mapped to the OFF position.

0xF (default) removes all ALRTBALSW masking, and places DCINMUX in the

OFF position.

TOPCELL2

7:4

Flex-Pack Behavior:

TOPCELL1/2 selects the SW pin to be connected to the DCIN pin. Selections

0x8 to 0xE map to SW[8] to SW[14]. Selections 0x0 to 0x7 and 0xF are not

supported and be mapped to an OFF position. In the OFF position, DCIN is

initially pulled to a diode below the highest SWn input.

Masking Behavior

TOPCELL1/2 also sets masking behavior in ALRTBALSW diagnostics. All

selections are supported for this function.

Top-Cell Selection 1 (Redundant Bitﬁeld):

Conﬁgures the top-cell position if less than 14 channels are used. Used to

properly mask the ALRTBALSW diagnostic alerts (always) and to make DCIN-

MUX selections when FLXPCKEN=1.

TOPCELL1

3:0

See TOPCELL2 for complete details on operation and redundant bitﬁeld

checking.

ALRTIRQEN (0ꢀ19)

ALRTIRQEN is a read-/write-accessible register that selects which STATUS1 alerts trigger interrupts through the

ALERT interface port(s), and are included in the DCByte and Alert Packet (UART) or ALERT bit (SPI) notifications.

Maxim Integrated │ 217

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Note: The information in the STATUS1 register itself (or any component terms rolled up into STATUS1) is not masked/

disabled by these settings, allowing the underlying data to always be available through STATUS1 readback.

BIT

Field

Reset

15

14

13

12

11

10

9

8

SCAN-

ALRTEN

MSMTCH- CELLOVST- CELLUVST- BLKOVST-

ALRTEN

0b1

BLKUVST-

ALRTEN

AUXOVST-

ALRTEN

–

ALRTEN

0b1

ALRTEN

0b1

ALRTEN

0b1

0b0

–

0b1

Access Type Write, Read

Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BIT

Field

Reset

7

6

5

4

3

2

1

0

AUXUVST-

ALRTEN

PEC-

ALRTEN

INTRFC-

ALRTEN

CAL-

ALRTEN

CBAL-

ALRTEN

FMEA-

2ALRTEN

FMEA-

1ALRTEN

–

0b1

–

0b1

Access Type Write, Read

Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

Scan-Complete Alert Enable

0 = ALRTSCAN masked (default)

1 = ALRTSCAN enabled

SCANALRTEN

15

Disabled by default since this is not a safety feature, but a notiﬁcation option.

Applies to the Alert Interface only in order to support interrupt-driven applica-

tions; ALRTSCAN is never included in the UART DCByte & Alert Packet, or

the SPI ALERT bit.

Cell-Voltage-Mismatch Alert Enable

0 = ALRTMSMTCH masked

MSMTCHALRTEN

CELLOVSTALRTEN

CELLUVSTALRTEN

BLKOVSTALRTEN

13

12

11

10

1 = ALRTMSMTCH enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Cell-Overvoltage-Status Summary-Alert Enable

0 = ALRTCELLOVST masked

1 = ALRTCELLOVST enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Cell-Undervoltage-Status Summary-Alert Enable

0 = ALRTCELLUVST masked

1 = ALRTCELLUVST enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Block-Overvoltage Status-Alert Enable

0 = ALRTBLKOVST masked

1 = ALRTBLKOVST enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Maxim Integrated │ 218

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Block Undervoltage Status Alert Enable

0 = ALRTBLKUVST masked

BLKUVSTALRTEN

9

1 = ALRTBLKUVST enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Auxiliary Overvoltage Status Summary Alert Enable

0 = ALRTAUXOVST masked

AUXOVSTALRTEN

AUXUVSTALRTEN

PECALRTEN

8

7

5

4

3

2

1

0

1 = ALRTAUXOVST enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Auxiliary Undervoltage Status Summary Alert Enable

0 = ALRTAUXUVST masked

1 = ALRTAUXUVST enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Packet Error Check (CRC) Alert Enable

0 = ALRTPEC masked

1 = ALRTPEC enabled (default)

Applies to the Alert Interface, UART Alert Packet, and SPI ALERT bit; ALRT-

PEC is not included in the UART DCByte.

Interface Speciﬁc Error Alert Enable

0 = ALRTINTRFC masked

1 = ALRTINTRFC enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

INTRFCALRTEN

CALALRTEN

Calibration Fault Alert Enable

0 = ALRTCAL masked

1 = ALRTCAL enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Cell Balancing Status Alert Enable

0 = ALRTCBAL masked

1 = ALRTCBAL enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

CBALALRTEN

FMEA2 Condition Summary Alert Enable

0 = ALRTFMEA2 masked

1 = ALRTFMEA2 enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

FMEA2ALRTEN

FMEA1ALRTEN

FMEA1 Condition Summary Alert Enable

0 = ALRTFMEA1 masked

1 = ALRTFMEA1 enabled (default)

Applies to the Alert Interface, UART DCByte & Alert Packet, and SPI ALERT

bit.

Maxim Integrated │ 219

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ALRTOVEN (0ꢀ1A)

ALRTOVEN is a read-/write-accessible register that enables overvoltage fault checks on selected input channels dur-

ing scans using either the ADC or Comparator.

BIT

15

14

13

12

11

10

9

8

BLKOV-

ALRTEN

Field

–

OVALRTEN[14:9]

Reset

–

0b0

0x0000

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

OVALRTEN[8:1]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Block Overvoltage Fault Check Enable

BLKOVALRTEN enables overvoltage fault checking on ADC Block measure-

ments against threshold BLKOVTHSET.

BLKOVALRTEN

14

Clearing also clears the associated Block alert.

Overvoltage Fault Check Enable

OVALRTEN[n] enables overvoltage fault checking on CELL[n] against thresh-

old OVTHSET (ADC) and COMPOVTH (Comparator).

Clearing also clears the associated cell alert in ALRTOVCELL and ALRTCOM-

POVREG.

OVALRTEN

13:0

ALRTUVEN (0ꢀ1B)

ALRTUVEN is a read-/write-accessible register that enables undervoltage fault checks on selected input channels dur-

ing scans using either the ADC or Comparator.

BIT

15

14

13

12

11

10

9

1

8

0

BLKUV-

ALRTEN

Field

–

UVALRTEN[14:9]

Reset

–

0b0

0x0000

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

UVALRTEN[8:1]

0x0000

Reset

Access Type

Write, Read

Maxim Integrated │ 220

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Block Undervoltage Fault Check Enable

BLKUVALRTEN enables undervoltage fault checking on ADC Block measure-

ments against threshold BLKUVTHSET.

BLKUVALRTEN

14

Clearing also clears the associated Block alert.

Undervoltage Fault Check Enable

UVALRTEN[n] enables undervoltage fault checking on CELL[n] against

threshold UVTHSET (ADC) and COMPUVTH (Comparator).

Clearing also clears the associated cell alert in ALRTOVCELL and ALRTCOM-

POVREG.

UVALRTEN

13:0

ALRTAUXOVEN (0ꢀ1C)

ALRTAUXOVEN is a read-/write-accessible register that enables auxiliary overvoltage (cold) fault checks on selected

Auxiliary channels during scans using either the ADC or Comparator.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

AUXOVALRTEN[5:4]

0x0

AUXOVALRTEN[3:0]

0x00

Reset

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Auxiliary Overvoltage (Cold) Fault Check Enable

AUXOVALRTEN[n] enables overvoltage (cold) fault checking on AUX[n]

against the ratiometric/absolute threshold AUXROVTHSET/AUXAOVTHSET

(ADC) and COMPAUXROVTH/COMPAUXAOVTH (Comparator), as selected

by AUXREFSEL[n].

AUXOVALRTEN

5:4

Clearing also clears the associated alert.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still readback the user setting.

Auxiliary Overvoltage (Cold) Fault Check Enable

AUXOVALRTEN[n] enables overvoltage (cold) fault checking on AUX[n]

against the ratiometric/absolute threshold AUXROVTHSET/AUXAOVTHSET

(ADC) and COMPAUXROVTH/COMPAUXAOVTH (Comparator), as selected

by AUXREFSEL[n].

AUXOVALRTEN

3:0

Clearing also clears the associated alert.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still read back the user setting.

Maxim Integrated │ 221

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ALRTAUXUVEN (0ꢀ1D)

ALRTAUXUVEN is a read-/write-accessible register that enables auxiliary undervoltage (hot) fault checks on selected

Auxiliary channels using either the ADC or Comparator.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

AUXUVALRTEN[5:4]

0x0

AUXUVALRTEN[3:0]

0x0

Reset

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Auxiliary Undervoltage (Hot) Fault Check Enable

AUXUVALRTEN[n] enables undervoltage (hot) fault checking on AUX[n]

against the ratiometric/absolute threshold AUXRUVTHSET/AUXAUVTHSET

(ADC) and COMPAUXRUVTH/COMPAUXAUVTH (Comparator), as selected

by AUXREFSEL[n].

AUXUVALRTEN

5:4

Clearing also clears the associated alert.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still readback the user setting.

Auxiliary Undervoltage (Hot) Fault Check Enable

AUXUVALRTEN[n] enables undervoltage (hot) fault checking on AUX[n]

against the ratiometric/absolute threshold AUXRUVTHSET/AUXAUVTHSET

(ADC) and COMPAUXRUVTH/COMPAUXAUVTH (Comparator), as selected

by AUXREFSEL[n].

AUXUVALRTEN

3:0

Clearing also clears the associated alert.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still read back the user setting.

ALRTCALTST (0ꢀ1E)

ALRTCALTST is a read-/write-accessible register that allows the user to force Calibration alerts to test readback and

interrupt logic. The forced alert(s) remain forced until this register is written back to zeros (assuming the existing

calibration data is with range).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

7

6

5

4

3

2

1

0

CALO-

STHRM-

ALRTFRC

CALOSAD-

CALRTFRC

CALOSR-

ALRTFRC

CALGAIN-

PALRTFRC RALRTFRC

CALGAIN-

Field

–

Reset

–

0b0

0b0 0b0

Access Type

Write, Read Write, Read Write, Read Write, Read Write, Read

Maxim Integrated │ 222

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

ADC Oﬀset Calibration Alert Force

0 = ALRTCALOSADC normal operation (default)

1 = ALRTCALOSADC forced if unmasked

Used to test alert functionality.

CALOSADCALRTFRC

4

Ramp LSA + ADC Oﬀset Calibration Alert Force

0 = ALRTCALOSR normal operation (default)

1 = ALRTCALOSR forced if unmasked

Used to test alert functionality.

CALOSRALRTFRC

3

2

1

0

Ratiometric ADC Oﬀset Calibration Alert Force

0 = ALRTCALOSTHRM normal operation (default)

1 = ALRTCALOSTHRM forced if unmasked

Used to test alert functionality.

CALOSTHRMALRTFRC

CALGAINPALRTFRC

CALGAINRALRTFRC

Pyramid Gain Calibration Alert Force

0 = ALRTCALGAINP normal operation (default)

1 = ALRTCALGAINP forced if unmasked

Used to test alert functionality.

Ramp Gain Calibration Alert Force

0 = ALRTCALGAINR normal operation (default)

1 = ALRTCALGAINR forced if unmasked

Used to test alert functionality.

OVTHCLRREG (0ꢀ1F)

OVTHCLR is a read-/write-accessible register that selects the cell overvoltage alert clear threshold used with unipolar

ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

OVTHCLR[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

OVTHCLR[5:0]

Reset

0x3FFF

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Unipolar Cell Overvoltage Alert Clear Threshold

14-bit threshold value at/below which ALRTOV alerts be cleared/deasserted

for unipolar cell measurements.

OVTHCLR

15:2

Note: For proper operation, this value should always be less than or equal to

OVTHSET.

Maxim Integrated │ 223

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OVTHSETREG (0ꢀ20)

OVTHSET is a read-/write-accessible register that selects the cell overvoltage alert set threshold used with unipolar ADC

measurements.

BIT

Field

15

14

13

12

11

10

9

8

OVTHSET[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

OVTHSET[5:0]

Reset

0x3FFF

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Unipolar Cell Overvoltage Alert Set Threshold

14-bit threshold value above which ALRTOV alerts be set/asserted for unipo-

lar cell measurements.

OVTHSET

15:2

A value of 0x3FFF eﬀectively disables overvoltage checking.

UVTHCLRREG (0ꢀ21)

UVTHCLR is a read-/write-accessible register that selects the cell undervoltage alert clear threshold used with unipolar

ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

UVTHCLR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

UVTHCLR[5:0]

Reset

0x0000

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Unipolar Cell Undervoltage Alert Clear Threshold

14-bit threshold value at/above which ALRTUV alerts be cleared/deasserted

for unipolar cell measurements.

UVTHCLR

15:2

Note: For proper operation, this value should always be greater than or equal

to UVTHSET.

Maxim Integrated │ 224

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

UVTHSETREG (0ꢀ22)

UVTHSET is a read-/write-accessible register that selects the cell undervoltage alert set threshold used with unipolar ADC

measurements.

BIT

Field

15

14

13

12

11

10

9

8

UVTHSET[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

UVTHSET[5:0]

Reset

0x0000

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Unipolar Cell Undervoltage Alert Set Threshold

14-bit threshold value below which ALRTUV alerts be set/asserted for unipolar

cell measurements.

UVTHSET

15:2

A value of 0x0000 eﬀectively disables undervoltage checking.

MSMTCHREG ((0ꢀ23))

MSMTCH is a read-/write-accessible register that selects the cell-voltage-mismatch alert threshold used with ADC cell

scan measurements.

BIT

Field

15

14

13

12

11

10

9

8

MSMTCH[13:6]

Reset

0x3FFF

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

MSMTCH[5:0]

Reset

0x3FFF

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Misimatch Alert Threshold

14-bit threshold value; if the diﬀerence between maximum and minimum cell

voltages exceeds this value, ALRTMSMTCH be set/asserted.

Whether only unipolar ADC measurements (POLARITYn = 0) are included

in mismatch calculations or all measurements are included is determined by

POLARITYCTRL:MINMAXPOL.

MSMTCH

15:2

Maxim Integrated │ 225

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIPOVTHCLRREG (0ꢀ24)

BIPOVTHCLR is a read-/write-accessible register that selects the cell overvoltage alert clear threshold used with bipo-

lar ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

BIPOVTHCLR[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BIPOVTHCLR[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Bipolar Cell Overvoltage Alert Clear Threshold

14-bit threshold value at/below which ALRTOV alerts be cleared/deasserted

for bipolar cell measurements. Bipolar format.

BIPOVTHCLR

15:2

Note: For proper operation, this value should always be less than or equal to

BIPOVTHSET.

BIPOVTHSETREG (0ꢀ25)

BIPOVTHSET is a read-/write-accessible register that selects the cell overvoltage alert set threshold used with bipolar

ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

BIPOVTHSET[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BIPOVTHSET[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Bipolar Cell Overvoltage Alert Set Threshold

14-bit threshold value above which ALRTOV alerts be set/asserted for bipolar

cell measurements. Bipolar format.

BIPOVTHSET

15:2

A value of 0x3FFF eﬀectively disables overvoltage checking.

Maxim Integrated │ 226

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIPUVTHCLRREG (0ꢀ26)

BIPUVTHCLR is a read-/write-accessible register that selects the cell undervoltage alert clear threshold used with

bipolar ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

BIPUVTHCLR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BIPUVTHCLR[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Bipolar Cell Undervoltage Alert Clear Threshold

14-bit threshold value at/above which ALRTUV alerts be cleared/deasserted

for bipolar cell measurements. Bipolar format.

BIPUVTHCLR

15:2

Note: For proper operation, this value should always be greater than or equal

to BIPUVTHSET.

BIPUVTHSETREG (0ꢀ27)

BIPUVTHSET is a read-/write-accessible register that selects the cell undervoltage alert set threshold used with bipolar

ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

BIPUVTHSET[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BIPUVTHSET[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Bipolar Cell Undervoltage Alert Set Threshold

14-bit threshold value below which ALRTUV alerts be set/asserted for bipolar

cell measurements. Bipolar format.

BIPUVTHSET

15:2

A value of 0x0000 eﬀectively disables undervoltage checking.

Maxim Integrated │ 227

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BLKOVTHCLRREG (0ꢀ28)

BLKOVTHCLR is a read-/write-accessible register that selects the block overvoltage alert clear threshold used with

ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

BLKOVTHCLR[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BLKOVTHCLR[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Block Overvoltage Alert Clear Threshold

14-bit threshold value at/below which the ALRTBLKOV alert be cleared/deas-

BLKOVTHCLR

15:2

serted.

Note: For proper operation, this value should always be less than or equal to

BLKOVTHSET.

BLKOVTHSETREG (0ꢀ29)

BLKOVTHSET is a read-/write-accessible register that selects the block overvoltage alert set threshold used with ADC

measurements.

BIT

Field

15

14

13

12

11

10

9

8

BLKOVTHSET[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BLKOVTHSET[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BLKOVTHSET

BITS

DESCRIPTION

Block Overvoltage Alert Set Threshold

14-bit threshold value above which the ALRTBLKOV alert be set/asserted.

15:2

A value of 0x3FFF eﬀectively disables overvoltage checking.

Maxim Integrated │ 228

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BLKUVTHCLRREG (0ꢀ2A)

BLKUVTHCLR is a read-/write-accessible register that selects the block undervoltage alert clear threshold used with

ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

BLKUVTHCLR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BLKUVTHCLR[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Block Undervoltage Alert Clear Threshold

14-bit threshold value at/above which the ALRTBLKUV alert be cleared/deas-

BLKUVTHCLR

15:2

serted.

Note: For proper operation, this value should always be greater than or equal

to BLKUVTHSET.

BLKUVTHSETREG (0ꢀ2B)

BLKUVTHSET is a read-/write-accessible register that selects the block undervoltage alert set threshold used with

ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

BLKUVTHSET[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BLKUVTHSET[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BLKUVTHSET

BITS

DESCRIPTION

Block Undervoltage Alert Set Threshold

14-bit threshold value below which the ALRTBLKUV alert be set/asserted.

15:2

A value of 0x0000 eﬀectively disables undervoltage checking.

Maxim Integrated │ 229

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

AUXROVTHCLRREG (0ꢀ30)

AUXROVTHCLR is a read-/write-accessible register that selects the overvoltage (cold) alert clear threshold used with

ratiometric auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXROVTHCLR[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXROVTHCLR[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Ratiometric Auxiliary Overvoltage (Cold) Alert Clear Threshold

14-bit overvoltage (cold) clear threshold value, at/below which ALRTAUXOV

alerts be cleared/deasserted.

AUXROVTHCLR

15:2

This threshold is applied for Auxiliary measurements where AUXREFSELn = 0

(ratio metric).

Note: For proper operation, this value should always be less than or equal to

AUXROVTHSET.

AUXROVTHSETREG (0ꢀ31)

AUXROVTHSET is a read-/write-accessible register that selects the overvoltage (cold) alert set threshold used with

Ratiometric Auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXROVTHSET[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXROVTHSET[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Ratiometric Auxiliary Overvoltage (Cold) Alert Set Threshold

14-bit overvoltage (cold) set threshold value, above which ALRTAUXOV alerts

be asserted.

This threshold is applied for Auxiliary measurements where AUXREFSELn = 0

(Ratio metric).

AUXROVTHSET

15:2

A value of 0x3FFF eﬀectively disables overvoltage checking.

Maxim Integrated │ 230

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

AUXRUVTHCLRREG (0ꢀ32)

AUXRUVTHCLR is a read-/write-accessible register that selects the undervoltage (hot) alert clear threshold used with

ratiometric auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXRUVTHCLR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXRUVTHCLR[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Ratiometric Auxiliary Undervoltage (Hot) Alert Clear Threshold

14-bit undervoltage (hot) clear threshold value, at/above which ALRTAUXUV

alerts be cleared/deasserted.

AUXRUVTHCLR

15:2

This threshold is applied for Auxiliary measurements where AUXREFSELn = 0

(ratio metric).

Note: For proper operation, this value should always be greater than or equal

to AUXRUVTHSET.

AUXRUVTHSETREG (0ꢀ33)

AUXRUVTHSET is a read-/write-accessible register that selects the undervoltage (hot) alert set threshold used with

ratiometric auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXRUVTHSET[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXRUVTHSET[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Ratiometric Auxiliary Undervoltage (Hot) Alert Set Threshold

14-bit undervoltage (hot) set threshold value, below which ALRTAUXUV alerts

be asserted.

This threshold is applied for Auxiliary measurements where AUXREFSELn = 0

(ratio metric).

AUXRUVTHSET

15:2

A value of 0x0000 eﬀectively disables undervoltage checking.

Maxim Integrated │ 231

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

AUXAOVTHCLRREG (0ꢀ34)

AUXOVTHCLR is a read-/write-accessible register that selects the overvoltage alert clear threshold used with Absolute

Auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXAOVTHCLR[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXAOVTHCLR[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Absolute Auxiliary Overvoltage Alert Clear Threshold

14-bit overvoltage clear threshold value, at/below which ALRTAUXOV alerts

be cleared/deasserted.

AUXAOVTHCLR

15:2

This threshold is applied for Auxiliary measurements where AUXREFSELn =

1 (Absolute).

Note: For proper operation, this value should always be less than or equal to

AUXAOVTHSET.

AUXAOVTHSETREG ((0ꢀ35))

AUXAOVTHSET is a read-/write-accessible register that selects the overvoltage alert set threshold used with Absolute

Auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXAOVTHSET[13:6]

0x3FFF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXAOVTHSET[5:0]

0x3FFF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Auxiliary Overvoltage Alert Set Threshold

14-bit overvoltage set threshold value, above which ALRTAUXOV alerts be

asserted.

This threshold is applied for Auxiliary measurements where AUXREFSELn =

1 (Absolute).

AUXAOVTHSET

15:2

A value of 0x3FFF eﬀectively disables overvoltage checking.

Maxim Integrated │ 232

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

AUXAUVTHCLRREG (0ꢀ36)

AUXAUVTHCLR is a read-/write-accessible register that selects the undervoltage alert clear threshold used with

Absolute Auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXAUVTHCLR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXAUVTHCLR[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Absolute Auxiliary Undervoltage Alert Clear Threshold

14-bit undervoltage clear threshold value, at/above which ALRTAUXUV alerts

be cleared/deasserted.

AUXAUVTHCLR

15:2

This threshold is applied for Auxiliary measurements where AUXREFSELn =

1 (Absolute).

Note: For proper operation, this value should always be greater than or equal

to AUXAUVTHSET.

AUXAUVTHSETREG (0ꢀ37)

AUXAUVTHSET is a read-/write-accessible register that selects the undervoltage alert set threshold used with

Absolute Auxiliary ADC measurements.

BIT

Field

15

14

13

12

11

10

9

8

AUXAUVTHSET[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUXAUVTHSET[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Absolute Auxiliary Undervoltage Alert Set Threshold

14-bit undervoltage set threshold value, below which ALRTAUXUV alerts be

asserted.

This threshold is applied for Auxiliary measurements where AUXREFSELn =

1 (Absolute).

AUXAUVTHSET

15:2

A value of 0x0000 eﬀectively disables undervoltage checking.

Maxim Integrated │ 233

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

COMPOVTHREG (0ꢀ38)

COMPOVTH is a read-/write-accessible register that selects the cell overvoltage alert threshold for the redundant com-

parator.

BIT

Field

15

14

13

12

11

10

9

8

COMPOVTH[9:2]

0x3FF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPOVTH[1:0]

0x3FF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Cell Overvoltage Alert Threshold

10-bit threshold value, of a 5V input range, above which ALRTCOMPOV

alerts be set/asserted by comparator scans.

A value of 0x3FF eﬀectively disables overvoltage checking.

Note: For proper operation, this value should always be greater than or

equal to COMPUVTH.

COMPOVTH

15:6

COMPUVTHREG (0ꢀ39)

COMPUVTH is a read-/write-accessible register that selects the cell undervoltage alert threshold for the redundant

comparator.

BIT

Field

15

14

13

12

11

10

9

8

COMPUVTH[9:2]

0x000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPUVTH[1:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Cell Undervoltage Alert Threshold

10-bit threshold value, of a 5V input range, below which ALRTCOMPUV alerts

be set/asserted by comparator scans.

A value of 0x000 eﬀectively disables undervoltage checking.

Note: For proper operation, his value should always be less than or equal to

COMPOVTH.

COMPUVTH

15:6

Maxim Integrated │ 234

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

COMPAUXROVTHREG (0ꢀ3A)

COMPAUXROVTH is a read-/write-accessible register that selects the overvoltage (cold) alert threshold applied during

ratiometric auxiliary comparator measurements.

BIT

Field

15

14

13

12

11

10

9

8

COMPAUXROVTH[9:2]

0x3FF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPAUXROVTH[1:0]

0x3FF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Ratiometric Auxiliary Overvoltage (Cold) Alert Threshold

10-bit overvoltage (cold) threshold value of a input range of V , above which

AA

ALRTCOMPAUXOV alerts be set/asserted by comparator scans.

This threshold is applied for Auxiliary measurements where AUXREFSELn = 0

(ratio metric).

COMPAUXROVTH

15:6

A value of 0x3FF eﬀectively disables overvoltage checking.

Note: For proper operation, this value should always be greater than or equal

to COMPAUXRUVTH.

COMPAUXRUVTHREG (0ꢀ3B)

COMPAUXRUVTH is a read-/write-accessible register that selects the undervoltage (hot) alert threshold applied during

ratiometric auxiliary comparator measurements.

BIT

Field

15

14

13

12

11

10

9

8

COMPAUXRUVTH[9:2]

0x000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPAUXRUVTH[1:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Ratiometric Auxiliary Undervoltage (Hot) Alert Threshold

10-bit undervoltage (hot) threshold value of a input range of V , below which

AA

ALRTCOMPAUXUV alerts be set/asserted by comparator scans.

This threshold is applied for Auxiliary measurements where AUXREFSELn=0

(ratio metric).

COMPAUXRUVTH

15:6

A value of 0x000 eﬀectively disables undervoltage checking.

Note: For proper operation, this value should always be less than or equal to

COMPAUXROVTH.

Maxim Integrated │ 235

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

COMPAUXAOVTHREG (0ꢀ3C)

COMPAUXAOVTH is a read-/write-accessible register that selects the overvoltage alert threshold applied during

Absolute Auxiliary comparator measurements.

BIT

Field

15

14

13

12

11

10

9

8

COMPAUXAOVTH[9:2]

0x3FF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPAUXAOVTH[1:0]

0x3FF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Absolute Auxiliary Overvoltage Alert Threshold

10-bit overvoltage threshold value, of an input range of V

above which

REF,

ALRTCOMPAUXOV alerts be set/asserted by comparator scans.

This threshold is applied for Auxiliary measurements where AUXREFSELn =

1 (Absolute).

COMPAUXAOVTH

15:6

A value of 0x3FF eﬀectively disables overvoltage checking.

Note: For normal operation, this value should always be greater than or equal

to COMPAUXAUVTH.

COMPAUXAUVTHREG (0ꢀ3D)

COMPAUXAUVTH is a read-/write-accessible register that selects the undervoltage alert threshold applied during

Absolute Auxiliary comparator measurements.

BIT

Field

15

14

13

12

11

10

9

8

COMPAUXAUVTH[9:2]

0x000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPAUXAUVTH[1:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Absolute Auxiliary Undervoltage Alert Threshold

10-bit undervoltage threshold value, of an input range of V

below which

REF,

ALRTCOMPAUXUV alerts be set/asserted by comparator scans.

This threshold is applied for Auxiliary measurements where AUXREFSELn =

1 (Absolute).

COMPAUXAUVTH

15:6

A value of 0x000 eﬀectively disables undervoltage checking.

Note: For proper operation, this value should always be less than or equal to

COMPAUXAOVTH.

Maxim Integrated │ 236

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

COMPOPNTHREG (0ꢀ3E)

COMPOPNTH is a read-/write-accessible register that selects the undervoltage alert threshold applied to Unipolar Cell

inputs in Open Diagnostic Mode.

BIT

Field

15

14

13

12

11

10

9

8

COMPOPNTH[9:2]

0x000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPOPNTH[1:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Cell Open Undervoltage Alert Threshold

10-bit threshold of a 5V input range, below which ALRTCOMPUV alerts be

set/asserted by comparator scans performed on Unipolar Cell inputs in Open

Diagnostic Mode (see CTSTCFG:CELLOPNDIAGSEL).

COMPOPNTH

15:6

A value of 0x000 eﬀectively disables open undervoltage checking.

COMPAUXROPNTHREG (0ꢀ3F)

COMPAUXROPNTH is a read-/write-accessible register that selects the undervoltage alert threshold applied to ratio-

metric auxiliary inputs in open-diagnostic mode.

BIT

Field

15

14

13

12

11

10

9

8

COMPAUXROPNTH[9:2]

0x000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPAUXROPNTH[1:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Ratiometric Auxiliary Open Undervoltage Alert Threshold:

10-bit undervoltage threshold value, of an input range of V below

AA,

which ALRTCOMPAUXUV alerts be set/asserted by comparator scans

performed on ratiometric auxiliary inputs in open-diagnostic mode (see

DIAGGENCFG:AUXDIAGSEL).

COMPAUXROPNTH

15:6

This threshold is applied for auxiliary measurements where AUXREFSELn = 0

(ratio metric).

A value of 0x000 eﬀectively disables undervoltage checking.

Maxim Integrated │ 237

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

COMPAUXAOPNTHREG (0ꢀ40)

COMPAUXAOPNTH is a read-/write-accessible register that selects the undervoltage alert threshold applied to

Absolute Auxiliary inputs in Open Diagnostic Mode.

BIT

Field

15

14

13

12

11

10

9

8

COMPAUXAOPNTH[9:2]

0x000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPAUXAOPNTH[1:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Comparator Absolute Auxiliary Open Undervoltage Alert Threshold

10-bit undervoltage threshold value, of an input range of V below

REF,

which ALRTCOMPAUXUV alerts be set/asserted by comparator scans

performed on Absolute Auxiliary inputs in Open Diagnostic Mode (see

DIAGGENCFG:AUXDIAGSEL).

COMPAUXAOPNTH

15:6

This threshold is applied forAuxiliary measurements whereAUXREFSELn = 1 (Absolute).

A value of 0x000 eﬀectively disables undervoltage checking.

COMPACCOVTHREG (0ꢀ41)

COMPACCOVTH is a read-/write-accessible register that selects the overvoltage alert threshold applied during com-

parator accuracy diagnostics.

BIT

Field

15

14

13

12

11

10

9

8

COMPACCOVTH[9:2]

0x3FF

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPACCOVTH[1:0]

0x3FF

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

End-of-Sequence Comparator Accuracy Diagnostic Overvoltage Alert Threshold

10-bit overvoltage threshold value of a 5V input range, used to validate the ac-

curacy of the comparator at the end of any measurement sequence using the

comparator if enabled (SCANCFG = 001 or 010 and COMPACCEN = 1).

Tested for the Cell Signal Path with COMP = V

through LSA2 (gain =

IN

REF

COMPACCOVTH

15:6

6/13) and DAC

= V

. A value above COMPACCOVTH result in the

REF

ALRTCOMPACCOV bit being set/asserted.

0x1D8 is the ideal value. A precise value can be selected based on information

from the Comparator Cell Signal Path Fault diagnostic. A value of 0x3FF

eﬀectively disables overvoltage checking (default).

Maxim Integrated │ 238

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

COMPACCUVTHREG (0ꢀ42)

COMPACCUVTH is a read-/write-accessible register that selects the undervoltage alert threshold applied during com-

parator accuracy diagnostics.

BIT

Field

15

14

13

12

11

10

9

8

COMPACCUVTH[9:2]

0x000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

–

4

–

3

–

2

–

1

–

0

–

COMPACCUVTH[1:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

End-of-Sequence Comparator Accuracy Diagnostic Undervoltage Alert Threshold

10-bit undervoltage threshold value of a 5V input range, used to validate the

accuracy of the comparator at the end of any measurement sequence using the

comparator if enabled (SCANCFG = 001 or 010 and COMPACCEN = 1).

Tested for the Cell Signal Path with COMP = V

through LSA2 (gain =

IN

REF

COMPACCUVTH

15:6

6/13) and DAC

= V

. A value below COMPACCUVTH result in the ALRT-

REF

COMPACCUV bit being set/asserted.

0x1D8 is the ideal value. A precise value can be selected based on information

from the Comparator Cell Signal Path Fault diagnostic. A value of 0x000 eﬀec-

tively disables undervoltage checking (default).

BALSHRTTHRREG (0ꢀ43)

BALSHRTTHR is a read-/write-accessible register that selects alert threshold used during the Balance Switch Short

Diagnostic mode.

BIT

Field

15

14

13

12

11

10

9

8

BALSHRTTHR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BALSHRTTHR[5:0]

0x0000

Reset

Access Type

Write, Read

Maxim Integrated │ 239

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Balance Switch Short Diagnostic Alert Threshold

14-bit undervoltage threshold used for the balancing switch short circuit diag-

nostic test (SCANCFG = 100).

Unipolar format. For BALSW Short Diagnostics, only cells with (POLARITYn =

0 and CELLENn = 1) are measured and checked.

BALSHRTTHR

15:2

The unipolar ADC cell-voltage results taken in this mode are compared

against the threshold; if any result is below the threshold, it is ﬂagged as a

balancing switch alert (ALRTBALSW). Results above the threshold are con-

sidered normal. The threshold should be set by the system controller prior to

making a diagnostic measurement.

BALLOWTHRREG ((0ꢀ44))

BALLOWTHR is a read-/write-accessible register that selects alert low threshold used during the Balance Switch Open

Diagnostic mode.

BIT

Field

15

14

13

12

11

10

9

8

BALLOWTHR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BALLOWTHR[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Balance Switch Open Diagnostic Alert Low Threshold

14-bit undervoltage threshold used for the balancing switch conducting and

cell sense wire diagnostic tests (SCANCFG=101, 110, and 111).

Bipolar format, typically a small positive value is selected. For BALSW Open

Diagnostics, only cells with (POLARITYn = 0 and BALSWENn = 1) are mea-

sured and checked. For Cell Sense Open Odd/Even Diagnostics, only odd/

even cells at/below TOPCELL1/2 with POLARITYn = 0 and are measured and

checked.

BALLOWTHR

15:2

The bipolar ADC cell results in this mode are compared against the threshold;

if any result is below the threshold, it is ﬂagged as a balancing switch alert

(ALRTBALSW). Results above the threshold are considered normal. The

threshold should be set by the system controller prior to making a diagnostic

measurement.

Maxim Integrated │ 240

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALHIGHTHRREG (0ꢀ45)

BALHIGHTHR is a read-/write-accessible register that selects alert High threshold used during the Balance Switch

Open Diagnostic mode.

BIT

Field

15

14

13

12

11

10

9

8

BALHIGHTHR[13:6]

0x0000

Reset

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

–

0

–

BALHIGHTHR[5:0]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Balance Switch Open Diagnostic Alert High Threshold

14-bit overvoltage threshold used for the balancing switch conducting and cell

sense wire diagnostic tests (SCANCFG = 101, 110, 111).

Bipolar format, typically a moderate positive value is selected, based on

external resistor characteristics. For BALSW Open Diagnostics, only cells

with (POLARITYn = 0 and BALSWENn = 1) are measured and checked. For

Cell Sense Open Odd/Even Diagnostics, only odd/even cells at/below TOP-

CELL1/2 with POLARITYn = 0 and are measured and checked.

The bipolar ADC cell results in this mode are compared against the threshold;

if any result is above the threshold, it is ﬂagged as a balancing switch alert

(ALRTBALSW). Results below the threshold are considered normal. The

threshold should be set by the system controller prior to making a diagnostic

measurement.

BALHIGHTHR

15:2

CELL1REG (0ꢀ47)

CELLn is a read-accessible register that holds the current value for each individual cell measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL1[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL1[5:0]

0x0000

Reset

Access Type

Read Only

Maxim Integrated │ 241

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

CELL1

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

Scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL2REG (0ꢀ48)

CELLn is a read-accessible register that holds the current value for each individual cell measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL2[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL2[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

CELL2

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

Scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL3REG (0ꢀ49)

CELLn is a read-accessible register that holds the current value for each individual cell measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL3[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL3[5:0]

0x0000

Reset

Maxim Integrated │ 242

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Access Type

BITFIELD

Read Only

–

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

CELL3

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

Scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL4REG (0ꢀ4A)

CELLn is a read-accessible register that holds the current value for each individual cell measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL4[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL4[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

CELL4

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

Scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL5REG (0ꢀ4B)

CELLn is a read-accessible register that holds the current value for each individual cell measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL5[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL5[5:0]

0x0000

Reset

Access Type

Read Only

Maxim Integrated │ 243

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

CELL5

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

Scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL6REG (0ꢀ4C)

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL6[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL6[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V.

CELL6

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL7REG ((0ꢀ4D))

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL7[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL7[5:0]

0x0000

Reset

Access Type

Read Only

Maxim Integrated │ 244

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V.

CELL7

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL8REG (0ꢀ4E)

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL8[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL8[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V.

If CELLEN=0, and the measurement was skipped during the latest ADC scan,

no internal data is updated, and ALU/IIR readback be determined by RDFILT.

Read only.

CELL8

15:2

CELL9REG (0ꢀ4F)

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL9[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL9[5:0]

0x0000

Reset

Access Type

Read Only

Maxim Integrated │ 245

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V.

If CELLEN = 0, and the measurement was skipped during the latest ADC scan,

no internal data is updated, and ALU/IIR readback be determined by RDFILT.

Read only.

CELL9

15:2

CELL10REG (0ꢀ50)

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL10[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL10[5:0]

Reset

0x0000

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

CELL10

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

Scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL11REG (0ꢀ51)

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL11[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL11[5:0]

0x0000

Reset

Access Type

Read Only

Maxim Integrated │ 246

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

If CELLEN = 0, and the measurement was skipped during the latest ADC scan,

no internal data is updated, and ALU/IIR readback be determined by RDFILT.

Read only.

CELL11

15:2

CELL12REG (0ꢀ52)

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL12[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL12[5:0]

Reset

0x0000

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V

CELL12

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL13REG (0ꢀ53)

CELLn is a read-accessible register that holds the current value for each individual cell-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL13[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL13[5:0]

Reset

0x0000

Access Type

Read Only

Maxim Integrated │ 247

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V.

CELL13

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

CELL14REG (0ꢀ54)

CELLn is a read-accessible register that holds the current value for each individual cell measurement result.

BIT

Field

15

14

13

12

11

10

9

8

CELL14[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

CELL14[5:0]

Reset

0x0000

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Voltage-Measurement Result:

CELLn[13:0] contains the 14-bit measurement result for CELLn.

Full-scale input range of 5V.

CELL14

15:2

If CELLEN = 0, and the measurement was skipped during the latest ADC

scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

BLOCKREG (0ꢀ55)

BLOCK is a read-accessible register that holds the current value for the total block-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

VBLOCK[13:6]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

VBLOCK[5:0]

0x0000

4

3

2

1

–

0

–

Reset

Maxim Integrated │ 248

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Access Type

BITFIELD

Read Only

–

BITS

DESCRIPTION

Block-Voltage-Measurement Result:

VBLOCK[13:0] contains the 14-bit measurement result for VBLK.

Full-scale input range of 65V.

VBLOCK

15:2

If BLOCKEN = 0, and the measurement was skipped during the latest ADC

scan, no internal data is updated, and ALU/IIR readback be determined by

RDFILT.

Read only.

TOTALREG (0ꢀ56)

TOTAL is a read-accessible register that holds the current value for the sum of all enabled-measurement results within

the stack.

BIT

Field

15

14

13

12

11

10

9

8

TOTAL[15:8]

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

0

TOTAL[7:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Total Cell-Voltage-Measurement Result:

TOTAL[15:0] contains the 16-bit sum of all cell-measurement results enabled

during the last scan by MEASUREEN1.

Full-scale range is 0.0 to 80.0V with a 1.22mV LSB (unipolar).

Read only.

Note: Make note of the following behavior:

TOTAL

15:0

Since disabled measurements retain their last results, it is possible there be

data in the result registers that were not included in the TOTAL result calcu-

lated for the last scan.

If cell and bus bar (unipolar and bipolar) measurements are mixed within a

scan, the summation be handled accordingly.

Totals below 0V cannot be supported, and be clipped at 0x0000 (can

apply to scans using only bipolar measurements).

DIAG1REG (0ꢀ57)

DIAG1 is a read-only register that contains the diagnostic result requested by the DIAGCFG:DIAGSEL1 selection

taken during the last ADC acquisition.

BIT

Field

15

14

13

12

11

10

9

8

DIAG1[13:6]

Maxim Integrated │ 249

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Reset

0x0000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

DIAG1[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

DIAG1 contains the 14-bit measurement result for the diagnostic selected by

DIAGCFG:DIAGSEL1.

DIAG1

15:2

DIAG2REG (0ꢀ58)

DIAG2 is a read-only register that contains the diagnostic result requested by the DIAGCFG:DIAGSEL2 selection

taken during the last ADC acquisition.

BIT

Field

15

14

13

12

11

10

9

8

DIAG2[13:6]

0x0000

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

DIAG2[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

DIAG2 contains the 14-bit measurement result for the diagnostic selected by

DIAGCFG:DIAGSEL2.

DIAG2

15:2

AUX0REG (0ꢀ59)

AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

AUX0[13:6]

0x0000

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUX0[5:0]

0x0000

Reset

Maxim Integrated │ 250

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Access Type

BITFIELD

Read Only

–

BITS

DESCRIPTION

Auxiliary-Voltage-Measurement Result:

AUXn[13:0] contains the 14-bit measurement result for AUXn.

Full-scale input range of V for ratiometric operation, V

for absolute

AA

REF

operation.

AUX0

15:2

If the port is not conﬁgured as an AUXINn input (see AUXGPIOCFG), the

result readback 0x0000 for the unused channel; otherwise, if AUXEN = 0 and

the measurement was skipped during the latest ADC Scan, the previously

determined result remain.

Read only.

AUX1REG (0ꢀ5A)

AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

AUX1[13:6]

0x0000

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUX1[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary-Voltage-Measurement Result:

AUXn[13:0] contains the 14-bit measurement result for AUXn.

Full-scale input range of V for ratiometric operation, V

for absolute

AA

REF

operation.

AUX1

15:2

If the port is not conﬁgured as an AUXINn input (see AUXGPIOCFG), the

result readback 0x0000 for the unused channel; otherwise, if AUXEN = 0 and

the measurement was skipped during the latest ADC scan, the previously

determined result remain.

Read only.

AUX2REG (0ꢀ5B)

AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

AUX2[13:6]

0x0000

Reset

Access Type

Read Only

BIT

7

6

5

4

3

2

1

0

Maxim Integrated │ 251

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Field

AUX2[5:0]

0x0000

–

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary-Voltage-Measurement Result:

AUXn[13:0] contains the 14-bit measurement result for AUXn.

Full-scale input range of V for ratiometric operation, V

for absolute

AA

REF

operation.

AUX2

15:2

If the port is not conﬁgured as an AUXINn input (see AUXGPIOCFG), the

result readback 0x0000 for the unused channel; otherwise, if AUXEN = 0 and

the measurement was skipped during the latest ADC scan, the previously

determined result remain.

Read only.

AUX3REG (0ꢀ5C)

AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

AUX3[13:6]

0x0000

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUX3[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary--Voltage-Measurement Result:

AUXn[13:0] contains the 14-bit measurement result for AUXn.

Full-scale input range of V for ratiometric operation, V

for absolute

AA

REF

operation.

AUX3

15:2

If the port is not conﬁgured as an AUXINn input (see AUXGPIOCFG), the

result readback 0x0000 for the unused channel.; otherwise, if AUXEN = 0 and

the measurement was skipped during the latest ADC scan, the previously

determined result remain.

Read only.

AUX4REG (0ꢀ5D)

AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary-measurement result.

BIT

Field

15

14

13

12

11

10

9

8

AUX4[13:6]

0x0000

Reset

Access Type

Read Only

Maxim Integrated │ 252

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUX4[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary-Voltage-Measurement Result:

AUXn[13:0] contains the 14-bit measurement result for AUXn.

Full-scale input range of V for ratiometric operation, V

for absolute

AA

REF

operation

AUX4

15:2

If the port is not conﬁgured as an AUXINn input (see AUXGPIOCFG), the

result readback 0x0000 for the unused channel; otherwise, if AUXEN = 0 and

the measurement was skipped during the latest ADC scan, the previously

determined result remain.

Read only.

AUX5REG (0ꢀ5E)

AUXn is a read-accessible register that holds the current value for each enabled individual auxiliary-measurement

result.

BIT

Field

15

14

13

12

11

10

9

8

AUX5[13:6]

0x0000

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

–

0

–

AUX5[5:0]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Auxiliary-Voltage-Measurement Result:

AUXn[13:0] contains the 14-bit measurement result for AUXn.

Full-scale input range of V for ratiometric operation, V

for absolute

AA

REF

operation.

AUX5

15:2

If the port is not conﬁgured as an AUXINn input (see AUXGPIOCFG), the

result readback 0x0000 for the unused channel; otherwise, if AUXEN = 0 and

the measurement was skipped during the latest ADC scan, the previously

determined result remain.

Read only.

POLARITYCTRL (0ꢀ5F)

POLARITYCTRL is a read-/write-accessible register that governs the measurement type used during scans. In general,

unipolar mode indicates a cell and bipolar mode indicates a bus bar.

Maxim Integrated │ 253

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIT

Field

15

14

13

12

11

10

9

8

MINMAX-

POL

–

POLARITY[14:9]

Reset

0b0

–

0x0000

Access Type Write, Read

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

POLARITY[8:1]

0x0000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

MIN/MAX Operating Mode:

0 = Only unipolar cell measurements are included in MINCELL, MAXCELL,

and ALRTMSMTCH calculations (default).

MINMAXPOL

15

1 = Only bipolar cell measurements are included in MINCELL, MAXCELL, and

ALRTMSMTCH calculations (useful in fuel cell applications).

Cell-Measurement Polarity Selection:

0 = Unipolar 0 to 5V input range (default)

1 = Bipolar -2.5V to +2.5V input

Bipolar cells are fault masked during BALSWDIAG ADC measurement scans.

MINMAXPOL determines whether bipolar cells are included in MIN/MAXCELL

and ALRTMSMTCH calculations.

POLARITY

13:0

Bipolar cell measurements are checked against BIPOVTH and BIPUVTH

thresholds, rather than OVTH and UVTH thresholds.

Bipolar cells are not included in comparator-measurement scans:

ALRTCOMPOV, ALRTCOMPUV alerts are not triggered.

AUXREFCTRL (0ꢀ60)

AUXREFCTRL is a read-/write-accessible register that governs the reference range used for enabled auxiliary chan-

nels during ADC and COMP acquisition sequences.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

AUXREFSEL[5:4]

0x0

AUXREFSEL[3:0]

0x0

Reset

Access Type

Write, Read, Ext

Maxim Integrated │ 254

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Auxiliary-Input-Reference Selection:

0 = Ratiometric, REF = V

(default)

THRM

1 = Absolute, REF = V

= 2.307V

REF

AUXREFSEL

5:4

This bit selects the reference used and which set of AUX OV, UV, and OPN

thresholds are used during ADC and comparator-acquisition sequences.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still reads back the user setting.

Auxiliary-Input-Reference Selection:

0 = Ratiometric, REF = V

(default)

THRM

1 = Absolute, REF = V

= 2.307V

REF

AUXREFSEL

3:0

This bit selects the reference used and which set of AUX OV, UV, and OPN

thresholds are used during ADC and comparator-acquisition sequences.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still reads back the user setting.

AUXTIMEREG (0ꢀ61)

AUXTIMEREG is a read-/write-accessible register that governs the settling time allowed for biasing AUX/GPIO pins

prior to measurements.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

AUXTIME[9:8]

Reset

–

0x000

Access Type

–

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

AUXTIME[7:0]

Reset

0x000

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Auxiliary Pre-Conversion-Settling TIme:

Conﬁgures the preconversion settling time for all enabled AUXn inputs from

0µs (default) up to 6.138ms according to the equation:

t

= (AUXTIME[9:0]) x 6μs

SETTLE

AUXTIME

9:0

This is to allow extra settling time if the application circuit requires it since the

THRM voltage is not driven out until the start of the acquisition (in auto mode).

This time is inserted at the beginning of each requested scan. If AUXTIME

has not expired, but no other scan measurement is active, the HVCP be

refreshed during the AUXTIME.

Maxim Integrated │ 255

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ACQCFG (0ꢀ62)

ACQCFG is a read-/write-accessible register that governs several aspects of the measurement and acquisition

procedure.

BIT

Field

Reset

15

14

ADCCALEN

0b0

13

12

11

10

9

8

ADCZSF-

SEN

COMPAC-

CEN

FOSR[1:0]

THRMMODE[1:0]

–

0b0

0b00

–

Access Type Write, Read Write, Read Write, Read

Write, Read

BIT

Field

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

End-of-Sequence ADC Stuck-At-Fault Diagnostic Enable:

0 = Disable ADC ZS/FS diagnostics (default)

1 = Enable ADC ZS/FS diagnostics

ADCZSFSEN

ADCCALEN

15

If enabled, at the end of any measurement sequence using the ADC

(SCANCFG ! = 010), the ADC is automatically tested with overdriven inputs de-

signed to force outputs to zero scale and full scale. Any result other than 0x000

or 0xFFF is reported through ALRTADCZS and ALRTADCFS, respectively.

ADC Calibration Enable:

0 = Calibration not applied to scan results

1 = Calibration applied to scan results

Note: Does not impact comparator operations.

14

13

End-of-Sequence Comparator Accuracy Diagnostic Enable:

0 = Disable COMPACC diagnostics (default)

1 = Enable COMPACC diagnostics

If enabled, at the end of any measurement sequence using the comaparator

(SCANCFG = 001 or 010), the comparator automatically be tested with

COMPACCEN

COMP = V

through the LSA2 path (gain = 6/13) and DAC

= V

IN

REF

REF REF

against bracketing thresholds COMPACCOVTHR and COMPACCUVTHR. If

an unexpected result is found, ALRTCOMPACCOV or ALRTCOMPACCUV be

issued.

Oversampling Frequency Selection:

00 = f

01 = f

1x = f

= Frequency determined by selected features

= 1.60kHz, useful for 50Hz rejection

= 1.92kHz, useful for 60Hz rejection

OSR

For ADC and comparator scans, F

sets a speciﬁc eﬀective sampling

OSR

frequency for use with oversampled acquisitions (OVSAMPL > 000). This

FOSR

12:11

can be used to place nulls at n x (f /OSR) to help reject noise at a given

OSR

frequency. For example, with f

= 1.60kHz and OSR = 32, noise at 50Hz

OSR

and its harmonics can be attenuated.

Selection 00 results in an arbitrary but maximum eﬀective sampling frequency

determined solely by the number of channels and diagnostics selected for

measurement, in addition to analog overhead operations (HVCP refresh, etc.).

Worst case is estimated at 2.2kHz with all features enabled.

Maxim Integrated │ 256

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Thermistor Bias Control Mode:

Controls application of V to the THRM pin through the internal switch, to

AA

bias external thermistors for measurement.

0x = Automatic mode (switch ON during acquisition mode)

10 = Manual oﬀ mode (switch always OFF)

11 = Manual on mode (switch always ON)

THRMMODE

10:9

BALSWDLY (0ꢀ63)

BALSWDLY is a read-/write-accessible register that selects the delay intervals used within manual and automated cell-

balancing operations when ADC measurements are requested.

BIT

Field

15

14

13

12

11

10

9

8

CELLDLY[7:0]

Reset

0x00

Access Type

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

SWDLY[7:0]

0x00

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Cell-Path Recovery-Delay Selection:

Time delay for C[n] (HVMUX) recovery from voltage drop during cell balancing

prior to ADC measurement.

Values of 0μs (default) to 24.480ms can be realized (96μs step size).

This delay is used in manual Cell-Balancing modes when using

AUTOBALSWDIS = 1 and ALTMUXSEL = 0. Also used in automatic cell

balancing and Discharge modes after each pair of even and odd discharge

cycles when CBMEASEN = 1x and ALTMUXSEL = 0.

CELLDLY

15:8

Cell-Balancing Switch-Path Recovery-Delay Selection:

Time delay for SW[n] (ALTMUX) recovery from voltage drop during cell

balancing prior to ADC Measurement.

Values of 0μs (default) to 24.480ms can be realized (96μs step size).

This delay is used in manual Cell-Balancing modes when using

AUTOBALSWDIS = 1 and ALTMUXSEL = 1. Also used in automatic cell

balancing and discharge modes after each pair of even and odd discharge

cycles when CBMEASEN = 1x and ALTMUXSEL = 1.

SWDLY

7:0

Maxim Integrated │ 257

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

MEASUREEN1 (0ꢀ64)

MEASUREEN1 is a read-/write-accessible register that governs the channels measured during ADC and COMP acqui-

sition sequences.

BIT

Field

15

–

14

13

12

11

10

9

8

BLOCKEN

0b0

CELLEN[14:9]

Reset

–

0x0000

Access Type

–

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

CELLEN[8:1]

Reset

0x0000

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Block-Voltage-Measurement Enable:

0 = Disable VBLK/TOPBLOCK measurement and automatic divider

connection (default)

1 = Enable VBLK/TOPBLOCK measurement and automatic divider connection

Applies to ADC scans only; block is not subject to comparator measurements.

In addition to enabling the ADC measurement, BLOCKEN automatically engage

the VBLOCK resistive divider for the duration of the scan.

BLOCKEN

14

Note: In FLXPCKEN1/2 applications (FLXPCKEN = 1), the resistive divider is

connected to a selected Cn pin, and the resulting bias current impact the Cn

result. Therefore, in Flex Pack applications, it is generally recommended to set

BLOCKEN = 1 only for scans with ALTMUXSEL = 1.

Cell-Voltage-Measurement Enable:

0 = Disable CELLn measurement (default)

1 = Enable CELLn measurement

CELLEN

13:0

Enables measurement of the respective cell in the acquisition mode.

MEASUREEN2 (0ꢀ65)

MEASUREEN2 is a read-/write-accessible register that governs the auxiliary channels measured during ADC and

COMP acquisition sequences, as well as IIR initialization.

BIT

Field

Reset

15

14

13

12

11

10

9

8

SCANI-

IRINIT

–

0b0

–

Access Type Write, Read

BIT

Field

7

–

6

–

5

4

3

2

1

0

AUXEN[5:4]

0x0

AUXEN[3:0]

0x0

Reset

Access Type

Write, Read, Ext

Maxim Integrated │ 258

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Sequencer IIR Initialization Request:

0 = IIR ﬁlter continuation (default)

1 = IIR ﬁlter initialized

In continuation mode, the current value in the IIR accumulators is kept

(presumably from previous cell measurements) and sequencer

measurements are amended normally.

SCANIIRINIT

15

In Initialization mode, the IIR accumulators be reinitialized to the ﬁrst

measurement taken, and further cell-balancing measurements are amended

normally.

Auxiliary-Input-Measurement Enable:

0 = Auxiliary ADC measurement disabled (default)

1 = Auxiliary ADC measurement enabled

Enables measurement of the respective auxiliary inputs in acquisition mode.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still reads back the user setting.

AUXEN

5:4

3:0

Auxiliary-Input-Measurement Enable:

0 = Auxiliary ADC measurement disabled (default)

1 = Auxiliary ADC measurement enabled

Enables measurement of the respective auxiliary inputs in acquisition mode.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still reads back the user setting.

AUXEN

SCANCTRL (0ꢀ66)

SCANCTRL is a read-/write-accessible register that governs the internal measurement acquisitions (scan) requested of

the device. The register also manages the handling of data generated as a result of any scan request.

ADC Scans are used for precision measurements of cell and auxiliary voltages.

COMP Scans are used for periodic safety/redundancy checking of ADC results, and in some cases, enhanced commu-

nication efficiency.

On Demand Calibration run an internal calibration of the ADC and update the Calibration Data Registers. All ADC mea-

surements requested by Scan and Diagnostic Configuration and Control settings be ignored.

Balance Switch and Cell Sense Wire Open ADC Diagnostic Scans are a special class of ADC Scan. Use of these set-

tings temporarily override other Scan and Diagnostic Configuration and Control settings. See BALSW and Cell Sense

Wire Open Diagnostics for details.

BIT

15

14

13

DATARDY

0b0

12

11

10

AMENDFILT

0b0

9

8

SCAN-

DONE

SCANTIME-

OUT

AUTO-

BALSWDIS

ALRTFILT-

SEL

SCAN-

CFG[2]

Field

RDFILT

0b0

Reset

0b0

0b000

Write 0 to

Clear, Read Clear, Read

Write 0 to

Write, Read,

Ext

Access Type

Write, Read Write, Read Write, Read Write, Read Write, Read

BIT

Field

7

6

5

4

3

2

1

0

ALTMUX-

SEL

SCAN-

MODE

SCANCFG[1:0]

0b000

OVSAMPL[2:0]

0b000

SCAN

0b0

Reset

0b0

Write, Read,

Pulse

Access Type

Write, Read

Write, Read Write, Read

Maxim Integrated │ 259

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Acquisition-Complete-Indicator Bit:

0 = Indicates a SCAN acquisition is in progress if requested

1 = Indicates the SCAN acquisition has completed

SCANDONE

15

Once a SCAN acquisition has completed, the device set this bit high to

indicate completion.

This bit is cleared by writing to zero. When this bit is high, further acquisitions

requested using SCAN are ignored. Writing to logic one has no internal eﬀect.

Scan-Timeout-Indicator Bit:

Indicates the acquisition did not complete in the expected period of time. The

timeout threshold depends on the oversampling conﬁguration.

If a SCANTIMEOUT is issued, the resulting partial data should be treated as

suspect and ignored. In applications using the IIR, SCANIIRINIT should be

issued to avoid any corruption resulting from the timeout event.

The acquisition watchdog can be disabled by setting SCANTODIS in the

DEVCFG2 register.

SCANTIMEOUT

14

Cleared by writing to logic zero to allow detection of future timeout events.

Writing to logic one has no internal eﬀect.

Data-Ready Indicator Bit:

Indicates the measurement data from the acquisition has been transferred

from the ALU to the data registers and may now be read. Data for all mea-

surement registers and MIN/MAX/TOTAL is transferred at the same time.

Cleared by writing to logic zero to allow detection of the next data transfer.

Writing to logic one has no internal eﬀect.

DATARDY

13

Automatic Balancing-Switch Disable:

0 = Cell-balance operations not impacted by measurement sequences

(default)

1 = Cell-balance manual operations temporarily disabled during measurement

sequences

Enables automatic suspension of active manual cell-balancing operations

during measurement sequences.

AUTOBALSWDIS

12

The delay for cell-recovery settling time and for the diagnostic recovery is

selected automatically based on the ALTMUXSEL setting for the sequence as

follows:

0 = CELLDLY is used

1 = SWDLY is used

Alert-Filtering Selection:

0 = Alert issuance based on raw sequencer results (default)

1 = Alert issuance based on IIR ﬁlter results

Determines whether the cell and block alerts are issued based on raw

sequencer outputs (oversampling still applies) or IIR ﬁltered outputs.

If mode 1 is selected, MEASUREEN2:SCANIIRINIT should be used with the

ﬁrst scan to avoid triggering false alerts due to the IIR settling behavior.

Note: This bit is ignored for measurement scans taken in automated Cell-

Balancing modes (ALRTFILTSEL = 1 is used).

ALRTFILTSEL

11

Maxim Integrated │ 260

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Amend-IIR Filter Enable:

0 = ADC result is not included in the IIR accumulator (default)

1 = ADC result is included in the IIR accumulator

When set high, for ADC outputs that have IIR ﬁlters/accumulators, the new

ADC conversion in the ALU is automatically scaled and transferred into the

IIR accumulator at the end of the sequence. This is often used for normal-

measurement sequences.

AMENDFILT

10

When set low, the new ADC conversion in the ALU is not transferred into the

IIR accumulator at the end of the sequence. This is often used for diagnostic-

measurement sequences where the ADC result would corrupt the settled

normal data.

Note: This bit is ignored for measurement scans taken in automated Cell-

Balancing modes (AMENDFILT = 1 is used).

Read-IIR Filter Selection:

0 = Unﬁltered ADC data is loaded into the output data registers (default)

1 = Filtered ADC data is loaded into the output data registers

This bit chooses the source for data loaded to the CELLnREG and

BLOCKREG registers for read back. The setting of this bit at the time of a

measurement scan request (SCAN = 1) also determines the source data

(ﬁltered/unﬁltered) used for TOTAL, MINCELL, MAXCELL, MSMTCH, and all

OV/UV alert computations.

RDFILT

9

Scan Conﬁguration:

Selects the type of scan to be performed based on the selections below.

FOSR selection applies to all scans where oversampling applies.

000 = ADC-only scan

001 = ADC+COMP scan (Pyramid only)

010 = COMP-only scan (Pyramid only)

011 = On-demand calibration

100 = Balancing switch short

101 = Balancing switch open

110 = Cell sense open odds

111 = Cell sense open evens

SCANCFG

8:6

Some of these selections are formatted by other register content. Some

selections temporarily modify/override other register content. See register

descriptions for further details.

For COMP scans, polarity is always defaulted to unipolar; any cell

measurements requested in bipolar mode are skipped.

On-demand calibration executes an automated routine that updates the

contents of the CALOSADC, CALOSR, CALOSTHRM, CALGAINP, and

CALGAINR correction coeﬃcients. No other measurements are taken during

this operation.

Note: This bitﬁeld is ignored for measurement scans taken in automated Cell-

Balancing modes (SCANCFG = 000 is used).

Maxim Integrated │ 261

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Oversampling Selection for ADC Acquisitions:

000 = Single acquisition

001 = 4x oversampling

010 = 8x oversampling

011 = 16x oversampling

OVSAMPL

5:3

100 = 32x oversampling

101 = 64x oversampling

11x = 128x oversampling

Note: This bitﬁeld is ignored during calibration (SCANCFG = 011) scans.

This bitﬁeld is ignored for measurement scans taken in automated cell-

balancing modes (OVSAMPL = 011 is used).

Cell-Measurement Path Selection:

0 = HVMUX signal path (default)

1 = ALTMUX signal path

See the Diagnostics section.

Note: Where ALTMUX settings disagree with SCANCFG (BALSWDIAG),

SCANCFG takes precedence.

ALTMUXSEL

SCANMODE

2

1

ADC-Scan Mode Selection:

0 = Pyramid scan mode (default)

1 = Ramp scan mode

Ramp scan mode is not supported for scans using the comparator or

calibration scan requests (the setting is ignored in these modes).

Note: This bit is ignored for measurement scans taken in automated Cell-

Balancing modes (SCANMODE = 0 is used).

Scan (Measurement Sequence) Request:

0 = Used to initiate a data transfer and/or set up measurement conditions

without initiating a measurement sequence

1 = Used to request a new measurement sequence (scan) and initiate a data

transfer

Acts as a strobe bit and therefore does not need to be cleared (self-clearing).

Always reads logic zero. Writes to SCANCTRL with SCAN = 1 requesting new

scans are ignored if a scan is already in progress, or if SCANDONE is high. In

this case, the content written to SCANCTRL[15:1] is accepted but the conﬂict-

ing scan will not be executed and ALRTRJCT be issued, notifying the user of

the conﬂict.

SCAN

0

Note: The intended use of this bit is to enter/exit BALSWDIAG modes using

SCANCFG, and allow the alternate conditions to settle prior to requesting the

measurement (with a subsequent write to SCANCRTL with SCAN = 1).

This bit can also be used to realize a variety of data-move options (see

DBLBUFEN and RDFILT for details), or to clear SCANDONE, SCANTIMEOUT,

and DATARDY bits without requesting a measurement sequence/scan.

ADCTEST1AREG (0ꢀ67)

ADCTEST1A is a read-/write-accessible register that contains user-specified arguments used in ALU diagnostics.

BIT

Field

Reset

15

ADCTSTEN

0b0

14

–

13

–

12

–

11

10

9

8

ADCTEST1A[11:8]

0x000

–

Access Type Write, Read

–

Write, Read

Maxim Integrated │ 262

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIT

Field

7

6

5

4

3

2

1

0

ADCTEST1A[7:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

ADC/ALU Self-Test Mode Enable:

0 = Normal operation (default)

1 = Enables the ALU test mode

This mode feeds 12-bit data from the ADCTEST registers directly into the ALU

instead of the ADC-conversion data. Scans can then be performed, conﬁrming

proper operation of the ALU and calibration MAC.

ADCTSTEN

15

Notes: No calibration coeﬃcients are applied to ensure deterministic results

(gain =1.0, oﬀset = 0.0).

ADCTESTEN is ignored for on-demand calibration scans (SCANCFG = 011) to

avoid miscalibration, and all scans performed during automated Cell-Balancing

modes to avoid inaccurate balancing results.

ALU ADC Input Argument 1A:

User-speciﬁed test data for the ALU diagnostic (ADCTESTEN = 1). This 12-bit

data is fed into the ALU during the ﬁrst conversion of odd-numbered samples

(e.g., ﬁrst sample).

ADCTEST1A

11:0

ADCTEST1BREG (0ꢀ68)

ADCTEST1B is a read-/write-accessible register that contains user-specified arguments used in ALU diagnostics.

BIT

Field

15

–

14

–

13

–

12

–

11

10

9

8

0

ADCTEST1B[11:8]

0x000

Reset

–

Access Type

–

Write, Read

BIT

Field

7

6

5

4

3

2

1

ADCTEST1B[7:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

ALU ADC Input Argument 1B:

User-speciﬁed test data for the ALU diagnostic (ADCTEST = 1). This 12-

bit data is fed into the ALU during the second conversion of odd-numbered

samples (e.g., ﬁrst sample).

ADCTEST1B

11:0

Maxim Integrated │ 263

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ADCTEST2AREG (0ꢀ69)

ADCTEST2A is a read-/write-accessible register that contains user-specified arguments used in ALU diagnostics.

BIT

Field

15

–

14

–

13

–

12

–

11

10

9

8

ADCTEST2A[11:8]

0x000

Reset

–

Access Type

–

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

ADCTEST2A[7:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

ALU ADC Input Argument 2A:

User-speciﬁed test data for the ALU diagnostic (ADCTEST = 1). This 12-bit

data is fed into the ALU during the ﬁrst conversion of even-numbered samples

in oversampling mode.

ADCTEST2A

11:0

ADCTEST2BREG (0ꢀ6A)

ADCTEST2B is a read-/write-accessible register that contains user-specified arguments used in ALU diagnostics.

BIT

Field

15

–

14

–

13

–

12

–

11

10

9

8

0

ADCTEST2B[11:8]

0x000

Reset

–

Access Type

–

Write, Read

BIT

Field

7

6

5

4

3

2

1

ADCTEST2B[7:0]

0x000

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

ALU ADC Input Argument 2B:

User-speciﬁed test data for the ALU diagnostic (ADCTEST = 1). This 12-bit

data is fed into the ALU during the second conversion of even-numbered

samples in oversampling mode.

ADCTEST2B

11:0

Maxim Integrated │ 264

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

DIAGCFG (0ꢀ6B)

DIAGCFG is a read-/write-accessible register that governs diagnostic source and mode options applied to the internal

measurement acquisitions (scans).

BIT

15

14

13

12

11

CTSTSRC

0b0

10

9

8

MUXDIAG-

BUS

MUXDIAG-

PAIR

Field

CTSTDAC[3:0]

MUXDIAGEN

0b0

Reset

0x0

0b0

Access Type

Write, Read

Write, Read Write, Read Write, Read Write, Read

BIT

Field

7

6

5

4

3

2

1

0

DIAGSEL2[3:0]

0x0

DIAGSEL1[3:0]

0x0

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Current-Level Conﬁguration for All Enabled Test Sources:

Per the table below (6.25µA LSB for Cn, AUXIN, 3.125µA LSB for HVMUX)

CTSTDAC

[3:0]

0x0

TEST SOURCE

Cn, AUXIN

6.25µA

CURRENT

HVMUX

3.125µA

6.250µA

9.375µA

...

0x1

12.50µA

18.75µA

...

CTSTDAC

15:12

0x2

...

0xD

87.5µA

43.75µA

46.875µA

50µA

0xE

93.75µA

100µA

0xF

Test Current-Source Polarity:

0 = Sink current to GND (default)

CTSTSRC

11

10

9

1 = Source current from V

AA

Note: Polarity selection applies to AUX test current sources only.

Selects the HVMUX output to which the HVMUX test current source is connected,

if MUXDIAGPAIR is enabled:

0 = Output used for even cells, C0, and AGND

MUXDIAGBUS

MUXDIAGPAIR

1 = Output used for odd cells, REF, and ALTREF

MUX Diagnostic Bus Conﬁguration:

0 = Both HVMUX test-current sources are connected to both HVMUX outputs (default)

1 = A single HVMUX test-current source is connected to only one HVMUX output (as

selected by MUXDIAGBUS)

HVMUX Test-Current Source(s) Enable:

0 = Disable (default)

MUXDIAGEN

8

1 = Enable

The current level is conﬁgured by CSTDAC and the connectivity is conﬁgured by

MUXDIAGPAIR and MUXDIAGBUS

Maxim Integrated │ 265

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Acquisition Diagnostic2-Measurement Selection:

0000 = No diagnostic requested

0001 = Die temperature (ADC = V

, ADC

= V

REF

)

IN

PTAT

REF

0010 = V (ADC = V

through LSAmp, ADC

= V

)

AA

IN

REF

AA

0011 = Cell signal-path ADC fault, V

(ADC = V

through LSAmp,

ALTREF

IN

ALTREF

ADC

= V

)

REF

0100 = Comparator-cell signal-path fault (ADC = V

through LSAmp2 - V

at

DAC

IN

REF

DAC

= 0x1D8 (6/13), ADC

= DAC

= V

, bipolar mode)

CODE

REF

0101 = Cell calibration (ADC = V

through LSAmp, ADC

= V

), calibration

IN

REF

gain and oﬀset coeﬃcients and chopping applied according to SCANMODE selection.

0110 = Oﬀset calibration (ADC = Short (Pyramid) or ADC = Short through LSAmp

IN

(Ramp), ADC

= V

, bipolar mode), calibration oﬀset coeﬃcients applied

REF

according to SCANMODE selection.

0111 = 3/4-scale DAC test (DAC = 0x2FF ADC = V

, ADC

= DAC

= V

).

IN

DAC

REF

1000 = 1/4-scale DAC test (DAC = 0x100 ADC = V

IN

REF

DIAGSEL2

7:4

1001 = THRM oﬀset calibration (ADC = Short, ADC

= V

, bipolar mode),

IN

REF

THRM

CALOSTHRM coeﬃcient applied.

Selects the second diagnostic measurement appended to the acquisition, with the result

stored in DIAG2. Appropriate calibrations (or factory defaults if ADCALEN = 0) and chop-

ping are applied as needed.

Detailed Diagnostics:

1010 = Zero-scale ADC test (0x0000, ADC = -V , ADC

= V

, bipolar mode),

IN

AA

REF

full result available through DIAG.

1011 = Full-scale ADC test (0x3FFC, ADC = V , ADC

= V

, bipolar mode), full

IN

AA

REF

result available through DIAG.

1100 = LSAMP oﬀset (ADC = V

, ADC

= V

, bipolar mode)

IN

LSA_0V

REF

Detailed diagnostics are normally performed at the end of an acquisition (with the

exception of LSAMP oﬀset, which is covered by the V diagnostic), and the

ALTREF

pass/fail results are available in the FMEA2 BIST alerts; however, if necessary to

examine detailed results, these can be made available in the DIAG2 register using the

modes above.

Maxim Integrated │ 266

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Acquisition Diagnostic1-Measurement Selection:

0000 = No diagnostic requested

0001 = Die temperature (ADC = V

, ADC

= V

REF

)

IN

PTAT

REF

0010 = V (ADC = V

through LSAmp, ADC

= V

)

AA

IN

REF

AA

0011 = Cell signal-path ADC fault, V

(ADC = V

through LSAmp,

ALTREF

IN

ALTREF

ADC

= V

)

REF

0100 = Comparator-cell signal-path fault (ADC = V

through LSAmp2 - V

at

DAC

IN

= DAC

REF REF

REF

DAC

= 0x1D8 (6/13), ADC

CODE

V

, bipolar mode)

REF

0101 = Cell calibration (ADC = V

through LSAmp, ADC

= V

). Calibration

IN

REF

gain and oﬀset coeﬃcients and chopping applied according to SCANMODE selection.

0110 = Oﬀset calibration (ADC = Short (Pyramid) or ADC = Short through LSAmp

IN

(ramp), ADC

= V

, bipolar mode). Calibration oﬀset coeﬃcients applied accord-

REF

ing to SCANMODE selection.

DIAGSEL1

3:0

0111 = 3/4-scale DAC test (DAC = 0x2FF, ADC = V

, ADC

= DAC

= V

)

IN

DAC

REF

1000 = 1/4-scale DAC test (DAC = 0x100, ADC. = V

, ADC

= DAC

= V

)

IN

DAC

REF

1001 = THRM oﬀset calibration (ADC = short, ADC

= V

, bipolar mode)

IN

REF

THRM

CALOSTHRM coeﬃcient applied.

Selects the ﬁrst diagnostic measurement appended to the acquisition, with the result

stored in DIAG1. Appropriate calibrations (or factory defaults if ADCALEN = 0) and

chopping are applied as needed.

Detailed Diagnostics:

1010 = Zero-scale ADC test (0x0000, ADC = -V , ADC

= V

, bipolar mode),

IN

AA

REF

full result available through DIAG

1011 = Full-scale ADC test (0x3FFC, ADC = V , ADC

= V

, bipolar mode),

IN

AA

REF

full result available through DIAG

1100 = LSAMP oﬀset (ADC = V

, ADC

= V

bipolar mode)

IN

LSA_0V

REF

REF.

Detailed diagnostics are normally performed at the end of an acquisition (with the

exception of LSAMP oﬀset, which is covered by the V diagnostic), and the

ALTREF

pass/fail results are available in the FMEA2 BIST alerts; however, if it is necessary to

examine detailed results, these can be made available in the DIAG1 register using the

modes above.

Maxim Integrated │ 267

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

CTSTCFG (0ꢀ6C)

CTSTCFG is a read-/write-accessible register that controls the application of diagnostic current sources to selected cell

input channels.

BIT

Field

Reset

15

14

13

12

11

10

9

8

CEL-

LOPNDIAG-

SEL

CTSTEN[14:8]

0b0

0x0000

Access Type Write, Read

Write, Read

BIT

Field

7

6

5

4

3

2

1

0

CTSTEN[7:0]

Reset

0x0000

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

Cell Open-Diagnostic-Mode Selection:

0 = Normal operation (default)

1 = Open-diagnostic operation

In normal mode (0), measured CELLn channels are selected by CELLEN and

measured with standard thresholds on a per-channel basis for both ADC and

comparator-acquisition sequences.

In open-diagnostic mode (1), measured CELLn channels are selected by

(CELLENn & !POLARITYn), on a per-channel basis. Only low-side comparator

checks are performed using alternate-open (OPN) thresholds.

Normally, in open-diagnostic modes, pulldown current sources are enabled on

all measured channels using CTSTEN, and only comparator measurements

are selected (SCANCFG = 010).

CELLOPNDIAGSEL

15

This mode is most often used with an appropriate auxiliary open-diagnostic

mode (AUXDIAGSEL = 010 or 011).

Cell Diagnostic-Current-Source Enable:

Enables the current sources connected to the corresponding cell inputs for

diagnostic testing. The current level is conﬁgured by the CTSTDAC in the

DIAGCFG register.

CTSTEN

14:0

Maxim Integrated │ 268

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

AUXTSTCFG (0ꢀ6D)

AUXTSTCFG is a read-/write-accessible register that controls the application of diagnostic modes and current sources

to selected auxiliary input channels.

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

Reset

–

Access Type

–

BIT

Field

7

–

6

–

5

4

3

2

1

0

AUXTSTEN[5:4]

0x0

AUXTSTEN[3:0]

0x0

Reset

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Auxiliary-Diagnostic Current-Source Enable:

Enables the current source connected to the corresponding auxiliary input for

diagnostic testing. The current level is conﬁgured by DIAGCFG:CTSTDAC

and the current direction is conﬁgured by DIAGCFG:CTSTSRC.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored but

still reads back the user setting.

AUXTSTEN

5:4

Auxiliary-Diagnostic Current-Source Enable:

Enables the current sources connected to the corresponding auxiliary input

for diagnostic testing. The current level is conﬁgured by DIAGCFG:CTSTDAC

and the current direction is conﬁgured by DIAGCFG:CTSTSRC.

Note: If the respective GPIOEN bit is set (GPIO mode), this bit is ignored, but

still reads back the user setting.

3:0

DIAGGENCFG (0ꢀ6E)

DIAGGENCFG is a read-/write-accessible register that controls the application of general diagnostic modes to the

selected auxiliary input paths.

BIT

Field

15

14

13

12

–

11

–

10

–

9

–

8

–

AUXDIAGSEL[2:0]

0b000

Reset

–

Access Type

Write, Read

–

BIT

Field

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

Reset

Access Type

Maxim Integrated │ 269

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

AUX Diagnostic Mode Selection:

00x = Normal operation (default)

010 = AUX accelerated discharge operation (ratio metric only)

011 = THRM output connected to AGND

100 = Reserved for Maxim Use Only

AUXDIAGSEL

15:13

101 = Reserved for Maxim Use Only

110 = Reserved for Maxim Use Only

111 = Reserved for Maxim Use Only

Control bits used for AUXINn pin diagnostic testing. Only to ports conﬁgured

as AUX inputs are tested.

BALSWCTRL(0ꢀ6F)

BALSWCTRL is a read-/write-accessible register that governs the behavior of the charge-balacing switches in manual

and automated cell-balacing modes.

Write access to this register is blocked during automated cell-balacing operations (CBMODE = 001, 1xx).

BIT

15

14

13

12

11

10

9

8

CBRE-

START

Field

–

BALSWEN[14:9]

0x0000

Reset

0b0

–

Write, Read,

Pulse

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

BALSWEN[8:1]

0x0000

Reset

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Maxim Integrated │ 270

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Watchdog Timer Restart for Manual Mode:

0 = CBTIMER continues to run

1 = CBTIMER is reset to zero

Acts as a strobe bit and therefore does not need to be cleared. Always reads

logic zero.

CBRESTART

15

Accessible and applies in manual mode only.

Writing 1 to CBRESTART after cell-balancing timer expiration has no eﬀect.

To perform another manual-mode cell-balancing event, user must issue a

separate write to the BALCTRL register.

Balance-Switch Enable:

BALSWEN

13:0

BALSWEN[n] enables the balancing switch (allowing conduction) between

SWn and SWn-1, balancing CELLn.

BALEXP1 (0ꢀ70)

BALEXPn is a read-/write-accessible register that holds the cell-balacing expiration time for CELLn (using the switch

across SWn and SWn-1).

BALEXP1 sets the expiration time for all group automated cell-balancing and discharge modes and the watchdog time-

out for manual cell-balacing mode.

Write access to this register is blocked during all cell-balancing operations (CBMODE! = 000).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP1[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP1[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP1

9:0

CBEXP1 is used as the master/watchdog timeout setting for manual,

discharge, and automated group Cell-Balancing modes.

Value 0x3FF operates balancing indeﬁnitely (no timer expiration). Default

value 0x000 disables cell balancing (preconﬁgured timer expiration).

Maxim Integrated │ 271

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALEXP2 (0ꢀ71)

BALEXP2 is a read-/write-accessible register that holds the cell-balacing expiration time for CELLn (using the switch

across SWn and SWn-1). Used in individual Auto Cell-Balancing modes only.

Write access to this register is blocked during automated cell-balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP2[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP2[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP2

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

BALEXP3 (0ꢀ72)

BALEXP3 is a read-/write-accessible register that holds the cell-balacing expiration time for CELLn (using the switch

across SWn and SWn-1). Used in individual auto Cell-Balancing modes only.

Write access to this register is blocked during automated cell-balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP3[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP3[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP3

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

Maxim Integrated │ 272

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALEXP4 (0ꢀ73)

BALEXP4 is a read-/write-accessible register that holds the cell-balancing expiration time for CELLn (using the switch

across SWn and SWn-1). Used in individual automated Cell-Balancing modes only.

Write access to this register is blocked during automated cell-balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP4[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP4[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP4

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

BALEXP5 (0ꢀ74)

BALEXP5 is a read-/write-accessible register that holds the Cell-Balacing-Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Auto-Cell Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP5[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP5[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP5

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

Maxim Integrated │ 273

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALEXP6 (0ꢀ75)

BALEXP6 is a read-/write-accessible register that holds the Cell-Balacing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP6[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP6[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP6

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

BALEXP7 (0ꢀ76)

BALEXP7 is a read-/write-accessible register that holds the Cell-Balacing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP7[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP7[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP7

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

Maxim Integrated │ 274

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALEXP8 (0ꢀ77)

BALEXP8 is a read-/write-accessible register that holds the Cell-Balacing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP8[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP8[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP8

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

BALEXP9 (0ꢀ78)

BALEXP9 is a read-/write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP9[9:8]

0x000

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP9[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP9

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

Maxim Integrated │ 275

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALEXP10 (0ꢀ79)

BALEXP10 is a read-/write-accessible register that holds the Cell-Balancing Expiration Time for CELLn (using the

switch across SWn and SWn-1).Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP10[9:8]

Reset

–

0x000

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP10[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration tme for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP10

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

BALEXP11 (0ꢀ7A)

BALEXP11 is a read-/write-accessible register that holds the Cell-Balacing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP11[9:8]

Reset

–

0x000

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP11[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP11

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

Maxim Integrated │ 276

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALEXP12 (0ꢀ7B)

BALEXP12 is a read-/write-accessible register that holds the Cell-Balacing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP12[9:8]

Reset

–

0x000

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP12[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP12

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

BALEXP13 (0ꢀ7C)

BALEXP13 is a read-/write-accessible register that holds the Cell-Balacing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP13[9:8]

Reset

–

0x000

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP13[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or

second) determined by CBMODE.

CBEXP13

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

Maxim Integrated │ 277

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALEXP14 (0ꢀ7D)

BALEXP14 is a read-/write-accessible register that holds the Cell-Balacing Expiration Time for CELLn (using the switch

across SWn and SWn-1). Used in Individual Automated Cell-Balancing modes only.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBEXP14[9:8]

Reset

–

0x000

Access Type

–

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

0

CBEXP14[7:0]

Reset

0x000

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Expiration Time:

Cell-balancing expiration time for CELLn; unit (LSB = hour, minute, or second)

determined by CBMODE.

CBEXP14

9:0

Value 0x3FF operates balancing indeﬁnitely (no timer expiration).

Default value 0x000 disables cell balancing (preconﬁgured timer expiration).

BALAUTOUVTHR (0ꢀ7E)

BALAUTOUVTHR is a read-/write-accessible register that selects the cell undervoltage exit threshold for the ADC

when used in Automated Cell-Balancing operations.

A write to this register allows direct setting or automatic selection of this threshold.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 1xx). Also, during

active measurement scans, all writes with CBUVMINCELL = 1 will be blocked and result in ALRTRJCT being issued

(since the MINCELL data may be altered as a result of the scan in progress).

A read from this register displays the current value of the threshold and the method used for its selection.

BIT

Field

15

14

13

12

11

10

9

8

CBUVTHR[13:6]

0x3FFF

Reset

Access Type

Write, Read, Ext

BIT

Field

7

6

5

4

3

2

1

–

0

CBUVMIN-

CELL

CBUVTHR[5:0]

Reset

0x3FFF

0b0

Write, Read,

Ext

Access Type

Write, Read, Ext

Maxim Integrated │ 278

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Undervoltage Threshold

14-bit ADC threshold, of a 5V input range, below which Cell Balancing Operations

are suspended on each CELL.

CBUVTHR

15:2

Default of 0x3FFF, ensures no cell balancing occur without prior conﬁguration.

Cell Balancing Undervoltage Threshold Selection

0 = User-Deﬁned CBUVTHR

1 = MINCELL-Deﬁned CBUVTHR

In mode 0, the value written to CBUVTHR during a valid write to

BALAUTOUVTHR be loaded to CBUVTHR.

CBUVMINCELL

0

In mode 1, the current value in the CELLn register corresponding to the

MINCELL address be automatically loaded to CBUVTHR during a valid write to

BALAUTOUVTHR (and the content in CBUVTHR during the write be ignored).

Note: Automated Cell Balancing with CBUVTHR checking is only supported for

unipolar cell measurements. If CBUVMINCELL = 1 is written while

MINMAXPOL = 1, CBUVTHR be set to 0x3FFF\h as a result.

BALDLYCTRL (0ꢀ7F)

BALDLYCTRL is a read-/write-accessible register that selects the delay/timing intervals used within Automated Cell-

Balancing operations.

Write access to this register is blocked during Automated Cell-Balancing operations (CBMODE = 001, 1xx).

BIT

Field

15

–

14

–

13

–

12

–

11

–

10

–

9

8

CBNTFYCFG[1:0]

0b00

Reset

–

Access Type

–

Write, Read, Ext

BIT

Field

7

–

6

–

5

–

4

–

3

–

2

1

0

CBCALDLY[2:0]

0b000

Reset

Access Type

Write, Read, Ext

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Notiﬁcation Alert Conﬁguration:

00 = Disable cell-balancing notiﬁcation alert (default)

01 = Notiﬁcation issued every 1 Hr

10 = Notiﬁcation issued every 2 Hrs

11 = Notiﬁcation issued every 4 Hrs

In automated and discharge modes, the cell-balancing notiﬁcation alert

CBNTFYCFG

9:8

(ALRTCBNTFY) can be issued to conﬁrm normal progression of automated

operations. The frequency of issuance is selected as described above, in real

time (i.e., not CBDUTY adjusted). Notiﬁcation alerts continue to be issued

during HOLDSHDNL.

Maxim Integrated │ 279

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Calibration Period Selection:

In automated and discharge modes, after each pair of even and odd cell-

balancing periods, a supervisory ADC measurement is taken (and checked

against CBUVTHR, if enabled/applicable).

CBCALDLY allows a calibration operation to be substituted in place of a mea-

surement at the frequency indicted below. A value of 000 (default) disables

CAL operations (only ADC operations are performed).

000 = Periodic calibration disabled

CBCALDLY

2:0

001 = 2 (every other) cycle

010 = 4 (every forth) cycle

011 = 8 cycles

100 = 12 cycles

101 = 16 cycles

110 = 24 cycles

111 = 32 cycles

If CBMEASEN = 0x (ADC/CAL measurements disabled), this bitﬁeld is ig-

nored and has no eﬀect.

BALCTRL (0ꢀ80)

BALCTRL is a read-/write-accessible register that initiates and controls all internal Cell-Balancing modes and

operations.

Any write to this register to a mode other than CBMODE = 000 (disable) restarts the CBTIMER at zero and launches

the requested mode of operation.

BIT

Field

15

14

13

12

11

10

9

8

CBACTIVE[1:0]

CBMODE[2:0]

0b000

CBIIRINIT

0b0

HOLDSHDNL[1:0]

0b00

Reset

0b00

Access Type

Read Only

Write, Read, Ext

Write, Read

BIT

7

6

5

4

3

2

1

0

CBDONE-

ALRTEN

Field

CBDUTY[3:0]

CBTEMPEN

0b0

CBMEASEN[1:0]

Reset

0x0

0b0

0x0

Access Type

Write, Read

Write, Read Write, Read

Write, Read

BITFIELD

BITS

DESCRIPTION

Cell Balancing Timer Active Indicator:

00 = Cell balancing is disabled (default)

01 = Cell balancing operations are active

10 = Cell balancing completed normally due to reaching CBUVTHR or CBEXP

exit conditions

CBACTIVE

15:14

11 = Cell balancing halted unexpectedly due to thermal exit (ALRTCBTEMP),

timeout (ALRTCBTIMEOUT), or calibration fault (ALRTCBCAL) conditions

Read only.

Maxim Integrated │ 280

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell Balancing Mode Selection

000 = Cell Balancing Disabled (default)

001 = Emergency/EOL Discharge by Hour

010 = Manual Cell Balancing by Second

011 = Manual Cell Balancing by Minute

100 = Auto Individual Cell Balancing by Second

101 = Auto Individual Cell Balancing by Minute

110 = Auto Group Cell Balancing by Second

111 = Auto Group Cell Balancing by Minute

CBMODE

13:11

Cell Balancing IIR Initialization Request

0 = IIR Filter Continuation (default)

1 = IIR Filter Initialized

CBIIRINIT

10

If enabled, the IIR ﬁlter contents be initialized during the ﬁrst measurement

scan and CBUVTHR checks be suspended for 16 measurement scans, giving

the IIR time to settle.

SHDNL Hold Mode Enable

00 = No Hold (default)

01 = SHDNL Held High for the duration of Automated Cell Balancing or Dis-

charge operation

HOLDSHDNL

9:8

10 = SHDNL Held High for duration of Automated Cell Balancing or Discharge

operations, plus 5 minutes or 6.25% of the maximum applicable CBEXP inter-

val (whichever is greater)

11 = SHDNL Held High for duration of Automated Cell Balancing or Discharge

operations, and until removed

Cell Balancing Duty Cycle

Sets the active duty cycle within each T

period.

CBEO

0000 = 6.25% (default)

0001 = 12.5%

...

CBDUTY

7:4

1110 = 93.75%

1111 = 100%, less NOL and Measurement/Calibration overhead.

Cell Balancing Complete Alert Enable

0 = ALRTCBDONE masked in STATUS1:ALRTCBAL (default)

1 = ALRTCBDONE included in STATUS1:ALRTCBAL

Masking of this alert component allows the user the choice to be notiﬁed only

for unexpected exits, or normal completions as well.

CBDONEALRTEN

CBTEMPEN

3

2

Cell Balancing Thermal Exit Enable

0 = Cell Balancing not impacted by ALRTTEMP (default)

1 = Cell Balancing halts in response to ALRTTEMP

Cell Balancing Measurement Enable

0x = Embedded ADC/CAL Measurements and CBUVTHR checking disabled

(default)

10 = Embedded ADC/CAL Measurements enabled, CBUVTHR checking

CBMEASEN

1:0

disabled

11 = Embedded ADC/CAL Measurements enabled, CBUVTHR checking

enabled

Note: Automated Cell Balancing with CBUVTHR checking is only supported

for unipolar cell measurements.

Maxim Integrated │ 281

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALSTAT (0ꢀ81)

BALSTAT is a read-accessible register that allows the monitoring of any Automated Cell-Balancing operations currently

in progress.

Once a CBMODE is initiated, all status bits persist and are cleared only when CBMODE is written to 000 (disabled) or

when a new CBMODE operation is initiated through CBSTART.

BIT

Field

15

14

13

12

11

10

9

8

CBACTIVE_M1[1:0]

0b00

CBUNIT[1:0]

CBCNTR[1:0]

CBTIMER[9:8]

Reset

0b00

0x000

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

0

CBTIMER[7:0]

Reset

0x000

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Timer Active Indicator (Mirror):

00 = Cell balancing is disabled (default)

01 = Cell balancing operations are active

10 = Cell balancing completed normally due to reaching CBUVTHR or CBEXP

exit conditions

CBACTIVE_M1

15:14

11 = Cell balancing halted unexpectedly due to thermal exit (ALRTCBTEMP),

Time Out (ALRTCBTIMEOUT), or Calibration Fault (ALRTCBCAL) conditions

Read only.

Cell-Balancing Timer Unit Indicator:

00 = Cell balancing is disabled (default)

01 = CBTIMER measures Seconds

10 = CBTIMER measures Minutes

11 = CBTIMER measures Hours

CBUNIT

13:12

Allows conﬁrmation of cell-balancing timer operating mode (LSB weight).

Read only,

Cell-Balancing Active Counter:

1Hz counter that can be read to verify CBTIMER operation/activity when the

CBTIMER is operated in minute or hour modes. The counter counts from 0 to

3, rolling over to 0 approximately every 4 seconds in all active Cell-Balancing

modes (CBMODE! = 000).

CBCNTR

11:10

Read only.

Notes:

During Hold SHDNL extension periods (HOLDSHDNL = 1x), CBCNTR continues

to run.

If the governing CBEXP setting is set to 0x3FF (inﬁnite), this counter continues to

run, even though it has no impact on the active Cell-Balancing mode.

Maxim Integrated │ 282

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Timer Value:

Reads the current cell-balancing timer value in seconds, minutes or hours,

depending on CBMODE, as indicated by CBUNIT.

Read only.

Notes:

CBTIMER

9:0

During SHDNL hold/extension periods (HOLDSHDNL = 1x), CBTIMER reads

back the governing expiration time (CBEXP), indicating that the requested bal-

ancing operation has completed.

If the governing CBEXP setting is set to 0x3FF (inﬁnite), this timer still runs and

rolls over, even though it has no impact on the active Cell-Balancing mode.

BALUVSTAT (0ꢀ82)

BALUVSTAT is a read-accessible register that relates current summary information on the Cell voltages vs. the

CBUVTHR undervoltage threshold.

BIT

Field

15

14

13

12

11

10

9

8

0

CBACTIVE_M2[1:0]

0b00

CBUVSTAT[14:9]

0x0000

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

CBUVSTAT[8:1]

0x0000

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Cell Balancing Timer Active Indicator (Mirror):

00 = Cell balancing is disabled (default)

01 = Cell-balancing operations are active

10 = Cell balancing completed normally due to reaching CBUVTHR or CBEXP

exit conditions

CBACTIVE_M2

15:14

11 = Cell balancing halted unexpectedly due to thermal exit (ALRTCBTEMP),

timeout (ALRTCBTIMEOUT), or calibration-fault (ALRTCBCAL) conditions

Read only.

Cell-Balance CBUVTHR Check Status:

CBUVSTAT[n] = 1 indicates the corresponding CELLn result falls below the

threshold speciﬁed by CBUVTHR and that cell-balancing operations on that

cell have ended.

Cleared only when CBMODE is written to 000 (disabled) or when a new

CBMODE operation is initiated through a write to BALCTRL.

Read only.

CBUVSTAT

13:0

Note: Automated cell balancing with CBUVTHR checking is only supported

for unipolar cell measurements in locations with BALSWENn = 1. The user

must also ensure CELLENn = 1 and POLARITYn = 0 to allow the required

measurement updates; if the measurement is not supported, balancing of the

cell automatically ends with a CBUVSTATn = 1 exit condition.

Maxim Integrated │ 283

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BALDATA (0ꢀ83)

BALDATA is a read-accessible register that relates current summary information on the Cell voltages vs. the

CBUVTHR undervoltage threshold.

BIT

Field

15

14

13

DATARDY_M

0b0

12

–

11

–

10

–

9

–

8

–

CBACTIVE_M3[1:0]

0b00

Reset

–

Write, Read,

Ext

Access Type

Read Only

–

BIT

Field

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

CBSCAN

0b0

Reset

Write, Read,

Pulse

Access Type

–

BITFIELD

BITS

DESCRIPTION

Cell-Balancing Timer Active Indicator (Mirror):

00 = Cell balancing is disabled (default)

01 = Cell-balancing operations are active

10 = Cell balancing completed normally due to reaching CBUVTHR or CBEXP

exit conditions

CBACTIVE_M3

15:14

11 = Cell balancing halted unexpectedly due to thermal exit (ALRTCBTEMP),

timeout (ALRTCBTIMEOUT), or calibration-fault (ALRTCBCAL) conditions

Read only.

Data-Ready Indicator Bit (Mirror):

Indicates the measurement data from the acquisition has been transferred to

the data registers and may now be read. Data for all measurement registers

and MIN/MAX/TOTAL is transferred at the same time.

Cleared by writing to logic zero to allow detection of the next data transfer.

Writing to logic one has no internal eﬀect.

DATARDY_M

13

This is a mirror of the DATARDY bit in SCANCFG, provided to support

readback of measurement results taken during automated and discharge Cell-

Balancing modes.

Manually Transfer Measurement Results from IIR to Data Registers:

0 = No transfer requested

1 = Measurement transferred from the IIR (regardless of RDFILT setting) to

data registers; once transfer is complete, DATARDY bit is set.

Acts as a strobe bit and therefore does not need to be cleared (self-clearing).

This bit has no eﬀect in cell-balancing manual or disable mode, or when CB-

MEASEN = 0x. Always reads logic zero.

CBSCAN

0

Maxim Integrated │ 284

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

ID1 (0ꢀ8C)

ID1 is a read-accessible register that contains the 2 LSBytes of the unique Device ID stored in ROM and subject to

ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

8

DEVID[15:8]

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

0

DEVID[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Device ID (Partial):

The two least-signiﬁcant bytes of the 24-bit factory-programmed device ID.

DEVID

15:0

ID1,0 always reads logic one. A valid device ID has two or more bits set to

logic one.

Read only.

ID2 (0ꢀ8D)

ID2 is a read-accessible register that contains the 2 MSBytes of the unique Device ID stored in ROM and subject to

ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

8

DEVID[31:24]

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

1

0

DEVID[23:16]

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

Device ID (Partial):

The most-signiﬁcant byte of the 24-bit factory-programmed device ID. A valid

device ID has two or more bits set to logic one.

Read only.

DEVID

15:0

Maxim Integrated │ 285

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OTP2 (0ꢀ8E)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP2[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP2[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data:

Read Only.

OTP2

15:0

OTP3 (0ꢀ8F)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP3[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP3[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data:

Read Only.

OTP3

15:0

Maxim Integrated │ 286

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OTP4 (0ꢀ90)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP4[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP4[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data

Read Only.

OTP4

15:0

OTP5 (0ꢀ91)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP5[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP5[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data

Read Only.

OTP5

15:0

Maxim Integrated │ 287

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OTP6 (0ꢀ92)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP6[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP6[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data:

Read Only.

OTP6

15:0

OTP7 (0ꢀ93)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP7[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP7[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data:

Read Only.

OTP7

15:0

Maxim Integrated │ 288

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OTP8 (0ꢀ94)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP8[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP8[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data

Read Only.

OTP8

15:0

OTP9 (0ꢀ95)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP9[15:8]

Read Only

Reset

Access Type

BIT

Field

7

6

5

4

3

2

OTP9[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data

Read Only.

OTP9

15:0

Maxim Integrated │ 289

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OTP10 (0ꢀ96)

Factory Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP10[15:8]

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

OTP10[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

Factory-Calibration Data:

Read Only.

OTP10

15:0

OTP11 (0ꢀ97)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

OTP11[15:8]

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

OTP11[7:0]

Read Only

Reset

Access Type

BITFIELD

OTP11

BITS

DESCRIPTION

Factory-Calibration Data:

Read Only.

15:0

Maxim Integrated │ 290

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

OTP12 (0ꢀ98)

Factory-Calibration Data ROM and subject to ROMCRC validation.

BIT

Field

15

14

13

12

11

10

9

1

8

0

ROMCRC[7:0]

Reset

Access Type

Read Only

BIT

Field

7

6

5

4

3

2

OTP12[7:0]

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

ROM CRC Value:

8-bit CRC value computed from the onboard read-only memory content. ID

and OTP ROM output data content is protected by an 8-bit CRC with

polynomial 0xA6 (x +x +x +x +1).

Read only.

ROMCRC

OTP12

15:8

8

6

3

2

Factory-Calibration Data:

Read Only.

7:0

Maxim Integrated │ 291

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

For zero-scale diagnostic: ADC

= V

and ADC

REF IN

Calibration-Alert Diagnostics

REF

= -V

AA

To validate the integrity of the calibration, the CALOS

ADCCALFRC,CALOSRALRTFRC,CALOSTHRMALR

TFRC, CALGAINPALRTFRC, CALGAINRALRTFRC bits

can be used to inject an expected overranged input to

the digital-calibration circuitry. This sets the correspond-

ing ALRTCALOSADC, ALRTCALOSR, ALRTCALOSTHRM,

ALRTCALGAINP, ALRTCALGAINR bit in the ALRTSUM reg-

ister and demonstrates proper functionality of digital circuitry.

If the result from the ADC is greater than 000h, an alert

is issued by setting the ALRTADCZS bit in the FMEA2

register.

The DIAGSEL1 and DIAGSEL2 registers can be configured

to obtain further diagnostic information regarding the ADC.

BATTERY PACK

PLUG

AC/DC CHARGING SWTICH

PRE CHARGING SWITCH

PLUG

MAIN HV+ CONTRACTOR

VEHICLE 12V PWR

PHASE 1

PHASE 2

PHASE 3

VEHICLE GND

BATTERY

MANAGEMENT

SYSTEM (BMS)

COMM BUS

COMM

BUS

VEHICLE

CONTROL

SYSTEM

(VCS)

INVERTER

SERVICE

SWTICH

MOTOR

PLUG

MAIN HV- CONTRACTOR

CHASSIS GROUND

Figure 96. Electric Vehicle System

Maxim Integrated │ 292

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Note: The analog verification of the calibration is performed

using the cell gain-calibration diagnostic, offset-calibration

diagnostic, and THRM offset-calibration diagnostic.

Supply Connection Diagnostics

The V , V , and V supply voltages are con-

DDL1 DDL2

DDL3

tinuously monitored to be above V

. If a supply

VDDL_OC

goes below the threshold, the ALRTVDDL1, ALRTVDDL2,

or ALRTVDDL3 alert is set.

MAIN HV+

INVERTER+

CONTACTOR

BATTERY

MODULE

PRE

CHARGING

PRE CHARGING

SWTICH

MAX17853

SLAVE

MONITOR

AND

AC/DC

CHARGING

AC/DC CHARGING

SWTICH

CONTROL

TEMP

UART

ALERT

INTERFACE

BATTERY

MODULE

MAX17853

SLAVE

MONITOR

AND

CONTROL

TEMP

UART

INTERFACE

ALERT

INTERFACE

BATTERY

MODULE

BATTERY

PACK

HVAC

MAX17853

SLAVE

MONITOR

AND

VEHICLE

12V PWR

MASTER

CONTROLLER

CONTROL

TEMP

SPI INTERFACE

UART INTERFACE

VEHICLE COMM BUS

(CAN INTERFACE)

ISOLATION

MAX17841

ALERT INTERFACE

GROUND

FAULT

CHECK

INVERTER-

MAIN HV- CONTACTOR

MICRO-Ω

SHUNT

CHASSIS GROUND

Figure 97. Daisy-Chain System

Maxim Integrated │ 293

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The GNDL1, GNDL2, and GNDL3 supply voltages are

ground goes below the threshold, the ALRTGNDL1,

ALRTGNDL2, or ALRTGNDL3 alert is set.

continuously monitored to be below V

. If a

GNDL_OC

MAIN HV+

INVERTER+

CONTACTOR

PRE

CHARGING

PRE CHARGING

SWTICH

AC/DC

CHARGING

AC/DC CHARGING

SWTICH

BATTERY

MODULE

MAX17853

CAN INTERFACE

SPI INTERFACE

µC ALERT INTERFACE

CAN

ISOLATOR

SLAVE

MONITOR

AND

CONTROL

TEMP

BATTERY

MODULE

MAX17853

CAN INTERFACE

SPI INTERFACE

µC ALERT INTERFACE

CAN

ISOLATOR

SLAVE

MONITOR

AND

CONTROL

TEMP

MASTER

CONTROLLER

BATTERY

PACK

HVAC

VEHICLE

12V PWR

BATTERY

MODULE

MAX17853

CAN INTERFACE

SPI INTERFACE

µC ALERT INTERFACE

VEHICLE COMM BUS

(CAN INTERFACE)

CAN

ISOLATOR

SLAVE

MONITOR

AND

GROUND

FAULT

CONTROL

TEMP

CHECK

INVERTER-

MAIN HV- CONTACTOR

MICRO-Ω

SHUNT

CHASSIS GROUND

Figure 98. Distributed System

Maxim Integrated │ 294

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

,whereas all components would require redundant imple-

mentation in a non-daisy-chain (distributed CAN system).

See the Distributed CAN Systems section for further infor-

Applications Information

Vehicle Applications

Battery cells can use various chemistries such as NiMH,

Li-ion (NMC, LFP, LTO), SuperCap or lead-acid. SuperCap

cells are used in fast-charge applications such as energy

storage for regenerative braking. An electric-vehicle sys-

tem may require a high-voltage battery pack voltage from

400V to 800V, which translates from 100 to 200 Li-ion

cells ,or up to 500 NiMH cells.

mation regarding its implementation.

Distributed CAN Systems

A distributed CAN system(Figure 98) employs an individual

CAN communication interface, battery-management micro-

controller, and transformer isolation between each battery

module and master controller/ECU. This system architec-

ture, although realizable, yields increased system cost.

A battery module is a number of cells connected in

series that can be connected with other modules to build

a high-voltage battery pack, as shown in Figure 96.

The modularity allows for economy, configurability, quick

assembly, and serviceability. The minimum number of

cells connected to any one device is limited by the

device’s minimum operating voltage. The 9V (min) for

Standard Module Conﬁguration

Power-Supply Connection

In a standard module configuration, both internal and

external protection circuits permit the MAX17853 to derive

its supply directly from the battery-module voltage using

a filter network connecting the DCIN input to the top cell

of the battery pack. These protection circuits protect

against transients such as those that can occur when

the battery voltage is first connected to the device, when

the vehicle inverter is connected to the battery stack, or

during charge/discharge transitions such as regenerative

braking. The internal circuits include 72V tolerant battery

inputs and a high-noise rejection ratio (PSRR) for the

internal low-voltage regulator.

V

DCIN

usually requires at least two Li-ion, six NiMH or six

SuperCap cells per module.

Battery-Management Systems

Daisy-Chain System

A daisy-chain system employs a communication link

between the host microcontroller and all the battery mod-

ules. The daisy-chain method reduces overall system cost

as it requires only a single microcontroller, CAN PHY, and

transformers between the lowest module and the host

The external protection circuit shown in Figure 99 filters

and clamps the DCIN input. During negative-voltage tran-

sients, the filter capacitor maintains power to the device

through the transient.

MODULE+

For maximum measurement accuracy, dedicated wires

separate from the cell sense wires should be used for the

power-supply connection (Kelvin sense). This eliminates

voltage drops in the sense wires induced by supply cur-

rent. If the application can tolerate the induced error, the

supply wires can serve as the sense wires to reduce the

wire count.

R80

100Ω

DCIN

C20

D80

Connecting Cell Inputs

2.2µF

SMCJ58A

100V

As mentioned in the previous section, the DCIN input

should be connected to the battery module's top cell to

prevent charge imbalance between cells. If the battery

module contains less than 14 cells, the lowest order inputs

(e.g., C1 and C0) should be utilized first and connected to

the lowest common-mode signals. Any unused cell inputs

should be shorted together, and unused switch inputs

should also be shorted together. The TOPCELL register

Figure 99. Power-Supply Connection

Maxim Integrated │ 295

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

must also be configured for stacks with less than 14 cells

to mask out any false alerts corresponding to the unused

channels.

The Flexible Pack (Flex Pack) Configuration provides

systemflexibilitysuchthatasingleMAX17853canmeetthe

requirements of: varying battery module configuration(s)

used across multiple mild EV, HEV, BEV distributed

daisy-chain systems, as well as distributed daisy-chain

Flexible Pack Conﬁguration

Power Supply, Cell Input Conﬁguration

TO CELL

N+1

MAX1785X

SENSE WIRE

R

C

N

FILTER

TO

HVMUX

C

R

FILTER

BIAS

SW

N

TO

ALTMUX

HV

R

BALANCE

BALSW

N

Q

BALANCE

R

GATE

CELL

N

D

C

GATE

R

C

SW

N-1

BIAS

TO

ALTMUX

SENSE WIRE

R

C

N-1

FILTER

TO

HVMUX

FILTER

AGND

TO CELL

N-1

Figure 100. External-Balancing FET

Table 80. FET-Balancing Components

COMPONENT NAME

TYPICAL VALUE OR PART

FUNCTION

R

1kΩ

100Ω

Voltage-divider for transistor bias

Hot-plug current-limiting resistor

Reverse-voltage gate protection

BIAS

GATE

R

D

C

S1B

1nF

Transient V

suppression

GS

R

Q

per application

SQ2310ES

Balancing current-limiting resistor

External switch

BALANCE

Maxim Integrated │ 296

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

systemsthatemployunequalmodulesizeswithinastandard

battery pack.

required by discrete external traces. Due to this internal

routing, the bill-of-materials (BOM) cost may be reduced

through the elimination of the DCIN filter resistor as well

as the block-voltage-measurement filter. Unused chan-

nels are left unconnected, allowing any battery wiring

harness to connect to a standard battery module. See the

This flexibility is allowed through internal supply routing of

the top battery cell as well as internal signal routing of the

block voltage, where these connections were otherwise

TO CELL

N+1

MAX1785X

SENSE WIRE

R

C

N

FILTER

TO

HVMUX

C

R

FILTER

BIAS

SW

N

TO

ALTMUX

HV

R

BALANCE

BALSW

N

Q

BALANCE

R

BASE

CELL

N

D

C

BASE

R

C

SW

N-1

BIAS

TO

ALTMUX

SENSE WIRE

R

C

N-1

FILTER

TO

HVMUX

FILTER

AGND

TO CELL

N-1

Figure 101. External Cell-Balancing BJT

Table 81ꢀ BJT Balancing Components

COMPONENT NAME

TYPICAL VALUE OR PART

FUNCTION

R

D

C

R

22Ω

15Ω

S1B

1nF

Voltage-divider for transistor bias

Hot-plug current-limiting resistor

Reverse emitter-base voltage protection

Transient VBE suppression

BIAS

BASE

per balancing current requirements

NST489AMT1

Balancing current-limiting resistor

External switch

BALANCE

Q

BALANCE

Maxim Integrated │ 297

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Flexible Pack Configuration section for further details on

implementation.

FLXPCKSCAN bit in the PACKCFG register, resulting in

total BOM cost reduction, as well as eliminating system

cost and constraints for calibration.

For non-distributed daisy-chain systems (centralized

systems), the Flex Pack eliminates the need to route

external sense wires as the voltage drops from the cell

cabling, which can be significantly reduced using the

External Cell Balancing

DAISY-CHAIN

DEVICE

N-1

N

GNDL[1, 2, 3]

(DEVICE )

MAX1785x

N

C40

15pF

R42

100kΩ

C42

2.2nF, 600V

R40

1.5kΩ

R50

47Ω

RXLP

RXLN

TXUP

TXUN

C43

2.2nF, 600V

R41

1.5kΩ

R51

47Ω

C41

R43

SIGNAL

15pF

100kΩ

TRACES OR

WIRE

HARNESS

GNDL[1, 2, 3]

(DEVICE

)

N-1

GNDL[1, 2, 3]

(DEVICE )

N

C50

2.2nF, 600V

C52

15pF

R52

100kΩ

R44

47Ω

R54

1.5kΩ

TXLP

TXLN

RXUP

RXUN

C51

2.2nF, 600V

R45

47Ω

R55

1.5kΩ

C53

R53

SIGNAL

15pF

100kΩ

TRACES OR

WIRE

HARNESS

GNDL[1, 2, 3]

(DEVICE

)

N-1

GNDL[1, 2, 3]

(DEVICE )

GNDL[1, 2, 3]

(DEVICE

N

)

N-1

Figure 102. UART Connection

Maxim Integrated │ 298

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

The cell-balancing current can be switched by external

transistors if more power dissipation is required. The inter-

nal switches can be used to switch the external transistors,

with the power limited by external current-limiting resistors.

event. R

inrush current. C

sient noise coupled from the drain to the gate to maintain

the transistor bias. The cell-balancing current is limited by

protects the device by limiting the hot-plug

GATE

can be added to attenuate tran-

GATE

R

. The various external cell-balancing summary

BALANCE

External Cell-Balancing using FET Switches

components are shown in Table 80.

An application circuit for cell balancing that employs FET

External Cell-Balancing Using BJT Switches

switches is shown in Figure 100. Q

is selected

BALANCE

for low V that meets the minimum V

requirements

An application circuit for cell balancing that employs

T

CELLn

of the application during balancing. D

protects

BJT switches is shown in Figure 101. Q

is

GATE

BALANCE

Q

from reverse V

voltage during a hot-plug

selected for power dissipation based on the IB drive

BALANCE

GS

V

DDL[2, 3]

MAX1785x

R46

10kΩ

R48

10kΩ

FMB3906

V

AA

R44

47Ω

TX[U, L]P

TX[U, L]N

TO REST OF

Tx CIRCUIT OR

Rx CIRCUIT

R45

47Ω

R47

R49

10kΩ

GNDL[2, 3]

Figure 103. High-Z Idle Mode Application Circuit

R44

47Ω

MAX1785x

TX[U, L]P

TO RECEIVER

R45

47Ω

TX[U, L]N

PESD1CAN

GNDL[2, 3]

Figure 104. External ESD Protection for UART Tx Ports

Maxim Integrated │ 299

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

MAX1785x

C50

2.2nF,

600V

C52

15pF

50V

R52

100kΩ

R54

1.5kΩ

100Ω

RX[U, L]P

FROM

TRANSMITTER

R55

1.5kΩ

100Ω

RX[U, L]N

C53

R53

C51

2.2nF,

600V

15pF

100kΩ

50V

PESD1CAN

GNDL[1, 2, 3]

Figure 105. External ESD Protection for UART Rx Ports

ISOLATED OR

NON-ISOLATED

INVERTING

MAX1785X

RXLP

LOGIC DRIVER

R

F

1.5kΩ

UART DATA

RXLN

C

f

15pF

Figure 106. Application Circuit for Single-Ended UART Mode

current available and the cell-balancing current. D

External Cell-Balancing Short-Circuit Detection

BASE

protects Q

from negative V

protects the device by limiting the hot-plug

during hot-plug

BALANCE

GS

A short-circuit fault in the external balancing path results

events. R

BASE

in continuous current flow through R

and

BALANCE

inrush current. The cell-balancing current is limited by

. The various external cell-balancing summary

Q . To detect this fault, the voltage drop across

BALANCE

R

BALANCE

components are shown in Table 81.

Maxim Integrated │ 300

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

the sense-wire parasitic resistance must be measurable. A

very small series resistor may be added for this purpose.

UART Supplemental ESD Protection

The UART ports may require supplemental protection to

meet IEC 61000-4-2 requirements for contact discharge.

The recommended circuits to meet ±8kV protection levels

are shown in Figure 104 and Figure 105. The protection

components should be placed as near as possible to the

signal’s entry point on the PCB.

UART Interface

The UART pins employ both internal and external circuits

to protect against noise. The recommended external filters

are shown in Figure 102. ESD protection is shown in Figure

104 and Figure 105.

Single-Ended Rx Mode

High-Z Idle Mode

To configure the lower port for single-ended Rx mode, the

RXLP input is connected to digital ground and the RXLN

input receives the inverted signal, just as it does for dif-

ferential mode. If the host cannot transmit inverted data,

then the signal must be inverted as shown in Figure 106.

Transmitter operation is not affected. If the up-stack

device is single-ended, only the TXUN signal is required.

The high-Z idle mode lowers radiated emissions from wire

harnesses by minimizing the charging and discharging of

the AC-coupling capacitors when entering and exiting the

idle mode. The application circuit shown in Figure 103 uses

a weak resistor-divider to bias the Tx lines to V

during

DDL

the high-Z idle period and pnp transistor clamps to limit the

maximum voltage at the Tx pins during high noise injection.

The resistor-divider and pnp clamps are not needed for

applications utilizing only the low-Z mode. The low-Z and

high-Z idle modes both exhibit a similar immunity to noise

injection. Low-Z mode may be preferred for ports driving

inductive loads to minimize ringing.

Note: In single-ended mode, SHDNL must be driven

externally.

UART Isolation

The UART is expected to communicate reliably in noisy

high-power battery environments where both high dV/dt

DAISY-CHAIN DEVICE

1

MAX17841

MAX1785x

GNDL[1, 2, 3]

(DEVICE )

1

15pF

47Ω

1.5kΩ

TXP

RXLP

RXLN

47Ω

TXN

SIGNAL TRACES OR

WIRE HARNESS

15pF

1nF

GNDL

GNDL[1, 2, 3]

GNDL

(DEVICE

GNDL[1, 2, 3]

(DEVICE )

)

MAX17841

1

Figure 107. UART Transformer Isolation

Maxim Integrated │ 301

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

supply noise and common-mode current injection induced

by electromagnetic fields are prevalent. Common-mode

currents can also be induced by parasitic coupling of the

system to a reference node such as a battery or vehicle

chassis. The daisy-chain physical layer is designed for

maximum noise immunity.

The AC-coupled differential communication architecture

has a ±30V common-mode range and +6V differential

swing. This range is in addition to the static common-

mode voltage across the AC-coupling capacitors between

modules. Transmitter drivers have low internal impedance

and are source-terminated by the application circuit so

that impedances are well matched in the high- and low-

driver states. This architecture minimizes differential noise

DAISY-CHAIN DEVICE

1

V

AA

MAX1785x

RXLP

FROM UART

DATA SOURCE

R

F

GNDL[1, 2, 3]

(DEVICE )

4.7kΩ

1

RXLN

C

f

15pF

GNDL[1, 2, 3]

(DEVICE )

1

ACPL-M72T

GND (UART

DATA SOURCE)

3.3V

R

OPTO

TXLN

TO UART

DATA SOURCE

GND (UART

DATA SOURCE)

ACPL-M72T

GNDL[1, 2, 3]

(DEVICE )

1

Figure 108. UART Optical Isolation

Maxim Integrated │ 302

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

µC

MAX1785x

5V REGULATOR

OUTPUT

V

DDL2

0.47µF

GNDL2

V

DDL3

0.47µF

CHASSIS GROUND

GND

GPO

GNDL3

SHDNL\

R

10kΩ

PULLUP

R

PULLUP

10kΩ

GPI

ALERTOUT

(PASSIVE DRIVE)

R

F

22Ω

SCLK

CSB

TXUN (SCLK)

TXLN (CSB)

TXLP (SDO)

TXLN (SDI)

R

22Ω

F

R

22Ω

F

MOSI

MISO

R

22Ω

F

Figure 109. 5V SPI Supply from System

Maxim Integrated │ 303

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

µC

MAX1785x

V

AA

1µF

AGND

5V REGULATOR

OUTPUT

V

DDL2

0.47µF

GNDL2

V

DDL3

0.47µF

CHASSIS GROUND

GND

GPO

GNDL3

SHDNL\

R

PULLUP

10kΩ

GPI

SCLK

CSB

ALERTOUT

(PASSIVE DRIVE)

R

22Ω

F

TXUN (SCLK)

R

22Ω

F

TXLN (CSB)

TXLP (SDO)

TXLN (SDI)

R

22Ω

F

MOSI

MISO

R

22Ω

F

Figure 110. 3.3V SPI Supply from Device V

LDO

AA

Maxim Integrated │ 304

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

induced by common-mode current injection. The receiver

inputs are filtered above the fundamental communication

frequency to prevent high-frequency noise from entering

the device. The system is designed for use with isolation

transformers or optocouplers to provide an even higher

degree of common-mode noise rejection in circuit locations

where extremely large common-mode noise is present,

such as between vehicle chassis and the high-voltage

battery-pack terminals.

Since a mid-pack service disconnect safety switch is

present in many battery packs, the device is designed

to communicate with the entire daisy-chain whether the

service-disconnect switch is engaged or open. This is

possible with daisy-chains that employ capacitor isolation.

DAISY-CHAIN DEVICE

N

N+1

MAX1785x

V

AA

(DEVICE )

N

V

AA

R

OPTO

ALERTOUT

ALERTIN

AGND

(DEVICE )

N

ACPL-M72T

AGND

(DEVICE

)

N+1

Figure 111. Single-End ALERT Interface in UART Mode

Maxim Integrated │ 305

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

µC

MAX1785x

5V REGULATOR

OUTPUT

V

DDL2

0.47µF

GNDL2

V

DDL3

0.47µF

CHASSIS GROUND

GND

GPO

GNDL3

SHDNL\

R

10kΩ

PULLUP

GPI

ALERTOUT

(ACTIVE DRIVE)

R

F

22Ω

SCLK

CSB

TXUN (SCLK)

TXLN (CSB)

TXLP (SDO)

TXLN (SDI)

R

22Ω

F

R

22Ω

F

MOSI

MISO

R

22Ω

F

Figure 112. Single-End ALERT Interface in SPI mode - Active Drive

Maxim Integrated │ 306

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

µC

MAX1785x

5V REGULATOR

OUTPUT

V

DDL2

0.47µF

GNDL2

V

DDL3

0.47µF

CHASSIS GROUND

GND

GPO

GNDL3

SHDNL\

R

10kΩ

PULLUP

R

PULLUP

10kΩ

GPI

ALERTOUT

(PASSIVE DRIVE)

R

F

22Ω

SCLK

CSB

TXUN (SCLK)

TXLN (CSB)

TXLP (SDO)

TXLN (SDI)

R

22Ω

F

R

22Ω

F

MOSI

MISO

R

22Ω

F

Figure 113. Single-End ALERT Interface in SPI mode - Passive Drive

Maxim Integrated │ 307

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

between the MAX17841B interface and the MAX1785x

UART Transformer Isolation

provides excellent isolation and common-mode noise

rejection (see Figure 107). The center-tap of a signal trans-

former may be used to enhance common-mode rejection

The UART ports may be transformer-coupled because of

their DC-balanced differential design. Transformer coupling

MAX1785X

COMMUNICATION

INITIALIZED

MAX1785X

FULLY FUNCTIONAL

YES

DUAL UART

CONFIGURATION

NO

YES

NO

SEND PREAMBLES FOR

~1MS/DEVICE UNTIL

RECEIVED BY MAX17841/

HOST

DOWN MASTER

CONFIGURATION

EXPECTED

ADDRESS

YES

ADDRESSING

ERROR

FAULT

SEND PREAMBLES

ON UP PATH UNTIL

RECEIVED BY

SEND PREAMBLES

ON DOWN PATH UNTIL

RECEIVED BY

NO

MAX17841/HOST

SEND HELLOALL COMMAND

FAULT OR

ADDRESSING

ERROR

YES

PEC ERROR

SEND PREAMBLES

FOR N+1 DAISY

CHAIN DEVICES ON

DOWN PATH

SEND PREAMBLES

FOR N+1 DAISY

CHAIN DEVICES ON

UP PATH

FAULT

HELLOALL

CORRECT RETURN

ADDRESS

NO

YES

SEND DOWNHOST COMMAND

SEND DOWN PATH HELLOALL

SEND UP PATH HELLOALL

YES

HELLOALL

CORRECT RETURN

ADDRESS

HELLOALL

CORRECT RETURN

ADDRESS

FAULT OR

COUNT ERROR

READ ADDRESS

REGISTER

YES

WRITEALL BA[4:0]

(IF RETURNED HELLOALL

ADDR[4:0 ]≠ 0X1F)

WRITEALL BA[4:0]

(IF INITIAL HELLOALL

ADDR[4:0] ≠ 0X00)

WRITEALL TA[4:0]

UART WITH

EXTERNAL

LOOPBACK

YES

CLEAR ALRTDUALUART

WRITEALL UARTCFG = 0B00

NO

SINGLE UART

WITH DIFF

ALERT

YES

WRITEALL UARTCFG = 0B10

WRITEDEVICE UARTCFG =

0B01 TO LAST DAISY CHAIN

DEVICE

UART WITH

INTERNAL

LOOPBACK

NO

FAULT OR

COUNT ERROR

Figure 114. Device Initialization Sequence

Maxim Integrated │ 308

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

by AC-coupling the node to local ground. Common-mode

currents that are able to pass through the parasitic cou-

pling of the primary and secondary are shunted to ground

to make a very effective common-mode noise filter.

the entire command propagated without errors. Using the

data-check and PEC bytes, complete transaction integrity

for READALL and READDEVICE command packets can

be verified.

UART Optical Isolation

PEC Errors

The daisy-chain may use optical isolation instead of trans-

former or capacitor isolation, as shown in Figure 108.

If the MAX17853 receives an invalid PEC byte, the cor-

responding ALRTPECUP, or ALRTPECDN bit in the

STATUS2 register, and the summary ALRTPEC bit in the

STATUS1 register are set. All single-UART configura-

tions set the ALRTPECUP bit, since the Up path is used

for received transactions. In a dual-UART configura-

tion, a PEC error in the Up path sets ALRTPECUP, and

a PEC error in the Down path set the ALRTPECDN.

The MAX17853 does not execute/accept any written

commands unless the received PEC byte matches the

calculated CRC Remainder, confirming the validity of

the received command and data stream. To confirm the

command was accepted, the host should perform an

appropriate read transaction to verify the contents of the

written register(s).

SPI Interface

V

DDL2

and VDDL3 are the supply pins for the SPI com-

munication. SPI communication supports both 5V and

3.3V. The SPI supply configuration with 5V provided by

the system is shown in Figure 109.

The SPI supply configuration with 3.3V provided by the

device's V LDO output is shown in Figure 110.

AA

ALERT Interface

V

DDL2

and V

are the supply pins for the Alert

DDL3

interface. When using the differential Alert interface in

the UART daisy-chain configuration, the recommended

external filters and ESD protection is same as the UART

interface. When using single-end Alert interface (i.e.,

ALERTIN and ALERTOUT pins) in the UART daisy-chain,

optical isolation is used, as shown in Figure 111.

PEC Calculations

When directly communicating with the MAX17853 through

the UART interface, the host must compute and send

the PEC byte, protecting the data sent to the device.

Likewise, for returned read packets, the host should store

the received data, perform the CRC calculation, and com-

pare the results to the received PEC byte provided by the

MAX17853 before accepting the data received as valid.

To support PEC-byte computation and checking, the host

must implement a CRC-8 (8-bit cyclic-redundancy check)

encoding and decoding algorithm based on the following

polynomial (0xA6):

In SPI mode, one MAX1785x is applied in the system.

The system can choose to supply V

and V

DDL2

DDL3

from the system's 5V or the device's V LDO output. An

AA

active CMOS ALERTOUT output setting in the system is

shown in Figure 112.

A passive pulup ALERTOUT setting in the system is

shown in Figure 113.

Device Initialization Sequence

8

6

3

2

Immediately after reset, all device addresses are set to

0x00 and the UART baud rate and receive modes have not

been auto-detected; therefore, the following initialization

sequence is recommended after every reset or after any

change to the hardware configuration.

P x = x + x + x + x + 1

( )

This polynomial is capable of protecting a data stream of

up to 247 bits with a Hamming distance of three, mean-

ing any data stream 247 bits or less in length with any

combination of 3 bits of error or less is guaranteed to be

identified. If more than 3 bits of error are encountered, the

PEC operation will very likely identify the problem, though

this cannot be mathematically guaranteed.

Error Checking

Data integrity is provided by Manchester encoding, par-

ity, character framing, and packet-error checking (PEC).

The combination of these features verify stage-to-stage

communication both in the write and read directions,

with a Hamming distance (HD) value of 6 for commands

with a length up to 247 bits (counted prior to Manchester

encoding and character framing. This is equivalent to the

longest possible command packet for a daisy-chain of

up to 13 devices. The data-check byte is present in the

READALL and READDEVICE commands to verify that

A hardware implementation of the CRC calculation is

shown in Figure 115. The CRC Engine shown is imple-

mented internally within the MAX17853; a similar imple-

mentation would be required in the host to support direct

UART communication, for purposes of generating the

PEC bytes sent to the MAX17853, or for checking PEC

bytes received from the MAX17853. The incoming UART

Maxim Integrated │ 309

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

data stream is fed into the CRC Engine LSB first. Once

the data stream has been completely shifted into the

engine, the CRC Remainder is known; this becomes the

PEC byte for both incoming and outgoing data, PEC[7:0]

=BIT[7:0] as shown (be sure to note the ordering of the

bits within the Remainder). Note that all UART transac-

tions supply the command and data stream LSB first.

For outgoing UART data streams, the MAX17853 first

clears the CRC Engine and then provides the outgo-

ing data stream to the CRC Engine, LSB first. After the

final bit of data is processed (in this case, the MSB of

the outgoing data stream is applied to the Engine), the

Engine is stopped and the CRC Remainder is known, so

this becomes the outgoing PEC byte. The outgoing PEC

byte, as calculated by the MAX17853 using its copy of the

CRC Engine, then follows within the UART transaction

(also LSB first). As the host receives the data stream from

the MAX17853, it should apply the data to its copy of the

CRC Engine (LSB first, in the order it arrives in the UART

transaction, until the MSB of the data stream is applied to

the engine). At this point, there are two equivalent ways

the host can complete the PEC operation to establish the

validity of the received data:

For incoming UART data streams, the MAX17853 first

clears the CRC Engine and then inputs the incoming data

stream into the CRC Engine, LSB first. After the final bit

of data is processed (in this case, the MSB of the incom-

ing data stream is applied to the Engine), the Engine is

stopped and the CRC Remainder is known. The incoming

PEC byte as calculated by the host using its copy of the

CRC Engine then follows within the UART transaction

(also LSB first), and is internally compared against the

CRC Remainder as calculated by the MAX17853. If the

PEC byte received matches the CRC Remainder calcu-

lated for the incoming data stream, the PEC operation is

successful, and the transaction is accepted and executed

by the MAX17853. If there is a mismatch, the MAX17853

rejects the transaction and issues the ALRTPEC status

bit, notifying the host of the issue so the transaction can

be resent.

● Direct Comparison Method: The host stops the CRC

Engine once the data stream MSB is applied and

compares the resulting CRC Remainder to the PEC

byte supplied by the MAX17853 (again, LSB first).

If the 2 bytes match, the data is accepted as valid;

otherwise, it should be rejected. This is the method

employed by the MAX17853 internally, as described

above.

BIT 0

BIT 1

BIT 2

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

INPUT DATA BITSTREAM (LSB FIRST)

Figure 115. PEC CRC Calculation

Maxim Integrated │ 310

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

● Zero-Remainder Method: The host continues CRC Engine computations after the data MSB is applied by

appending the received PEC byte to the end of the data stream, LSB first (i.e., in the order received during the

UART transaction). Once the MSB of the PEC byte arrives at the input of the CRC Engine, if the resulting CRC

Remainder=00h, the data is accepted as valid; otherwise, it should be rejected.

PEC Calculation Pseudocode

The host uses the algorithm to process all bytes received in the command packet prior to the PEC byte itself. Neither

the PEC nor the alive-counter bytes are part of the calculation. The bits are processed in the order they are received,

LSB first. A byte-wise pseudo-code algorithm is shown below, but lookup table solutions are also possible to reduce host

calculation time.

For commonly issued command packets, the host can pre-calculate (hard-code) the PEC byte. For commonly- used par-

tial packets, the CRC value of a partial calculation may be used as the initial value for a subsequent run-time calculation.

Function PEC_Calculation(ByteList(), NumberOfBytes, CRCByte)

{

// CRCByte is initialized to 0 for each ByteList in this implementation, where

// ByteList contains all bytes of a single command. It is passed into the

// function in case a partial ByteList calculation is needed.

// Data is transmitted and calculated in LSb first format

// Polynomial = x^8+x^6+x^3+x^2+1 = 1010_0110_1 = 0xA6

POLY = 8’hB2 // 10110010b – Polynomial binary representation is from left to right for

LSB first (0xA6 -> 0xB2)

//Loop once for each byte in the ByteList

For ByteCounter = 0 to (NumberOfBytes – 1)

(

//Bitwise XOR the current CRC value with the ByteList byte

CRCByte = CRCByte XOR ByteList(ByteCounter)

//Process each of the 8 CRCByte remainder bits

For BitCounter = 1 To 8

(

// The LSb should be shifted toward the highest order polynomial

// coefficient. This is a right shift for data stored LSb to the right

// and POLY having high order coefficients stored to the right.

// Determine if LSb = 1 prior to right shift

If CRCByte[1] = 1 Then

// When LSb = 1, right shift and XOR CRCByte value with 8 LSbs

// of the polynomial coefficient constant. “/ 2” must be a true right

// shift in the target CPU to avoid rounding problems.

CRCByte = ((CRCByte / 2) XOR POLY)

Else

//When LSb = 0, right shift by 1 bit. “/ 2” must be a true right

// shift in the target CPU to avoid rounding problems.

CRCByte = (CRCByte / 2)

End If

//Truncate the CRC value to 8 bits if necessary

Maxim Integrated │ 311

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

CRCByte = CRCByte AND 8'hFF

//Proceed to the next bit

Next BitCounter

OTP9[0:15], OTP10[0:15], OTP11[0:15], OTP12[0:7].

Note that this is essentially the entire ID/OTP content pro-

vided LSB-first - ID1[0] is the first bit applied to the CRC

Engine and OTP12,7 is the last, and all 200 bits must be

applied. At this point, there are two equivalent ways the

)

//Operate on the next data byte in the

ByteList

host can complete the ROMCRC operation to establish

the validity of the received ID/OTP data:

Next ByteCounter

)

● Direct Comparison Method: The host stops the CRC

Engine once the ID/OTP MSB is applied and com-

pares the resulting CRC Remainder to the ROMCRC

byte supplied by the MAX17853 as ROMCRC[7:0]

(OTP12[15:8]). If the 2 bytes match, the data is

accepted as valid; otherwise, it should be rejected

and retried in case of a communication fault. If the

failure persists, this may indicate a problem within

the MAX17853 ROM.

// All calculations done; CRCByte value is

the CRC byte for ByteList() and

// the initial CRCByte value

Return CRCByte

}

ROMCRC Calculation

For safety purposes, the factory-trimmed ROM (OTP)

content can be read back by the user and checked for

errors using an 8-bit CRC (cyclic-redundancy check).

ROMCRC is an 8-bit CRC Remainder computed using the

ID/OTP content and stored in OTP12[15:8] at the factory.

Both the ID and OTP output data content (excluding

OTP12[15:8], which ROMCRC[7:0]) and is protected by

the ROMCRC operation. To support ROMCRC compu-

tation and checking, the host must implement a CRC-8

encoding and decoding algorithm based on the following

polynomial (0xA6):

● Zero-Remainder Method: The host continues CRC

Engine computations after the data stream is applied

by appending the received ROMCRC byte to the

end of the data stream, LSB first (i.e., continu-

ing the concatenation pattern shown above with

OTP12[8:15], with OTP12,15 now being the last bit

applied). Once the MSB of the ROMCRC byte arrives

at the input of the CRC Engine, if the resulting CRC

Remainder=00h, the data is accepted as valid;

otherwise, it should be rejected and retried in case of

a communication fault. If the failure persists, this may

indicate a problem within the MAX17853 ROM.

8

6

3

2

P x = x + x + x + x + 1

( )

Note: When using direct UART communication and a

Block Readback of the ID/OTP content, the ROMCRC

operation can be computed on the arriving data stream

in the order received directly from the MAX17853 (since

the UART interface transmits data LSB-first). If using this

method, only the 200-bit OTP content should be applied

to the CRC Engine (with or without the trailing ROMCRC,

depending on the validation method selected above). If

using the MAX17853 in UART mode in conjunction with

a MAX17841, or in SPI mode, the host should first gather

the entire contents of the ID/OTP, and then concatenate it

and apply it to the CRC Engine as described above (with

or without the trailing ROMCRC, depending on the valida-

tion method selected above).

This polynomial is capable of protecting the 200 bit ID/

OTP content with a Hamming Distance of three, meaning

any combination of three bits of error or less is guaranteed

to be identified. If more than three bits of error are encoun-

tered, the ROMCRC operation very likely identify the prob-

lem, though this cannot be mathematically guaranteed.

A hardware implementation of the CRC calculation is

shown in Figure 116. The CRC Engine shown would be

implemented within the host. The same engine is used

in the production trim software to compute and store

the ROMCRC byte at the factory, using the computation

method outlined below. Be sure to note the ordering of

the bits within the Remainder, as shown in the figure (i.e.

BIT[7:0] = ROMCRC [7:0]). Note that this is also the same

CRC Engine used for PEC Byte CRC operations in UART

mode.

In all cases, the user-interface transactions issued to

fetch the ID/OTP data also will be protected by PEC

operations (UART) or CRC operations (SPI). If either

the PEC or CRC checks fail for the transaction itself, an

interface issue has been identified. The user should retry

the failed transactions to ensure the ID/OTP data and

ROMCRC have been accurately received prior to accept-

ing the results of the ROMCRC operation.

To complete the ROMCRC operation, the host would first

clear the CRC Engine and then apply the entire 200-bit

content of the ID/OTP data received from the MAX17853

concatenated in the in the following order: ID1[0:15],

ID2[0:15], OTP2[0:15], OTP3[0:15], OTP4[0:15],

OTP5[0:15], OTP6[0:15], OTP7[0:15], OTP8[0:15],

Maxim Integrated │ 312

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

BIT 0

BIT 1

BIT 2

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

INPUT DATA BITSTREAM (LSB FIRST)

Figure 116. ROMCRC Calculation

5) The SHDNL capacitor and associated trace routing

should be kept away and shielded from potential

noise sources and digital signals such as those

present with the communication or alert interfaces as

these may aﬀect the voltage seen by the SHDNL pin.

PCB Layout Recommendations

Careful PCB layout is critical to achieving the best accu-

racy performance and robust performance against environ-

mental conditions.

Layout Procedure

6) C traces are recommended to be routed on the

n

1) Place the charge-pump capacitor close to the

CPP and CPN pins and on the same layer as the

MAX17853. Care should be taken to avoid using vias

to prevent unwanted coupling into adjacent signals

and planes.

same layer as the MAX17853 to avoid the potential

sources for noise injection into the primary measure-

ment path. These traces carry a negligible current

and can be kept at minimum trace widths.

7) SW traces should be optimized for width in the

n

2) Place the decoupling capacitors on the V

, V

DCIN AA

,

permissible layout (20 mil recommended) to eliminate

excessive voltage drop due to the balancing

operation.

V

DDL1

close to the respective pins and on the same

layer as the MAX17853. V

and V

should

DDL2

DDL3

be placed close to the pins and is preferred on the

same layer if possible. All capacitors should not

share a ground return and each should via directly to

the AGND internal layer.

8) UART Rx and Tx ports should be routed for a 100Ω

diﬀerential impedance. If the MAX17853 is used in

a distributed BMS system, ESD protection is recom-

mended placed as close to the UART communication

connector with the ground return via’ed directly to the

AGND plane to clamp transient events before they

can couple to other nodes, which may aﬀect device

performance. For centralized BMS systems, ESD

components on the UART can be omitted.

3) AGND, GNDL1, GNDL2, GNDL3, AUXGND should

via directly to a solid AGND plane placed under the

MAX17853. Traces and vias should not be shared

within before they enter the AGND plane.

4) The DCIN input resistor must be sized depending on

both device current consumption (I

) and board

9) SPI operation will be driven by a system microcon-

troller, which is located on the same ground place as

the MAX17853. Depending on trace length, optional

source termination may be required to ensure that

overshoot or undershoot does not violate the

Absolute Maximum Operating Conditions. This

source termination should be placed close to the Tx

pins of the device.

DCIN

current consumption (I

) to prevent false

VAA_LOAD

ALRTHVHDRM alerts. Adjustment of the DCIN resis-

tor due to external loading should follow the following

equation: R

= R

x

DCIN_LOAD

/I ).

DCIN_NOM

(1 - I

DCIN VAA_LOAD

Note: In FlexPack operation, the DCIN ﬁlter resistor

is omitted.

Maxim Integrated │ 313

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Ordering Information

PART

TEMP RANGE

PIN-PACKAGE

64 LQFP

MAX17853ACB/V+

-40°C to +125°C

/V Denotes an automotive-qualified package.

+Denotes a lead(Pb)-free/RoHS-compliant package.

Maxim Integrated │ 314

www.maximintegrated.com

MAX17853

14-Channel High-Voltage Data-Acquisition System

Revision History

REVISION REVISION

PAGES

CHANGED

DESCRIPTION

NUMBER

DATE

0

7/18

Initial release

—

Updated Beneﬁts and Features, Package Information, Electrical Characteristics table,

Note 15, removed Note 18, updated Notes SPI-4 and SPI5, Pin Description, ADC

Input Range, Ramp-Mode Acquisition Time, Comparator Acquisition, Cell Statistics,

Temperature Alerts, Cell-Balancing Mode Conﬁgurations, Address Cyclic-Redundancy

Check—CRCA[2:0] (DI[22:20]), Input Data Cyclic-Redundancy Check—CRCD[2:0]

(DI[2:0]), Address Cyclic Redundancy Check—CRCA[2:0] (DI[22:20)]), Input-Data

Cyclic-Redundany Check—CRCD[2:0] (DI[2:0]), Output-Data Cyclic-Redundancy

Check—CRCO[2:0] (DO[2:0]), Status Cyclic Redundancy Check—CRCS[2:0]

(DO[26:24]), Table 66, VERSION (0x00), DEVCFC1 (0x14), and Ordering Information

1, 23, 25, 26,

29, 32, 36, 65,

73, 74, 94, 95,

136–139, 141,

148, 185, 208,

314

1

1/19

2

3

4

5

3/19

8/19

11/19

5/20

Updated Figure 1 and Figure 3

40. 42

314

29

Updated Ordering Information to remove MAX17853GCB/V+

Updated Electrical Characteristics table

Updated Beneﬁts and Features

1

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


型号：	MAX17853
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	14-Channel High-Voltage Data-Acquisition System
文件：	总315页 (文件大小：4043K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX17853 [MAXIM]

相关型号：

MAX17853ACB

MAX17853ACBV

MAX17880

MAX178ACNG

MAX178ACNG+

MAX178ACWG

MAX178ACWG+

MAX178AENG

MAX178AEWG

MAX178AEWG+

MAX178AEWG+T

MAX178AMRG