MAX1798EUP+ [MAXIM]
CDMA Cellular/PCS System Power Supplies; CDMA蜂窝/ PCS系统电源
| 型号： | MAX1798EUP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | CDMA Cellular/PCS System Power Supplies |
| 文件： | 总19页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1655; Rev 2; 5/10
CDMA Cellular/PCS System
Power Supplies
8/MX179A
General Description
Features
The MAX1798/MAX1798A/MAX1799/MAX1799A system
power supplies are designed specifically for CDMA cel-
lular/PCS handsets. Each device contains five low-
dropout linear regulators (LDOs), a 140ms (min) reset
timer, a serial interface, push-on/push-off control logic,
and two general-purpose open-drain outputs. Only the
serial interface is different between the MAX1798/
MAX1798A/MAX1799/MAX1799A: the MAX1798/
MAX1798A feature an SPI™-compatible serial interface,
and the MAX1799/MAX1799A feature an I2C-compati-
ble interface. The “A” parts have a -13% reset thresh-
old, the non-A parts have a 9.5% threshold. The “A”
parts have a 175 delay on a reset-triggered shutdown,
the non-A shutdown instantly.
Each linear regulator features extremely low dropout
voltage, specified at two-thirds of the maximum output
current. LDO1 is rated for 300mA, while LDOs 2–5 are
each rated for 150mA. All LDOs are optimized for low
noise and isolation. Each LDO can be individually
enabled and disabled through the serial port, as well as
individually programmed to any of 32 voltages from
1.8V to 3.3V.
o One 300mA Low-Noise LDO
o Four 150mA Low-Noise LDOs
o 45µV
Noise from 10Hz to 100kHz
RMS
o >60dB Crosstalk Isolation Below 10kHz
o >60dB PSRR Below 10kHz
o 125mV (max) Dropout (OUT1 at 200mA)
o 100mV (max) Dropout (OUT2–5 at 100mA)
o Programmable Output Voltages
1.8V to 3.3V in 32 Steps
o 140ms (min) Reset Timer
o SPI- or I2C-Compatible Serial Interface
o Push-On/Push-Off Control Logic
o Two 150mA General Purpose Open-Drain Outputs
o Overcurrent and Thermal Protection (all LDOs)
o 1µA Shutdown Current
The MAX1798/MAX1798A/MAX1799/MAX1799As’ wide
2.5V to 5.5V input voltage range makes them compati-
ble with a wide range of input supplies, including a sin-
gle lithium-ion (Li+) cell battery. Both devices are
available in thermally-enhanced 20-pin TSSOP and
TQFN exposed pad (EP) packages. Evaluation kits in
TSSOP (MAX1798EVKIT and MAX1799EVKIT) are avail-
able to facilitate designs.
o 20-Pin Thermally-Enhanced TSSOP or TQFN
Packages
Applications
CDMA Cellular/PCS Handsets
Typical Operating Circuit
PDAs, Palmtops, and Handy-Terminals
Single-Cell Li+ Systems
IRQ
ONO
OFF
IN4/5
IN2/3
IN1
2- or 3-Cell NiMH, NiCd, or Alkaline Systems
WDOUT
2.5V
TO 5.5V
V
OUT1
RSO
CC
Ordering Information
RESET
TEMP
RANGE
MAX1798
MAX1798A*
MAX1799
PIN-
INTER-
FACE
PART
TX
RX
ON
OUT2
OUT3
OUT4
PACKAGE
MAX1799A*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
MAX1798ETP+
MAX1798EUP+
MAX1798AETP+
MAX1798AEUP+
20 TQFN
SPI
SPI
SPI
SPI
CS (AS)
SCLK (SCK)
DIN (SDA)
BP
BBA
20 TSSOP-EP*
20 TQFN
SPI OR I2C
AUDIO OR
PLL + VCO
OUT5
V
IN1
20 TSSOP-EP*
VIBRATOR
DR1
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
0.01µF
DR2
EP
GND
PGND
Ordering Information continued and Pin Configurations
appear at end of data sheet.
BACKLIGHT
( ) ARE FOR MAX1799/MAX1799A.
*-13% RESET THRESHOLD AND SHUTDOWN RESET TIMER ADDED.
SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
CDMA Cellular/PCS System
Power Supplies
ABSOLUTE MAXIMUM RATINGS
OFF, DR1, DR2 to GND............................................-0.3V to +6V
RSO................................................................................25mA
IN1, IN2/3, IN4/5, DIN (SDA) to GND.......................-0.3V to +6V
SCLK (SCK), BP, ON to GND...................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
20-Pin TQFN (derate 33.8mW/°C above +70°C) ...............2W
20-Pin TSSOP (derate 37.7mW/°C above +70°C) .............2W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
RSO, ONO to GND .................................-0.3V to (V
+ 0.3V)
OUT1
PGND to GND..................................................................... 0.3V
OUT1, CS (AS) to GND..............................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
IN1
IN2/3
IN4/5
OUT2, OUT3 to GND...............................-0.3V to (V
OUT4, OUT5 to GND...............................-0.3V to (V
Continuous Sink Current
DR1, DR2...............................................................100mA
RMS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
-ELECTRICAL CHARACTERISTICS
(V
= V
= V
= V
= V
= V
= V
= 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
OFF
IN1
IN2/3
IN4/5
SCLK (SCK)
DIN (SDA)
CS (AS)
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
= 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
T
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IN1, IN2/3, IN4/5 Operating
Voltage
2.5
5.5
V
Undervoltage Lockout IN1
Undervoltage Lockout IN2/3
Undervoltage Lockout IN4/5
Power-On Reset Threshold
Supply Current in Shutdown
Supply Current (Standby)
Supply Current (All Outputs On)
BP Voltage
V
IN1 rising edge
2.10
2.10
2.10
0.9
2.30
2.30
2.30
2.45
2.45
2.45
2.1
V
V
UVLO-1
V
IN2/3 rising edge
UVLO-2/3
UVLO-4/5
V
IN4/5 rising edge
V
IN1 falling edge
V
I
1
10
µA
µA
µA
V
OFF = 0, ON = IN1
OUT1 ON, other regulators OFF I
SHDN
I
= 0
OUT1
113
367
1.250
0.2
230
680
1.269
5
ON
All regulators ON, I
= 0
OUT_
I
BP
≤ 1nA
1.231
BP Supply Rejection
2.5V ≤ V
≤ 5.5V
mV
IN1
OUT1 REGULATOR
Output Accuracy
I
= 70mA (Note 3)
-2
-3
2
3
%
%
OUT1
Output Accuracy
(Line and Load)
1mA ≤ I
2.5V ≤ V
≤ 300mA,
OUT1
≤ 5.5V, V
= 1.8V (Note 3)
OUT1
IN1
Nominal Voltage Adjust Range
32 steps through serial interface; Tables 2, 3
1.8
3.3
V
I
I
= 1mA (Notes 1, 3)
1
OUT1
OUT1
Dropout Voltage
mV
= 200mA (Notes 1, 3)
73
125
8/MX179A
Load Regulation
Line Regulation
Current Limit
0.1mA ≤ I
≤ 300mA
-0.003
-0.03
500
%/mA
%/V
OUT1
2.5V ≤ V
≤ 5.5V, V
= 1.8V (Note 3)
OUT1
-0.15
320
0.11
850
IN1
mA
Output-Discharge Switch
Resistance in Shutdown
Regulator output turned off
25
300
Ω
(MAX1798/MAX1799)
(MAX1798A/MAX1799A)
= 4.7µF
-9.5
-15
-7.5
-13
45
-5.5
-11
OUT1 rising and
falling
OUT1 Reset Threshold
Output Voltage Noise
%
f = 10Hz to 100kHz, C
µV
OUT
RMS
2
_______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= V
= V
= V
= V
= 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
OFF
IN1
IN2/3
IN4/5
SCLK (SCK)
DIN (SDA)
CS (AS)
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
= 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
T
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT2–5 REGULATORS
Output Accuracy
I
= 50mA (Note 3)
-2
-3
2
3
%
%
OUT_
Output Accuracy
(Line and Load)
1mA ≤ I
2.5V ≤ V
≤ 150mA,
OUT_
≤ 5.5V, V
= 1.8V (Note 3)
OUT_
IN_
Nominal Voltage Adjust Range
32 steps through serial interface; Tables 2, 3
1.8
3.3
V
I
= 1mA (Notes 1, 3)
1
OUT_
OUT_
Dropout Voltage
mV
I
= 100mA (Notes 1, 3)
50
100
Load Regulation
Line Regulation
Current Limit
1mA ≤ I
2.5V ≤ V
≤ 150mA
-0.005
-0.02
250
%/mA
%/V
OUT_
≤ 5.5V, V
= 1.8V (Note 3)
-0.15
160
0.11
500
IN_
OUT_
mA
Output-Discharge Switch
Resistance
Regulator output turned off
f = 10Hz to 100kHz, C
110
45
300
Ω
Output Voltage Noise
= 2.2µF
µV
RMS
OUT
LOGIC AND CONTROL INPUTS (ON, OFF, RSO, DIN (SDA), SCLK (SCK), CS (AS))
Reset Timer
140
35
235
60
430
110
ms
Watchdog Timer
ms
OUT1 Shutdown Timer
(MAX1798A/MAX1799A only)
175
295
540
0.4
ms
Input Low Level
Input High Level
V
V
V
IL
V
IH
1.6
I
I
= 3mA
= 6mA
0.4
0.6
DIN (SDA)
SDA Output Low Level
(MAX1799 only)
V
DIN (SDA)
80
155
360
0.5
kΩ
OFF Pulldown Resistance
OFF = 5.5V
ONO Output Low Level
ONO Output High Level
RSO Output Low Level
I
I
I
I
= 1mA
= -1mA
= 1mA, V
= 0
0.05
V
V
V
V
ONO
ONO
RSO
RSO
V
-
-
OUT1
0.5
= 1V
0.5
IN1
V
RSO Output High Level
(Internal Pullup Resistor)
OUT1
0.5
9
14
19
kΩ
RSO Reset Resistance
RSO = 2.48V
= I = 100mA (Note 3)
DR1, DR2 Output Low Level
I
0.2
0.5
V
DR1
DR2
DR1, DR2 OFF Current
(Leakage)
I
V
DR1
= V = 5.5V
DR2
-1
1
µA
OFF
THERMAL SHUTDOWN
Threshold
160
10
°C
°C
Hysteresis
_______________________________________________________________________________________
3
CDMA Cellular/PCS System
Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= V
= V
= V
= V
= 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
OFF
IN1
IN2/3
IN4/5
SCLK (SCK)
DIN (SDA)
CS (AS)
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
T
A
= 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
I2C (SMB) TIMING (MAX1799/MAX1799A)
Clock Frequency
400
kHz
µs
SCK
Bus-Free Time Between START
and STOP
t
1.3
0.6
BUF
Hold Time Repeated START
Condition
t
t
µs
HD_STA
SCK Low Period
SCK High Period
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time Repeated START
Condition
0.6
µs
SU_STA
HD_DAT
Data Hold Time
Data Setup Time
t
0
µs
ns
t
100
SU_DAT
Maximum Pulse Width of Spikes
that Must Be Suppressed by the
Input Filter of Both SDA and
SCK Signals
t
50
ns
µs
SP
Setup Time for STOP Condition
t
0.6
SU_STO
SPI TIMING (MAX1798/MAX1798A)
SCLK Clock Frequency
SCLK Low Period
f
2
MHz
ns
SCLK
t
cl
125
125
0
SCLK High Period
t
ns
ch
HD_DAT
Data Hold Time
Data Setup Time
t
ns
t
125
ns
SU_DAT
CS Assertion to SCLK Rising
Edge Setup Time
t
200
200
200
ns
ns
ns
CSS
CS Deassertion to SCLK Rising
Edge Setup Time
t
CS1
SCLK Rising Edge to CS
Deassertion
t
CSH
SCLK Rising Edge to CS
Assertion
8/MX179A
t
t
200
300
ns
ns
CSO
CS High Period
CSW
4
_______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
ELECTRICAL CHARACTERISTICS
(V
= V
= V
= V
= V
= V
= V
= 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
OFF
IN1
IN2/3
IN4/5
SCLK (SCK)
DIN (SDA)
CS (AS)
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
= -40°C to +85°C, unless otherwise noted.) (Note 2)
T
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IN1, IN2/3, IN4/5 Operating
Voltage
(Note 1)
2.5
5.5
V
Undervoltage Lockout IN1
Undervoltage Lockout IN2/3
Undervoltage Lockout IN4/5
Power-On Reset Threshold
Supply Current in Shutdown
Supply Current (Standby)
Supply Current (All Outputs On)
BP Voltage
V
IN1 rising edge
2.10
2.10
2.10
0.9
2.45
2.45
2.45
2.1
V
V
UVLO-1
V
IN2/3 rising edge
UVLO-2/3
UVLO-4/5
V
IN4/5 rising edge
V
IN1 falling edge
V
I
10
µA
µA
µA
V
OFF = 0, ON = IN1
OUT1 ON, other regulators OFF I
SHDN
I
= 0
OUT1
230
680
1.275
ON
All regulators ON, I
= 0
OUT_
I
BP
≤ 1nA
1.225
OUT1 REGULATOR
Output Accuracy
I
= 70mA (Note 3)
-2.5
-3.5
1.8
2.5
3.5
%
%
OUT1
Output Accuracy
(Line and Load)
1mA ≤ I
2.5V ≤ V
≤ 300mA,
OUT1
≤ 5.5V, V
= 1.8V (Note 3)
OUT1
IN1
Nominal-Voltage Adjust Range
Dropout Voltage
32 steps through serial interface; Tables 2, 3
= 200mA (Notes 1, 3)
3.3
125
0.11
850
V
I
mV
%/V
mA
OUT1
Line Regulation
2.5V ≤ V
≤ 5.5V, V
= 1.8V (Note 3)
OUT1
-0.15
320
IN1
Current Limit
Output-Discharge Switch
Resistance in Shutdown
Regulator output turned off
300
Ω
MAX1798/MAX1799
-9.5
-15
-5.5
-11
OUT1 rising and
falling
OUT1 Reset Threshold
%
MAX1798A/MAX1799A
OUT2–5 REGULATORS
Output Accuracy
I
= 50mA (Note 3)
-2.5
-3.5
1.8
2.5
3.5
%
%
OUT_
Output Accuracy
(Line and Load)
1mA ≤ I
2.5V ≤ V
≤ 150mA,
OUT_
≤ 5.5V, V
= 1.8V (Note 3)
OUT_
IN_
Nominal-Voltage Adjust Range
Dropout Voltage
32 steps through serial interface; Tables 2, 3
= 100mA (Notes 1, 3)
3.3
100
0.11
500
V
I
mV
%/V
mA
OUT_
Line Regulation
2.5V ≤ V
≤ 5.5V, V
= 1.8V (Note 3)
OUT_
-0.15
160
IN_
Current Limit
Output-Discharge Switch
Resistance in Shutdown
Regulator output turned off
300
Ω
_______________________________________________________________________________________
5
CDMA Cellular/PCS System
Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= V
= V
= V
= V
= 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
OFF
IN1
IN2/3
IN4/5
SCLK (SCK)
DIN (SDA)
CS (AS)
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
= -40°C to +85°C, unless otherwise noted.) (Note 2)
T
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC AND CONTROL INPUTS (ON, OFF, RSO DIN (SDA), SCLK (SCK), CS (AS))
Reset Timer
140
35
430
110
ms
ms
Watchdog Timer
OUT1 Shutdown Timer
(MAX1798A/MAX1799A only)
175
540
0.4
ms
Input Low Level
Input High Level
V
V
V
IL
V
IH
1.6
I
I
= 3mA
= 6mA
0.4
0.6
DIN (SDA)
SDA Output Low Level
(MAX1799 only)
V
DIN (SDA)
0 ≤ V ≤ V ; ON, DIN (SDA),
SCLK (SCK), and CS (AS) only
IN
IN1
Logic Input Current
-1
1
µA
80
360
0.5
kΩ
OFF Pulldown Resistance
OFF = 5.5V
ONO Output Low Level
I
I
I
I
= 1mA
= -1mA
= 1mA, V
= 0
V
ONO
ONO
RSO
RSO
V
V
-
-
OUT1
0.5
ONO Output High Level
V
V
V
= 1V
0.5
RSO Output Low Level
IN1
RSO Output High Level
(Internal Pullup Resistor)
OUT1
0.5
9
19
kΩ
RSO Reset Resistance
RSO = 2.48V
= I = 100mA (Note 3)
DR1, DR2 Output Low Level
I
0.5
V
DR1
DR2
DR1, DR2 OFF Current
(Leakage)
I
V
DR1
= V = 5.5V
DR2
-1
1
µA
OFF
I2C (SMB) TIMING (MAX1799/MAX1799A)
Clock Frequency
400
kHz
µs
SCK
Bus-Free Time Between START
and STOP
t
1.3
0.6
BUF
Hold Time Repeated START
Condition
t
t
µs
HD_STA
SCK Low Period
SCK High Period
t
1.3
0.6
µs
µs
LOW
8/MX179A
t
HIGH
Setup Time Repeated START
Condition
0.6
µs
SU_STA
HD_DAT
Data Hold Time
t
0
89
µs
ns
µs
Data Setup Time
t
t
100
0.6
SU_DAT
Setup Time for STOP Condition
SU_STO
6
_______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= V
= V
= V
= V
= 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
OFF
IN1
IN2/3
IN4/5
SCLK (SCK)
DIN (SDA)
CS (AS)
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
SPI TIMING (MAX1798/MAX1798A)
SCLK Clock Frequency
SCLK Low Period
f
2
MHz
ns
SCLK
t
cl
125
125
0
SCLK High Period
t
ns
ch
HD_DAT
Data Hold Time
Data Setup Time
t
ns
t
125
ns
SU_DAT
CS Assertion to SCLK Rising
Edge Setup Time
t
200
200
200
ns
ns
ns
CSS
CS Deassertion to SCLK Rising
Edge Setup Time
t
CS1
SCLK Rising Edge to CS
Deassertion
t
CSH
CSO
SCLK Rising Edge to CS
Assertion
t
t
200
300
ns
ns
CS High Period
CSW
Note 1: The dropout voltage is defined as (V - V
) when V
is 100mV below the value of V
for V = V + 1V.
IN OUT
IN
OUT
OUT
OUT
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
Note 3: Specifications are guaranteed by design, not production tested in the ETP (TQFN) packages.
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
OUTPUT VOLTAGE ACCURACY (OUT2–5)
vs. LOAD CURRENT
OUTPUT VOLTAGE ACCURACY (OUT1)
vs. TEMPERATURE
OUTPUT VOLTAGE ACCURACY (OUT1)
vs. LOAD CURRENT
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
2.0
I
= 70mA
LOAD
V
= 2.98V
OUT1(NOM)
1.5
1.0
0.5
V
= 3.3V
OUT1
V
= 3.3V
OUT1
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
V
= 2.98V
V
V
= 1.8V
OUT1
OUT1
V
= 2.98V
250
OUT1
= 1.8V
125
OUT1
0
25
50
75
100
150
-40
-15
10
35
60
85
0
50
100
150
200
300
LOAD CURRENT (mA)
TEMPERATURE (°C)
LOAD CURRENT (mA)
_______________________________________________________________________________________
7
CDMA Cellular/PCS System
Power Supplies
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
GROUND-PIN CURRENT (OUT1)
vs. TEMPERATURE
GROUND-PIN CURRENT (OUT1)
GROUND-PIN CURRENT (OUT1)
vs. SUPPLY VOLTAGE (V
)
vs. LOAD CURRENT
IN1
200
400
350
300
250
200
150
100
50
200
190
V
= 2.98V
V
= 3.6V
V
I
= 3.6V
OUT1
IN1
IN
190
180
170
160
150
140
130
120
110
100
OUT2–5 OFF
= 200mA
V
= 3.3V
LOAD
OUT1
180
170
160
150
140
I
= 200mA
LOAD
V
= 1.8V
OUT1
200
V
= 2.98V
OUT1
I
= 0
LOAD
0
0
50
100
150
250
300
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
LOAD CURRENT (mA)
TEMPERATURE (°C)
DROPOUT VOLTAGE (OUT1)
vs. LOAD CURRENT
DROPOUT VOLTAGE (OUT2–5)
vs. LOAD CURRENT
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
90
80
150
125
150
125
C
= 2.2µF
OUT2–5
70
60
T
= +85°C
A
100
75
50
25
0
100
75
50
25
0
T
= +85°C
A
50
40
30
20
10
0
C
= 4.7µF
OUT1
T
= +25°C
A
T
= -40°C
T
= +25°C
125
A
A
V
= 2.98V
= 10mA
OUT_
T
= -40°C
A
I
LOAD
C
= 0.01µF
BP
0.01
0.1
1
10
100
1000
0
50
100
150
200
250
300
0
25
50
75
100
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FREQUENCY (kHz)
CHANNEL-TO-CHANNEL ISOLATION
vs. FREQUENCY
OUTPUT NOISE vs. LOAD CURRENT
OUTPUT NOISE
70
60
50
40
30
20
10
0
OUT1 = 2.98V
8/MX179A
C
= 4.7µF
OUT1
60
50
40
OUT2–5 = 2.98V
= 2.2µF
C
OUT2–5
30
20
10
0
OUT2/3 = 2.98V
C
I
= 2.2µF
f = 10Hz TO 100kHz
OUT2/3
= 100mA
f = 10Hz TO 100kHz
= 0.01µF
C
C
= 2.2µF, I
= 10mA
LOAD
OUT2
= 0.01µF
BP
LOAD
C
= 0.01µF
C
BP
BP
0.1
1
10
100
1000
1
10
100
1000
100µs/div
, 50µV/div
V
FREQUENCY (kHz)
LOAD CURRENT (mA)
OUT
8
_______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
LINE-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
MAX1798/99-13
MAX1798/99-14
V
I
= 3.7V TO 4.0V, V
= 2.98V
OUT
V
I
= 3.5V, V
= 2.98V
OUT1
IN
IN1
= 100mA
= 20mA TO 200mA, OUT2/3/4/5 = OFF
LOAD
LOAD
20µs/div
2µs/div
LOAD-TRANSIENT RESPONSE
(NEAR DROPOUT)
ENTERING SHUTDOWN
MAX1798/99-15
OFF
2V/div
V
OUT1
1V/div
V
= 3.1V, V
= 2.98V
IN1
OUT1
I
= 20mA TO 200mA, OUT2/3/4/5 = OFF
I
= 0
LOAD
LOAD
2µs/div
10ms/div
TSSOP/TQFN SAFE OPERATING AREA
(POWER DISSIPATION LIMIT)
STARTUP
1000
900
800
700
600
500
400
300
200
MAX TOTAL OUTPUT CURRENT
ON
2V/div
V
= 1.8V
V
OUT
V
OUT
= 2.98V
2V/div
OUT
RSO
2V/div
T
T
= +25°C
= +85°C
A
A
40ms/div
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
CDMA Cellular/PCS System
Power Supplies
Pin Description
PIN
NAME
FUNCTION
TSSOP
QFN
2
Chip-Select Input for SPI (MAX1798/MAX1798A). Address Select Input for I C (MAX1799/
MAX1799A).
1
19
CS (AS)
SCLK
(SCK)
Clock Input for Serial Interface. Data is read on the rising edge of the clock. SCLK for
MAX1798/MAX1798A. SCK for MAX1799/MAX1799A.
2
3
20
1
DIN
(SDA)
Data Input for Serial Interface. Data is read on the rising edge of the clock. DIN for
MAX1798/MAX1798A. SDA for MAX1799/MAX1799A.
On Output. Indicates the state of ON. After initial power-up, the logic level of this pin follows that
of ON. Used to signal the microcontroller (µC) for an OFF request (allows push-on/push-off).
4
5
6
7
2
3
4
5
ONO
GND
BP
Ground
1.25V Reference Bypass. Connect a 0.01µF bypass capacitor to GND for reduced noise.
Do not load this pin.
PGND
Power Ground
Reset Output. Holds the µC system reset line low during initial startup and whenever OUT1 falls
out of regulation. RSO has a 140ms (min) timeout period and is an open-drain output with an
internal 14kΩ pullup to OUT1. The RSO line maintains a valid low output level for IN1 as low as
1V.
8
6
RSO
2Ω Open-Drain Driver Output 1. Maximum sink current is 150mA (100mA
10 LEDs for backlight or a vibrator motor.
). Can drive up to
RMS
9
7
8
DR1
DR2
2Ω Open-Drain Driver Output 2. Maximum sink current is 150mA (100mA
10 LEDs for backlight or a vibrator motor.
). Can drive up to
RMS
10
OFF Input. A low level to this pin when ON is high turns off the IC once the watchdog timer has
timed out. A high-level input keeps the chip on. There is an internal 155kΩ pulldown resistor at
this input.
11
9
OFF
Output 5, Output of Linear Regulator 5; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND.
12
13
14
10
11
12
OUT5
IN4/5
OUT4
Supply Inputs 4 and 5. Voltage supply for linear regulators 4 and 5.
Output 4, Output of Linear Regulator 4; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND.
Output 1, Output of Linear Regulator 1; 300mA (max) Output Current. Connect a 4.7µF ceramic
bypass capacitor to PGND.
15
16
17
18
19
13
14
15
16
17
OUT1
IN1
8/MX179A
Supply Input 1. Voltage supply for linear regulator 1 and serial interface.
Output 3, Output of Linear Regulator 3; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND.
OUT3
IN2/3
OUT2
Supply Inputs 2 and 3. Voltage supply for linear regulators 2 and 3.
Output 2, Output of Linear Regulator 2; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND
ON Input. An active-low turns on the device, enabling LDO1, RESET, the ON/OFF logic, and the
serial interface.
20
—
18
—
ON
EP
Exposed Pad. Connect the exposed pad to a ground plane to provide heat sinking.
10 ______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
Table 1. Control Data Byte
COMMAND
DIN (SDA)
D2
FUNCTION
C2
C1
C0
D4
D3
D1
D0
U2
Update DAC Outputs
OUT1 DAC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
U5
U1
DAC1 (Table 2)
OUT2 DAC
DAC1 (Table 2)
OUT3 DAC
DAC1 (Table 2)
OUT4 DAC
DAC1 (Table 2)
OUT5 DAC
DAC1 (Table 2)
Driver Outputs
ON/OFF Conrol
X
X
X
DR2
ON2
DR1
ON1
ON5
ON4
ON3
Note: C2 is MSB, and D0 is LSB. X = Don’t care.
OUT2–5 are set to 2.98V, but turned off. The control
data byte must be used to turn them on. If V falls
Detailed Description
IN1
The MAX1798/MAX1798A/MAX1799/MAX1799A drive
CDMA cellular and PCS handsets or systems with
inputs from 2.5V to 5.5V. The devices contain five
LDOs, two open-drain outputs, and a reset output as
shown in Figure 1. All outputs are individually program-
mable through either an SPI (MAX1798/MAX1798A) or
I2C (MAX1799/MAX1799A) serial-port interface. The
outputs may be turned on or off individually through the
serial interface. Their output voltages are adjustable
from 1.8V to 3.3V in 32 increments. At power-up, all
outputs are at a default value of 2.98V, but only OUT1
is on. OUT1 is rated for 300mA and optimized for low
dropout. OUT2–5 are rated for 150mA. All LDOs are
optimized for low noise, high isolation, and low dropout.
below 1V, a POR circuit resets all LDO voltages to
2.98V and OUT2–5 are turned off. If V or V fall
IN2/3
IN4/5
below 2.15V, the UVLO circuit turns off the correspond-
ing output, but all LDO voltages remain at their prior
settings. OUT2–5 are optimized for low noise and high
isolation.
Open-Drain Outputs
The open-drain N-channel MOSFETs (DR1 and DR2,
Figure 2) have a nominal 2Ω on-resistance and can be
used to drive up to 10 LEDs for backlight or a vibrator
motor. DR1 and DR2 can sink 100mA
(max). At
RMS
power-up, DR1 and DR2 are high impedance and are
commanded on by the control data byte.
Linear Regulator 1
Regulator 1 is a low-dropout linear regulator that
sources 300mA (max), operating from a 2.5V to 5.5V
RSO
RSO is an open-drain output, connected to OUT1
through an internal 14kΩ resistor. At power-up, OUT1
turns on and RSO is held low for 140ms (min). When RSO
goes high, OFF must be brought high within 35ms to
keep OUT1 on. Otherwise, if OFF is low, the watchdog
timer circuit counts down 35ms (min), and RSO is
actively held low while the entire device turns off.
input voltage (V ). OUT1 is turned on by using the on
IN1
button. OUT1 is turned off by using either the off pin or
the serial port. Its output can be adjusted from 1.8V to
3.3V from the SPI or I2C serial-port interface by setting
the control data byte (Table 1). OUT1 is always on
when the MAX1798/MAX1798A/MAX1799/MAX1799A
are on. If OUT1 is turned off, the entire IC shuts down. If
The MAX1798/MAX1799 RSO goes low when OUT1
droops by more than 7.5% 2% of its programmed out-
put voltage. The MAX1798A/MAX1799A RSO goes low
when OUT1 droops by more than 13% 2% of its pro-
grammed output voltage. RSO stays low for 140ms
(min) after OUT1 rises above the threshold. During this
time, the watchdog timer circuit is inactive.
V
falls below 1V, a POR circuit resets all LDO volt-
IN1
ages to 2.98V and OUT1 is left on while OUT2–5 are
turned off.
Linear Regulators 2–5
Regulators 2–5 are LDOs that source 150mA (max)
from input voltages (V
and V
) of 2.5V to 5.5V.
IN4/5
IN2/3
The MAX1798A/MAX1799A have an additional timer
circuit to shut down the regulators when the RSO and
watchdog timer time out. If the OUT1 voltage level ever
exceeds the RSO threshold level before the reset and
OUT2–5 can be turned on or off and adjusted from 1.8V
to 3.3V through the SPI or I2C serial-port interface by
setting the control data byte (Table 1). At power-up,
______________________________________________________________________________________ 11
CDMA Cellular/PCS System
Power Supplies
ONO
OFF
ON DETECT
IRQ
WDOUT
ON
ON/OFF
LOGIC
OFF
ON
155kΩ
100kΩ
THERMAL SHUTDOWN
1.8V TO 3.3V
300mA
OUT1
LDO1
(LOW NOISE, 0.3Ω)
IN1
V
CC
4.7µF
5-BIT DAC
14kΩ
ACTIVE-LOW
RESET
(140ms)
RSO
RESET
THERMAL SHUTDOWN
1.8V TO 3.3V
150mA
LDO2
(LOW NOISE, 0.5Ω)
OUT2
OUT3
OUT4
OUT5
TX
RX
5-BIT DAC
2.2µF
IN2/3
10µF
THERMAL SHUTDOWN
1.8V TO 3.3V
150mA
LDO3
(LOW NOISE, 0.5Ω)
5-BIT DAC
2.2µF
THERMAL SHUTDOWN
1.8V TO 3.3V
150mA
LDO4
(LOW NOISE, 0.5Ω)
BBA + TCXO
5-BIT DAC
2.2µF
IN4/5
THERMAL SHUTDOWN
1.8V TO 3.3V
150mA
LDO5
(LOW NOISE, 0.5Ω)
V
BATT
AUDIO OR
PLL + VCO
2.5V TO 5.5V
5-BIT DAC
2.2µF
V
BATT
DR1
DR2
VIBRATOR
MOTOR
2Ω
CS (AS)*
CONTROL
REGISTERS
8/MX179A
SCLK (SCK)*
DIN (SDA)*
SERIAL PORT
SPI OR I2C
2Ω
(ON/OFF
AND V
OUT
PROGRAMMING)
BP
MAX1798/MAX1798A
MAX1799/MAX1799A
0.01µF
GND
PGND
( ) *ARE FOR MAX1799.
Figure 1. Typical Application Circuit/Functional Diagram
12 ______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
A
B
C
D
E
F
G
H
I
J
K
L
M
t
t
HIGH
LOW
SCL
SDA
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:DAT
t
t
SU:STO
BUF
A = START CONDITION
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
E = SLAVE PULLS SMBDATA LINE LOW
Figure 2. I2C-Compatible Serial-Interface Timing Diagram
ON
(INPUT)
OUT1
140ms min
35ms max
140ms min
RSO
(OUTPUT)
10µs min
35ms max
52ms typ
OFF
(INPUT)
35ms max
ONO
(OUTPUT)
PULSED HIGH
OR CONTINUOUS HIGH
Figure 3. Push-On/Push-Off Startup and Shutdown Timing Diagram
watchdog timers time out, the shutdown timer is reset.
The shutdown timer requires continuous low RSO signal
and continuous nontriggered watchdog timer to shut
down the regulators.
140ms (min). At this time, OUT1 is on and set to 2.98V,
while OUT2–5 are disabled and set to 2.98V. To stay
on, the OFF pin must be in a high state within 35ms
(min) or the device will shut down and can only be
turned on by pressing the ON button. While ON is held
low, the status of OFF is irrelevant and OUT1 and the
serial port are on.
ON and OFF Logic
See Figure 3. The MAX1798/MAX1798A/MAX1799/
MAX1799A power up when V
is greater than 2.5V
IN1
After initial power-up, the logic level of ONO follows the
logic level of ON but is level-shifted to OUT1 high volt-
age. This signal can be used to interrupt the system
controller, which can subsequently manage an orderly
shutdown through the serial port by turning off OUT1.
and ON is low (ON button is pressed down momentari-
ly). When ON returns high, the device remains on. It
turns on OUT1 and the serial interface port. Once
OUT1 is in regulation, RSO stays low an additional
______________________________________________________________________________________ 13
CDMA Cellular/PCS System
Power Supplies
Hard Shutdown
To shut down the MAX1798/MAX1798A/MAX1799/
MAX1799A, drive OFF low or allow the internal resistor
to pull down OFF while ON is high. The device shuts
down after the watchdog timer has cleared (35ms min,
52ms typ). During shutdown, all LDO outputs and RSO
are actively pulled to GND, the open-drain drivers are
in a high-impedance state, and the serial port and reset
timer are inactive. Previously programmed output volt-
age data is retained in the internal registers as long as
CS along with SCLK and DIN to communicate. The seri-
al port operates when the device is enabled, even when
RSO is low. The MAX1798/MAX1798A can support a
2MHz (max) data rate. This SPI-compatible port uses
the CPOL = CPHA = 0 protocol.
I2C-Compatible Serial Interface
Use an I2C-compatible 2-wire serial interface with the
MAX1799/MAX1799A to control the ON/OFF state and
output voltage of each regulator, the ON/OFF state of
the drivers, and to shut down the device. Use standard
I2C-compatible write-byte commands to program the
IC. Figure 2 is a timing diagram for the I2C protocol.
The MAX1799/MAX1799A is always a slave to the bus
master. The serial port operates when the device is
enabled, even when OUT1 and RSO are low. When AS
is high, the address is 0111111. When AS is low, the
address is 1001111. Two MAX1799/MAX1799A devices
can be controlled by a single bus master.
V
> 2.1V. If the device is turned back on by the ON
IN1
button, OUT1 automatically is enabled with the preshut-
down output voltage. OUT2–5 automatically return to
their preshutdown voltages once they are enabled
through the serial interface.
Soft Shutdown
The serial port can also be used to shut down the
MAX1798/MAX1798A/MAX1799/MAX1799A. Using the
control data byte to disable OUT1 will shut down the
entire device. Once shut down, the only means to turn
on the device is through a momentary low on the ON
button.
Output Voltage
The MAX1798/MAX1798A/MAX1799/MAX1799A are
supplied with factory-set output voltages. At power-up,
all DACS are set for 2.98V, while only OUT1 is enabled;
all other LDO outputs and drivers are off. OUT2–5,
DR1, and DR2 must be enabled on with the serial port.
OUT2–5 can be individually programmed through the
serial port from 1.8V to 3.3V in 32 steps, either while on
or off. OUT1 can be programmed in 32 steps from 1.8V
to 3.3V only while on. (If OUT1 is off, the serial port is
also off, and OUT1 cannot be programmed.) If OUT1 is
turned off through the serial port or the OFF pin, the
entire chip, including the serial port, will be shut down.
However, all previously programmed DAC settings will
be retained as long as a valid supply voltage is main-
Control Data Byte
The control data byte is 8 bits long (3 command bits
and 5 data bits). The first 3 bits specify the action to be
taken, while the last 5 bits set the output voltage or
ON/OFF status. Each regulator has an individual DAC
that sets the output voltage. The DAC registers are
double buffered to allow for simultaneous updating of
all outputs. The output voltage is programmed per
Table 2 or Table 3. At power-up, if no specific voltage
is programmed, OUT1–5 will be set for 2.98V. All DAC
programming must be shifted from the double buffer to
the DACs with the update DAC command (Table 1,
000XXXXX) for the programmed voltages to be seen at
the LDO outputs. The DACs can be updated one at a
time or all at once after all desired outputs are pro-
grammed. The ON/OFF status of the LDOs and drivers
is not double-buffered and takes immediate effect upon
CS returning high (SPI compatible) or upon the ninth
rising edge of SCK during the command byte (Figure 2,
edge L). A one turns on the LDO output or driver out-
put, and a zero turns it off.
tained on IN1 (V
> 2.1V).
IN1
Current Limit
The MAX1798/MAX1798A/MAX1799/MAX1799A
include current limiting on each LDO output. OUT1 has
a current limit set at 500mA (320mA min), while
OUT2–5 have current limits set at 250mA (160mA min).
When the LDO output is in current limit, the current-lim-
iter device monitors and controls the pass transistor’s
gate voltage, limiting the output current available from
the LDO. Once the excessive load is removed, normal
function resumes automatically.
8/MX179A
SPI-Compatible Serial Interface
Use an SPI-compatible 3-wire serial interface with the
MAX1798/MAX1798A to control the ON/OFF state and
output voltage of each regulator, the ON/OFF state of
the drivers, and to shut down the device. Figures 4a
and 4b are timing diagrams for the SPI protocol. The
MAX1798/MAX1798A is a write-only device and uses
14 ______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
Table 2. OUT1–5 Output Voltages
(Binary Format)
Table 3. OUT1–5 Output Voltages
(Hexadecimal Format)
DAC_ DATA
DAC_ DATA
OUT1–
OUT1–
D4
D3
D2
D1
D0
OUT5
OUT4
OUT3
OUT2
OUT1
OUT5
OUT5
1.800
1.827
1.854
1.883
1.912
1.942
1.974
2.006
2.039
2.074
2.109
2.146
2.184
2.224
2.265
2.308
2.352
2.398
2.445
2.495
2.547
2.601
2.657
2.716
2.777
2.842
2.909
2.980
3.054
3.132
3.214
3.300
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.800
1.827
1.854
1.883
1.912
1.942
1.974
2.006
2.039
2.074
2.109
2.146
2.184
2.224
2.265
2.308
2.352
2.398
2.445
2.495
2.547
2.601
2.657
2.716
2.777
2.842
2.909
2.980
3.054
3.132
3.214
3.300
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
______________________________________________________________________________________ 15
CDMA Cellular/PCS System
Power Supplies
INSTRUCTION
EXECUTED
CS
1
8
SCLK
DIN
A0
A2 A1
D4 D3 D2 D1 DO
Figure 4a. Serial-Interface Timing Diagram
CS
t
CSW
t
CSH0
t
CSS0
t
CSH1
t
CH
SCLK
t
t
CL
t
CSS1
DS
t
DH
DIN
Figure 4b. Detailed Serial-Interface Timing Diagram
Thermal-overload protection is designed to protect the
MAX1798/MAX1798A/MAX1799/MAX1799A in the
event of fault conditions. For continual operation, do not
exceed the absolute maximum junction-temperature
Thermal-Overload Protection
The MAX1798/MAX1798A/MAX1799/MAX1799A inte-
grate a separate thermal monitor for each linear regula-
tor. When the junction temperature of any LDO exceeds
8/MX179A
rating of T = +150°C.
J
T = +160°C, the specific thermal sensor signals the
J
shutdown logic, turning off the pass transistor and
allowing that LDO to cool. The thermal sensor turns the
pass transistor on again after the LDO’s junction tem-
perature cools by 10°C, resulting in a pulsed output
during continuous thermal-overload conditions. Due to
the substrate’s thermal conductivity, a thermal overload
on one LDO may possibly affect other LDOs on the
device.
Noise Reduction
Bypass BP to GND with an external 0.01µF bypass
capacitor. The MAX1798/MAX1798A/MAX1799/
MAX1799A exhibit 45µV
of output voltage noise.
RMS
Graphs of Output Noise vs. Load Current, Output Noise
(10Hz to 100kHz), PSRR vs. Frequency, and Channel-
to-Channel Isolation vs. Frequency appear in the
Typical Operating Characteristics.
16 ______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
When operating from sources other than batteries,
Applications Information
improved supply noise rejection and transient response
can be achieved by increasing the values of the input
and output bypass capacitors and through passive fil-
tering techniques. The Typical Operating Character-
istics show the MAX1798/MAX1798A/MAX1799/
MAX1799A line- and load-transient responses.
Capacitor Selection and
Regulator Stability
Use a 10µF low-ESR ceramic capacitor on the
MAX1798/MAX1798A/MAX1799/MAX1799A’s input if all
the supply inputs are connected together. Larger input
capacitance and lower ESR provide better supply noise
rejection and line-transient response. If IN1, IN2/3, and
IN4/5 are connected to different supply voltages,
bypass each input with a 4.7µF low-ESR ceramic
capacitor.
Load-Transient Considerations
The MAX1798/MAX1798A/MAX1799/MAX1799A load-
transient response graphs (see Typical Operating
Characteristics) show three components of the output
response: the output capacitor’s ESR spike, the regula-
tor’s transient settling response, and the DC shift due to
the LDO’s load regulation. Increasing the output capaci-
tor’s value and decreasing the ESR reduce the over-
shoot.
A minimum 4.7µF low-ESR ceramic capacitor is recom-
mended on OUT1, and a minimum 2.2µF low-ESR
ceramic capacitor is recommended on OUT2–5. The
MAX1798/MAX1798A/MAX1799/MAX1799A are stable
with output capacitors in the ESR range of 10mΩ to 1Ω.
Use larger capacitors to reduce noise and improve
load-transient response, stability, and power-supply
rejection.
Dropout Voltage
A regulator’s minimum input-output voltage differential
(dropout voltage) determines the lowest usable supply
voltage. In battery-powered systems, this determines
the useful end-of-life battery voltage. Because the
MAX1798/MAX1798A/MAX1799/MAX1799A use P-
channel MOSFET pass transistors, their dropout volt-
age is a function of drain-to-source on-resistance
Note that some ceramic dielectrics exhibit large capac-
itance and ESR variation with temperature. With
dielectrics such as Z5U and Y5V, it may be necessary
to use a minimum 4.7µF on OUT2–5 to ensure stability
at temperatures below -10°C. With X7R or X5R
dielectrics, 2.2µF should be sufficient at all operating
temperatures. Tantalum capacitors may cause instabili-
ty with the MAX1798/MAX1798A/MAX1799/MAX1799A
and are not recommended for this application.
(R
) multiplied by the load current. See the
DS(ON)
Dropout Voltage (OUT1) vs. Load Current graph in the
Typical Operating Characteristics.
Use a 0.01µF bypass capacitor at BP for low output-
voltage noise. Increasing the capacitance will slightly
decrease the output noise but will increase the startup
time. Values above 0.1µF provide no performance
advantage and are not recommended.
Ordering Information (continued)
TEMP
INTER-
FACE
PIN-
PACKAGE
PART
RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
MAX1799ETP+
MAX1799EUP+
MAX1799AETP+
20 TQFN
I2C
I2C
I2C
I2C
Line-Transient Considerations
The MAX1798/MAX1798A/MAX1799/MAX1799A are
designed to deliver low dropout voltages and low qui-
escent currents in battery-powered systems. Power-
supply rejection is >60dB at low frequencies and rolls
off above 10kHz. See the Power-Supply Rejection Ratio
(PSRR) vs. Frequency graph in the Typical Operating
Characteristics.
20 TSSOP-EP
20 TQFN
MAX1799AEUP+ -40°C to +85°C
20 TSSOP-EP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________ 17
CDMA Cellular/PCS System
Power Supplies
Pin Configurations
TOP VIEW
+
TOP VIEW
CS (AS)
SCLK (SCK)
DIN (SDA)
ONO
1
2
3
4
5
6
7
8
9
20 ON
19 OUT2
18 IN2/3
17 OUT3
16 IN1
20
19
18
17
16
+
MAX1798
MAX1798A
MAX1799
MAX1799A
GND
DIN (SDA)
ON0
1
15 OUT3
14 IN1
BP
15 OUT1
2
PGND
14
OUT4
MAX1798
MAX1798A
MAX1799
MAX1799A
RSO
13 IN4/5
12 OUT5
GND
BP
3
4
13 OUT1
12 OUT4
DR1
OFF
11
DR2 10
TSSOP
PGND
5
11 IN4/5
( ) ARE FOR MAX1799/MAX1799A ONLY.
6
7
8
9
10
THIN QFN
Package Information
✕
✕
5mm 5mm 0.75mm
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
( ) ARE FOR MAX1799/MAX1799A ONLY.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 TQFN
T2055+4
21-0140
21-0108
20 TSSOP-EP
U20E+1
8/MX179A
18 ______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
8/MX179A
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
2
5/10
Replaced QFN package with TQFN package
1, 2, 7, 9, 10, 17, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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