MAX1845 [MAXIM]
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit; 双路，高效率，降压型控制器，带有精确限流
| 型号： | MAX1845 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit |
| 文件： | 总27页 (文件大小：540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1955; Rev 2; 1/03
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
General Description
Features
The MAX1845 is a dual PWM controller configured for
step-down (buck) topologies that provides high efficien-
cy, excellent transient response, and high DC output
accuracy necessary for stepping down high-voltage bat-
teries to generate low-voltage chipset and RAM power
supplies in notebook computers. The CS_ inputs can be
used with low-side sense resistors to provide accurate
current limits or can be connected to LX_, using low-side
MOSFETs as current-sense elements.
o Ultra-High Efficiency
o Accurate Current-Limit Option
o Quick-PWM™ with 100ns Load-Step Response
o 1% V Accuracy over Line and Load
OUT
o Dual Mode™ Fixed 1.8V/1.5V/Adj or 2.5V/Adj Outputs
o Adjustable 1V to 5.5V Output Range
o 2V to 28V Battery Input Range
The on-demand PWM controllers are free running, con-
stant on-time with input feed-forward. This configuration
provides ultra-fast transient response, wide input-output
differential range, low supply current, and tight load-reg-
ulation characteristics. The MAX1845 is simple and easy
to compensate.
o 200/300/420/540kHz Nominal Switching Frequency
o Adjustable Overvoltage Protection
o 1.7ms Digital Soft-Start
o Drives Large Synchronous-Rectifier FETs
o Power-Good Window Comparator
o 2V 1% Reference Output
Single-stage buck conversion allows the MAX1845 to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the 5V system supply instead of the bat-
tery at a higher switching frequency) allows the minimum
possible physical size.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
The MAX1845 is intended for generating chipset, DRAM,
CPU I/O, or other low-voltage supplies down to 1V. For a
single-output version, refer to the MAX1844 data sheet.
The MAX1845 is available in 28-pin QSOP and 36-pin
thin QFN packages.
MAX1845EEI
-40°C to +85°C
28 QSOP
36 Thin QFN
6mm ✕ 6mm
MAX1845ETX
-40°C to +85°C
Applications
Minimal Operating Circuit
Notebook Computers
5V INPUT
BATTERY
CPU Core Supplies
4.5V TO 28V
V
V
V+
DD
Chipset/RAM Supply as Low as 1V
1.8V and 2.5V I/O Supplies
UVP
OVP
CC
MAX1845EEI
ILIM1
ILIM2
ON1
ON2
BST1
DH1
LX1
BST2
DH2
LX2
OUTPUT1
1.8V
OUTPUT2
2.5V
DL1
DL2
CS2
TON
CS1
OUT1
PGOOD
REF
OUT2
SKIP
FB2
FB1
GND
Pin Configurations appear at end of data sheet.
Quick-PWM and Dual Mode are trademarks of Maxim Integrated
Products.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ to AGND..............................................................-0.3 to +30V
LX_ to BST_ ..............................................................-6V to +0.3V
DH2 to LX2 ..............................................-0.3V to (V + 0.3V)
REF Short Circuit to GND...........................................Continuous
V
V
to AGND............................................................-0.3V to +6V
to PGND............................................................-0.3V to +6V
CC
DD
BST2
AGND to PGND.....................................................-0.3V to +0.3V
PGOOD, OUT_ to AGND..........................................-0.3V to +6V
OVP, UVP, ILIM_, FB_, REF,
Continuous Power Dissipation (T = +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C)........860mW
36-Pin 6mm ✕ 6mm Thin QFN
(derate 26.3mW/°C above +70°C).............................2105mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
A
SKIP, TON, ON_ to AGND......................-0.3V to (V
DL_ to PGND..............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
CC
DD
BST_ to AGND........................................................-0.3V to +36V
CS_ to AGND.............................................................-6V to +30V
DH1 to LX1 ..............................................-0.3V to (V
+ 0.3V)
BST1
Note 1: For the MAX1845EEI, AGND and PGND refer to a single pin designated GND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V
noted.)
= V = 5V, SKIP = AGND, V+ = 15V, T = 0°C to +85°C, typical values are at +25°C, unless otherwise
CC A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLERS
V+
Battery voltage, V+
, V
2
28
Input Voltage Range
V
V
/V
CC DD
V
4.5
5.5
CC DD
FB1 to AGND
FB1 to V
1.782
1.485
0.99
1.8
1.5
1
1.818
1.515
1.01
V+ = 2V to 28V, I
= 0 to 8A, SKIP = V
+25°C to +85°C
LOAD
,
CC
CC
FB1 to OUT1
FB1 to AGND
DC Output Voltage OUT1
(Note 2)
V
V
V
V
OUT1
1.773
1.477
0.985
1.8
1.5
1
1.827
1.523
1.015
V+ = 2V to 28V, I
LOAD
= 0 to 8A, SKIP = V
0°C to +85°C
,
FB1 to V
CC
CC
FB1 to OUT1
V+ = 4.5V to 28V,
FB2 to AGND
2.475
0.99
2.5
1
2.525
1.01
I
= 0 to 4A,
LOAD
SKIP = V
,
CC
FB2 to OUT2
FB2 to AGND
FB2 to OUT2
+25°C to +85°C
DC Output Voltage OUT2
(Note 2)
OUT2
V+ = 4.5V to 28V,
2.463
0.985
2.5
1
2.537
1.015
I
= 0 to 4A,
LOAD
SKIP = V
,
CC
0°C to +85°C
OUT1, OUT2
OVP, FB_
Output Voltage Adjust Range
Dual-Mode Threshold, Low
1
5.5
V
V
0.05
0.1
2.0
0.15
V
-
V
-
CC
CC
OVP, ILIM_
FB1
1.5
0.4
Dual-Mode Threshold, High
V
1.9
75
2.1
R
R
V
V
= 1.5V
= 2.5V
OUT1
OUT1
OUT2
OUT_ Input Resistance
kΩ
100
OUT2
FB_ Input Bias Current
Soft-Start Ramp Time
I
-0.1
0.1
µA
µs
FB
Zero to full ILIM
1700
2
_______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
noted.)
= V = 5V, SKIP = AGND, V+ = 15V, T = 0°C to +85°C, typical values are at +25°C, unless otherwise
CC A
DD
PARAMETER
SYMBOL
CONDITIONS
TON = AGND
TON = REF
MIN
120
153
222
316
160
205
301
432
125
125
125
125
TYP
137
174
247
353
182
234
336
483
135
135
135
135
400
1100
<1
MAX
153
195
272
390
204
263
371
534
145
145
145
145
500
1500
5
UNITS
V+ = 24V,
= 2V
On-Time, Side 1 (Note 3)
t
t
ns
ON1
ON2
V
OUT1
TON = float
TON = V
CC
TON = AGND
TON = REF
TON = float
V+ = 24V,
= 2V
On-Time, Side 2 (Note 3)
ns
%
V
OUT2
TON = V
CC
TON = AGND
TON = REF
TON = float
On-time 2 with
respect to on-
time 1
On-Time Tracking (Note 3)
Minimum Off-Time (Note 3)
TON = V
CC
t
ns
µA
µA
µA
OFF
Quiescent Supply Current (V
Quiescent Supply Current (V
)
)
I
FB_ forced above the regulation point
FB_ forced above the regulation point
Measured at V+
CC
CC
I
DD
DD
Quiescent Supply Current (V+)
I+
25
70
ON1 = ON2 = AGND, OVP = V
or AGND
<1
5
CC
Shutdown Supply Current (V
)
µA
µA
µA
CC
ON1 = ON2 = AGND, V
ON1 = ON2 = AGND
= 1.8V
1
5
OVP
Shutdown Supply Current (V
)
<1
5
DD
ON1 = ON2 = AGND, measured at V+,
Shutdown Supply Current (V+)
<1
2
5
V
= AGND or 5V
CC
Reference Voltage
V
V
= 4.5V to 5.5V, no external REF load
= 0 to 50µA
1.98
10
2.02
0.01
V
V
REF
CC
Reference Load Regulation
REF Sink Current
I
REF
REF in regulation
µA
V
REF Fault Lockout Voltage
Falling edge, hysteresis = 40mV
1.6
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
OVP = AGND, with respect to error-
comparator trip threshold
112
-28
114
117
28
%
1V < V
< 1.8V, external feedback,
OVP
0
0
mV
measured at FB_ with respect to V
OVP
Overvoltage Comparator Offset
(Adjustable-Threshold Mode)
1V < V
< 1.8V, internal feedback,
OVP
measured at OUT_ with respect to OUT_
regulation point
-3.5
+3.5
100
%
OVP Input Leakage Current
1V < V
< 1.8V
-100
<1
nA
µs
OVP
Overvoltage Fault Propagation
Delay
FB_ forced 2% above trip threshold
1.5
UVP = V , with respect to error-comparator
CC
trip threshold
Output Undervoltage Threshold
65
10
70
75
30
%
Output Undervoltage Protection
Blanking Time
From ON_ signal going high
ms
_______________________________________________________________________________________
3
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
noted.)
= V = 5V, SKIP = AGND, V+ = 15V, T = 0°C to +85°C, typical values are at +25°C, unless otherwise
CC A
DD
PARAMETER
SYMBOL
CONDITIONS
AGND - V _, ILIM_ = V
MIN
40
TYP
50
MAX
60
UNITS
Current-Limit Threshold (Fixed)
mV
CS
CC
AGND - V _, ILIM_ = 0.5V
40
50
60
CS
Current-Limit Threshold
(Adjustable)
mV
V
AGND - V _, ILIM_ = 1V
85
100
115
2.5
CS
ILIM_ Adjustment Range
V
_
0.3
ILIM
Negative Current-Limit Threshold
(Fixed)
V
_ - AGND, ILIM_ = V , T = +25 oC
-75
-60
-45
mV
oC
V
CS
CC
A
Thermal Shutdown Threshold
Hysteresis = 15oC
160
V
Undervoltage Lockout
Rising edge, hysteresis = 20mV, PWMs
disabled below this level
CC
4.05
4.4
Threshold
MAX1845EEI
BST - LX forced to 5V
1.5
1.5
1.5
1.5
0.5
0.5
5
6
Ω
Ω
Ω
Ω
Ω
Ω
DH Gate-Driver On-Resistance
(Note 4)
MAX1845ETX
MAX1845EEI
DL, high state
5
DL Gate-Driver On-Resistance
(Note 4)
MAX1845ETX
6
MAX1845EEI
DL, low state
1.7
2.7
DL Gate-Driver On-Resistance
(Note 4)
MAX1845ETX
DH_ Gate Driver Source/Sink
Current
V
_ = 2.5V, V
_ = V _ = 5V
1
A
DH
BST
LX
DL_ Gate Driver Sink Current
DL_ Gate Driver Source Current
V
V
_ = 2.5V
_ = 2.5V
3
1
A
A
DL
DL
ON_, SKIP
2.4
Logic Input High Voltage
Logic Input Low Voltage
V
V
V
IH
V
0.4
-
CC
UVP
ON_, SKIP
0.8
V
IL
UVP
0.05
V
0.4
-
CC
V
level
CC
TON Input Logic level
Float level
REF level
3.15
1.65
3.85
2.35
0.5
3
V
AGND level
Logic Input Current
Logic Input Current
TON (AGND or V
)
CC
-3
-1
µA
µA
ON_, SKIP, UVP
1
With respect to error-comparator trip
threshold, falling edge
PGOOD Trip Threshold (Lower)
PGOOD Trip Threshold (Upper)
PGOOD Propagation Delay
-12.5
+7.5
-10
+10
1.5
-7.5
%
%
µs
With respect to error-comparator trip
threshold, rising edge
+12.5
Falling edge, FB_ forced 2% below PGOOD
trip threshold
PGOOD Output Low Voltage
PGOOD Leakage Current
I
= 1mA
0.4
1
V
SINK
High state, forced to 5.5V
µA
4
_______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V
= V = 5V, SKIP = AGND, V+ = 15V, T = -40°C to +85°C, unless otherwise noted.) (Note 5)
CC A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLERS
V+
Battery voltage, V+
, V
2
28
Input Voltage Range
V
V
V
V
/V
CC DD
V
4.5
5.5
CC DD
FB1 to AGND
FB1 to V
1.773
1.477
0.985
2.463
0.985
1
1.827
1.523
1.015
2.537
1.015
5.5
V+ = 2V to 28V, SKIP = V
,
,
CC
DC Output Voltage, OUT1 (Note 2)
DC Output Voltage, OUT2 (Note 2)
V
V
OUT1
OUT2
CC
I
= 0 to 10A
LOAD
FB1 to OUT1
FB2 to AGND
FB2 to OUT2
V+ = 2V to 28V, SKIP = V
= 0 to 10A
CC
I
LOAD
Output Voltage Adjust Range
Dual-Mode Threshold (Low)
OUT1, OUT2
OVP, FB_
V
V
0.05
0.15
V
-
V
0.4
-
CC
CC
OVP, ILIM_
1.5
1.9
75
Dual-Mode Threshold (High)
V
FB_
2.1
R
R
V
V
= 1.5V
= 2.5V
OUT1
OUT2
OUT1
OUT2
OUT_ Input Resistance
FB_ Input Bias Current
kΩ
100
I
-0.1
120
153
217
308
160
205
295
422
125
125
125
125
0.1
153
195
272
390
204
263
371
534
145
145
145
145
500
µA
FB
TON = AGND
TON = REF
TON = float
On-Time, Side 1 (Note 3)
On-Time, Side 2 (Note 3)
t
t
V+ = 24V, V
V+ = 24V, V
= 2V
= 2V
ns
ns
%
ON1
ON2
OUT1
OUT2
TON = V
CC
TON = AGND
TON = REF
TON = float
TON = V
CC
TON = AGND
TON = REF
TON = float
On-time 2, with
respect to on-time 1
On-Time Tracking (Note 3)
Minimum Off-Time (Note 3)
TON = V
CC
t
ns
µA
µA
µA
V
OFF
Quiescent Supply Current (V
Quiescent Supply Current (V
)
)
I
FB forced above the regulation point
FB forced above the regulation point
Measured at V+
1500
5
CC
CC
DD
I+
I
DD
Quiescent Supply Current (V+)
Reference Voltage
70
V
V
= 4.5V to 5.5V, no external REF load
= 0 to 50uA
1.98
112
2.02
0.01
REF
CC
Reference Load Regulation
I
V
REF
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
OVP = GND, with respect to FB_ regulation
point, no load
117
%
UVP = V , with respect to FB_ regulation
CC
point, no load
Output Undervoltage Threshold
Current-Limit Threshold (Fixed)
65
35
75
65
%
AGND - V _, ILIM_ = V
mV
CS
CC
_______________________________________________________________________________________
5
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
= V = 5V, SKIP = AGND, V+ = 15V, T = -40°C to +85°C, unless otherwise noted.) (Note 5)
CC A
DD
PARAMETER
SYMBOL
CONDITIONS
AGND - V _, ILIM_ = 0.5V
MIN
35
TYP
MAX
65
UNITS
CS
Current-Limit Threshold
(Adjustable)
mV
AGND - V _, ILIM_ = 1V
CS
80
120
V
Undervoltage Lockout
Rising edge, hysteresis = 20mV, PWMs
disabled below this level
CC
4.05
2.4
4.4
V
V
Threshold
ON_, SKIP
Logic Input High Voltage
V
IH
V
-
CC
UVP
0.4
ON_, SKIP
0.8
0.05
3
Logic Input Low Voltage
Logic Input Current
V
V
IL
UVP
TON (AGND or V
)
CC
-3
-1
µA
ON_, SKIP, UVP
1
Note 2: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error compara-
tor threshold by 50% of the output voltage ripple. In discontinuous conduction (SKIP = AGND, light load), the output voltage will
have a DC regulation higher than the error-comparator threshold by approximately 1.5% due to slope compensation.
Note 3: On-time and off-time specifications are measured from 50% point to 50% point at DH_ with LX_ = GND, BST_ = 5V, and a
250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the QFN
package. The MAX1845EEI and MAX1845ETX contain the same die, and the QFN package imposes no additional resis-
tance in-circuit.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, components from Table 1, V = 15V, SKIP = GND, TON = unconnected, T = +25°C, unless otherwise noted.)
A
IN
FREQUENCY vs. INPUT VOLTAGE
(TON = FLOAT, SKIP = V
)
CC
FREQUENCY vs. LOAD CURRENT
400
400
350
300
250
200
150
100
50
OUT1
350
300
250
200
OUT1, SKIP = V
CC
CC
OUT2, SKIP = V
OUT2
OUT1, SKIP = GND
150
100
I
I
= 8A
= 4A
OUT1
OUT2
OUT2, SKIP = GND
1
50
0
0
4
8
12
16
20
21
0.01
0.1
10
INPUT VOLTAGE (V)
LOAD CURRENT (A)
6
_______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, V = 15V, SKIP = GND, TON = unconnected, T = +25°C, unless otherwise noted.)
A
IN
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP = GND)
EFFICIENCY vs. LOAD CURRENT
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP = V
(8A COMPONENTS, SKIP = V )
)
CC
CC
100
15.0
13.5
12.0
10.5
9.0
7.5
6.0
4.5
3.0
1.5
0
1100
1000
900
800
700
600
500
400
300
200
100
0
V
= V = 5V
DD
CC
90
80
V+ = 7V
I
DD
V+ = 20V
I
CC
70
60
V
= V = 5V
DD
CC
V+ = 12V
50
40
30
20
10
I
I+ (25µA TYP)
CC
I
(600nA typ)
DD
I+
OUT1 = 1.8V
5
10
15
20
25
30
0.01
0.1
1
10
5
10
15
20
25
30
SUPPLY VOLTAGE V+ (V)
LOAD CURRENT (A)
SUPPLY VOLTAGE V+ (V)
EFFICIENCY vs. LOAD CURRENT
(4A COMPONENTS, SKIP = GND)
EFFICIENCY vs. LOAD CURRENT
(8A COMPONENTS, SKIP = GND)
EFFICIENCY vs. LOAD CURRENT
(4A COMPONENTS, SKIP = V
)
CC
100
100
100
95
90
85
80
75
70
65
60
55
90
80
V+ = 7V
V+ = 7V
95
90
85
80
75
V+ = 20V
V+ = 7V
70
60
V+ = 20V
V+ = 12V
V+ = 20V
50
40
30
20
10
V+ = 12V
V+ = 12V
OUT2 = 2.5V
OUT1 = 1.8V
OUT2 = 2.5V
50
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
NORMALIZED OVERVOLTAGE PROTECTION
THRESHOLD vs. OVP VOLTAGE
CURRENT-LIMIT TRIP POINT
vs. ILIM VOLTAGE
LOAD-TRANSIENT RESPONSE
(4A COMPONENTS, PWM MODE, V
= 2.5V)
OUT2
MAX1845 toc07a
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
250
230
210
190
170
150
130
110
90
V
OUT2
100mV/div
I
OUT2
70
2A/div
50
30
10
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
OVP VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
20µs/div
ILIM VOLTAGE (V)
_______________________________________________________________________________________
7
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, V = 15V, SKIP = GND, TON = unconnected, T = +25°C, unless otherwise noted.)
A
IN
SHUTDOWN WAVEFORM
STARTUP WAVEFORM
LOAD-TRANSIENT RESPONSE
(4A COMPONENTS, SKIP = GND, V
= 2.5V)
(4A COMPONENTS, SKIP = GND, V
= 2.5V)
(8A COMPONENTS, PWM MODE, V
= 1.8V)
OUT2
OUT2
OUT1
MAX1845 toc09
MAX1845 toc09
MAX1845 toc07b
V
OUT2
1V/div
V
OUT2
1V/div
V
OUT1
100mV/div
I
I
OUT2
5A/div
OUT2
2A/div
I
OUT1
5A/div
100µs/div
400µs/div
20µs/div
Pin Description
PIN
NAME
FUNCTION
QSOP
QFN
Output Voltage Connection for the OUT1 PWM. Connect directly to the junction of the external
inductor and output filter capacitors. OUT1 senses the output voltage to determine the on-time
and also serves as the feedback input in fixed-output modes.
1
32
OUT1
FB1
Feedback Input for OUT1. Connect to GND for 1.8V fixed output or to V for 1.5V fixed output, or
CC
connect to a resistor-divider network from OUT1 for an adjustable output between 1V and 5.5V.
2
3
4
33
34
35
Current-Limit Threshold Adjustment for OUT1. The current-limit threshold at CS1 is 0.1 times the
voltage at ILIM1. Connect a resistor-divider network from REF to set the current-limit threshold
ILIM1
V+
between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to V
current-limit threshold.
to assert 50mV default
CC
Battery Voltage-Sense Connection. Connect to input power source. V+ is only used to adjust the
DH_ on-time for pseudofixed-frequency operation.
On-Time Selection Control Input. This four-level input pin sets the DH_ on-time to determine the
operating frequency.
TON
AGND
REF
FREQUENCY (OUT1) (kHz)
FREQUENCY (OUT2) (kHz)
620
485
345
235
460
355
255
170
5
1
TON
Open
V
CC
Pulse-Skipping Control Input. Connect to V
to enable pulse-skipping operation.
for low-noise forced-PWM mode. Connect to AGND
CC
6
2
SKIP
8
_______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Pin Description (continued)
PIN
NAME
FUNCTION
QSOP
QFN
Power-Good Open-Drain Output. PGOOD is low when either output voltage is off or is more than
10% above or below the normal regulation point.
7
3
PGOOD
OVP
Overvoltage Protection Threshold. An overvoltage fault occurs if the voltage on FB1 or FB2 is
greater than the programmed overvoltage trip threshold. Adjustment range is 1V (100%) to 1.8V
(180%). Connect OVP to GND to set the default overvoltage threshold of 114% of nominal.
8
4
Connect to V to disable OVP and clear the OVP latch.
CC
Undervoltage Protection Threshold. An undervoltage fault occurs if the voltage on FB1 or FB2 is less
9
5
7
UVP
REF
than the undervoltage trip threshold (70% of nominal). Connect UVP to V to enable undervoltage
CC
protection. Connect to GND to disable undervoltage protection and clear the UVP latch.
+2.0V Reference Voltage Output. Bypass to GND with 0.22µF (min) capacitor. Can supply 50µA
for external loads.
10
11
12
8
ON1
ON2
OUT1 ON/OFF Control Input. Connect to AGND to turn OUT1 off. Connect to V to turn OUT1 on.
CC
11
OUT2 ON/OFF Control Input. Connect to AGND to turn OUT2 off. Connect to V to turn OUT2 on.
CC
Current-Limit Threshold Adjustment for OUT2. The current-limit threshold at CS2 is 0.1 times the
voltage at ILIM2. Connect a resistor-divider network from REF to set the current-limit threshold
13
12
ILIM2
between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to V
current-limit threshold.
to assert 50mV default
CC
Feedback Input for OUT2. Connect to GND for 2.5V fixed output, or connect to a resistor-divider
network from OUT2 for an adjustable output between 1V and 5.5V.
14
15
13
14
FB2
Output Voltage Connection for the OUT2 PWM. Connect directly to the junction of the external
inductor and output filter capacitors. OUT2 senses the output voltage to determine the on-time
and also serves as the feedback input in fixed-output modes.
OUT2
Current-Sense Input for OUT2. CS2 is the input to the current-limiting circuitry for valley current
limiting. For lowest cost and highest efficiency, connect to LX2. For highest accuracy, use a sense
resistor. See the Current-Limit Circuit (ILIM_) section.
16
15
CS2
External Inductor Connection for OUT2. Connect to the switched side of the inductor. LX2 serves
as the internal lower supply voltage rail for the DH2 high-side gate driver.
17
18
16
18
LX2
DH2
High-Side Gate Driver Output for OUT2. Swings from LX2 to BST2.
Boost Flying Capacitor Connection for OUT2. Connect to an external capacitor and diode
according to the standard application circuit in Figure 1. See MOSFET Gate Drivers (DH_, DL_)
section.
19
19
BST2
DL2
20
21
20
21
Low-Side Gate-Driver Output for OUT2. DL2 swings from PGND to V
.
DD
Supply Input for the DL Gate Drivers. Connect to system supply voltage, +4.5V to +5.5V. Bypass
to PGND with a low-ESR 4.7µF capacitor.
V
V
DD
CC
Analog Supply Input. Connect to system supply voltage, +4.5V to +5.5V, with a 20Ω series
resistor. Bypass to AGND with a 1µF capacitor.
22
23
22
—
GND
Ground. Combined analog and power ground. Serves as negative input for CS_ amplifiers.
_______________________________________________________________________________________
9
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Pin Description (continued)
PIN
NAME
FUNCTION
QSOP
—
QFN
23
AGND
PGND
DL1
Analog Ground. Serves as negative input for CS_ amplifiers. Connect backside pad to AGND.
Power Ground
—
24
24
26
Low-Side Gate-Driver Output for OUT1. DL1 swings from PGND to V
.
DD
Boost Flying Capacitor Connection for OUT1. Connect to an external capacitor and diode according
to the standard application circuit in Figure 1. See the MOSFET Gate Drivers (DH_, DL_)
section.
25
27
BST1
26
27
28
30
DH1
LX1
High-Side Gate Driver Output for OUT1. Swings from LX1 to BST1.
External Inductor Connection for OUT1. Connect to the switched side of the inductor. LX1 serves
as the internal lower supply voltage rail for the DH1 high-side gate driver.
Current-Sense Input for OUT1. CS1 is the input to the current-limiting circuitry for valley current
limiting. For lowest cost and highest efficiency, connect to LX1. For highest accuracy, use a sense
resistor. See the Current-Limit Circuit (ILIM_) section.
28
31
CS1
N.C.
6, 9, 10,
17, 25,
29, 36
—
No Connection
efficiency and eliminates the cost associated with the
Standard Application Circuit
The standard application circuit (Figure 1) generates a
1.8V and a 2.5V rail for general-purpose use in note-
book computers.
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator such as the MAX1615.
See Table 1 for component selections. Table 2 lists
component manufacturers.
The power input and 5V bias inputs can be connected
together if the input source is a fixed 4.5V to 5.5V sup-
ply. If the 5V bias supply is powered up prior to the bat-
tery supply, the enable signal (ON1, ON2) must be
delayed until the battery voltage is present to ensure
Detailed Description
The MAX1845 buck controller is designed for low-volt-
age power supplies for notebook computers. Maxim’s
proprietary Quick-PWM pulse-width modulator in the
MAX1845 (Figure 2) is specifically designed for han-
dling fast load steps while maintaining a relatively con-
stant operating frequency and inductor operating point
over a wide range of input voltages. The Quick-PWM
architecture circumvents the poor load-transient timing
problems of fixed-frequency current-mode PWMs while
avoiding the problems caused by widely varying
switching frequencies in conventional constant-on-time
and constant-off-time PWM schemes.
startup. The 5V bias supply must provide V
and
CC
gate-drive power, so the maximum current drawn is:
I
= I + f (Q + Q ) = 5mA to 30mA (typ)
BIAS
CC
G1
G2
where I
is 1mA typical, f is the switching frequency,
CC
and Q
and Q
are the MOSFET data sheet total
G2
G1
gate-charge specification limits at V = 5V.
GS
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time current-mode type with
voltage feed-forward (Figure 3). This architecture relies
on the output filter capacitor’s effective series resis-
tance (ESR) to act as a current-sense resistor, so the
output ripple voltage provides the PWM ramp signal.
The control algorithm is simple: the high-side switch on-
5V Bias Supply (V
CC
and V )
DD
The MAX1845 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
10 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
time is determined solely by a one-shot whose pulse
remains relatively constant, resulting in easy design
methodology and predictable output voltage ripple.
The on-times for side 1 are set 35% higher than the on-
times for side 2. This is done to prevent audio-frequen-
cy “beating” between the two sides, which switch
asynchronously for each side. The on-time is given by:
width is inversely proportional to input voltage and
directly proportional to output voltage. Another one-shot
sets a minimum off-time (400ns typ). The on-time one-
shot is triggered if the error comparator is low, the low-
side switch current is below the current-limit threshold,
and the minimum off-time one-shot has timed out
(Table 3).
On-Time = K (V
+ 0.075V) / V
IN
OUT
where K is set by the TON pin-strap connection (Table
4), and 0.075V is an approximation to accommodate
for the expected drop across the low-side MOSFET
switch. One-shot timing error increases for the shorter
on-time settings due to fixed propagation delays; it is
approximately 12.5% at higher frequencies and 10%
at lower frequencies. This translates to reduced switch-
ing-frequency accuracy at higher frequencies (Table
4). Switching frequency increases as a function of load
current due to the increasing drop across the low-side
MOSFET, which causes a faster inductor-current dis-
charge ramp. The on-times guaranteed in the Electrical
Characteristics tables are influenced by switching
delays in the external high-side power MOSFET.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time for both controllers. This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltage. The high-side switch on-time is inversely pro-
portional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algo-
rithm results in a nearly constant switching frequency
despite the lack of a fixed-frequency clock generator.
The benefits of a constant switching frequency are
twofold: First, the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band;
second, the inductor ripple-current operating point
V
= 5V
DD
BIAS SUPPLY
D3
C8
1µF
C9
4.7µF
CMPSH-3A
V
IN
7V TO 24V
4
R1
20Ω
21
9
22
V+
V
UVP
DD
11
V
ON1
CC
ON/OFF
C11
3
12
8
CONTROLS
ILIM1
ILIM2
1µF
ON2
OVP
13
C2
✕
2
10µF
MAX1845EEI
C1
25
26
19
18
BST1
DH1
BST2
✕
3
10µF
L2
Q1
Q2
L1
2.2µH
Q3
Q4
DH2
OUTPUT1
1.8V, 8A
OUTPUT2
2.5V, 4A
4.7µH
C5
0.1µF
C6
0.1µF
27
24
17
20
LX1
LX2
DL2
C4
470µF
C3
470µF
D1
D2
✕
3
DL1
TON
5
28
1
16
CS2
CS1
OUT1
15
6
OUT2
SKIP
5V
10
R2
10mΩ
REF
FB1
GND
C7
0.22µF
R1
5mΩ
14
7
2
100kΩ
FB2
23
POWER-GOOD
INDICATOR
PGOOD
Figure 1. Standard Application Circuit
______________________________________________________________________________________ 11
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Table 1. Component Selection for
Standard Applications
Table 2. Component Suppliers
FACTORY FAX
[Country Code]
MANUFACTURER
USA PHONE
SIDE 1: 1.8V AT 8A/
SIDE 2: 2.5V AT 4A
COMPONENT
Input Range
Central Semiconductor
Dale/Vishay
516-435-1110 [1] 516-435-1824
203-452-5664 [1] 203-452-5670
4.5V to 28V
Fairchild Semiconductor 408-822-2181 [1] 408-721-1635
Fairchild Semiconductor
FDS6612A or
International Rectifier
IRF7807
International Rectifier
IRC
Kemet
NIEC (Nihon)
Sanyo
310-322-3331 [1] 310-322-3332
800-752-8708 [1] 828-264-7204
408-986-0424 [1] 408-986-1442
805-867-2555* [81] 3-3494-7414
619-661-6835 [81] 7-2070-1174
Q1 High-Side MOSFET
Q2 Low-Side MOSFET
Fairchild Semiconductor
FDS6670A or
International Rectifier
IRF7805
408-988-8000
[1] 408-970-3950
800-554-5565
Siliconix
Sumida
Taiyo Yuden
TDK
847-956-0666 [81] 3-3607-5144
408-573-4150 [1] 408-573-4159
847-390-4461 [1] 847-390-4405
Q3, Q4 High/Low-Side
MOSFETs
Fairchild Semiconductor
FDS6982A
*Distributor
D1, D2 Rectifier
Nihon EP10QY03
Central Semiconductor
CMPSH-3A
D3 Rectifier
both dead times. It occurs only in PWM mode (SKIP =
high) when the inductor current reverses at light or neg-
ative load currents. With reversed inductor current, the
inductor’s EMF causes LX to go high earlier than nor-
mal, extending the on-time by a period equal to the
low-to-high dead time.
2.2µH
Panasonic ETQP6F2R2SFA
or
Sumida CDRH127-2R4
L1 Inductor
L2 Inductor
For loads above the critical conduction point, the actual
switching frequency is:
4.7µH
Sumida CDRH124-4R7MC
V
+ V
DROP1
OUT
10µF, 25V
Taiyo Yuden
f =
t
(V + V
)
C1 (3), C2 (2) Input
Capacitor
ON IN
DROP2
TMK432BJ106KM or
TDK C4532X5R1E106M
where V
1 is the sum of the parasitic voltage drops
DROP
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V is
470µF, 6V
Kemet T510X477M006AS or
Sanyo 6TPB330M
DROP2
the sum of the resistances in the charging path; and
C3 (3), C4 Output Capacitor
t
is the on-time calculated by the MAX1845.
ON
Automatic Pulse-Skipping Switchover
5mΩ, 1%, 1W
In skip mode (SKIP = GND), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is effected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
tinuous and discontinuous inductor-current operation
(also known as the critical conduction point). For a 7V
to 24V battery range, of this threshold is relatively con-
stant, with only a minor dependence on battery voltage:
R
R
IRC LR2512-01-R005-F or
SENSE1
SENSE2
D
WSL-2512-R005F
ALE
10mΩ, 1%, 0.5W
IRC LR2010-01-R010-F or
D
WSL-2010-R010F
ALE
Two external factors that influence switching-frequency
accuracy are resistive drops in the two conduction
loops (including inductor and PC board resistance) and
the dead-time effect. These effects are the largest con-
tributors to the change of frequency with changing load
current. The dead-time effect increases the effective
on-time, reducing the switching frequency as one or
K × V
V -V
IN OUT_
OUT_
I
≈
LOAD(SKIP)
2L
V
IN
12 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
V+
2V TO 28V
I
I
LIM2
LIM1
V+
V
DD
5V INPUT
V
DD
PGND*
V
- 1V
V
- 1V
CC
CC
V
DD
V
DD
0.5V
0.5V
V+
V+
BST1
BST2
MAX1845
DH1
LX1
DH2
LX2
PWM
CONTROLLER
(FIGURE 3)
PWM
CONTROLLER
(FIGURE 3)
CS2
DL2
CS1
V
V
DD
DD
DL1
OUT 2
FB2
OUT1
FB1
V
DD
V
CC
UVP
OVP
TON
SKIP
PGOOD
20Ω
2V REF
REF
AGND*
FAULT1
FAULT2
ON1
ON2
* IN THE MAX1845EEI, AGND AND PGND ARE INTERNALLY CONNECTED AND CALLED GND.
Figure 2. Functional Diagram
where K is the on-time scale factor (Table 4). The load-
current level at which PFM/PWM crossover occurs,
LOAD(SKIP)
rent, which is a function of the inductor value (Figure
4). For example, in the standard application circuit with
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
I
, is equal to 1/2 the peak-to-peak ripple cur-
V
= 2.5V, V = 15V, and K = 2.96µs (Table 4),
OUT1
IN
switchover to pulse-skipping operation occurs at I
LOAD
= 0.7A or about 1/6 full load. The crossover point
occurs at an even lower value if a swinging (soft-satu-
ration) inductor is used.
______________________________________________________________________________________ 13
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
V+
TOFF 1-SHOT
TON
FROM
OUT
ON-TIME
COMPUTE
TRIG
Q
TO DH DRIVER
TO DL DRIVER
SHUTDOWN
TON
S
R
Q
Q
TRIG
1-SHOT
ERROR
AMP
FROM ILIM
COMPARATOR
S
R
REF
Q
FROM
OPPOSITE
PWM
FROM ZERO-CROSSING
COMPARATOR
OVP
1.14V
0.1V
OUT_
FB_
TO
OPPOSITE
PWM
FEEDBACK
MUX
(SEE FIGURE 9)
S
R
Q
x2
V
- 1V
CC
0.7V
1.1V
0.9V
S
R
TIMER
Q
FAULT
UVP
TO PGOOD
OR-GATE
Figure 3. PWM Controller (One Side Only)
include larger physical size and degraded load-tran-
sient response (especially at low input voltage levels).
low-side switch on-time. This causes the low-side gate-
drive waveform to become the complement of the high-
side gate-drive waveform. This in turn causes the
inductor current to reverse at light loads as the PWM
DC output accuracy specifications refer to the threshold
of the error comparator. When the inductor is in continu-
ous conduction, the output voltage will have a DC regula-
tion higher than the trip level by 50% of the ripple. In
discontinuous conduction (SKIP = GND, light-load), the
output voltage will have a DC regulation higher than the
trip level by approximately 1.5% due to slope compensa-
tion.
loop strives to maintain a duty ratio of V
/V . The
OUT IN
benefit of forced-PWM mode is to keep the switching
frequency fairly constant, but it comes at a cost: The
no-load battery current can be 10mA to 40mA, depend-
ing on the external MOSFETs.
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response,
providing sink-current capability for dynamic output
voltage adjustment, and improving the cross-regulation
Forced-PWM Mode (SKIP = High)
The low-noise, forced-PWM mode (SKIP = high) dis-
ables the zero-crossing comparator, which controls the
14 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Table 3. Operating Mode Truth Table
ON1
ON2
SKIP
DL1/DL2
MODE
COMMENTS
Low-power shutdown state. If overvoltage protection is
GND
GND
X
High*/High*
Shutdown
enabled, DL1 and DL2 are forced to V , ensuring
DD
overvoltage protection, I
< 1µA (typ).
CC
Run (PWM), Low Noise,
Side 1 Only
V
GND
V
V
V
Switching/High*
High*/Switching
CC
CC
CC
CC
Run (PWM), Low Noise,
Side 2 Only
Low-noise, fixed frequency PWM at all load conditions.
Low noise, high I .
Q
GND
V
V
CC
CC
Switching/
Switching
Run (PWM), Low Noise,
Both Sides Active
V
V
CC
CC
Run (PWM/PFM), Skip
Mode, Side 1 Only
GND
GND
GND
GND
Switching/High*
High*/Switching
Normal operation with automatic PWM/PFM switchover
for pulse skipping at light loads. Best light-load
efficiency.
Run (PWM/PFM), Skip
Mode, Side 2 Only
GND
V
V
CC
CC
Switching/
Switching
Run (PWM/PFM), Skip
Mode, Both Sides Active
V
V
CC
CC
Fault latch has been set by overvoltage protection circuit,
undervoltage protection circuit, or thermal shutdown.
V
X
High*/High*
Fault
CC
Device will remain in fault mode until V
cycled or ON1/ON2 is toggled.
power is
CC
*DL_ high only if overvoltage protection enabled (see Output Overvoltage Protection section).
of multiple-output applications that use a flyback trans-
former or coupled inductor.
nected to V . The logic threshold for switchover to the
CC
50mV default value is approximately V
- 1V.
CC
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signal seen by CS_ and GND. Mount or
place the IC close to the low-side MOSFET and sense
resistor with short, direct traces, making a Kelvin sense
connection to the sense resistor. In Figure 1, the
Schottky diodes (D1 and D2) provide current paths
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a unique “valley” current-
sensing algorithm. If the magnitude of the current-sense
signal at CS_ is above the current-limit threshold, the
PWM is not allowed to initiate a new cycle (Figure 5). The
actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple cur-
rent. Therefore, the exact current-limit characteristic and
maximum load capability are a function of the sense
resistance, inductor value, and battery voltage.
parallel to the Q2/R
and Q4/R
current
SENSE
SENSE
paths, respectively. Accurate current sensing requires
D1/D2 to be off while Q2/Q4 conducts. Avoid large cur-
rent-sense voltages that, combined with the voltage
across Q2/Q4, would allow D1/D2 to conduct. If very
large sense voltages are used, connect D1/D2 in paral-
lel with Q2/Q4 only.
There is also a negative current limit that prevents exces-
sive reverse inductor currents when V
is sinking cur-
OUT
rent. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
therefore tracks the positive current limit when ILIM is
adjusted.
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving mod-
erate-size, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
The current-limit threshold is adjusted with an internal
5µA current source and an external resistor at ILIM. The
current-limit threshold adjustment range is from 25mV
to 250mV. In the adjustable mode, the current-limit
threshold voltage is precisely 1/10 the voltage seen at
ILIM. The threshold defaults to 50mV when ILIM is con-
V
BATT
- V
differential exists. An adaptive dead-time
OUT
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
______________________________________________________________________________________ 15
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
I
PEAK
∆i
∆t
V
-V
BATT OUT
=
L
I
PEAK
I
I
LOAD
LIMIT
I
= I
/2
LOAD PEAK
0
ON-TIME
TIME
0
TIME
Figure 5. ‘‘Valley’’ Current-Limit Threshold Point
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time
circuit to work properly. Otherwise, the sense circuitry
in the MAX1845 will interpret the MOSFET gate as “off”
while there is actually still charge left on the gate. Use
very short, wide traces measuring 10 to 20 squares (50
to 100 mils wide if the MOSFET is 1 inch from the
MAX1845).
A continuously adjustable analog soft-start function can
be realized by adding a capacitor in parallel with the
ILIM external resistor-divider network. This soft-start
method requires a minimum interval between power-
down and power-up to discharge the capacitor.
Power-Good Output (PGOOD)
The PGOOD window comparator continuously monitors
the output voltage for both overvoltage and undervolt-
age conditions. In shutdown, standby, and soft-start,
PGOOD is actively held low. After a digital soft-start
has terminated, PGOOD is released when the output is
within 10% of the error-comparator threshold. The
PGOOD output is a true open-drain type with no para-
sitic ESD diodes. Note that the PGOOD window detec-
tor is independent of the output overvoltage and
undervoltage protection (UVP) thresholds.
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typ) internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.5Ω typical on-resistance. This helps
prevent DL from being pulled up during the fast rise-
time of the inductor node, due to capacitive coupling
from the drain to the gate of the low-side synchronous-
rectifier MOSFET. However, for high-current applica-
tions, some combinations of high- and low-side FETs
might be encountered that will cause excessive gate-
drain coupling, which can lead to efficiency-killing,
EMI-producing shoot-through currents. This is often
remedied by adding a resistor in series with BST, which
increases the turn-on time of the high-side FET without
degrading the turn-off time (Figure 6).
Output Overvoltage Protection
The output voltage can be continuously monitored for
overvoltage. When overvoltage protection is enabled, if
the output exceeds the overvoltage threshold, overvolt-
age protection is triggered and the DL low-side gate-
drivers are forced high. This activates the low-side
MOSFET switch, which rapidly discharges the output
capacitor and reduces the input voltage.
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when V
rises above
CC
Note that DL latching high causes the output voltage to
dip slightly negative when energy has been previously
stored in the LC tank circuit. For loads that cannot toler-
ate a negative voltage, place a power Schottky diode
across the output to act as a reverse polarity clamp.
approximately 2V, resetting the fault latch and soft-start
counter and preparing the PWM for operation. V
CC
undervoltage lockout (UVLO) circuitry inhibits switch-
ing. DL is low if the overvoltage protection (OVP) is dis-
abled. DL is high if the overvoltage protection is
enabled (see the Output Overvoltage Protection sec-
Connect OVP to GND to enable the default trip level of
114% of the nominal output. To adjust the overvoltage
protection trip level, apply a voltage from 1V (100%) to
1.8V (180%) at OVP. Disable the overvoltage protection
tion) when V
rises above 4.2V, whereupon an inter-
CC
nal digital soft-start timer begins to ramp up the
maximum allowed current limit. The ramp occurs in five
steps: 20%, 40%, 60%, 80%, and 100%; 100% current
is available after 1.7ms 50%.
by connecting OVP to V
.
CC
16 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
1) Input Voltage Range. The maximum value
+5V
(V
) must accommodate the worst-case high
V
IN(MAX)
IN
AC adapter voltage. The minimum value (V
)
IN(MIN)
5Ω
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selector
switches. Lower input voltages result in better effi-
ciency.
BST
DH
LX
2) Maximum Load Current. There are two values to
consider. The peak load current (I
) deter-
LOAD(MAX)
mines the instantaneous component stresses and
filtering requirements, and thus drives output capac-
itor selection, inductor saturation rating, and the
design of the current-limit circuit. The continuous
MAX1845
Figure 6. Reducing the Switching-Node Rise Time
load current (I
) determines the thermal stress-
LOAD
es and thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents.
The overvoltage trip level depends on the internal or
external output voltage feedback divider and is restrict-
ed by the output voltage adjustment range (1V to 5.5V)
and by the absolute maximum rating of OUT_. Setting
the overvoltage threshold higher than the output volt-
age adjustment range is not recommended.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
2
.
are proportional to frequency and V
IN
Output Undervoltage Protection
The output voltage can be continuously monitored for
undervoltage. When undervoltage protection is
4) Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output
noise. The minimum practical inductor value is one
that causes the circuit to operate at the edge of criti-
cal conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit.
enabled (UVP = V ), if the output is less than 70% of
CC
the error-amplifier trip voltage, undervoltage protection
is triggered. If an overvoltage protection threshold is
set, the DL low-side gate driver is forced high. This
activates the low-side MOSFET switch, which rapidly
discharges the output capacitor, reduces the input
voltage, and grounds the outputs. If the overvoltage
protection is disabled (OVP = V ) and an undervolt-
CC
age event occurs, the gate drivers are turned off and
the outputs float. Connect UVP to GND to disable
undervoltage protection.
The MAX1845’s pulse-skipping algorithm initiates
skip mode at the critical conduction point. So, the
inductor operating point also determines the load-
current value at which PFM/PWM switchover occurs.
The optimum point is usually found between 20%
and 50% ripple current.
Note that DL latching high causes the output voltage to
dip slightly negative when energy has been previously
stored in the LC tank circuit. For loads that cannot tol-
erate a negative voltage, place a power Schottky diode
across the output to act as a reverse polarity clamp.
Also, note the nonstandard logic levels if actively dri-
ving UVP (see the Electrical Characteristics).
Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as fol-
lows:
Design Procedure
V
(V - V
)
OUT IN
OUT
L =
V
× f × LIR × I
LOAD(MAX)
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good
switching frequency and inductor operating point, and
the following four factors dictate the rest of the design:
IN
Example: I
= 8A, V = 15V, V
= 1.8V,
OUT
LOAD(MAX)
IN
f = 300kHz, 25% ripple current or LIR = 0.25:
1.8V (15V - 1.8V)
L =
= 2.3µH
15V × 345kHz × 0.25 × 8A
______________________________________________________________________________________ 17
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
7a). Use the worst-case value for R
from the
DS(ON)
MOSFET data sheet, and add a margin of 0.5%/°C for
the rise in R with temperature. Use the calculat-
DS(ON)
ed R
and I
from step 1 above to determine
DS(ON)
L(MIN)
the current-limit threshold voltage. If the default 50mV
threshold is unacceptable, set the threshold value as in
step 2 above.
inductor current (I
):
PEAK
✕
I
= I
+ [(LIR / 2)
I
]
PEAK
LOAD(MAX)
LOAD(MAX)
In all cases, ensure an acceptable current limit consid-
ering current-sense and resistor accuracies.
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low V - V dif-
Output Capacitor Selection
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
Also, the capacitance value must be high enough to
absorb the inductor energy going from a full-load to no-
load condition without tripping the OVP circuit.
IN
OUT
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maxi-
mum duty factor, which can be calculated from the on-
time and minimum off-time:
2
For CPU core voltage converters and other applications
where the output is subject to violent load transients,
the output capacitor’s size depends on how much ESR
is needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
(∆I
)
× L
-V
LOAD(MAX)
V
=
SAG
2 × C × DUTY (V
)
F
IN(MIN) OUT
where:
DUTY =
K (V
+ 0.075V) V
IN
OUT
K (V
+ 0.075V) V
+ min off-time
OUT
OUT
V
DIP
LOAD(MAX)
R
≤
ESR
where minimum off-time = 400ns typ (Table 4).
I
The amount of overshoot during a full-load to no-load
transient due to stored inductor energy can be calculat-
ed as:
In non-CPU applications, the output capacitor’s size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
✕
V
SOAR
= L
I
2 / (2 C
V
)
PEAK
OUT OUT
VP−P
RESR
≤
where I
is the peak inductor current.
LIR × ILOAD(MAX)
PEAK
Determining the Current Limit
For most applications, set the MAX1845 current limit by
the following procedure:
1) Determine the minimum (valley) inductor current
(IL
) under conditions when V is small, V
is
(MIN)
IN
OUT
large, and load current is maximum. The minimum
MAX1845
MAX1845
inductor current is I
rent (Figure 4).
minus half the ripple cur-
LOAD
LX
LX
2) The sense resistor determines the achievable cur-
rent-limit accuracy. There is a trade-off between cur-
rent-limit accuracy and sense-resistor power
dissipation. Most applications employ a current-
sense voltage of 50mV to 100mV. Choose a sense
resistor such that:
DL
CS
DL
CS
R
= Current-Limit Threshold Voltage / I
L(MIN)
SENSE
a)
b)
Extremely cost-sensitive applications that do not
require high-accuracy current sensing can use the on-
resistance of the low-side MOSFET switch in place of
the sense resistor by connecting CS_ to LX_ (Figure
Figure 7. Current-Sense Configurations
18 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Table 4. Frequency Selection Guidelines
SIDE 1
FREQUENCY
SIDE 1
K-FACTOR
SIDE 2
FREQUENCY
(kHz)
SIDE 2
K-FACTOR
(µs)
APPROXIMATE
K-FACTOR
ERROR (%)
TON SETTING
(kHz)
(µs)
V
235
345
485
620
4.24
2.96
2.08
1.63
170
255
355
460
5.81
4.03
2.81
2.18
10
10
CC
FLOAT
REF
12.5
12.5
AGND
The actual microfarad capacitance value required
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR and volt-
age rating rather than by capacitance value (this is true
of tantalums, OS-CONs™, and other electrolytics).
10mΩ (max) ESR. Their typical combined ESR results in
a zero at 11.3kHz, well within the bounds of stability.
Do not put high-value ceramic capacitors directly
across the outputs without taking precautions to ensure
stability. Large ceramic capacitors can have a high-
ESR zero frequency and cause erratic, unstable opera-
tion. However, it is easy to add enough series
resistance by placing the capacitors a couple of inches
downstream from the inductor and connecting OUT_ or
the FB_ divider close to the inductor.
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent V
SAG
and V
from causing problems during load tran-
SOAR
sients. Also, the capacitance must be great enough to
prevent the inductor’s stored energy from launching the
output above the overvoltage protection threshold.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback-
loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough volt-
age ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immedi-
ately after the 400ns minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR.
load edge is no longer a problem (see the V
and
SAG
V
SOAR
equations in the Transient Response section).
Output Capacitor Stability
Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The point of instability
is given by the following equation:
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
f
SW
π
f
≤
ESR
where:
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX1845 EV kit manual) and carefully observe the out-
put voltage ripple envelope for overshoot and ringing. It
helps to simultaneously monitor the inductor current
with an AC current probe. Do not allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
1
f
=
ESR
2 × π × R
× C
F
ESR
For a typical 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero fre-
quencies of 15kHz. In the design example used for
inductor selection, the ESR needed to support 20mV
P-P
ripple is 20mV/2A = 10mΩ. Three 470µF/6V Kemet
T510 low-ESR tantalum capacitors in parallel provide
OS-CON is a trademark of Sanyo.
______________________________________________________________________________________ 19
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
become an issue until the input is greater than approxi-
Input Capacitor Selection
mately 15V.
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
RMS
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resistance to power-up
surge currents:
2
CV f switching loss equation. If the high-side MOSFET
chosen for adequate R
at low battery voltages
DS(ON)
V
V -V
(
)
OUT IN OUT
becomes extraordinarily hot when subjected to
, reconsider the choice of MOSFET.
I
= I
LOAD
RMS
V
V
IN(MAX)
IN
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for bench eval-
uation, preferably including a verification using a ther-
mocouple mounted on Q1:
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>5A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
ensure that the conduction losses at the minimum
input voltage do not exceed the package thermal limits
or violate the overall thermal budget. Check to ensure
that conduction losses plus switching losses at the
maximum input voltage do not exceed the package
ratings or violate the overall thermal budget.
2
C
× V
× f ×I
LOAD
RSS
IN(MAX)
PD(Q1 switching) =
I
GATE
where C is the reverse transfer capacitance of Q1,
RSS
and I
is the peak gate-drive source/sink current
GATE
(1A typ).
Choose a low-side MOSFET (Q2) that has the lowest
possible R
, comes in a moderate to small pack-
For the low-side MOSFET, Q2, the worst-case power
dissipation always occurs at maximum battery voltage:
DS(ON)
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX1845 DL gate driver can drive Q2; in other
words, check that the gate is not pulled up by the high-
side switch turning on due to parasitic drain-to-gate
capacitance, causing cross-conduction problems.
Switching losses are not an issue for the low-side MOS-
FET since it is a zero-voltage switched device when
used in the buck topology.
V
2
OUT
PD(Q2) = 1 -
I
× R
DS ON
LOAD
(
)
V
IN MAX
(
)
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
but are not quite high enough to exceed
LOAD(MAX)
the current limit. To protect against this possibility,
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty cycle
extremes. For the high-side MOSFET, the worst-case-
power dissipation (PD) due to resistance occurs at min-
imum battery voltage:
“overdesign” the circuit to tolerate:
✕
I
= I
+ (LIR / 2)
I
LOAD(MAX)
LOAD
LIMIT(HIGH)
where I
is the maximum valley current
LIMIT(HIGH)
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. If short-circuit
protection without overload protection is adequate,
V
2
OUT
PD(Q1 resistance) =
I
× R
DS ON
LOAD
(
)
V
enable overvoltage protection, and use I
calculate component stresses.
to
LOAD(MAX)
IN MIN
(
)
Generally, a small high-side MOSFET is desired in
order to reduce switching losses at high input voltages.
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency is not critical.
However, the R
required to stay within package
DS(ON)
power-dissipation limits often limits how small the MOS-
FET can be. Again, the optimum occurs when the
switching (AC) losses equal the conduction (R
)
DS(ON)
losses. High-side switching losses do not usually
20 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Dropout Design Example:
Applications Information
V
OUT
= 1.8V
Dropout Performance
fsw = 600kHz
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the nonadjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the slower on-time settings. When work-
ing with low input voltages, the duty-cycle limit must be
calculated using the worst-case values for on- and off-
times. Manufacturing tolerances and internal propaga-
tion delays introduce an error to the TON K-factor. This
error is greater at higher frequencies (Table 4). Also,
keep in mind that transient response performance of
buck regulators operating close to dropout is poor, and
bulk output capacitance must often be added (see the
K = 1.63µs, worst-case K = 1.4175µs
t
= 500ns
OFF(MIN)
V
= V
= 100mV
DROP1
DROP2
h = 1.5
✕
V
= (1.8V + 0.1V) / [1 - (0.5µs 1.5) / 1.4175µs]
+ 0.1V - 0.1V = 3.8V
IN(MIN)
Calculating again with h = 1 gives an absolute limit of
dropout:
✕
V
= (1.8V + 0.1V) / [1 - (0.5µs 1) / 1.4175µs]
+ 0.1V - 0.1V = 2.8V
IN(MIN)
V
equation in the Design Procedure section).
SAG
Therefore, V must be greater than 2.8V, even with
IN
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
very large output capacitance, and a practical input
voltage with reasonable output capacitance would be
3.8V.
)
DOWN
as much as it ramps up during the on-time (∆I ). The
UP
ratio h = ∆I / ∆I
is an indicator of ability to slew
UP
DOWN
the inductor current higher in response to increased
load and must always be greater than 1. As h ap-
proaches 1, the absolute minimum dropout point, the
inductor current will be less able to increase during each
Fixed Output Voltages
The MAX1845’s dual-mode operation allows the selec-
tion of common voltages without requiring external
components (Figure 8). Connect FB1 to GND for a fixed
switching cycle, and V
will greatly increase unless
SAG
1.8V output or to V
for a 1.5V output, or connect FB1
CC
additional output capacitance is used.
directly to OUT1 for a fixed 1V output.
A reasonable minimum value for h is 1.5, but this may
be adjusted up or down to allow trade-offs between
Connect FB2 to GND for a fixed 2.5V output or to OUT2
for a fixed 1V output.
V
, output capacitance, and minimum operating
SAG
voltage. For a given value of h, calculate the minimum
operating voltage as follows:
Setting V
OUT
_ with a Resistor-Divider
The output voltage can be adjusted from 1V to 5.5V
with a resistor-divider network (Figure 9). The equation
for adjusting the output voltage is:
✕
V
= [(V
+ V
) / {1 - (t
OFF(MIN)
h / K)}]
IN(MIN)
OUT
+ V
DROP1
- V
DROP2
DROP1
where V
and V
are the parasitic voltage
DROP1
DROP2
R1
R2
V
= V
1 +
OUT_
FB_
drops in the discharge and charge paths (see the On-
Time One-Shot (TON) section), t is from the
OFF(MIN)
where V _ is 1.0V and R2 is about 10kΩ.
Electrical Characteristics, and K is taken from Table 4.
The absolute minimum input voltage is calculated with h
= 1.
FB
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. This is
especially true for dual converters, where one channel
can affect the other. The switching power stages
require particular attention (Figure 10). Refer to the
MAX1845 evaluation kit data sheet for a specific layout
example.
If the calculated V
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
is greater than the required
IN(MIN)
able V
. If operation near dropout is anticipated,
SAG
SAG
calculate V
to ensure adequate transient response.
Use a four-layer board. Use the top side for power
components and the bottom side for the IC and the
sensitive ground components. Use the two middle lay-
ers as ground planes, with interconnections between
the top and bottom layers as needed. If possible,
______________________________________________________________________________________ 21
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
V
BATT
OUT1
OUT2
DH_
TO ERROR TO ERROR
FIXED
1.5V
FIXED
2.5V
AMP1
AMP2
V
OUT
FIXED
1.8V
MAX1845
DL_
CS_
FB1
2V
FB2
R1
R2
OUT_
FB_
0.1V
MAX1845
GND
0.1V
Figure 8. Feedback Mux
Figure 9. Setting V
with a Resistor-Divider
OUT
mount all of the power components on the top side of
the board, with connecting terminals flush against one
another.
USE AGND PLANE TO:
USE PGND PLANE TO:
- BYPASS V
- BYPASS V AND REF
CC
DD
- TERMINATE EXTERNAL FB, ILIM,
OVP DIVIDERS, IF USED
- PIN-STRAP CONTROL
INPUTS
- CONNECT IC GROUND
TO TOP-SIDE STAR GROUND
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. Short power traces and load con-
nections are essential for high efficiency. Using thick
copper PC boards (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PC board
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mil-
liohm of excess trace resistance causes a measurable
efficiency penalty.
AGND PLANE
PGND PLANE
VIA TO TOP-SIDE
GROUND
AGND PLANE
Place the current-sense resistors close to the top-side
star-ground point (where the IC ground connects to the
top-side ground plane) to minimize current-sensing
errors. Avoid additional current-sensing errors by using
a Kelvin connection from CS_ pins to the sense resis-
tors.
V
IN
Q1
Q3
The following guidelines are in order of importance:
Q4
Q2
C
C
C
IN IN
IN
• Keep the space between the ground connection of
the current-sense resistors short and near the via to
the IC ground pin.
D2
D1
L1
L2
• Minimize the resistance on the low-side path. The
low-side path starts at the ground of the low-side
FET, goes through the low-side FET, through the
inductor, through the output capacitor, and returns
to the ground of the low-side FET. Minimize the resis-
tance by keeping the components close together
and the traces short and wide.
C1
C2
VIA TO OUT1
VIA TO PGND PLANE AND IC GND
TOP-SIDE GROUND PLANE
NOTCH
VIA TO CS1
• Minimize the resistance in the high-side path. This
Figure 10. PC Board Layout Example
path starts at V , goes through the high-side FET,
IN
22 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
through the inductor, through the input capacitor,
5) On the board’s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
The top-side star ground is a star connection of the
input capacitors, side 1 low-side MOSFET, and side
2 low-side MOSFET. Keep the resistance low
between the star ground and the source of the low-
side MOSFETs for accurate current limit. Connect
the top-side star ground (used for MOSFET, input,
and output capacitors) to the small PGND island with
a short, wide connection (preferably just a via).
and back to the input.
• When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Minimize crosstalk between side 1 and side 2 by
directing their switching ground currents into the star
ground with a notch as shown in Figure 10. If multi-
ple layers are available (highly recommended), cre-
ate PGND1 and PGND2 islands on the layer just
below the top-side layer (refer to the MAX1845 EV kit
for an example) to act as an EMI shield. Connect
each of these individually to the star-ground via,
which connects the top side to the PGND plane. Add
one more solid ground plane under the IC to act as
an additional shield, and also connect that to the
star-ground via.
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF,
ILIM_, FB_).
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (sense resistor, C -, C
-, D1
OUT
IN
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the synchronous
rectifiers MOSFETs, preferably on the back side in
order to keep CS_, GND, and the DL_ gate-drive line
short and wide. The DL_ gate trace must be short
and wide, measuring 10 squares to 20 squares
(50mils to 100mils wide if the MOSFET is 1 inch from
the controller IC).
6) Connect the output power planes directly to the out-
put filter capacitor positive and negative terminals
with multiple vias.
3) Group the gate-drive components (BST_ diode and
Chip Information
TRANSISTOR COUNT: 4795
PROCESS: BiCMOS
capacitor, V
bypass capacitor) together near the
DD
controller IC.
4) Make the DC-DC controller ground connections as
follows: Create a small analog ground plane (AGND)
near the IC. Connect this plane directly to GND
under the IC, and use this plane for the ground con-
nection for the REF and V
bypass capacitors,
CC
FB_, OVP, and ILIM_ dividers (if any). Do not con-
nect the AGND plane to any ground other than the
GND pin. Create another small ground island
(PGND), and use it for the V
bypass capacitor,
DD
placed very close to the IC. Connect the PGND
plane directly to GND from the outside of the IC.
______________________________________________________________________________________ 23
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Pin Configurations
TOP VIEW
OUT1
FB1
1
2
3
4
5
6
7
8
9
28 CS1
27 LX1
26 DH1
25 BST1
24 DL1
23 GND
TON
SKIP
PGOOD
OVP
1
2
3
4
5
6
7
8
9
27 BST1
26 DL1
ILIM1
V+
25 N.C.
24 PGND
23 AGND
UVP
N.C.
TON
MAX1845ETX
22
21
20
V
V
DL2
CC
MAX1845EEI
SKIP
PGOOD
OVP
REF
DD
22
21
V
V
ON1
CC
DD
N.C.
19 BST2
UVP
20 DL2
19 BST2
18 DH2
17 LX2
16 CS2
15 OUT2
REF 10
ON1 11
ON2 12
ILIM2 13
FB2 14
THIN QFN
QSOP
24 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Note: The MAX1845EEI does not have a heat slug.
______________________________________________________________________________________ 25
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D2/2
D/2
k
E/2
E2/2
C
(NE-1) X
e
E
E2
L
k
L
e
(ND-1) X
e
C
C
L
L
L
L
e
e
A
A1
A2
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
36, 40L QFN THIN, 6x6x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0141
B
2
26 ______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
D2
E2
PKG.
CODES
MIN. NOM. MAX. MIN. NOM. MAX.
3.60 3.70 3.80 3.60 3.70 3.80
4.00 4.10 4.20 4.00 4.10 4.20
T3666-1
T4066-1
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
PROPRIETARY INFORMATION
TITLE:
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40L QFN THIN, 6x6x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0141
B
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
27 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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