MAX1858EEG+T [MAXIM]
Dual Switching Controller, Voltage-mode, 10A, 600kHz Switching Freq-Max, BICMOS, PDSO24, 0.150 INCH, QSOP-24;
| 型号： | MAX1858EEG+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller, Voltage-mode, 10A, 600kHz Switching Freq-Max, BICMOS, PDSO24, 0.150 INCH, QSOP-24 控制器 |
| 文件： | 总22页 (文件大小：551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2966; Rev 0; 10/03
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
General Description
Features
The MAX1858A/MAX1875A/MAX1876A dual, synchro-
nized, step-down controllers generate two outputs from
input supplies ranging from 4.5V to 23V. Each output is
adjustable from sub-1V to 18V and supports loads of 10A
or higher. Input voltage ripple and total RMS input ripple
current are reduced by synchronized 180° out-of-phase
operation.
o 4.5V to 23V Input Supply Range
o 0 to 18V Output Voltage Range (Up to 10A)
o Adjustable Lossless Foldback Current Limit
o Adjustable 100kHz to 600kHz Switching
Frequency
The switching frequency is adjustable from 100kHz to
600kHz with an external resistor. Alternatively, the con-
troller can be synchronized to an external clock gener-
ated by another MAX1858A/MAX1875A/MAX1876A or a
system clock. One MAX1858A/MAX1875A/MAX1876A
can be set to generate an in-phase, or 90° out-of-
phase, clock signal for synchronization with additional
controllers. This allows two controllers to operate either
as an interleaved two- or four-phase system with each
output shifted by 90°. The MAX1858A/MAX1875A/
MAX1876A feature soft-start. The MAX1858A also fea-
tures first-on/last-off power sequencing and soft-stop.
o Optional Synchronization
o Clock Output for Master/Slave Synchronization
o 4 x 90° Out-of-Phase Step-Down Converters
(Using Two Controllers, Figure 7)
o Prebias Startup (MAX1875A/MAX1876A)
o Power Sequencing (MAX1858A)
o RST Output with 140ms Minimum Delay
(MAX1858A/MAX1876A)
o Fixed-Frequency Pulse-Width Modulation (PWM)
The MAX1858A/MAX1875A/MAX1876A eliminate the
need for current-sense resistors by utilizing the low-side
MOSFET’s on-resistance as a current-sense element.
This protects the DC-DC components from damage dur-
ing output-overload conditions or output short-circuit
faults without requiring a current-sense resistor.
Adjustable foldback current limit reduces power dissipa-
tion during short-circuit conditions. The MAX1858A/
MAX1876A include a power-on reset (POR) output to sig-
nal the system when both outputs reach regulation.
Operation
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 QSOP
MAX1858AEEG
MAX1875AEEG
MAX1876AEEG
24 QSOP
24 QSOP
The MAX1858A/MAX1875A/MAX1876A ensure that the
output voltage does not swing negative when the input
power is removed or when EN is driven low. The
MAX1875A/MAX1876A also allow prebias startup with-
out discharging the output.
Pin Configuration
TOP VIEW
COMP2
1
2
3
4
5
6
7
8
9
24 EN
The MAX1858A/MAX1875A/MAX1876A are available in a
24-pin QSOP package. Use the MAX1875 evaluation kit
or the MAX1858 evaluation kit to evaluate the
MAX1858A/MAX1875A/MAX1876A.
FB2
ILIM2
OSC
V+
23 DH2
22
LX2
21 BST2
20 DL2
Applications
MAX1858A
MAX1875A
MAX1876A
REF
19 V
L
Network Power Supplies
GND
CKO
SYNC
18 PGND
17 DL1
Telecom Power Supplies
DSP, ASIC, and FPGA Power Supplies
Set-Top Boxes
16 BST1
ILIM1 10
FB1 11
15
14
LX1
Broadband Routers
Servers
DH1
COMP1 12
13 RST (N.C.)
() ARE FOR THE MAX1875A ONLY
Desknote Computers
QSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +25V
PGND to GND .......................................................-0.3V to +0.3V
FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V
VL to GND Short Circuit .............................................Continuous
REF to GND Short Circuit...........................................Continuous
V to GND ..................-0.3V to the lower of +6V and (V+ + 0.3V)
L
BST1, BST2 to GND ...............................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
Continuous Power Dissipation (T = +70°C)
A
24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DH1 to LX1 ..............................................-0.3V to (V
DH2 to LX2 ..............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
BST1
BST2
DL1, DL2 to PGND........................................-0.3V to (V + 0.3V)
L
CKO, REF, OSC, ILIM1, ILIM2,
COMP1, COMP2 to GND..........................-0.3V to (V + 0.3V)
L
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 12V, EN = ILIM_ = V , SYNC = GND, I = 0mA, PGND = GND, C
= 0.22µF, C = 4.7µF (ceramic), R = 60kΩ,
OSC
L
VL
REF
VL
compensation components for COMP_ are from Figure 1, T = -40°C to +85°C (Note 1), unless otherwise noted.)
A
PARAMETER
GENERAL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 2)
V = V+ (Note 2)
4.5
4.5
23.0
5.5
6
V+ Operating Range
V
L
V+ Operating Supply Current
V+ Standby Supply Current
Thermal Shutdown
V unloaded, no MOSFETs connected
L
3.5
0.3
mA
mA
°C
EN = LX_ = FB_ = 0V
0.6
Rising temperature, typical hysteresis = 10°C
+160
100
50
ILIM_ = V
75
32
125
62
L
Current-Limit Threshold
PGND - LX_
mV
R
R
= 100kΩ
= 600kΩ
ILIM_
ILIM_
225
300
375
V
REGULATOR
L
Output Voltage
5.5V < V+ < 23V, 1mA < I
< 50mA
4.75
4.1
5
5.25
4.3
V
V
LOAD
V Undervoltage Lockout Rising
L
Trip Level
4.2
V Undervoltage Lockout
L
Hysteresis
(Note 3)
100
mV
REFERENCE
Output Voltage
Reference Load Regulation
SOFT-START
I
= 0µA
1.98
0
2.00
4
2.02
10
V
REF
0µA < I
< 50µA
mV
REF
Internal 6-bit DAC for one converter to ramp from 0V to
full scale (Note 4)
DC-DC
clocks
Digital Ramp Period
1024
64
Soft-Start Steps
Steps
FREQUENCY
0°C to +85°C
84
80
100
100
600
250
115
120
660
303
Low End of Range
R
= 60kΩ
kHz
OSC
-40°C to +85°C
High End of Range
R
R
= 10kΩ
= 10kΩ
540
kHz
ns
OSC
OSC
DH_ Minimum Off-Time
2
_______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 12V, EN = ILIM_ = V , SYNC = GND, I = 0mA, PGND = GND, C
= 0.22µF, C = 4.7µF (ceramic), R = 60kΩ,
OSC
L
VL
REF
VL
compensation components for COMP_ are from Figure 1, T = -40°C to +85°C (Note 1), unless otherwise noted.)
A
PARAMETER
SYNC Range
CONDITIONS
MIN
TYP
MAX
UNITS
Switching frequency must be set to half of the SYNC
frequency
200
1200
kHz
High
100
100
SYNC Input Pulse Width
(Note 4)
Low
ns
ns
SYNC Rise/Fall Time
ERROR AMPLIFIER
FB_ Input Bias Current
(Note 4)
100
250
1.015
1.02
2.70
2.9
nA
V
0°C to +85°C
-40°C to +85°C
0°C to +85°C
-40°C to +85°C
0.985
0.98
1.25
1.2
1.00
1.00
1.8
FB_ Input Voltage Set Point
FB_ to COMP_ Transconductance
mS
1.8
DRIVERS
DL_, DH_ Break-Before-Make Time
C
= 5nF
30
1.5
3
ns
LOAD
Low
High
Low
High
2.5
5
DH_ On-Resistance
DL_ On-Resistance
Ω
0.6
3
1.5
5
Ω
LOGIC INPUTS (EN, SYNC)
Input Low Level
Typical 15% hysteresis, V = 4.5V
0.8
+1
0.4
V
V
L
Input High Level
V = 5.5V
L
2.4
-1
Input High/Low Bias Current
LOGIC OUTPUTS (CKO)
Output Low Level
V
= 0 or 5.5V
+0.1
µA
EN
V = 5V, sinking 5mA
L
V
V
Output High Level
COMP_
V = 5V, sourcing 5mA
L
4.0
Pulldown Resistance During
Shutdown and Current Limit
17
Ω
RST OUTPUT (MAX1858A/MAX1876A ONLY)
Both FBs must be over this to allow the reset timer to
start; there is no hysteresis
Output-Voltage Trip Level
Output Low Level
0.87
140
0.9
0.93
V
V
V = 5V, sinking 3.2mA
L
0.4
0.3
1
V = 1V, sinking 0.4mA
L
Output Leakage
V+ = V = 5V, V
= 5.5V, V = 1V
µA
ms
µs
L
RST
FB
Reset Timeout Period
FB_ to Reset Delay
V
= 1V
315
4
560
FB_
FB_ overdrive from 1V to 0.85V
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: Operating supply range is guaranteed by V line regulation test. Connect V+ to V for 5V operation.
L
L
Note 3: When V falls and UVLO is tripped, the device is latched and V must be discharged below 2.5V before normal operation
L
L
can resume.
Note 4: Guaranteed by design and not production tested.
_______________________________________________________________________________________
3
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Typical Operating Characteristics
(Circuit of Figure 1, V = 12V, T = +25°C, unless otherwise noted.)
IN
A
V VOLTAGE ACCURACY
L
vs. LOAD CURRENT
EFFICIENCY vs. LOAD
OUTPUT VOLTAGE ACCURACY vs. LOAD
0.5
0
100
90
80
70
60
50
40
30
20
10
0
1.0
0.8
OUT2
OUT1
0.6
0.4
-0.5
-1.0
-1.5
-2.0
0.2
OUT2
OUT1
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
50
100
150
0.1
1
10
100
0
5
10
15
LOAD CURRENT (mA)
LOAD (A)
LOAD (A)
LOAD TRANSIENT RESPONSE (OUTPUT 1)
LOAD TRANSIENT RESPONSE (OUTPUT 2)
SWITCHING FREQUENCY vs. R
OSC
MAX1858A/75A/76A toc05
MAX1858A/75A/76A toc06
600
500
400
300
200
100
0
V
OUT2
50mV/div
V
OUT1
50mV/div
AC-COUPLED
AC-COUPLED
V
V
OUT1
OUT2
50mV/div
50mV/div
AC-COUPLED
AC-COUPLED
10A
10A
I
I
OUT1
OUT2
0A
0A
10µs/div
10µs/div
0
10
20
30
(kΩ)
40
50
60
R
OSC
SOFT-START AND SOFT-STOP WAVEFORM
SOFT-START AND SOFT-STOP WAVEFORM
(MAX1858A ONLY)
(MAX1858A ONLY)
MAX1858A/75A/76A toc08
MAX1858A/75A/76A toc07
10V
EN
0V
EN PULLED HIGH BEFORE V
REACHES 0V.
OUT1
5V
EN
0V
V
OUT1
1V/div
V
OUT1
1V/div
= 300mA
I
= 300mA
OUT1
I
OUT1
0V
0V
V
OUT2
1V/div
V
OUT2
1V/div
= 300mA
I
= 300mA
OUT2
I
OUT2
0V
0V
2ms/div
2ms/div
4
_______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, T = +25°C, unless otherwise noted.)
IN
A
START AND STOP WAVEFORM
(MAX1875A/MAX1876A ONLY)
RESET TIMEOUT
INPUT POWER REMOVAL
(MAX1858A/MAX1876A ONLY)
MAX1858A/75A/76A toc10
MAX1858A/75A/76A toc11
MAX1858A/75A/76A toc09
10V
EN
V
IN
0V
EN
0
10V/div
0V
V
1V/div
V
OUT1
OUT1
1V/div
= 300mA
V
OUT2
I
OUT1
0V
I
= 300mA
OUT1
0V
0V
V
OUT1
0V
V
OUT2
1V/div
V
OUT2
1V/div
I
= 300mA
OUT2
I
= 300mA
OUT2
V
RST
0V
0V
0V
PREBIAS STARTUP
5ms/div
100ms/div, 5V/div
2ms/div
EXTERNALLY SYNCHRONIZED
SWITCHING WAVEFORM
OUT-OF-PHASE WAVEFORM
CKO OUTPUT WAVEFORM
MAX1858A/75A/76A toc13
MAX1858A/75A/76A toc12
MAX1858A/75A/76A toc14
5V
SYNC
0V
V
SYNC = GND
V
OUT1
20mV/div
12V
5V
V
5V
V
V
CK0
0V
LX1
CK0
0V
0V
12V
10V
LX1
0V
10V
LX1
0V
V
V
V
LX2
0V
V
V
OUT1
10mV/div
OUT1
10mV/div
V
OUT2
AC-COUPLED
AC-COUPLED
20mV/div
400ns/div
1µs/div
400ns/div
SHORT-CIRCUIT CURRENT FOLDBACK
CKO OUTPUT WAVEFORM
AND RECOVERY
MAX1858A/75A/76A toc15
MAX1858A/75A/76A toc16
SYNC = V
L
I
V
= 10A (5A/div)
OUT1
5V
= 1.8V (1V/div)
OUT1
V
CK0
0V
10V
LX1
0V
V
I
= 2.5V (1V/div)
= 10A (5A/div)
V
OUT2
SHORT
V
OUT2
OUT2
V
OUT1
10mV/div
400ns/div
4ms/div
_______________________________________________________________________________________
5
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Pin Description
PIN
NAME
FUNCTION
Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series resistor
1
COMP2 (R
) and capacitor (C
) to GND in parallel with a second compensation capacitor (C
COMP2A
) as
COMP2B
COMP2
shown in Figure 1.
Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive divider between REG2’s output and GND to
adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB2 to a resistive
voltage-divider from REF to REG2’s output. See the Setting the Output Voltage section.
2
3
FB2
Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to 100mV if
ILIM2 is connected to V . Connect a resistor (R
) from ILIM2 to GND to adjust the REG2’s current-limit
ILIM2
L
ILIM2
threshold (V
) from 50mV (R
= 100kΩ) to 300mV (R
= 600kΩ). See the Setting the Valley Current
ITH2
ILIM2
ILIM2
Limit section.
Oscillator Frequency Set Input. Connect a resistor from OSC to GND (R ) to set the switching frequency from
OSC
100kHz (R
= 60kΩ) to 600kHz (R
= 10kΩ). The controller still requires R
when an external clock is
OSC
OSC
OSC
4
OSC
connected to SYNC. When using an external clock, select R
as described above, and set the external clock
OSC
frequency to twice the desired switching frequency.
5
6
7
V+
Input Supply Voltage. 4.5V to 23V.
REF
GND
2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor.
Analog Ground
Clock Output. Clock output for external 2- or 4-phase synchronization (see the Clock Synchronization (SYNC,
CKO) section).
8
CKO
Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect SYNC to a
200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase operation as a master
9
SYNC
controller. Connect SYNC to V for 4-phase operation as a master controller (see the Clock Synchronization
L
(SYNC, CKO) section).
Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to 100mV if
ILIM1 is connected to V . Connect a resistor (R
) from ILIM1 to GND to adjust REG1’s current-limit threshold
ILIM1
10
11
12
ILIM1
FB1
L
(V
ITH1
) from 50mV (R
= 100kΩ) to 300mV (R
= 600kΩ). See the Setting the Valley Current Limit section.
ILIM1
ILIM1
Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive divider between REG1’s output and GND to
adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB1 to a resistive
voltage-divider from REF and REG1’s output. See the Setting the Output Voltage section.
Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series resistor
COMP1 (R
) and capacitor (C
) to GND in parallel with a second compensation capacitor (C
COMP1A
) as
COMP1B
COMP1
shown in Figure 1.
Open-Drain Reset Output (MAX1858A/MAX1876A Only). RST is low when either output voltage is more than 10%
below its regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output
RST
voltage (V _ > 0.9V), RST becomes high impedance after a 140ms delay and remains high impedance as long
as both outputs maintain regulation. Connect a resistor between RST and the logic supply for logic-level
FB
13
voltages.
N.C.
Connect to GND or leave unconnected for the MAX1875A.
6
_______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Pin Description (continued)
PIN
NAME
FUNCTION
14
DH1
High-Side Gate-Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1. DH1 is low during UVLO.
External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the inductor. LX1
serves as the lower supply rail for the DH1 high-side gate driver.
15
16
LX1
Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic capacitor and
diode according to Figure 1.
BST1
DL1
17
18
Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to V . DL1 is low during UVLO.
L
PGND Power Ground
Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers and external
boost circuitry for the high-side gate drivers.
19
20
21
V
L
DL2
Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to V . DL2 is low during UVLO.
L
Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic capacitor and
diode according to Figure 1.
BST2
External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the inductor. LX2
serves as the lower supply rail for the DH2 high-side gate driver.
22
LX2
23
24
DH2
EN
High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2. DH2 is low during UVLO.
Active-High Enable Input. A logic low shuts down both controllers. Connect to V for always-on operation.
L
tor current exceeds the selected valley current limit (see
Detailed Description
the Current-Limit Circuit (ILIM_) section), the high-side
DC-DC PWM Controller
MOSFET does not turn on at the appropriate clock edge
and the low-side MOSFET remains on to let the inductor
current ramp down.
The MAX1858A/MAX1875A/MAX1876A step-down con-
verters use a PWM voltage-mode control scheme (Figure
2) for each out-of-phase controller. The controller gener-
ates the clock signal by dividing down the internal oscil-
lator or SYNC input when driven by an external clock, so
each controller’s switching frequency equals half the
Synchronized Out-of-Phase Operation
The two independent regulators in the MAX1858A/
MAX1875A/MAX1876A operate 180° out-of-phase to
reduce input filtering requirements, reduce electromag-
netic interference (EMI), and improve efficiency. This
effectively lowers component cost and saves board
space, making the MAX1858A/MAX1875A/MAX1876A
ideal for cost-sensitive applications.
oscillator frequency (f
= f /2). An internal transcon-
OSC
SW
ductance error amplifier produces an integrated error
voltage at the COMP pin, providing high DC accuracy.
The voltage at COMP sets the duty cycle using a PWM
comparator and a ramp generator. At each rising edge
of the clock, REG1’s high-side N-channel MOSFET turns
on and remains on until either the appropriate duty cycle
or until the maximum duty cycle is reached. REG2 oper-
ates out-of-phase, so the second high-side MOSFET
turns on at each falling edge of the clock. During each
high-side MOSFET’s on-time, the associated inductor
current ramps up.
Dual-switching regulators typically operate both
controllers in-phase, and turn on both high-side
MOSFETs at the same time. The input capacitor must
then support the instantaneous current requirements of
both controllers simultaneously, resulting in increased
ripple voltage and current when compared to a single
switching regulator. The higher RMS ripple current
lowers efficiency due to power loss associated with the
input capacitor’s effective series resistance (ESR). This
typically requires more low-ESR input capacitors in
parallel to minimize input voltage ripple and ESR-related
losses, or to meet the necessary ripple-current rating.
During the second-half of the switching cycle, the high-
side MOSFET turns off and the low-side N-channel
MOSFET turns on. Now the inductor releases the stored
energy as its current ramps down, providing current to
the output. Under overload conditions, when the induc-
_______________________________________________________________________________________
7
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
V
IN
6V - 23V
CMPSH-3A
R
0.1µF
V+
4.7Ω
V+
V
L
C
C
VL
4.7µF
V+
0.22µF
4.7Ω
4.7Ω
C
C
2
IN1
10µF
IN2
×
10µF
BST1
BST2
×
2
C
C
BST2
0.1µF
BST1
0.1µF
N
DH1
LX1
DH2
LX2
DL2
OUTPUT2
= 2.5V
OUTPUT1
= 1.8V
H1*
N
N
H2*
L1
L2
1.1µH
V
V
OUT
OUT
1.1µH
C
OUT1
C
4
OUT2
220µF
×
4
220µF
×
**
N
DL1
**
L1*
R1A
R2A
L2*
8.06kΩ
15kΩ
PGND
FB1
FB2
R
R
COMP2
8.2kΩ
COMP1
5.9kΩ
R2B
10kΩ
R1B
10kΩ
COMP1
COMP2
C
C
C
C
COMP2A
6800pF
COMP1A
0.01µF
COMP1B
100pF
COMP2B
100pF
D2
CMSSH-3
D3
CMSSH-3
MAX1858A
MAX1875A
MAX1876A
REF
10kΩ
C
REF
0.22µF
OSC
CKO
GND
CLOCK OUTPUT
RESET OUTPUT
ON
118kΩ
SYNC
ILIM1
ILIM2
V
L
RST (MAX1858A/
MAX1876A ONLY)
96.5kΩ
140kΩ
EN
*IRF7811W
**OPTIONAL
OFF
84.5kΩ
Figure 1. Standard 600kHz Application Circuit
With dual, synchronized, out-of-phase operation, the
MAX1858A/MAX1875A/MAX1876As’ high-side MOSFETs
turn on 180° out-of-phase. The instantaneous input cur-
rent peaks of both regulators no longer overlap, resulting
in reduced RMS ripple current and input voltage ripple.
This reduces the required input capacitor ripple-current
rating, allowing fewer or less expensive capacitors, and
reduces shielding requirements for EMI. The Out-of-
Phase Waveforms in the Typical Operating Charac-
teristics demonstrate synchronized 180° out-of-phase
operation.
Internal 5V Linear Regulator (V )
L
All MAX1858A/MAX1875A/MAX1876A functions are
internally powered from an on-chip, low-dropout 5V
regulator. The maximum regulator input voltage (V+) is
23V. Bypass the regulator’s output (V ) with a 4.7µF
L
ceramic capacitor to PGND. The V dropout voltage is
L
typically 500mV, so when V+ is greater than 5.5V, V is
L
typically 5V. The MAX1858A/MAX1875A/MAX1876A
also employs an undervoltage lockout circuit that dis-
ables both regulators when V falls below 4.2V. V
L
L
should also be bypassed to GND with a 0.1µF capaci-
tor. When V falls and UVLO is tripped, the device is
L
latched and V must be discharged below 2.5V before
L
normal operation can resume.
8
_______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
REF
V+
5V LINEAR
REGULATOR
MAX1858A
MAX1875A
MAX1876A
V
REF
2.0V
GND
COMP1
FB1
V
L
BST1
DH1
LX1
CONVERTER 1
SOFT-START DAC
(SEQUENCING—
MAX1858A ONLY)
R
S
Q
Q
DL1
PGND
1V
P-P
OSC
SYNC
CK0
OSCILLATOR
5µA
RST
(MAX1858A/
MAX1876A ONLY)
ILIM1
RESET
EN
UVLO
AND
SHUTDOWN
V
REF
V - 0.5V
L
V
L
BST2
DH2
LX2
CONVERTER 2
COMP2
FB2
DL2
ILIM2
Figure 2. Functional Diagram
The internal V linear regulator can source over 50mA to
L
For example, when switched at 600kHz, a single large
✕
supply the IC, power the low-side gate driver, charge the
external boost capacitor, and supply small external
loads. When driving large FETs, little or no regulator cur-
rent may be available for external loads.
FET with 18nC total gate charge requires 18nC 600kHz
= 11mA. To drive larger MOSFETs, or deliver larger
loads, connect V to an external power supply from 4.5V
L
to 5.5V.
_______________________________________________________________________________________
9
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
E
F
G
J
A
C
D
H
I
L
UVLO
B
K
V
L
EN
VOUT_
SS_
DH_
DL_
M
O
N
MAX1875A/MAX1876A POWER-ON-OFF SEQUENCING DEFINITIONS
SYMBOL
DEFINITION
UVLO
VL
EN
Undervoltage lockout trip level is provided in the Electrical Characteristics table.
Internal 5V Linear-Regulator Output
Active-High Enable Input
VOUT_
Output Voltage
SS_
DH_
DL_
A
Internal Soft-Start Input Signal into Error Amplifier
High-Side Gate-Driver Output
Low-Side Gate-Driver Output
V rising while below the UVLO threshold. EN is low.
L
B
V is greater than the UVLO threshold. EN is low.
L
C
D
EN is pulled high.
Normal operation
E
V enters UVLO.
L
F
V exits UVLO.
L
G
H
Resumes normal operation
EN is pulled low.
I
EN is pulled high.
J
Resumes normal operation
K
V drops below UVLO threshold while EN is high.
L
L
Resumes normal operation
M
N
O
UVLO is activated and DL_ is latched low.
Exiting UVLO: DL_ remains latched low until the first fall of DH_ is detected.
DL_ is low after EN is pulled low.
Figure 3. MAX1875A/MAX1876A Detailed Power-On-Off Sequencing
10 ______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
UVLO
B
C
D
E
F
G
H
I
J
K
L
M
A
V
L
EN
VOUT1
SS1
VOUT2
SS2
DH1
DL1
DH2
DL2
N
O
P
MAX1858A POWER-ON-OFF SEQUENCING DEFINITIONS
SYMBOL
SYMBOL
DEFINITION
DEFINITION
Normal operation
V enters UVLO.
L
V exits UVLO.
L
D
E
F
Undervoltage threshold value is provided in the
UVLO
Electrical Characteristics table.
Internal 5V Linear-Regulator Output
V
L
Active-High Enable Input
Regulator 1 Output Voltage
Regulator 1: Internal Soft-Start Input Signal into Error Amplifier
Regulator 2 Output Voltage
Regulator 2: Internal Soft-Start Input Signal into Error Amplifier
Regulator 1: High-Side Gate-Driver Output
Regulator 1: Low-Side Gate-Driver Output
Regulator 2: High-Side Gate-Driver Output
Regulator 2: Low-Side Gate-Driver Output
Resumes normal operation. DH1 and DL1 start switching.
DH2 and DL2 are off.
EN is pulled low and then high.
VOUT1 must reach 0V before restarting due to the cycling
of the enable in region H (above).
EN
VOUT1
SS1
VOUT2
SS2
DH1
DL1
DH2
DL2
A
G
H
I
J
K
L
M
N
VOUT1 recovers.
VOUT2 recovers.
V enters UVLO before VOUT2 fully recovers.
L
V exits UVLO.
L
UVLO latches DL_ low.
V rising while below the UVLO threshold. EN is low.
L
V is greater than the UVLO threshold. EN is low.
L
Exiting UVLO: DL_ remains latched low until the first fall
of DH_ is detected.
B
O
P
EN is pulled high. DH1 and DL1 start switching. DH2 and
DL2 are off.
C
DL_ is high after EN is pulled low and soft-stop is complete.
Figure 4. MAX1858A Detailed Power-On-Off Sequencing
______________________________________________________________________________________ 11
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
High-Side Gate-Drive Supply (BST_)
Gate-drive voltages for the high-side N-channel switch-
es are generated by the flying-capacitor boost circuits
(Figure 5). A boost capacitor (connected from BST_ to
LX_) provides power to the high-side MOSFET driver.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch.
Additionally, the MAX1858A/MAX1875A/MAX1876A use
the synchronous rectifier to ensure proper startup of the
boost gate-driver circuit and to provide the current-limit
signal.
The internal pulldown transistor that drives DL_ low is
robust, with a 0.5Ω (typ) on-resistance. This low on-
resistance helps prevent DL_ from being pulled up dur-
ing the fast rise time of the LX_ node, due to capacitive
coupling from the drain to the gate of the low-side syn-
chronous-rectifier MOSFET. However, for high-current
applications, some combinations of high- and low-side
FETs can cause excessive gate-drain coupling, leading
to poor efficiency, EMI, and shoot-through currents.
This can be remedied by adding a resistor (typically
less than 5Ω) in series with BST_, which increases the
turn-on time of the high-side FET without degrading the
turn-off time (Figure 5).
On startup, the synchronous rectifier (low-side MOSFET)
forces LX_ to ground and charges the boost capacitor to
5V. On the second half-cycle, after the low-side MOSFET
turns off, the high-side MOSFET is turned on by closing
an internal switch between BST_ and DH_. This provides
the necessary gate-to-source voltage to turn on the high-
side switch, an action that boosts the 5V gate-drive
signal above V . The current required to drive the high-
IN
✕
side MOSFET gates (f
Q ) is ultimately drawn
G
SWITCH
from V .
L
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving moder-
ate-size N-channel high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen with large V - V
differential. The DL_ low-side
IN
OUT
drive waveform is always the complement of the DH_
high-side drive waveform (with controlled dead time to
prevent cross-conduction or “shoot-through”). An adap-
tive dead-time circuit monitors the DL_ output and pre-
vents the high-side FET from turning on until DL_ is fully
off. There must be a low-resistance, low-inductance path
from the DL_ driver to the MOSFET gate in order for the
adaptive dead-time circuit to work properly. Otherwise,
the sense circuitry in the MAX1858A/MAX1875A/
MAX1876A interprets the MOSFET gate as “off” while
there is actually charge still left on the gate. Use very
short, wide traces (50mils to 100mils wide if the MOSFET
is 1in from the device). The dead time at the DH-off edge
is determined by a fixed 30ns internal delay.
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a “valley” current-sens-
ing algorithm that uses the on-resistance of the low-side
MOSFET as a current-sensing element. If the current-
sense signal is above the current-limit threshold, the
MAX1858A/MAX1875A/MAX1876A do not initiate a new
cycle (Figure 6). Since valley current sensing is
employed, the actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
tor ripple current. Therefore, the exact current-limit char-
acteristic and maximum load capability are a function of
the low-side MOSFET’s on-resistance, current-limit
threshold, inductor value, and input voltage. The reward
for this uncertainty is robust, lossless overcurrent sens-
ing that does not require costly sense resistors.
INPUT
(V )
IN
V
-I
L
PEAK
4.7Ω
BST_
DH_
LX_
I
I
LOAD
LIMIT
MAX1875A
0
TIME
Figure 5. Reducing the Switching-Node Rise Time
12 ______________________________________________________________________________________
Figure 6. “Valley” Current-Limit Threshold Point
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Procedure section). The current-limit thresh-
old is adjusted with an external resistor at ILIM_ (Figure
1). The adjustment range is from 50mV to 300mV, cor-
responding to resistor values of 100kΩ to 600kΩ. In
adjustable mode, the current-limit threshold across the
low-side MOSFET is precisely 1/10th the voltage seen
at ILIM_. However, the current-limit threshold defaults
Output-Voltage Sequencing
After the startup circuitry enables the controller, the
MAX1858A begins the startup sequence. Regulator 1
(OUT1) powers up with soft-start enabled. Once the first
converter’s soft-start sequence ends, regulator 2 (OUT2)
powers up with soft-start enabled. Finally, when both con-
verters complete soft-start and both output voltages
exceed 90% of their nominal values, the reset output
(RST) goes high (see the Reset Output section). Soft-stop
is initiated by pulling EN low. Soft-stop occurs in reverse
order of soft-start, allowing last-on/first-off operation.
to 100mV when ILIM is tied to V . The logic threshold
L
for switchover to this 100mV default value is approxi-
mately V - 0.5V.
L
Adjustable foldback current limit reduces power dissi-
pation during short-circuit conditions (see the Design
Procedure section).
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by LX_ and PGND. The IC
must be mounted close to the low-side MOSFET with
short, direct traces making a Kelvin-sense connection
so that trace resistance does not add to the intended
sense resistance of the low-side MOSFET.
RST
Reset Output (
) (MAX1858A/
MAX1876A Only)
RST is an open-drain output. RST pulls low when either
output falls below 90% of its nominal regulation voltage.
Once both outputs exceed 90% of their nominal regulation
voltages and both soft-start cycles are completed, RST
goes high impedance. To obtain a logic-voltage output,
connect a pullup resistor from RST to the logic supply volt-
age. A 100kΩ resistor works well for most applications. If
unused, leave RST grounded or unconnected.
Undervoltage Lockout and Startup
Clock Synchronization (SYNC, CKO)
SYNC serves two functions: SYNC selects the clock out-
put (CKO) type used to synchronize slave controllers, or it
serves as a clock input so the MAX1858A/MAX1875A/
MAX1876A can be synchronized with an external clock
signal. This allows the MAX1858A/MAX1875A/MAX1876A
to function as either a master or slave. CKO provides a
clock signal synchronized to the MAX1858A/MAX1875A/
MAX1876As’ switching frequency, allowing either in-
IF V drops below 4.2V, the MAX1858A/MAX1875A/
L
MAX1876A assume that the input supply and reference
voltages are too low to make valid decisions and activate
the undervoltage lockout (UVLO) circuitry, which latches
DL and DH low to inhibit switching. RST is also forced
low during UVLO. To reset the latch and be ready for the
next V rise, V must be pulled below 2.5V.
L
L
In addition, to ensure proper startup, the value of the
capacitor at REF to GND must meet the following con-
dition:
phase (SYNC = GND) or 90° out-of-phase (SYNC = V )
L
synchronization of additional DC-DC controllers (Figure 7).
The MAX1858A/MAX1875A/MAX1876A support the fol-
lowing three operating modes:
-4
-1
C
REF
> ((8.29 x 10 ) / V
) - (1.97 x 10 / f
)
+_SLOPE
S_MAX
where V
slew rate.
is the actual input-voltage rise time’s
+_SLOPE
• SYNC = GND: The CKO output frequency equals
REG1’s switching frequency (f
= f ) and the
DH1
CKO
For example, if the switching frequency is set at
600kHz nominal, which is 660kHz (max), and the input-
CKO signal is in phase with REG1’s switching fre-
quency. This provides 2-phase operation when syn-
chronized with a second slave controller.
voltage rise time’s slew rate is 1.6V/mS, then C
REF
is cho-
should be greater than 0.22µF. Make sure C
REF
• SYNC = V : The CKO output frequency equals two
L
sen large enough to cover for worst-case capacitance
tolerances and temperature coefficient.
times REG1’s switching frequency (f
= 2f
)
DH1
CKO
and the CKO signal is phase shifted by 90° with
respect to REG1’s switching frequency. This pro-
vides 4-phase operation when synchronized with a
second MAX1858A/MAX1875A/MAX1876A (slave
controller).
Enable (EN), Soft-Start, and Soft-Stop
Pull EN high to enable or low to shut down both regula-
tors. See the timing diagrams, Figures 3 and 4, for
more detail.
______________________________________________________________________________________ 13
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
• SYNC Driven by External Oscillator: The controller
Design Procedure
generates the clock signal by dividing down the
Effective Input Voltage Range
Although the MAX1858A/MAX1875A/MAX1876A con-
trollers can operate from input supplies ranging from
4.5V to 23V, the input voltage range can be effectively
limited by the MAX1858A/MAX1875A/MAX1876As’
duty-cycle limitations. The maximum input voltage is
SYNC input signal, so that the switching frequency
equals half the synchronization frequency (f
SYNC
=
SW
f
/2). REG1’s conversion cycles initiate on the ris-
ing edge of the internal clock signal. The CKO output
frequency and phase match REG1’s switching fre-
quency (f
= f
) and the CKO signal is in
DH1
CKO
limited by the minimum on-time (t
):
phase. Note that the MAX1858A/MAX1875A/
MAX1876A still require R when SYNC is external-
ON(MIN)
OSC
V
ly clocked and the internal oscillator frequency should
OUT
V
≤
IN(MAX)
be set to 50% of the synchronization frequency (f
SW
t
f
ON(MIN) SW
= 0.5 f
).
SYNC
where t
is 100ns. The minimum input voltage is
ON(MIN)
Thermal Overload Protection
limited by the switching frequency and minimum off-
time, which determine the maximum duty cycle
Thermal overload protection limits total power dissipation
in the MAX1858A/MAX1875A/MAX1876A. When the
(D
= 1 - f
t
):
MAX
SW OFF(MIN)
device’s die-junction temperature exceeds T = +160°C,
J
an on-chip thermal sensor shuts down the device, forcing
DL_ and DH_ low, allowing the IC to cool. The thermal
sensor turns the part on again after the junction tempera-
ture cools by 10°C. During thermal shutdown, the regula-
tors shut down, RST goes low, and soft-start is reset. If
V
1-f
+ V
DROP1
OUT
V
=
+ V
-V
IN(MIN)
DROP2 DROP1
t
SW OFF(MIN)
where V
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances. V is
the sum of the resistances in the charging path, includ-
ing high-side switch, inductor, and PC board resis-
tances.
DROP1
the V linear-regulator output is short circuited, thermal-
L
DROP2
overload protection is triggered.
MAX1858A
MAX1875A
MAX1876A
MAX1858A
MAX1875A
MAX1876A
MAX1858A
MAX1875A
MAX1876A
CK0
SYNC
CK0
SYNC
OSC
OSC
OSC
SYNC
SYNC
V
V
L
L
SLAVE
SLAVE
MASTER
MASTER
3-OUTPUT APPLICATION
4-OUTPUT APPLICATION
180° PHASE SHIFT
90° PHASE SHIFT
DH1
MASTER
DH1
MASTER
DH2
DH2
DH1
DH
SLAVE
SLAVE
DH2
Figure 7. Synchronized Controllers
14 ______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Setting the Output Voltage
For 1V or greater output voltages, set the MAX1858A/
MAX1875A/MAX1876A output voltage by connecting a
OUT_
REF
voltage-divider from the output to FB_ to GND (Figure
8). Select R_B (FB_ to GND resistor) to between 1kΩ
R_A
R_C
and 10kΩ. Calculate R_A (OUT_ to FB_ resistor) with
the following equation:
FB_
FB_
V
V
R_B
OUT
R_A = R_B
-1
R_A
MAX1858A
MAX1875A
MAX1876A
MAX1858A
MAX1875A
MAX1876A
SET
where V
= 1V (see the Electrical Characteristics)
OUT_
SET
and V
can range from V
to 18V.
SET
OUT
V
> 1V
V
< 1V
OUT_
OUT_
For output voltages below 1V, set the MAX1858A/
MAX1875A/MAX1876A output voltage by connecting a
voltage-divider from the output to FB_ to REF (Figure
8). Select R_C (FB to REF resistor) in the 1kΩ to 10kΩ
range. Calculate R_A with the following equation:
Figure 8. Adjustable Output Voltage
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX1858A/MAX1875A/MAX1876A:
inductance value (L), peak-inductor current (I
), and
PEAK
V
V
V
SET- OUT
R_A = R_C
DC resistance (R ). The following equation assumes a
DC
V
REF- SET
constant ratio of inductor peak-to-peak AC current to DC
average current (LIR). For LIR values too high, the RMS
currents are high, and therefore I2R losses are high.
Large inductances must be used to achieve very low LIR
values. Typically, inductance is proportional to resis-
tance (for a given package type), which again makes I2R
losses high for very low LIR values. A good compromise
between size and loss is a 30% peak-to-peak ripple cur-
rent to average-current ratio (LIR = 0.3). The switching
frequency, input voltage, output voltage, and selected
LIR determine the inductor value as follows:
where V
= 1V, V
= 2V (see the Electrical
SET
REF
OUT
Characteristics), and V
can range from 0 to V
.
SET
Setting the Switching Frequency
The controller generates the clock signal by dividing
down the internal oscillator or SYNC input signal when
driven by an external oscillator, so the switching frequen-
cy equals half the oscillator frequency (f
= f /2).
OSC
SW
The internal oscillator frequency is set by a resistor
(R ) connected from OSC to GND. The relationship
OSC
between f
and R
is:
SW
OSC
V
(V -V
)
OUT IN OUT
L =
9
6×10 (Ω -Hz)
V f
I
LIR
IN SW OUT
R
=
OSC
f
SW
where V , V
, and I
are typical values (so that
IN OUT
OUT
efficiency is optimum for typical conditions). The switch-
where f
is in Hz and R
is in Ω. For example, a
OSC
600kHz switching frequency is set with R
Higher frequencies allow designs with lower inductor
values and less output capacitance. Consequently,
peak currents and I R losses are lower at higher
switching frequencies, but core losses, gate-charge
currents, and switching losses increase.
SW
ing frequency is set by R
(see the Setting the
OSC
= 10kΩ.
OSC
Switching Frequency section). The exact inductor value
is not critical and can be adjusted in order to make
trade-offs among size, cost, and efficiency. Lower
inductor values minimize size and cost, but also
improve transient response and reduce efficiency due
to higher peak currents. On the other hand, higher
inductance increases efficiency by reducing the RMS
current. However, resistive losses due to extra wire turns
can exceed the benefit gained from lower AC current
levels, especially when the inductance is increased
without also allowing larger inductor dimensions.
2
A rising clock edge on SYNC is interpreted as a syn-
chronization input. If the SYNC signal is lost, the inter-
nal oscillator takes control of the switching rate,
returning the switching frequency to that set by R
.
OSC
This maintains output regulation even with intermittent
SYNC signals. When an external synchronization signal
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The
is used, R
should set the switching frequency to
OSC
one-half SYNC rate (f
).
SYNC
______________________________________________________________________________________ 15
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
inductor’s saturation rating must exceed the peak-
P
× V
OUT
inductor current at the maximum defined load current
FB
R
=
FBI
-6
(I
):
LOAD(MAX)
5×10 (1-P
)
FB
and
LIR
2
I
= I
+
I
LOAD(MAX)
PEAK
LOAD(MAX)
10× V (1-P )×R
FBI
ITH
FB
R
=
ILIM
V
-10× V (1-P )
[
]
OUT
ITH FB
Setting the Valley Current Limit
The minimum current-limit threshold must be high
enough to support the maximum expected load current
with the worst-case low-side MOSFET on-resistance
value since the low-side MOSFET’s on-resistance is
used as the current-sense element. The inductor’s valley
If R
results in a negative number, select a low-side
ILIM_
MOSFET with lower R
or increase P
or a com-
DS(ON)
FB_
bination of both for the best compromise of cost, effi-
ciency, and lower power dissipation during short circuit.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
current occurs at I
minus half of the ripple
LOAD(MAX)
current. The current-sense threshold voltage (V
)
ITH
should be greater than voltage on the low-side MOSFET
during the ripple-current valley:
requirement (I
as defined by the following equation:
) imposed by the switching currents
RMS
LIR
2
V
>R
×I
× 1-
ITH
DS(ON,MAX) LOAD(MAX)
V
(V -V
)
where R
is the on-resistance of the low-side
OUT IN OUT
DS(ON)
I
=I
RMS LOAD
MOSFET (N ). Use the maximum value for R
L
DS(ON)
V
IN
from the low-side MOSFET’s data sheet, and additional
margin to account for R rise with temperature is
also recommended. A good general rule is to allow
0.5% additional resistance for each °C of the MOSFET
junction temperature rise.
I
has a maximum value when the input voltage equals
RMS
DS(ON)
twice the output voltage (V = 2V
), so I
=
IN
OUT
RMS(MAX)
I
/ 2. For most applications, nontantalum capacitors
LOAD
(ceramic, aluminum, polymer, or OS-CON) are preferred
at the input due to their robustness with high inrush cur-
rents typical of systems that can be powered from very
low impedance sources. Additionally, two (or more)
smaller-value low-ESR capacitors can be connected in
parallel for lower cost. Choose an input capacitor that
exhibits less than +10°C temperature rise at the RMS
input current for optimal long-term reliability.
Connect ILIM_ to VL for the default 100mV (typ) cur-
rent-limit threshold. For an adjustable threshold, con-
nect a resistor (R
_) from ILIM_ to GND. The
ILIM
relationship between the current-limit threshold (V _)
ITH
and R
_ is:
ILIM
V
ITH_
R
=
Output Capacitor
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt-
age, and transient response. The output ripple has two
components: variations in the charge stored in the out-
put capacitor, and the voltage drop across the capaci-
tor’s ESR caused by the current flowing into and out of
the capacitor:
ILIM_
0.5µA
where R
_ is in Ω and V _ is in V.
ILIM
ITH
An R
resistance range of 100kΩ to 600kΩ corre-
ILIM
sponds to a current-limit threshold of 50mV to 300mV.
When adjusting the current limit, 1% tolerance resistors
minimize error in the current-limit threshold.
For foldback current limit, a resistor (R ) is added
from ILIM pin to output. The value of R
can then be calculated as follows:
FBI
ILIM
and R
FBI
V
≅ V
+ V
RIPPLE
RIPPLE(ESR) RIPPLE(C)
First select the percentage of foldback, P , from 15%
FB
to 30%, then:
16 ______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
The output voltage ripple as a consequence of the ESR
and output capacitance is:
To determine the loop gain (A ), consider the gain from
L
FB to COMP (A
), from COMP to LX (A
),
COMP/FB
LX/COMP
). The total loop gain is:
and from LX to FB (A
FB/LX
V
=I
R
RIPPLE(ESR) P-P ESR
A = A
× A
× A
LX/COMP FB/LX
L
COMP/FB
I
P-P
V
=
RIPPLE(C)
8C
f
OUT SW
where:
V
-V
V
OUT
IN OUT
g
V
M _COMP
I
=
COMP
P-P
A
=
≅
×
COMP / FB
f
L
V
SW
IN
V
SC
COMP
FB
1+ sR
1+ sR
C
COMP COMP _A
where I
is the peak-to-peak inductor current (see the
P-P
Inductor Selection section). These equations are suitable
for initial capacitor selection, but final values should be
verified by testing in a prototype or evaluation circuit.
C
COMP COMP _B
assuming an ideal integrator, and assuming that
is much less than C
C
:
COMP_A
COMP_B
As a general rule, a smaller inductor ripple current results
in less output ripple voltage. Since inductor ripple current
depends on the inductor value and input voltage, the out-
put ripple voltage decreases with larger inductance and
increases with higher input voltages. However, the induc-
tor ripple current also impacts transient-response perfor-
V
V
IN
LX
A
=
=
LX/COMP
V
V
COMP
RAMP
where V
= 1V
:
RAMP
P-P
V
mance, especially at low V - V
differentials. Low
OUT
IN
V
1+sR C
ESR OUT
inductor values allow the inductor current to slew faster,
replenishing charge removed from the output filter capac-
itors by a sudden load step. The amount of output-volt-
age sag is also a function of the maximum duty factor,
which can be calculated from the minimum off-time and
switching frequency:
FB
SET
V
OUT
A
=
≅
=
FB/LX
2
V
S LC
+ SR
C
+1
LX
OUT
ESR OUT
V
1+ SR
C
SET
ESR OUT
2
V
V
S LC
+1
OUT
OUT
OUT
Therefore:
g
V
2
OUT
1+ SR
C
V
L(I
-I
)
+ t
OFF(MIN)
M _COMP
COMP COMP _A
IN
LOAD1 LOAD2
A
≅
×
×
V f
L
IN SW
SC
1+ SR
C
V
RAMP
V
=
COMP _A
COMP COMP _B
SAG
V
-V
IN OUT
V
1+ SR C
ESR OUT
2C
V
-t
SET
OUT OUT
OFF(MIN)
×
×
V f
2
IN SW
V
OUT
S LC
+1
OUT
where t
is the minimum off-time (see the
OFF(MIN)
Electrical Characteristics), and f
For an ideal integrator, this loop gain approaches infinity
is set by R
(see
SW
OSC
at DC. In reality the g amplifier has a finite output
M
the Setting the Switching Frequency section).
impedance, which imposes a finite, but large, loop gain.
It is this large loop gain that provides DC load accuracy.
The dominant pole occurs due to the integrator, and for
this analysis, it can be approximated to occur at DC.
Compensation
Each voltage-mode controller section employs a
transconductance error amplifier whose output is the
compensation point of the control loop. The control loop
is shown in Figure 9. For frequencies much lower than
Nyquist, the PWM block can be simplified to a voltage
R
COMP
creates a zero at:
1
f
=
Z _COMP _A
2π × R
C
COMP _ COMP _A
amplifier. Connect R
and C
from COMP
COMP_
COMP_A
to GND to compensate the loop (Figure 9). The inductor,
output capacitor, compensation resistor, and compen-
sation capacitors determine the loop stability. Since the
inductor and output capacitor are chosen based on per-
formance, size, and cost, select the compensation resis-
tor and capacitors to optimize control-loop stability.
The inductor and capacitor form a double pole at:
1
f
=
LC
2π × LC
OUT
______________________________________________________________________________________ 17
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
At some higher frequency, the output capacitor’s
impedance becomes insignificant compared to its ESR,
and the LC system becomes more like an LR system,
turning a double pole into a single pole. This zero
occurs at:
The following loop-gain equation can be found by using
these previous approximations with Figure 9:
g
×R
×R
V
V
SET
M_COMP
COMP ESR
IN
A ≅
×
×
L
V
V
sL
RAMP
OUT
1
Setting the loop gain to 1 and solving for the crossover
frequency yields:
f
=
ESR
2π × R
C
ESR OUT
A final pole is added using C
to reduce the
COMP_B
V
V
SET
IN
f
= GBW =
×
gain and attenuate noise after crossover. This pole
CO
V
V
OUT
RAMP
(f ) occurs at:
COMP_B
g
× R
× R
COMP ESR
M _COMP
×
1
f
=
2π × L
COMP _B
2π × R
C
COMP COMP _B
To ensure stability, select R
criteria:
to meet the following
COMP
Figure 10 shows a Bode plot of the poles and zeros in
their relative locations.
• Unity-gain crossover must occur below 1/5th of the
switching frequency.
Near crossover, the following approximations can be
made to simplify the loop-gain equation:
• For reasonable phase margin using type 1 compen-
✕
sation, f
must be larger than 5
f
.
CO
ESR
• R
has much higher impedance than C
.
COMP
COMP
This is true if, and only if, crossover occurs above
. If this is true, C can be ignored
Choose C
so that f
equals half f
Z_COMP_A LC
COMP_A
using the following equation:
f
Z_COMP_A
(as a short to ground).
COMP_A
2 × LC
OUT
• R is much higher impedance than C
. This is
OUT
ESR
C
=
COMP _A
true if, and only if, crossover occurs well after the out-
put capacitor’s ESR zero. If this is true, C
R
COMP
OUT
becomes an insignificant part of the loop gain and can
be ignored (as a short to ground).
Choose C
CO
so that f
occurs at 3 times
COMP_B
COMP_B
using the following equation:
f
• C
is much higher impedance than R
COMP
COMP_B
1
C
=
and can be ignored (as an open circuit). This is true
COMP _B
2π × 3 × f
× R
COMP
if, and only if, crossover occurs far below f
.
COMP_B
CO
GAIN = +V /V
IN RAMP
DH
P
N
L
L
V
OUT
W
LX
N
LX
V
DL
FB
C
M
R
ESR
R
ESR
=
FB
C
C
OUT
OUT
COMP_
g
M_COMP
COMP_
g
M_COMP
V
R
SET
COMP_
V
R
SET
COMP_
C
COMP_A
C
COMP_B
C
COMP_A
C
COMP_B
Figure 9. Fixed-Frequency Voltage-Mode Control Loop
18 ______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
MOSFET Selection
The MAX1858A/MAX1875A/MAX1876As’ step-down
controller drives two external logic-level N-channel
MOSFETs as the circuit switch elements. The key
selection parameters are:
BODE PLOT FOR VOLTAGE-
MODE CONTROLLERS
50
40
30
20
10
0
f
LC
• On-resistance (R
)
DS(ON)
f
ESR
• Maximum drain-to-source voltage (V
)
DS(MAX)
f
Z-COMP_A
f
f
SWITCH
CO
• Minimum threshold voltage (V
)
TH(MIN)
• Total gate charge (Q )
g
-10
-20
-30
-40
• Reverse transfer capacitance (C
• Power dissipation
)
RSS
f
COMP_B
0.1
All four N-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V
4.5V. For maximum efficiency, choose a high-side
MOSFET (N _) that has conduction losses equal to the
H
≥
GS
0.001
0.01
1
FREQUENCY (MHz)
switching losses at the optimum input voltage. Check to
ensure that the conduction losses at minimum input
voltage do not exceed MOSFET package thermal limits,
or violate the overall thermal budget. Also, check to
ensure that the conduction losses plus switching losses
at the maximum input voltage do not exceed package
ratings or violate the overall thermal budget.
Figure 10. Voltage-Mode Loop Analysis
Q
+Q
GD
GS
I
P
= V I
f
NH(SWITCHING)
INLOAD SW
GATE
Ensure that the MAX1858A/MAX1875A/MAX1876A DL_
I
is the average DH driver-output current capability
GATE
determined by:
gate drivers can drive N _. In particular, check that the
L
dv/dt caused by N _ turning on does not pull up the N _
H
L
gate through N _’s drain-to-gate capacitance. This is the
L
V
L
I
=
most frequent cause of cross-conduction problems.
GATE
2 R
+R
+R
DS(ON)DH
GATE GMOSFET
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. All MOSFETs must be selected
so that their total gate charge is low enough that V can
L
power all four drivers without overheating the IC:
where R
is the high-side MOSFET driver’s on-
DS(ON)DH
resistance (5Ω max), R
is any series resistance
GATE
between DH and BST (Figure 5), and R
is the
GMOSFET
internal gate resistance of the external MOSFET:
P
= V × Q × f
G _ TOTAL SW
VL
IN
MOSFET package power dissipation often becomes a
dominant design factor. I2R power losses are the great-
est heat contributor for both high-side and low-side
V
V
2
OUT
P
=I
R
NH(CONDUCTION) LOAD DS(ON)NH
IN
MOSFETs. I2R losses are distributed between N _ and
P
=P
+P
H
NH(TOTAL)
NH(SWITCHING) NH(CONDUCTION)
N _ according to duty factor as shown in the equations
L
V
2
OUT
below. Switching losses affect only the high-side
MOSFET, since the low-side MOSFET is a zero-voltage
switched device when used in the buck topology.
P
=I
R
1-
NL LOAD DS(ON)NL
V
IN
where P
is the conduction power loss
NH(CONDUCTION)
in the high-side MOSFET, and P is the total low-side
Calculate MOSFET temperature rise according to pack-
age thermal-resistance specifications to ensure that
both MOSFETs are within their maximum junction tem-
perature at high ambient temperature. The worst-case
NL
power loss.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DL_ and DH_ to increase the MOSFETs’ turn-on
and turn-off times.
dissipation for the high-side MOSFET (P ) occurs at
NH
both extremes of input voltage, and the worst-case dis-
sipation for the low-side MOSFET (P ) occurs at maxi-
NL
mum input voltage.
______________________________________________________________________________________ 19
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Dropout design example:
Applications Information
V
OUT
= 5V
Dropout Performance
When working with low input voltages, the output-volt-
age adjustable range for continuous-conduction opera-
f
t
= 600kHz
SW
OFF(MIN)
= 250ns
= V
tion is restricted by the minimum off-time (t
).
OFF(MIN)
V
= 100mV
DROP2
DROP1
For best dropout performance, use the lowest (100kHz)
switching-frequency setting. Manufacturing tolerances
and internal propagation delays introduce an error to
the switching frequency and minimum off-time specifi-
cations. This error is more significant at higher frequen-
cies. Also, keep in mind that transient response
performance of buck regulators operated close to
dropout is poor, and bulk output capacitance must
h = 1.5
5V +100mV
V
=
IN(MIN)
1-1.5(600kHz)(250ns)
+100mV −100mV = 6.58V
Calculating again with h = 1 gives the absolute limit of
dropout:
often be added (see the V
equation in the Design
SAG
Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
5V +100mV
1-(600kHz)(250ns)
V
=
)
IN(MIN)
DOWN
as much as it ramps up during the maximum on-time
(∆I ). The ratio h = ∆I /∆I is an indicator of the
+100mV −100mV = 6V
UP
UP DOWN
ability to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
Therefore, V must be greater than 6V, even with very
IN
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 6.58V.
each switching cycle and V
greatly increases
SAG
Improving Noise Immunity
Applications where the MAX1858A/MAX1875A/
MAX1876A must operate in noisy environments can
typically adjust their controller’s compensation to
improve the system’s noise immunity. In particular,
high-frequency noise coupled into the feedback loop
causes jittery duty cycles. One solution is to lower the
crossover frequency (see the Compensation section).
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between V
, output
SAG
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
V
1-hf
+ V
DROP1
OUT
V
=
+ V
-V
IN(MIN)
DROP2 DROP1
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switch-
ing losses and clean, stable operation. This is especially
true for dual converters where one channel can affect
the other. Refer to the MAX1858 EV kit or MAX1875 EV
kit data sheet for specific layout examples.
t
SW OFF(MIN)
where V
is the sum of the parasitic voltage drops
DROP1
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V is
DROP2
the sum of the resistances in the charging path, includ-
ing high-side switch, inductor, and PC board resis-
If possible, mount all the power components on the top
side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
tances; and t
is from the Electrical
OFF(MIN)
Characteristics. The absolute minimum input voltage is
calculated with h = 1.
• Isolate the power components on the top side from
the analog components on the bottom side with a
ground shield. Use a separate PGND plane under
the OUT1 and OUT2 sides (referred to as PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run the
power plane ground currents on the top side only.
If the calculated V+
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
is greater than the required
(MIN)
able V
calculate V
response.
. If operation near dropout is anticipated,
SAG
SAG
to be sure of adequate transient
20 ______________________________________________________________________________________
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
• Use a star-ground connection on the power plane to
• Make all pin-strap control input connections (ILIM_,
SYNC, and EN) to analog ground (GND) rather than
power ground (PGND).
minimize the crosstalk between OUT1 and OUT2.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
Layout Procedure
1) Place the power components first, with ground termi-
• Connect GND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
step 4 of the Layout Procedure section.
nals adjacent (N _ source, C _, and C
_). Make
OUT
L
IN
all these connections on the top layer with wide, cop-
per-filled areas (2oz copper recommended).
2) Mount the controller IC adjacent to the synchronous-
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz vs. 1oz) to enhance
full-load efficiency by 1% or more.
rectifier MOSFETs (N _), preferably on the back
L
side in order to keep LX_, PGND_, and DL_ traces
short and wide. The DL_ gate trace must be short
and wide, measuring 50mils to 100mils wide if the
low-side MOSFET is 1in from the controller IC.
• LX_ and PGND connections to the synchronous rec-
tifiers for current limiting must be made using Kelvin-
sense connections to guarantee the current-limit
accuracy. With 8-pin SO MOSFETs, this is best done
by routing power to the MOSFETs from outside
using the top copper layer, while connecting PGND
and LX_ underneath the 8-pin SO package.
3) Group the gate-drive components (BST_ diodes and
capacitors, and V bypass capacitor) together near
L
the controller IC.
4) Make the DC-DC controller ground connections as
follows: create a small analog ground plane near the
IC. Connect this plane to GND and use this plane for
the ground connection for the reference (REF) V+
bypass capacitor, compensation components, feed-
back dividers, OSC resistor, and ILIM_ resistors (if
any). Connect GND and PGND together under the
IC (this is the only connection between GND and
PGND).
• When trade-offs in trace lengths must be made,
allow the inductor-charging path to be made longer
than the discharge path. Since the average input
current is lower than the average output current in
step-down converters, this minimizes the power dis-
sipation and voltage drops caused by board resis-
tance. For example, allow some extra distance
between the input capacitors and the high-side
MOSFET rather than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
5) On the board’s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
Chip Information
TRANSISTOR COUNT: 6688
• Ensure that the feedback connection to C
is
OUT_
short and direct.
PROCESS: BiCMOS
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from the sensitive analog areas
(REF, COMP_, ILIM_, and FB_). Use PGND1 and
PGND2 as EMI shields to keep radiated noise away
from the IC, feedback dividers, and analog bypass
capacitors.
______________________________________________________________________________________ 21
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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