MAX1889 [MAXIM]
Triple-Output TFT LCD Power Supply with Fault Protection; 三输出TFT LCD电源，带有故障保护
| 型号： | MAX1889 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Triple-Output TFT LCD Power Supply with Fault Protection |
| 文件： | 总32页 (文件大小：793K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2485; Rev 1; 10/02
Triple-Output TFT LCD Power Supply
with Fault Protection
General Description
Features
The MAX1889 provides the three regulated output volt-
ages required for active matrix, thin-film transistor liquid
crystal displays (TFT LCDs). It combines a high-perfor-
mance step-up regulator with two linear-regulator con-
trollers and multiple levels of protection circuitry for a
complete power-supply system.
o High-Performance Step-Up Regulator
Fast Transient Response
Current-Mode Control Architecture
Built-In High-Efficiency N-Channel Power
MOSFET
Current-Limit Comparator
>85% Efficiency
Selectable Switching Frequency
(500kHz/1MHz)
Internal Soft-Start
The main DC-DC converter is a high-frequency
(500kHz/1MHz), current-mode step-up regulator with
an integrated N-channel power MOSFET that allows the
use of ultra-small inductors and ceramic capacitors.
With its high closed-loop bandwidth performance, the
MAX1889 provides fast transient response to pulsed
loads while operating with efficiencies over 85%. The
positive and negative linear-regulator controllers post-
regulate charge-pump outputs for TFT gate-on and
gate-off supplies.
o Positive Linear-Regulator Controller
o Negative Linear-Regulator Controller
o Triple-Level Protection Against Smoke or Fire
Input Switch Replaces Input Fuse
Output Overload Detection with Timer Latch
Thermal Shutdown
The MAX1889 has a unique input switch control that
can replace the typical input fuse by disconnecting the
load from the input supply when a fault is detected.
The fault detector monitors all three regulated output
voltages and can monitor current from the input supply
as well. Additionally, the MAX1889 enters thermal shut-
down when its overtemperature threshold is reached.
o 2.7V to 5.5V Input Operating Range
o Ultra-Small External Components
o 1µA Shutdown Current (max)
o 1mA Quiescent Current (max)
o Ultra-Thin 16-Pin QFN Package
(0.8mm Maximum Thickness)
The MAX1889 undervoltage lockout is set at 2.5V (max)
to allow the input supply to droop under pulsed load
conditions while avoiding any unexpected behavior
when its input voltage dips momentarily. Also, the built-
in soft-start and cycle-by-cycle current limiting prevent
input surge currents during power-up.
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX1889ETE
-40°C to +85°C 16 Thin QFN (5mm ✕ 5mm)
MAX1889EGE* -40°C to +85°C 16 QFN (5mm ✕ 5mm)
* Future product—Contact factory for availability.
The MAX1889 is available in a 16-pin thin QFN pack-
age with a maximum thickness of 0.8mm for ultra-thin
LCD panel design.
Pin Configuration
Applications
Notebook Computer Displays
TOP VIEW
LCD Monitors
16
15
14
13
Car Navigation Displays
SHDN
PGND
GND
TGND
LX
1
2
3
4
12
11
10
9
MAX1889
FREQ
FBP
REF
5
6
7
8
THIN QFN
(5mm x 5mm)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Triple-Output TFT LCD Power Supply
with Fault Protection
ABSOLUTE MAXIMUM RATINGS
IN, SHDN, OCN, OCP,
FB, FBP, FBN, FREQ to GND ...............................-0.3V to +6V
PGND to GND..................................................................... 0.3V
LX to PGND ............................................................-0.3V to +14V
DRVP to GND .........................................................-0.3V to +30V
Continuous Power Dissipation (T = +70°C)
16-Pin QFN (derate 19.2mW/°C above +70°C) .........1538mW
Operating Temperature Range
MAX1889EGE..................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
A
REF, GATE, TGND to GND..........................-0.3V to (V + 0.3V)
IN
IN
DRVN to GND .....................................(V - 28V) to (V + 0.3V)
IN
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 3V, SHDN = IN, C
= 0.22µF, PGND = GND, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
IN
REF
A
A
PARAMETER
IN Supply Range
SYMBOL
CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNITS
V
V
IN
V
V
rising
falling
2.55
2.2
2.7
2.85
2.5
IN
IN
IN Undervoltage Lockout
(UVLO) Threshold
350mV typical
hysteresis
V
V
UVLO
2.35
IN Quiescent Current
IN Shutdown Current
I
V
V
= V
= 1.5V, V = 0V (Note 1)
FBN
1.0
mA
µA
V
IN
FB
FBP
= 0, V = 5V
0.1
1.250
160
1.0
SHDN
IN
REF Output Voltage
V
-2µA < I
< 50µA
1.231
1.269
REF
REF
Thermal Shutdown
°C
MAIN STEP-UP REGULATOR
Main Output Voltage Range
V
f
V
13
V
MHz
kHz
%
MAIN
OSC
IN
V
V
= V
0.85
1
500
85
1.15
FREQ
FREQ
IN
Operating Frequency
= 0V
Oscillator Maximum Duty Cycle
FB Regulation Voltage
FB Fault Trip Level
80
90
V
I
= 200mA, slope = 0 (Note 2)
LX
1.229
0.95
1.242
1.0
1.254
1.05
V
FB
V
falling
V
FB
Load Regulation
I
= 0 to full load
= 2.7V to 5.5V
= 1.5V
-1.6
0.2
%
MAIN
Line Regulation
V
V
%/V
nA
mΩ
µA
A
IN
FB Input Bias Current
LX Switch On-Resistance
LX Leakage Current
LX Current Limit
I
-100
1.6
+100
450
20
FB
FB
R
250
0.01
2.1
LX(ON)
I
V
= 13V
LX
LX
I
2.8
LIM
LX RMS Current Rating
Not tested
1.4
A
4096 /
Soft-Start Period
t
s
SS
f
OSC
Soft-Start Step Size
V
/32
V
REF
POSITIVE LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage
FBP Fault Trip Level
V
I
= 0.2mA
falling
1.213
0.96
-50
1.25
1.0
1.288
1.04
+50
V
V
FBP
DRVP
V
V
V
FBP
FBP Input Bias Current
FBP Effective Transconductance
I
= 1.25V
nA
mS
FBP
FBP
= 10V, I
= 0.1mA to 2mA
75
DRVP
DRVP
2
_______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
ELECTRICAL CHARACTERISTICS (continued)
(V = 3V, SHDN = IN, C
= 0.22µF, PGND = GND, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
IN
REF
A
A
PARAMETER
FBP Line Regulation
Bandwidth
SYMBOL
CONDITIONS
= 0.2mA, V = 2.7V to 5.5V
MIN
TYP
MAX
UNITS
mV
I
1
DRVP
IN
(Note 3)
200
5
kHz
mA
DRVP Sink Current
DRVP Off-Leakage Current
I
V
V
= 1.1V, V
= 10V
= 28V
DRVP
FBP
FBP
DRVP
DRVP
= 1.1V, V
0.1
10
µA
NEGATIVE LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage
FBN Fault Trip Level
FBN Input Bias Current
FBN Effective Transconductance
FBN Line Regulation
Bandwidth
V
I
= 0.2mA
rising
95
325
-50
75
125
400
155
475
+50
mV
mV
nA
FBN
DRVN
V
V
V
FBN
FBN
I
= 0V
FBN
= -10V, I
= 0.1mA to 2mA
DRVN
mS
mV
kHz
mA
µA
DRVN
DRVN
I
= 0.2mA, V = 2.7V to 5.5V
1
IN
(Note 2)
200
5
DRVN Sink Current
I
I
V
V
= 200mV, V
= -10V
DRVN
FBN
FBP
DRVN
DRVN Off-Leakage Current
LOGIC SIGNAL (SHDN)
Input Low Voltage
= -0.1V, V
= -20V
0.1
10
0.4
1
DRVN
100mV typical hysteresis, V = 2.7V to 5.5V
V
V
IN
Input High Voltage
V
= 2.7V to 5.5V
1.6
IN
Input Current
0.01
0.01
µA
SHDN
LOGIC SIGNAL (FREQ)
0.3 x
Input Low Voltage
Input High Voltage
0.15 x V typical hysteresis
V
IN
V
IN
0.7 x
V
V
IN
Input Current
I
I
1
µA
FREQ
OVERCURRENT COMPARATOR
Input Offset Voltage
-5
+5
mV
nA
,
OCN
Input Bias Current
V
= V
= V
IN
-50
1.5
+50
OCN
OCP
I
OCP
OCN, OCP Input
Common-Mode Range
0.8 x
V
IN
V
FAULT TIMER AND GATE DRIVER
V
V
= 0V, 32768/f
64
64
FREQ
FREQ
OSC
Fault Timer Period
t
ms
µA
FAULT
= V , 65536/f
IN
OSC
GATE Output Sink Current
During Slew
I
V
V
= 1.5V, during turn-on transition
< 0.5V
6
12
18
GATE
GATE
GATE
GATE Output
Pulldown Resistance
200
200
Ω
Ω
GATE Output Pullup Resistance
_______________________________________________________________________________________
3
Triple-Output TFT LCD Power Supply
with Fault Protection
ELECTRICAL CHARACTERISTICS
(V = 3V, SHDN = IN, C
= 0.22µF, PGND = GND, T = -40°C to +85°C.) (Note 4)
A
IN
REF
PARAMETER
SYMBOL
CONDITIONS
MIN
2.7
MAX
5.5
UNITS
IN Supply Range
V
V
IN
V
V
V
V
rising
falling
2.55
2.2
2.85
2.5
IN
IN
FB
IN ULVO Threshold
V
V
UVLO
IN Quiescent Current
IN Shutdown Current
REF Output Voltage
I
= V
= 1.5V, V = 0V (Note 1)
FBN
1.0
mA
µA
V
IN
FBP
= 0, V = 5V
1.0
SHDN
IN
V
-2µA < I
< 50µA
1.231
1.269
REF
REF
MAIN STEP-UP REGULATOR
Main Output Voltage Range
Operating Frequency
Oscillator Maximum Duty Cycle
FB Regulation Voltage
FB Fault Trip Level
V
f
V
13
1.25
92
V
MHz
%
MAIN
IN
V
= V
0.75
78
OSC
FREQ
IN
V
I
= 200mA, slope = 0 (Note 2)
LX
1.215
0.96
1.260
1.04
0.45
+100
450
V
FB
V
V
V
falling
V
FB
IN
Line Regulation
= 2.7V to 5.5V
= 1.5V
%/V
nA
mΩ
A
FB Input Bias Current
LX Switch On-Resistance
LX Current Limit
I
-100
1.6
FB
FB
R
LX(ON)
I
2.8
LIM
POSITIVE LINEAR-REGULATOR CONTROLLER
FBP Regulation Voltage
FBP Fault Trip Level
FBP Input Bias Current
FBP Effective Transconductance
Bandwidth
V
I
= 0.2mA
falling
1.213
0.96
-50
60
1.288
1.04
+50
V
V
FBP
FBP
DRVP
V
V
V
FBP
I
= 1.25V
nA
mS
kHz
mA
FBP
= 10V, I
= 0.1mA to 2mA
= 10V
DRVP
DRVP
(Note 2)
= 1.1V, V
200
5
DRVP Sink Current
I
V
FBP
DRVP
DRVP
NEGATIVE LINEAR-REGULATOR CONTROLLER
FBN Regulation Voltage
FBN Fault Trip Level
FBN Input Bias Current
FBN Effective Transconductance
Bandwidth
V
I
= 0.2mA
rising
95
325
-50
60
155
475
+50
mV
mV
nA
FBN
DRVN
V
V
V
FBN
I
= 0V
FBN
FBN
= -10V, I
= 0.1mA to 2mA
DRVN
mS
kHz
mA
DRVN
(Note 2)
= 200mV, V
200
5
DRVN Sink Current
LOGIC SIGNAL (SHDN)
Input Low Voltage
I
I
V
= -10V
DRVN
DRVN
FBN
100mV typical hysteresis
0.4
1
V
V
Input High Voltage
Input Current
1.6
µA
SHDN
4
_______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
ELECTRICAL CHARACTERISTICS (continued)
(V = 3V, SHDN = IN, C
= 0.22µF, PGND = GND, T = -40°C to +85°C.) (Note 4)
A
IN
REF
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC SIGNAL (FREQ)
Input Low Voltage
0.15 x V typical hysteresis
0.3 x V
1
V
V
IN
IN
Input High Voltage
0.7 x V
IN
Input Current
I
I
µA
FREQ
OVERCURRENT COMPARATOR
Input Offset Voltage
-5
+5
mV
nA
,
OCN
Input Bias Current
V
= V
= V
IN
-50
+50
OCN
OCP
I
OCP
OCN, OCP Input
Common-Mode Range
0.8 x
V
IN
1.5
V
FAULT TIMER AND GATE DRIVER
GATE Output Sink Current
I
V
V
= 1.5V, during turn-on transition
< 0.5V
6
18
µA
Ω
GATE
GATE
GATE
GATE Output
Pulldown Resistance
200
200
GATE Output Pullup Resistance
Ω
Note 1: Quiescent current does not include switching losses.
Note 2: FB regulation voltage is tested with no slope compensation ramp. Slope compensation needs to be included when selecting
resisitors for setting the output voltage (see Main Step-Up Regulator and Output Voltage Selection sections).
Note 3: Guaranteed by design. Not production tested.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
Typical Operating Characteristics
(Circuit of Figure 1, V = +3.3V, V
IN
= +9V, V = +20V, V = -7V, SHDN = FREQ = IN, PGND = GND, T = +25°C, unless
MAIN
PL
NL
A
otherwise noted.)
STEP-UP REGULATOR EFFICENCY
STEP-UP REGULATOR OUTPUT VOLTAGE
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT (V
= 9V)
vs. LOAD CURRENT (V
= 13V)
vs. LOAD CURRENT (V
= 9V)
MAIN
MAIN
MAIN
100
90
100
9.1
9.0
8.9
8.8
8.7
8.6
8.5
90
80
70
60
50
80
V
= 2.7V
IN
A
B
V
IN
= 3.3V
C
A
B
70
C
V
IN
= 5.5V
60
A: V = 2.7V
IN
A: V = 2.7V
IN
B: V = 3.3V
B: V = 3.3V
IN
IN
C: V = 5.5V
IN
C: V = 5.5V
IN
50
100
1
10
1000
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
_______________________________________________________________________________________
5
Triple-Output TFT LCD Power Supply
with Fault Protection
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, V
IN
= +9V, V = +20V, V = -7V, SHDN = FREQ = IN, PGND = GND, T = +25°C, unless
MAIN
PL
NL
A
otherwise noted.)
STEP-UP REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT (V = 13V)
STEP-UP REGULATOR LOAD-TRANSIENT
STEP-UP REGULATOR SWITCHING
FREQUENCY vs. INPUT VOLTAGE
RESPONSE (0 TO 200mA)
MAIN
MAX1889 toc06
13.1
13.0
12.9
12.8
12.7
12.6
12.5
1100
1A
1000
900
800
700
600
500
A
500mA
0
V
= 2.7V
IN
V
= 3.3V
IN
V
V
= 3.3V
IN
9V
= 9V
MAIN
MAIN
B
I
= 200mA
8.9V
200mA
0
V
IN
= 5.5V
C
1
10
100
1000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
10µs/div
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
A: INDUCTOR CURRENT, 500mA/div
B: V
= 9V, 100mV/div, AC-COUPLED
= 0 TO 200mA, 200mA/div
MAIN
MAIN
C: I
STEP-UP REGULATOR SOFT-START
(10mA LOAD) FROM
STEP-UP REGULATOR SOFT-START
(200mA LOAD) FROM
STEP-UP REGULATOR LOAD-TRANSIENT
SLOW-RISING INPUT SUPPLY
RESPONSE (0 TO 1A, 2µs PULSE)
SLOW-RISING INPUT SUPPLY
MAX1889 toc08
MAX1889 toc07
MAX1889 toc09
5V
2A
1A
5V
0
A
A
0
A
5V
0
0
5V
0
B
B
5V
5V
9V
C
C
B
0
8.9V
8.8V
0
10V
10V
5V
0
1A
0
5V
0
C
D
D
1ms/div
10µs/div
1ms/div
A: V , 5V/div
GATE
A: INDUCTOR CURRENT, 1A/div
IN
B: V
A: V , 5V/div
IN
GATE
, 5V/div
B: V
= 9V, 100mV/div, AC-COUPLED
= 0 TO 1A, 1A/div
B: V
, 5V/div
MAIN
MAIN
C: V , 5V/div
C: I
C2
C: V , 5V/div
C2
D: V
= 9V, 5V/div
MAIN
D: V
= 9V, 5V/div
MAIN
6
_______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, V
IN
= +9V, V = +20V, V = -7V, SHDN = FREQ = IN, PGND = GND, T = +25°C, unless
MAIN
PL
NL
A
otherwise noted.)
POWER-UP SEQUENCE FROM
STEP-UP REGULATOR SOFT-START
STEP-UP REGULATOR SOFT-START
SLOW-RISING INPUT SUPPLY
(200mA LOAD) USING SHDN CONTROL
(10mA LOAD) USING SHDN CONTROL
MAX1889 toc10
MAX1889 toc12
MAX1889 toc11
5V
0
5V
0
5V
0
A
A
A
B
5V
0
5V
0
5V
0
B
B
20V
5V
5V
C
C
C
10V
0
0
0
10V
10V
0
5V
0
5V
0
D
D
D
-10V
2ms/div
1ms/div
1ms/div
A: V , 5V/div
IN
MAIN
A: V
B: V
, 5V/div
SHDN
GATE
A: V
, 5V/div
SHDN
B: V
= 9V, 5V/div
, 5V/div
B: V
, 5V/div
GATE
C: V = 20V, 10V/div
C: V , 5V/div
C: V , 5V/div
D: V
PL
C2
MAIN
C2
MAIN
D: V = -7V, 10V/div
NL
D: V
= 9V, 5V/div
= 9V, 5V/div
POWER-UP SEQUENCE
USING SHDN CONTROL
STEP-UP REGULATOR NORMAL OPERATION
POSITIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. LOAD CURRENT
(200mA LOAD)
MAX1889 toc13
MAX1889 toc14
5V
0
26.2
A
B
10V
26.0
25.8
25.6
25.4
25.2
25.0
5V
0
A
5V
0
20V
9.05V
B
C
D
10V
0
9V
1A
C
0
500mA
0
V
MAIN
= 3.3V
IN
I
= 200mA
-10V
2ms/div
1
1µs/div
= 9V, 50mV/div, AC-COUPLED
0.1
10
LOAD CURRENT (mA)
A: V
B: V
, 5V/div
A: V , 5V/div
MAIN
C: INDUCTOR CURRENT, 500mA/div
SHDN
MAIN
PL
LX
= 9V, 5V/div
B: V
C: V = 20V, 10V/div
D: V = -7V, 10V/div
NL
_______________________________________________________________________________________
7
Triple-Output TFT LCD Power Supply
with Fault Protection
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, V
IN
= +9V, V = +20V, V = -7V, SHDN = FREQ = IN, PGND = GND, T = +25°C, unless
MAIN
PL
NL
A
otherwise noted.)
POSITIVE CHARGE-PUMP INCREMENTAL
EFFICIENCY vs. LOAD CURRENT
NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. LOAD CURRENT
NEGATIVE CHARGE-PUMP INCREMENTAL
EFFICIENCY vs. LOAD CURRENT
100
-8.2
100
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
-8.3
-8.4
-8.5
-8.6
EFF = (V
IN(LOAD)
✕ I ) /
OUT OUT
EFF = (V
(P
✕ I ) /
OUT
IN(NOLOAD)
V
I
= 3.3V
MAIN
OUT
IN
(P
- P
)
- P
)
= 200mA
IN(NOLOAD)
IN(LOAD)
-8.7
0.1
1
10
0.1
1
10
0.1
1
10
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
NEGATIVE LINEAR-REGULATOR
LOAD REGULATION
POSITIVE LINEAR-REGULATOR
LOAD REGULATION
POSITIVE LINEAR-REGULATOR
LOAD-TRANSIENT RESPONSE
MAX1889 toc20
0
0
-0.08
-0.16
-0.24
-0.32
-0.40
-0.03
-0.06
-0.09
-0.12
-0.15
A
20V
19.95V
10mA
0
B
2ms/div
A: V = 20V, 50mV/div, AC-COUPLED
0.1
1
10
0.1
1
10
LOAD CURRENT (mA)
LOAD CURRENT (mA)
PL
B: I = 0 TO 10mA, 10mA/div
PL
8
_______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = +3.3V, V
IN
= +9V, V = +20V, V = -7V, SHDN = FREQ = IN, PGND = GND, T = +25°C, unless
MAIN
PL
NL
A
otherwise noted.)
OVERCURRENT PROTECTION RESPONSE
NEGATIVE LINEAR-REGULATOR
OVERCURRENT PROTECTION RESPONSE
TO OVERLOAD DURING STARTUP
LOAD-TRANSIENT RESPONSE
TO OVERLOAD DURING NORMAL OPERATION
MAX1889 toc23
MAX1889 toc22
MAX1889 toc24
5V
0
5V
A
B
A
B
0
5V
0
-6.95V
-7V
5V
A
0
20V
C
D
10V
0
10V
0
C
D
0
B
0
0
-10mA
-10V
-10V
20ms/div
400µs/div
20ms/div
= 9V, 5V/div; I = 200mA TO 1.5A
A: V
B: V
, 5V/div
A: V = -7V, 50mV/div, AC-COUPLED
NL
B: I = 0 TO -10mA, 10mA/div
A: V
B: V
, 5V/div
GATE
MAIN
PL
GATE
MAIN
PL
, 5V/div; I
= 1.5A
MAIN
NL
MAIN
C: V , 10V/div; I = 10mA
D: V , 10V/div; I = 10mA
C: V = 20V, 10V/div; I = 10mA
PL
NL
PL
D: V = -7V, 10V/div; I = 10mA
NL
NL
NL
REFERENCE VOLTAGE vs. LOAD CURRENT
LX CURRENT LIMIT vs. INPUT VOLTAGE
1.250
1.249
1.248
1.247
1.246
1.245
2.4
2.3
2.2
2.1
2.0
0
10 20 30 40 50 60 70 80 90 100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
LOAD CURRENT (µA)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
Triple-Output TFT LCD Power Supply
with Fault Protection
Pin Description
PIN
NAME
FUNCTION
Active-Low Shutdown Control Input. Pull SHDN below the 0.4V logic-low level to turn off all sections
of the device and pull the GATE pin high. Pull SHDN above the 1.6V logic-high level to enable the
device. Do not leave SHDN floating.
1
SHDN
Power Ground. PGND is the source of the N-channel power MOSFET. Connect PGND to the analog
ground (GND) at the device’s pins.
2
3
4
PGND
GND
REF
Analog Ground. Connect GND to the power ground (PGND) at the device’s pins.
Internal Reference Bypass Terminal. Connect a 0.22µF ceramic capacitor from REF to the analog
ground (GND). External load capability is at least 50µA.
Main Step-Up Regulator Feedback Input. FB regulates to 1.25V nominal. Connect FB to the center of
5
6
FB
a resistive voltage-divider between the main output (V
main step-up regulator output voltage. Place the resistive voltage-divider close to the pin.
) and the analog ground (GND) to set the
MAIN
Negative Linear-Regulator Feedback Input. FBN regulates to 125mV nominal. Connect FBN to the
center of a resistive voltage-divider between the negative output (V
FBN
) and the REF to set the
NEG
negative linear-regulator output voltage. Place the resistive voltage-divider close to the pin.
Negative Linear-Regulator Base Drive. Open drain of an internal P-channel MOSFET. Connect DRVN
to the base of the external linear-regulator NPN pass transistor (see Pass Transistor Selection
section).
7
8
DRVN
DRVP
Positive Linear-Regulator Base Drive. Open drain of an internal N-channel MOSFET. Connect DRVP
to the base of the external linear-regulator PNP pass transistor (see Pass Transistor Selection
section).
Positive Linear-Regulator Feedback Input. FBP regulates to 1.25V nominal. Connect FBP to the
center of a resistive voltage-divider between the positive output (V
) and the analog ground (GND)
POS
9
FBP
to set the positive linear-regulator output voltage. Place the resistive voltage-divider close to the pin.
Frequency Select Input. Pull FREQ above logic-high level (0.7 × V ) to set the frequency to 1MHz
IN
and pull FREQ below logic-low level (0.3 × V ) to set the frequency to 500kHz. Do not leave FREQ
10
FREQ
IN
floating.
11
12
LX
Switching Node. Drain of the internal N-channel power MOSFET for the main step-up regulator.
Internal connection. Connect this pin to ground.
TGND
Overcurrent Comparator Inverting Input. OCN connects to the center tap of a resistive voltage-
divider connected to the drain of the input protection P-channel MOSFET (see the Input Overcurrent
Protection section). If unused, connect OCN to REF.
13
OCN
Overcurrent Comparator Noninverting Input. OCP is connected to the center tap of a resistive
voltage-divider that sets the input overcurrent threshold (see the Input Overcurrent Protection
section). If unused, connect OCP to GND.
14
15
16
OCP
GATE
IN
Gate Driver Output to the External P-Channel MOSFET (see the Input Overcurrent Protection section).
If unused, leave GATE open.
Supply Input. The supply voltage powers all the control circuitry. The input voltage range is from 2.7V
to 5.5V. Bypass with a 0.1µF ceramic capacitor between IN and GND, as close to the pins as
possible.
10 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
V
MAIN
9V
LX
V
L1
4.7µH
IN
2.7V TO 5.5V
D1
P1
C2
3.3µF
6.3V
C3
3.3µF
6.3V
C4
4.7µF
10V
C5
4.7µF
10V
C6
4.7µF
10V
R15
R16
150kΩ
1%
43.2kΩ
R2
51.1kΩ
1%
1%
R17
1MΩ
13
OCN
11
LX
R1
10Ω
C22
1000pF
C23
100pF
R6
75kΩ
1%
C16
0.01µF
C1
0.47µF
15
5
GATE
FB
R7
R18
12.1kΩ
10kΩ
14
16
1%
OCP
IN
C17
220pF
R3
150kΩ
1%
12
4
TGND
REF
R5
R4
1MΩ
1MΩ
1
REF
SHDN
FREQ
C7
0.22µF
10
MAX1889
3
2
GND
LX
LX
PGND
C8
0.1µF
C11
0.1µF
C12
0.1µF
R8
3kΩ
D3
D4
R11
3kΩ
D2
C20
470pF
C24
2200pF
C9
0.15µF
C13
0.15µF
C14
0.1µF
R19
15kΩ
R20
51kΩ
7
6
8
9
Q1
DRVN
FBN
DRVP
FBP
Q2
R9
150kΩ
1%
R12
301kΩ
1%
V
NL
-7V
V
PL
+20V
R10
R13
C10
1µF
C15
1µF
24.3kΩ
20kΩ
1%
1%
C19
1000pF
C21
1000pF
EXTERNAL LOGIC SIGNAL
(ENABLE = LOW)
REF
OPTIONAL
OPTIONAL
R14
221kΩ
EXTERNAL LOGIC SIGNAL
(ENABLE = LOW)
V
MAIN
ANALOG GROUND
(GND)
POWER GROUND
(PGND)
Figure 1. Standard Application Circuit
______________________________________________________________________________________ 11
Triple-Output TFT LCD Power Supply
with Fault Protection
V
IN
FREQ
REF
SHDN
IN
REFERENCE
1.25V
GATE
DRIVER
GATE
REF
EN
EN
REFOK
OCN
OCP
+
-
+
-
OVERCURRENT
COMPARATOR
EN
+
-
UVLO
COMPARATOR
2.70V
2.35V
OSCILLATOR
OSC
SLOPE_COMP
V
MAIN
ONP ONMN
LX
FB
SEQUENCE
AND FAULT
DETECTOR
FAULTM
MAIN STEP-UP
WITH SOFT-START
PGND
EN
THERMAL
SHUTDOWN
SSDONE
DRVP
FBP
+
-
V
PL
ANALOG
GAIN BLOCK
+
-
FAULT
COMPARATOR
+
-
+
-
+
-
0.125V
ANALOG
GAIN BLOCK
DRVN
MAX1889
-
V
NL
+
+
-
0.35V
FBN
FAULT
COMPARATOR
REF
Figure 2. MAX1889 System Functional Diagram
12 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Table 1. Component List
Detailed Description
The MAX1889 contains a high-performance, step-up
switching regulator, two low-cost linear-regulator con-
trollers, and multiple levels of protection circuitry. Figure
2 shows the system functional diagram of the device.
DESIGNATION
DESCRIPTION
3.3µF, 6.3V X5R ceramic capacitors (0805)
Taiyo Yuden JMK212BJ335MG
C2, C3
The output voltage of the main step-up converter (V
)
4.7µF, 10V X7R ceramic capacitors (1210)
Taiyo Yuden LMK352BJ475MF
MAIN
C4, C5, C6
D1
can be set from V to 13V with an external resistive volt-
IN
age-divider. The high switching frequency (500kH/1MHz)
of the main step-up converter and current-mode control
provide fast transient response and allow the use of low-
profile inductors and ceramic capacitors. The internal
power MOSFET minimizes the external component count
while achieving high efficiency by incorporating a loss-
less current-sensing technology.
1.0A, 30V Schottky diode (S-flat)
Toshiba CRS02
200mA, 25V dual-series Schottky diodes
(SOT23)
Fairchild BAT54S
D2, D3, D4
250mA, 75V switching diode (SOT23)
Central Semiconductor CMPD914
D5
L1
The switching node (LX) can generate both positive
and negative voltage supplies by driving charge-pump
stages of capacitors and diodes. The user can use as
many charge-pump stages as needed to generate sup-
ply voltages of more than +30V and -15V. The positive
and negative linear-regulator controllers postregulate
the charge-pump supply voltages and allow users to
program power-up sequencing as well.
6.8µH, 1.3A inductor
Coilcraft LPO2506IB-682
2.4A, 20V P-channel MOSFET
(3-pin SuperSOT)
Fairchild FDN304P
P1
200mA, 40V NPN bipolar transistor (SOT23)
Fairchild MMBT3904
The unique input switch control of the MAX1889 senses
the current drawn from the input power supply by moni-
toring the voltage drop across the input P-channel
MOSFET and latches off if an overcurrent condition
lasts for more than the fault timer period. In addition, all
three outputs are monitored for fault conditions that last
longer than the fault latch timer. If the junction tempera-
ture of the IC exceeds +160°C, the device goes into a
latched shutdown state.
Q1
Q2
200mA, 40V PNP bipolar transistor (SOT23)
Fairchild MMBT3906
Standard Application Circuit
The standard application circuit (Figure 1) of the
MAX1889 generates +9V, +20V, and -7V outputs for
TFT LCD displays. The input voltage is from 2.7V to
5.5V. Table 1 lists the recommended component
options and Table 2 lists the component suppliers.
Main Step-Up Regulator
The main step-up regulator switches at 1MHz (or 500kHz)
and employs a current-mode control architecture to
maximize loop bandwidth to provide fast-transient
response to pulsed loads found in source drivers for TFT
LCD panels. Also, the high switching frequency allows
the use of low-profile inductors and capacitors to
minimize the thickness of LCD panel designs. The
integrated high-efficiency MOSFET and the IC’s built-in
soft-start function reduce the number of external com-
ponents required while controlling inrush current.
Table 2. Component Suppliers
SUPPLIER
PHONE
FAX
WEBSITE
www.coilcraft.com
Coilcraft
Fairchild
847-639-6400
408-822-2000
800-348-2496
949-455-2000
847-639-1469
408-822-2102
847-925-0899
949-859-3963
www.fairchildsemi.com
www.t-yuden.com
www.toshiba.com
Taiyo Yuden
Toshiba
______________________________________________________________________________________ 13
Triple-Output TFT LCD Power Supply
with Fault Protection
Depending on the input-to-output voltage ratio, the reg-
ulator controls the output voltage and the power deliv-
ered to the output by modulating the duty cycle (D) of
the power MOSFET in each switching cycle. The duty
cycle of the MOSFET is approximated by:
inductor. The inductor current ramps up linearly, storing
energy in a magnetic field. Once the sum of the feed-
back voltage error-amplifier output, slope-compensa-
tion, and current-feedback signals trip the multi-input
PWM comparator, the MOSFET turns off, and the flip-
flop resets. Since the inductor current is continuous, a
transverse potential develops across the inductor that
turns on the diode (D1). The voltage across the inductor
becomes the difference between the output voltage and
the input voltage. This discharge condition forces the
current through the inductor to ramp back down, trans-
ferring the energy to the output capacitor and the load.
The MOSFET remains off for the rest of the clock cycle.
V
-V
MAIN IN
D ≈
V
MAIN
On the rising edge of the internal clock, the controller
sets a flip-flop, which turns on the N-channel MOSFET
(Figure 3). The input voltage is applied across the
LX
RESET DOMINANT
OSC
S
PGND
R
Q
ILIM
COMPARATOR
+
-
+
-
ILIM
MAX1889
CURRENT
SENSE
+
-
SLOPE_COMP
FB
+
Σ
-
+
-
REFOUT
SSOK
REFIN
CLK
REF
+
-
FAULT M
SOFT-START
+
-
EN
ONMN
SSDONE
Figure 3. Main Step-Up Regulator Functional Diagram
14 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
put (Figure 1). The regulator controller is designed to
be stable with an output capacitor of 0.1µF or more.
Positive Linear-Regulator Controller
The positive linear regulator provides the positive high
voltage for the TFT LCD gate drivers. The high voltage
can be produced using a charge-pump circuit as shown
in Figure 1. Use as many stages as necessary to obtain
the required output voltage (see the Selecting the
Number of Charge-Pump Stages section). The positive
linear-regulator controller is an analog gain block with an
open-drain N-channel output. It drives an external PNP
pass transistor with a 3kΩ base-to-emitter resistor to
post-regulate the charge-pump output (Figure 1). The
regulator controller is designed to be stable with an out-
put capacitor of 0.1µF or more.
The negative linear regulator is enabled as soon as the
main step-up regulator is enabled. To enable the regula-
tor using an external control signal, apply the logic-control
input through an open-drain output or an N-channel MOS-
FET (Figure 1). Additional delay can be added with exter-
nal circuitry (see the Applications Information section).
Note that the voltage rating of the DRVN output is
V
- 28V. If higher voltages are present, an external
IN
cascode PNP transistor should be used with the emitter
connected to DRVN, the base to GND, and the collec-
tor to the base of the NPN.
To enable the regulator using an external control signal,
apply the logic-control input in series with a signal
diode (Figure 1). Additional delay can be added with
external circuitry.
Undervoltage Lockout (UVLO)
The UVLO comparator of the MAX1889 compares the
input voltage at the IN pin with the UVLO threshold (2.7V
rising, 2.35V falling, typ) to ensure that the input voltage is
high enough for reliable operation. The 350mV (typ) hys-
teresis prevents supply transients from causing a restart.
Once the input voltage exceeds the UVLO threshold, the
controller enables the reference block. Once the refer-
ence is above 1.05V, an internal 12µA current source
pulls the GATE pin low and turns on an external P-chan-
nel MOSFET switch (P1, Figure 1) that connects the input
supply to the regulator. When the input voltage falls below
the UVLO threshold, the controller sets the fault latch and
pulls GATE high with an internal 100Ω switch to turn off
P1 quickly (Figure 4).
Note that the voltage rating of the DRVP output is 28V.
If higher voltages are present, an external cascode
NPN transistor should be used with the emitter con-
nected to DRVP, the base to V
the base of the PNP.
, and the collector to
MAIN
Negative Linear-Regulator Controller
The negative linear regulator provides the negative volt-
age required to supply gate drivers in TFT LCD panels.
The negative voltage can be produced using a charge
pump circuit as shown in Figure 1. Use as many stages
as necessary to obtain the required output voltage (see
the Selecting the Number of Charge-Pump Stages sec-
tion). The negative linear-regulator controller is an ana-
log gain block with an open-drain P-channel output. It
drives an external NPN pass transistor with a 3kΩ base-
to-emitter resistor to postregulate the charge-pump out-
Reference Voltage (REF)
The reference output is nominally 1.25V, and can
source at least 50µA (see the Typical Operating
Characteristics). Bypass REF with a 0.22µF ceramic
capacitor connected between REF and GND.
Oscillator Frequency (FREQ)
The internal oscillator frequency is pin programmable.
IN
Connect FREQ to ground for 500kHz operation and to V
IN
for 1MHz operation. Note that the soft-start period scales
with the oscillator frequency (see the Soft-Start section).
GATE
Shutdown (SHDN)
A logic-low signal on the SHDN pin disables all device
functions including the reference. When shut down, the
supply current drops to 0.1µA (typ) to maximize battery
life. The output capacitance, feedback resistors, and load
current determine the rate at which each output voltage
decays. A logic-high signal on the SHDN pin activates the
MAX1889 (see the Power-Up Sequencing section). Do not
leave the pin floating. If unused, connect SHDN to IN.
Toggling SHDN or cycling IN clears the fault latch.
L
+
-
C
0.625V
IN
12µA
EN
Figure 4. External Input P-Channel MOSFET Switch Control
______________________________________________________________________________________ 15
Triple-Output TFT LCD Power Supply
with Fault Protection
Power-Up Sequencing and
Inrush Current Control
Input Overcurrent Protection
The high-side overcurrent comparator of the MAX1889
provides input overcurrent protection when it is used
together with the external P-channel MOSFET switch P1
(Figure 1). Connect resistive voltage-dividers from the
source and drain of P1 to GND to set the overcurrent
threshold. The center taps of the dividers are connected
to the overcurrent comparator inputs (OCN and OCP)
See the Setting the Input Overcurrent Threshold section
for information on calculating resistor values. An overcur-
rent event activates the fault-protection circuitry.
Once SHDN is high, the MAX1889 enables the UVLO
circuitry and compares the input voltage with the UVLO
rising threshold (2.7V, typ). If the input voltage exceeds
the UVLO rising threshold, the reference is enabled.
When the reference voltage ramps up above 1.05V
(typ), the MAX1889 enables the oscillator and turns on
the external P-channel MOSFET P1 (Figure 1) by
pulling GATE low. GATE is pulled down with a 12µA
current source. Add a capacitor from the gate of P1 to
its drain to slow down the turn-on rate of the MOSFET,
and reduce inrush current. Once GATE reaches around
0.6V, an internal N-channel MOSFET turns on and pulls
GATE to ground in order to maximize the enhancement
of the external P-channel MOSFET. As P1 fully turns on,
the main step-up regulator powers up with soft-start
(see the Soft-Start section). The negative linear regula-
tor is enabled at the same time as the main step-up
regulator. The positive linear regulator is enabled after
the soft-start routine is completed. The fault detection
timer begins after the main step-up regulator has fin-
ished its soft-start period.
Fault Protection
Once the soft-start routine is completed, if the output of
the main regulator or either linear regulator is below its
respective fault-detection threshold, or the input overcur-
rent comparator pulls high, the MAX1889 activates the
fault timer. If the fault condition still exists after the 64ms
fault-timer duration, the MAX1889 sets the fault latch,
which shuts down all the outputs except the reference,
which remains active. After removing the fault condition,
toggle SHDN (below 0.4V) or cycle the input voltage
(below 2.2V) to clear the fault latch and reactivate the
device.
Soft-Start
The soft-start of the main step-up regulator (Figure 3) is
achieved by ramping up the reference voltage of the
multi-input PWM comparator in 4096 oscillator clock
cycles. The 4096 clock cycles correspond to 4.096ms
for 1MHz operation and 8.192ms for 500kHz operation.
The reference of the PWM comparator comes from a
5-bit DAC that generates 32 steps when the reference
ramps up from 0V to its final value. This soft-start
method allows a gradual increase of the output voltage
to reduce the input surge current (see the startup
waveforms in the Typical Operating Characteristics).
The average input current is given as:
Thermal Shutdown
The thermal shutdown feature limits total power dissipa-
tion in the MAX1889. When the junction temperature
(T ) exceeds +160°C, a thermal sensor sets the fault
J
latch (Figure 2), which shuts down all the outputs
except the reference, allowing the device to cool down.
Once the device cools down by 15°C, toggle SHDN
(below 0.4V) or cycle the input voltage (below 2.2V) to
clear the fault latch and reactivate the device.
Design Procedure
Main Step-Up Regulator
Output Voltage Selection
2
V
×C
OUT
MAIN
Adjust the output voltage by connecting a resistive volt-
I
=
IN_AVG
age-divider from the output (V
) to GND with the
MAIN
V
× t × η
IN SS
center tap connected to FB (Figure 1). Select R7 in the
10kΩ to 50kΩ range. Calculate R6 with the following
equations:
where V
is the main step-up regulator output volt-
MAIN
age, V is the input voltage, C
is the main step-up
OUT
IN
regulator output capacitor, η is the efficiency of the
R6 =R7 (V
/V )-1
MAIN FB
step-up regulator, and t is the soft-start period
SS
where
(4.096ms for 1MHz operation and 8.192ms for 500kHz
operation).
VMAIN − VIN
VFB =1.242V − (D × 20mV) and D ≈
VMAIN
For example, at V = 3V, V
IN
= 9V, D ≈ 0.66, and V
FB
MAIN
= 1.229V.
V
can range from V to 13V.
IN
MAIN
16 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Inductor Selection
The minimum inductance value, peak current rating,
series resistance, and size are factors to consider when
selecting the inductor. These factors influence the con-
verter’s efficiency, maximum output load capability,
transient response time, and output voltage ripple. For
most applications, values between 3.3µH and 20µH
work best with the MAX1889’s switching frequencies.
The power loss due to the inductor’s series resistance
(P ) can be approximated by the following equation:
LR
2
I
× V
MAIN
2
MAIN
P
=I
R ≅
R
L
LR (LAVG)
L
V
IN
where I
is the average inductor current and R is
L
L(AVG)
the inductor’s series resistance. For best performance,
select inductors with resistance less than the internal
N-channel MOSFET’s on-resistance (0.25Ω typ). To
minimize radiated noise in sensitive applications, use a
shielded inductor.
The maximum load current, input voltage, output volt-
age, and switching frequency determine the inductor
value. For a given load current, higher inductor value
results in lower peak current and, thus, less output rip-
ple, but degrades the transient response and possibly
increases the size of the inductor. The equations pro-
vided here include a constant defined as LIR, which is
the ratio of the peak-to-peak inductor current ripple to
the average DC inductor current. For a good compro-
mise between the size of the inductor, power loss, and
output voltage ripple, select an LIR of 0.3 to 0.5. The
inductance value is then given by:
Output Capacitor
The output capacitor affects the circuit stability and out-
put voltage ripple. A 10µF ceramic capacitor works well
in most applications. Depending on the output capaci-
tor chosen, feedback compensation may be required
or desirable to increase the loop-phase margin or
increase the loop bandwidth for transient response
(see the Feedback Compensation section).
2
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohm ripple due to
the capacitor’s equivalent series resistance (ESR):
V
V
-V
1
IN(TYP)
MAIN IN(TYP)
f
L =
η
V
I
LIR
MAIN MAIN(MAX) OSC
where η is the efficiency, f
is the oscillator frequency
OSC
V
= V
+ V
RIPPLE
RIPPLE(ESR) RIPPLE(C)
(see the Electrical Characteristics), and I
includes
MAIN
V
≈I
R
and
RIPPLE(ESR) PEAK ESR(COUT),
the primary load current and the input supply currents
for the charge pumps. Considering the typical applica-
tion circuit, the maximum average DC load current
I
C
V
V
-V
f
MAIN
MAIN IN
V
≈
RIPPLE(C)
OUT
MAIN OSC
(I ) is 200mA with a 9V output. Based on the
MAIN(MAX)
above equations, and assuming 85% efficiency and a
switching frequency of 1MHz, the inductance value is
9.4µH for an LIR of 0.3. The inductance value is 5.6µH
for an LIR of 0.5. The inductance in the standard appli-
cation circuit is chosen to be 6.8µH.
where I
is the peak inductor current (see the Inductor
PEAK
Selection section). For ceramic capacitors, the output volt-
age ripple is typically dominated by V ). The volt-
RIPPLE(C
age rating and temperature characteristics of the output
capacitor must also be considered.
The inductor’s peak current rating should be higher than
the peak inductor current throughout the normal operat-
ing range. The peak inductor current is given by:
Step-Up Regulator Compensation
The loop stability of a current-mode step-up regulator
can be analyzed using a small-signal model. In continu-
ous conduction mode (CCM), the loop-gain transfer
function consists of a dominant pole, a high-frequency
pole, a right-half-plane (RHP) zero, and an ESR zero. In
the case of ceramic output capacitors, the ESR zero is at
a very high frequency.
I
V
LIR
2
1
MAIN(MAX) MAIN
I
=
1+
PEAK
V
η
IN(MIN)
Under fault conditions, the inductor current can reach the
internal LX current limit (see the Electrical Characteristics).
However, soft saturation inductors and the controller’s fast
current-limit circuitry protect the device from failure during
such a fault condition.
The inductor’s DC resistance can significantly affect
efficiency due to conduction losses in the inductor.
______________________________________________________________________________________ 17
Triple-Output TFT LCD Power Supply
with Fault Protection
Therefore, the dominant pole and the RHP zero deter-
mine the loop response of the step-up regulator. The fre-
quency of the dominant pole is:
zero-pole pair to the loop by connecting an RC network
from the FB pin to the main output (lead compensation).
The frequencies of the pole and zero for the lag com-
pensation are:
1
f
=
P_DOMINANT
2πR C
1
L
f
=
P _FB
R1× R2
R1+ R2
where R is the load resistance and C is the output
L
capacitor. The frequency of the RHP zero is:
2π R4
C1
1
f
=
2
R
Z _FB
L
f
= 1-D
2πR4 × C1
Z_RHP
2πL
The frequencies of the zero and pole for the lead com-
pensation are:
where D is the duty cycle, L is the inductance, and the
DC gain is given by:
1
f
=
Z _FF
2π R2 + R3 × C2
(
)
R1
(1−D)
A
= 20log
×
×R
DC
L
R1+R2
R
1
CS
f
=
P _FF
R1× R2
R1+ R2
where R is the internal current-sense resistor, and R1
CS
and R2 are the feedback divider resistors in Figure 5.
2π R3 +
C2
However, adding lead or lag compensation (Figure 5)
can be useful to adjust the trade-off between stability
and transient response. If greater phase margin is need-
ed for stability, and lower bandwidth is acceptable, add
a pole-zero pair by connecting an RC network from the
FB pin to ground (lag compensation). Conversely, if
higher bandwidth is required for faster transient
response, and lower phase margin is acceptable, add a
The compensation resistors R3 and R4 change the AC
gain affecting the loop bandwidth and phase margin at
crossover. Reducing the bandwidth too much (FB com-
pensation) harms the transient response, while increas-
ing it too much harms phase margin and stability. As a
rule, start with R3 (or R4) approximately equal to half of
R1 (or R2). In a typical application, the compensation
capacitors C1 and C2 can be in the range between
100pF to 1000pF. Then, check the stability by monitoring
the transient response waveform when a pulsed load is
applied to the output.
L
D
V
IN
V
MAIN
Using Compensation for Improved Soft-Start
The digital soft-start of the main step-up regulator limits
the average input current during startup. In order to
smooth out each step of the digital soft-start, add a low-
frequency lead compensation network (Figure 5). The
network effectively spreads out the switching pulses
and lowers the peak inductor currents.
R3
C2
D1
LX
R2
R1
C
R
L
FB
R4
C1
MAX1889
The smoothing network is active only during soft-start
when the output voltage rises. Positive changes in the
output are instantaneously coupled to the FB pin
through D1 and feed-forward capacitor C2. This
arrangement generates a smoothly rising output volt-
age. When the output voltage reaches regulation, C2
charges up through R3 and D1 turns off. In most appli-
cations, the lead compensation is not needed and can
be disabled by making R3 large. With R3 > R2, the
pole and the zero in the compensation network are very
close to one another and cancel out.
GND
PGND
Figure 5. External Compensation
18 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Input Capacitor
The input capacitor (C ) reduces the current peaks
IN
If the comparator and resistors are ideal, the threshold
is at the current where both inputs are equal:
drawn from the input supply and reduces noise injection
into the device. Two 3.3µF ceramic capacitors are used
in the standard application circuit (Figure 1) because of
the high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator typically runs
directly from the output of another regulated supply.
R2
R1+R2
R4
R3+R4
V
×
= V -I
×R
×
(
)
IN
IN L(MAX)
DS(MAX)
I
is the average inductor current at maximum load
condition and minimum input voltage, and given by:
L(MAX)
V
Typically, C can be reduced below the values used in
IN
OUT
I
=
×I
LOAD(MAX)
L(MAX)
the standard applications circuit. Ensure a low noise sup-
η × V
IN(MIN)
ply at the IN pin by using adequate C . Alternatively,
IN
greater voltage variation can be tolerated on C if IN is
where η is the efficiency of the main step-up regulator.
If the step-up regulator’s minimum input voltage is 2.7V,
output voltage is 9V and maximum load current is 0.3A.
Assuming 80% efficiency, the maximum average induc-
tor current is:
IN
decoupled from C using an RC lowpass filter (see R1,
IN
C1 in Figure 1).
Rectifier Diode
The MAX1889’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 1A Schottky
diode complements the internal MOSFET well.
9V
I
=
× 0.3A = 1.25A
L(MAX)
0.8 × 2.7V
is the maximum on-state drain-to-source
R
DS(MAX)
resistance of P1. The maximum R
be found in the MOSFET data sheet, but that number
does not include the temperature coefficient.
at +25°C can
DS(ON)
Input P-Channel MOSFET
Select the input P-channel MOSFET based on the cur-
rent rating, voltage rating, gate threshold, and on-resis-
tance. The MOSFET must be able to handle the peak
input current (see the Inductor Selection section). The
drain-to-source voltage rating of the input MOSFET
should be higher than the maximum input voltage.
Because the MOSFET conducts the full input current,
the on-resistance should be low enough for higher effi-
ciency. Use a low-threshold MOSFET to ensure that the
switch is fully enhanced at lowest input voltages.
Since the temperature coefficient for the resistance is
0.5%/°C, R
can be calculated with the following
DS(MAX)
equation:
R
=R
× 1+ 0.005× T -25
(
)
DS(MAX)
DS_25°C
J
where T is the actual MOSFET junction temperature in
J
normal operation due to ambient temperature rise and
self-heating caused by power dissipation. As an exam-
ple, consider Fairchild FDN304P, which has a maxi-
mum R
at room temperature of 70mΩ.
DS(ON)
Setting the Input Overcurrent Threshold
The high-side comparator of the MAX1889 provides
input overcurrent protection when used in conjunction
with an external P-channel MOSFET P1. The accuracy
of the overcurrent threshold is affected by many fac-
tors, including comparator offset, resistor tolerance,
input voltage range, and variations in MOSFET
R
DS(ON)
V
IN
R1
R3
R
. The input overcurrent comparator is only
DS(ON)
OCP
OCN
intended to protect against catastrophic failures. This
function is similar to an input fuse.
To minimize the impact of the comparator’s input offset
on the current-sense accuracy, the sense voltage
should be close to the upper limit of the common-mode
range, which extends up to 80% of the input voltage.
The resistive voltage-divider (R3/R4), combined with
the on-state resistance of P1, sets the overcurrent
threshold. The center of R3/R4 is connected to the
inverting input (OCN) as shown in Figure 6.
OC COMP
R2
R4
Figure 6. Setting the Overcurrent Threshold
______________________________________________________________________________________ 19
Triple-Output TFT LCD Power Supply
with Fault Protection
If the junction temperature is +100°C, the maximum on-
V
R2× R3+R4
(
)
IN(TYP)
state resistance overtemperature is:
I
=
× 1-
TH_TYP
R
R4× R1+R2
(
)
DS(TYP)
R
= 70mΩ × 1+ 0.005× 100-25 =100mΩ
(
)
]
[
DS(MAX)
The following example shows how to apply the above
equations in the design. If 1% resistors are used, then
For given R1 and R2 values, the ideal ratio of R3/R4
can be determined:
ε = 0.01. To set V
to be around 75% of V , select
IN
OCP
R1 = 51.1kΩ and R2 = 150kΩ. Assume that the mini-
mum input voltage is 2.7V and the typical input voltage
is 3.3V, the average inductor current at maximum load
V
-I
×R
R3 R1+R2
IN PEAK(MAX) DS(MAX)
=
×
-1
is 1.25A, and the maximum R
of P1 is 100mΩ:
R4
R2
V
DS(ON)
IN
To consider the effect of resistor tolerance, comparator
offset, and input voltage variation, the minimum threshold
equation is:
1-0.01
1+ 0.01
k =
= 0.9802
R2× 1+ ε
(
)
R3
R4
2.7V -1.25A × 0.1Ω
150kΩ
150kΩ + 0.9802× 51.1kΩ
V
×
+ 5mV =
IN(MIN)
= 0.9802×
= 0.2637
-1
R1× 1-ε +R2× 1+ ε
(
)
(
)
2.7V ×
+ 0.005V
R4× 1-ε
(
)
V
-I
×R
×
(
)
IN(MIN) L(MAX)
DS(MAX)
R3× 1+ ε +R4× 1-ε
(
)
(
)
where V
is the minimum expected value of the
IN(MIN)
If R4 =150kΩ, then R3 = 39.2kΩ. The typical overcurrent
input voltage, ε is the tolerance of the resistors and the
5mV is the worst-case input offset voltage of the com-
parator. To simplify the equation, define a constant k as
follows:
threshold is:
150kΩ × 39.2kΩ +150kΩ
(
)
3.3V
0.047Ω
I
=
× 1-
TH_TYP
150kΩ × 51.1kΩ +150kΩ
(
)
1-ε
k =
= 4.15A
1+ ε
The minimum threshold equation becomes:
Charge Pumps
Selecting the Number of
Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meets the output
requirement.
R2
V
×
+ 5mV =
IN(MIN)
k ×R1+R2
-I ×R
k ×R4
R3+k ×R4
V
×
(
)
IN(MIN) L(MAX)
DS(MAX)
The number of positive charge-pump stages is given by:
Solving for R3/R4 yields:
V
+ V
-V
-2× V
D
PL
DROPOUT MAIN
N
=
POS
V
V
-I
×R
R2
R2+k ×R1
MAIN
R3
R4
IN(MIN) L(MAX)
DS(MAX)
= k ×
-1
V
×
+ 5mV
where N
is the number of positive charge-pump
is the positive linear-regulator output,
is the main step-up regulator output, V is the
POS
PL
IN(MIN)
stages, V
V
MAIN
D
The R3/R4 ratio guarantees the required minimum level
for I . The typical overcurrent threshold is given by:
forward voltage drop of the charge-pump diode, and
is the dropout margin for the linear regula-
L(MAX)
V
DROPOUT
tor. Use V
= 2V.
DROPOUT
20 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
The number of negative charge-pump stages is given by:
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
-V + V
NL
DOPOUT
N
=
NEG
V
-2× V
MAIN
D
I
LOAD
C
≥
OUT
where N
is the number of negative charge-pump
is the negative linear-regulator output,
2f
V
NEG
OSC RIPPLE
stages, V
NL
V
is the main step-up regulator output, V is the
where V
is the peak-to-peak value of the output
RIPPLE
MAIN
D
forward voltage drop of the charge-pump diode, and
is the dropout margin for the linear regulator.
ripple.
V
DROPOUT
Charge-Pump Rectifier Diodes
Use V
= 2V.
DROPOUT
Use Schottky diodes with a current rating equal to or
greater than two times the average charge-pump input
current.
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to V
and the first stage of the
MAIN
negative charge pump is connected to ground.
Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
Linear-Regulator Controllers
Output Voltage Selection
Adjust the positive linear-regulator output voltage by
stage to V or another available supply.
IN
connecting a resistive voltage-divider from V to GND
PL
If the first charge-pump stage is powered from V
then the above equations become:
,
IN
with the center tap connected to FBP (Figure 1). Select
R13 in the range of 10kΩ to 30kΩ.
Calculate R12 with the following equation:
V
+ V
- V
PL
DROPOUT IN
N
=
=
POS
NEG
R12 = R13 [(V / V
PL
) - 1]
FBP
V
- 2 × V
D
MAIN
where V = 1.25V.
FBP
-V + V
+ V
IN
NL
DROPOUT
N
Adjust the negative linear-regulator output voltage by
connecting a resistive voltage-divider from V to REF
NL
V
- 2 × V
D
MAIN
with the center tap connected to FBN (Figure 1). Select
R10 in the range of 10kΩ to 30kΩ. Calculate R9 with the
following equation:
Flying Capacitor
Increasing the flying capacitor (C ) value increases the
X
output current capability. Increasing the capacitance
indefinitely has a negligible effect on output current
capability because the internal switch resistance and
the diode impedance limit the source impedance. A
0.1µF ceramic capacitor works well in most low-current
applications. The flying capacitor’s voltage rating must
exceed the following:
R9 = R10 [(V
- V ) / (V
- V
)]
FBN
FBN
NL
REF
where V
= 125mV, V
= 1.25V. Note that REF is
REF
FBN
only guaranteed to source 50µA. Using a resistor less
than 20kΩ for R10 results in higher bias current than
REF can supply. Connecting another resistor (R14)
from V
to REF (Figure 1) can solve this problem
MAIN
because the main output can supply part of the resis-
tor’s (R10) bias current. Use the following equation to
determine the value of R14:
V
>N× V
MAIN
CX
where N is the stage number in which the flying capaci-
tor appears, and V is the main output voltage. For
V
-V
MAIN
MAIN REF
R14 =
example, the two-stage positive charge pump in the
typical application circuit (Figure 1) where V = 9V
V
-V
REF FBN
R10
-40µA
MAIN
contains two flying capacitors. The flying capacitor in
the first stage (C14) requires a voltage rating over 9V.
The flying capacitor in the second stage (C13) requires
a voltage rating over 18V.
Drawing only 40µA from REF leaves the remaining
10µA for other purposes.
Pass Transistor Selection
The pass transistor must meet specifications for current
gain (β), input capacitance, collector-emitter saturation
voltage, and power dissipation.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
______________________________________________________________________________________ 21
Triple-Output TFT LCD Power Supply
with Fault Protection
The transistor’s current gain limits the guaranteed maxi-
During startup, the LDO outputs are below their respec-
mum output current to:
tive setpoints, and the base drive to the pass transis-
tors is a maximum. The large drive currents can cause
the charge-pump outputs to collapse. If the charge-
pump loading is objectionable, base resistors can be
added between the drive outputs (DRVN and DRVP)
and the pass transistors (Figure 7). These resistors limit
the maximum drive current and prevent discharging the
charge pump’s output capacitors. Select the minimum
base drive current to meet the maximum required LDO
output current:
V
BE
I
= I
-
β
MIN
LOAD(MAX)
DRV
R
BE
where I
is the minimum base-drive current, and R
BE
DRV
is the pullup resistor connected between the transis-
tor’s base and emitter. Furthermore, the transistor’s cur-
rent gain increases the linear regulator’s DC loop gain
(see the Stability Requirements section), so excessive
gain destabilizes the output. Therefore, transistors with
current gain over 100 at the maximum output current
are not recommended. The transistor’s input capaci-
tance and input resistance also create a second pole,
which could be low enough to make the output unsta-
ble when heavily loaded.
I
LDOOUT(MAX)
I
=
DRIVE(MIN)
β
MIN
The resistance required to guarantee this base current is:
V
-V
LDOIN(MAX) BE
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output voltage
differential that the linear regulator supports.
Alternatively, the package’s power dissipation could limit
the usable maximum input-to-output voltage differential.
The maximum power dissipation capability of the transis-
tor’s package and mounting must exceed the actual
power dissipation in the device. The power dissipation
equals the maximum load current times the maximum
input-to-output voltage differential:
R
≤
BASE
I
DRIVE(MIN)
β
V
-V
(
)
MIN LDOIN(MAX) BE
=
I
LDOOUT(MAX)
As a consequence of adding the base resistors, a volt-
age change at DRVN and DRVP accompanies changes
in drive current. This voltage change can be coupled
through parasitic capacitance to the LDO feedback
pins. If the rate of voltage change is sufficiently large, it
can cause instability.
P =I
(V
-V
) =
LOAD(MAX) LDOIN LDOOUT
I
V
LOAD(MAX) CE
V
N
V
P
C20
470pF
C24
2200pF
MAX1889
R20
51kΩ
R19
15kΩ
7
6
8
9
DRVN
FBN
DRVP
FBP
Q1
Q2
V
NL
V
PL
REF
Figure 7. Limiting LDO Drive Current During Startup
22 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
To avoid excessive voltage coupling, a small capacitor
3) A third pole is set by the linear regulator’s feedback
resistance and the capacitance (including stray
capacitance) between FB_ and GND (for the posi-
tive LDO) and FBN and GND (for the negative LDO)
(Figure 8):
can be added in parallel with the base resistor. The
resulting RC time constant should be between 5µs to
50µs.
Stability Requirements
The MAX1889 linear-regulator controllers use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, the
pass transistor, the base-emitter resistor, and the out-
put capacitor determine the loop stability. If the output
capacitor and pass transistor are not properly selected,
the linear regulator can be unstable.
1
f
=
=
POLE(FB)_POS
2πC (R12II R13)
FB
1
f
POLE(FB)_NEG
2πC (R9II R10)
FB
4) If the second and third poles occur well after unity-
gain crossover, the linear regulator remains stable:
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
f
> 2f
A
POLE(CBE)
POLE(CLDO) V(LDO)
I
h
However, if the ESR zero occurs before the unity-gain
crossover, cancel the zero with the feedback pole by
changing circuit components such that:
5.5
BIAS FE
A
=
1+
V
REF
V(LDO)
V
T
I
LOAD
where V is 26mV at room temperature, and I
is the
T
BIAS
BE
1
current through the base-to-emitter resistor (R ). This
f
≈
POLE(FB)
bias resistor is typically 3kΩ, providing 0.23mA of cur-
rent, biasing the LDO near its regulation voltage setpoint.
2πC
R
OUT ESR
For most applications where ceramic capacitors are
used, the ESR zero always occurs after the crossover.
The output capacitor and the load resistance create the
dominant pole in the system. The pass transistor’s input
capacitance creates a second pole in the system.
Additionally, the output capacitor’s ESR generates a zero.
A capacitor connected between the output and the
feedback node improves the transient response,
reduces the noise coupled into the feedback loop, and
maintains the correct regulation point (Figure 8).
To achieve stable operation, use the following equations
to verify that the linear regulator is properly compensated:
1) First, determine the dominant pole set by the linear
Output Capacitor Selection
Typically, more output capacitance provides the best
solution, since this also reduces the output voltage drop
immediately after a load transient. Connect at least a
0.1µF capacitor between the linear regulator’s output and
ground, as close to the external pass transistor as possi-
ble. Depending on the selected pass transistor, larger
capacitor values may be required for stability (see the
Stability Requirements section). Furthermore, the output
capacitor’s ESR affects stability. Use output capacitors
with an ESR less than 200mΩ to ensure stability and opti-
mum transient response. Once the minimum capacitor
value for stability is determined, verify that the linear regu-
lator’s output does not contain excessive noise. Although
adequate for stability, small capacitor values can provide
too much bandwidth, making the linear regulator sensitive
to noise. Larger capacitor values reduce the bandwidth,
thereby reducing the regulator’s noise sensitivity. If noise
on the ground reference causes the design to be margin-
ally stable for the negative linear regulator, bypass the
negative output back to its reference voltage. This tech-
nique reduces the differential noise on the output.
regulator’s output capacitor and the load resistor:
I
1
LOAD(MAX)
f
=
=
POLE(CLDO)
2πC
R
2πC
V
LDO LDO
LDO LOAD
The unity gain crossover of the linear regulator is:
= A
f
f
V(LDO) POLE(CLDO)
CROSSOVER
2) Next, determine the second pole set by the base-
to-emitter capacitance (including the transistor’s
input capacitance), the transistor’s input resistance,
and the base-to-emitter pullup resistor:
1
f
=
=
POLE(CBE)
2πC (R II R
)
BE BE
IN
+ V h
V h
R
2πC
I
BE LOAD T FE
R
BE BE T FE
_______________________________________________________________________________________ 23
Triple-Output TFT LCD Power Supply
with Fault Protection
spikes. All the other ground connections, such as
Applications Information
the IN pin bypass capacitor and the linear regulator
output capacitors, should be star-connected to the
backside of the device with wide traces. Make no
other connections between these separate ground
planes.
PC Board Layout
Careful PC board layout is extremely important for
proper operation. Use the following guidelines for good
PC board layout:
1) Minimize the area of high-current loops by placing
the input capacitors, inductor, output diode, and
output capacitors less than 0.2in (5mm) from the LX
and PGND pins. Connect these components with
traces as wide as possible. Avoid using vias in the
high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
3) Place IN pin and REF pin bypass capacitors as
close to the device as possible.
4) Place all feedback voltage-divider resistors as close
to their respective feedback pins as possible. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Care should be taken to avoid running any feedback
trace near LX or the switching nodes in the charge
pumps.
2) Create islands for the analog ground (GND), power
ground (PGND), and linear regulator ground. Star-
connect them to the backside pad of the device.
The REF bypass capacitor and both feedback
dividers should be connected to the analog ground
island (GND). The step-up regulator’s input and out-
put capacitors, and the charge-pump components
should be a wide power ground plane. The power
ground plane should be connected to the power
ground pin (PGND) with a wide trace. Maximizing
the width of the power ground traces improves effi-
ciency and reduces output voltage ripple and noise
5) Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
6) Minimize the size of LX node while keeping it wide
and short. Keep the LX node away from feedback
nodes (FB, FBP, and FBN) and analog ground. Use
DC traces as shield if necessary.
Refer to the MAX1889 evaluation kit for an example of
proper board layout.
R8
3kΩ
R11
3kΩ
V
N
V
P
MAX1889
7
6
8
9
DRVN
FBN
DRVP
FBP
Q1
Q2
R12
301kΩ
1%
R9
150kΩ
1%
V
NL
V
PL
C19
1000pF
C21
1000pF
R13
20kΩ
1%
R10
24.3kΩ
1%
REF
Figure 8. LDO Compensation
24 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Additional Application Circuits
V
N
V
P
Operation with Output Voltage >13V
The maximum output voltage of the step-up regulator is
13V, which is limited by the absolute maximum rating of
the internal power MOSFET. To achieve higher output
voltage, an external N-channel MOSFET can be cas-
coded with the internal FET (Figure 9). Since the gate of
the external FET is biased from the input supply, use a
logic-level FET to ensure that the FET is fully enhanced
at the minimum input voltage. The current rating of the
FET needs to be higher than the internal current limit.
V
IN
V
MAIN
15V
LX
Changing Power-Up Sequence
The power-up sequencing of the linear regulators can be
controlled using external delays. Figure 10 shows an
application where the negative linear-regulator output
powers up with a certain delay after the positive linear
regulator reaches regulation. The resistors R1, R2, and
the capacitor C form an RC network that provides the
power-up delay. The time constant of this RC network is:
FB
STEP-UP
REGULATOR
PGND
R1×R2
MAX1889
τ =
C
R1+R2
Select the ratio of R1 and R2 so that:
Figure 9. Operation with Output Voltage >13V Using Cascoded
MOSFET
R2
R1
V
+ V
= 0
N
PL
R1+R2
R1+R2
The required RC time constant is:
4ms
or:
τ =
=1.68ms
9
20
R1
R2
V
N
= -
20 + 9
0.7-0.125
ln
V
PL
With this R1/R2 ratio, the power-up delay can be calcu-
lated as:
Choose C = 0.1µF, then R1//R2 = 16.8kΩ. Use stan-
dard resistor values: R1 = 56kΩ and R2 = 24kΩ.
R1
V
PL
R1+R2
V -0.125V
τ
= τln
D
Disabling Input MOSFET Switch
If the input protection MOSFET is not needed, disable
the input overcurrent comparator by connecting the
OCP pin to ground, the OCN pin to V . Leave the
IN
GATE pin floating (Figure 11).
D
where V is the forward voltage drop of the diode and
D
0.125V is the FBN regulation point.
As a design example, assume the positive linear-regu-
Generating Gamma Reference Voltage
The reference voltage for the Gamma correction resis-
tor string can be produced using the linear-regulator
controller. If the voltage difference between the main
lator output V is +20V, the negative charge-pump
PL
output V is -9V, and the required power-up delay time
N
t
D
is 4ms:
boost voltage (V
) and the Gamma reference volt-
R1
R2 20
9
MAIN
T
=
age is 400mV or greater, the emitter of the PNP pass
transistor should be connected to V
.
MAIN
______________________________________________________________________________________ 25
Triple-Output TFT LCD Power Supply
with Fault Protection
V
P
V
N
V
IN
V
MAIN
+9V
LX
FB
STEP-UP
REGULATOR
V
N
PGND
DRVN
MAX1889
NEGATIVE
REGULATOR
V
P
FBN
V
NL
-7V
DRVP
FBP
POSITIVE
REGULATOR
REF
R1
REF
V
PL
+20V
V
N
GND
R2
C
V
PL
Figure 10. Controlling Power-Up Sequence with External Delay
Chip Information
If the voltage difference is less than 400mV, then the
emitter of the PNP should be connected to a high sup-
TRANSISTOR COUNT: 2396
PROCESS: BiCMOS
ply voltage. The V output has two charge-pump
P
stages added to V
. The emitter of the PNP can be
MAIN
connected to the output of the first stage as shown in
Figure 12. For higher efficiency, the first charge-pump
stage can be connected to V rather than V
IN
this reduces the power loss.
as
MAIN,
26 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
V
P
V
N
V
V
MAIN
9V
IN
3.3V OR 5V
LX
FB
GATE
IN
SWITCH
CONTROL
STEP-UP
REGULATOR
OCP
PGND
OCN
MAX1889
REF
REF
GND
Figure 11. Disabling Input Protection MOSFET Switch
______________________________________________________________________________________ 27
Triple-Output TFT LCD Power Supply
with Fault Protection
V
P
V
N
V
IN
V
MAIN
+9V
LX
FB
STEP-UP
REGULATOR
V
N
PGND
DRVN
FBN
MAX1889
NEGATIVE
REGULATOR
V
NL
-7V
DRVP
FBP
POSITIVE
REGULATOR
REF
V
GAMMA
REF
+8.9V
GND
Figure 12. Generating Gamma Reference Voltage
28 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 29
Triple-Output TFT LCD Power Supply
with Fault Protection
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
30 ______________________________________________________________________________________
Triple-Output TFT LCD Power Supply
with Fault Protection
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0140
C
2
______________________________________________________________________________________ 31
Triple-Output TFT LCD Power Supply
with Fault Protection
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0140
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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