MAX191BEWG+T [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial, Parallel, 8 Bits Access, CMOS, PDSO24, SOP-24;
| 型号： | MAX191BEWG+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial, Parallel, 8 Bits Access, CMOS, PDSO24, SOP-24 |
| 文件： | 总24页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4506; Rev 4; 2/97
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 12-Bit Resolution, 1/2LSB Linearity
♦ +5V or ±5V Operation
♦ Built-In Track/Hold
♦ Internal Reference with Adjustment Capability
The MAX191 is a monolithic, CMOS, 12-bit analog-to-
digital converter (ADC) featuring differential inputs,
track/hold (T/H), internal voltage reference, internal or
external clock, and parallel or serial µP interface. The
MAX191 has a 7.5µs conversion time, a 2µs acquisition
time, and a guaranteed 100ksps sample rate.
♦ Low Power: 3mA Operating Mode
20µA Power-Down Mode
The MAX191 operates from a single +5V supply or from
dual ±5V supplies, allowing ground-referenced bipolar
input signals. The device features a logic power-down
input, which reduces the 3mA VDD supply current to
50µA max, including the internal-reference current.
♦ 100ksps Tested Sampling Rate
♦ Serial and 8-Bit Parallel µP Interface
♦ 24-Pin Narrow DIP and Wide SO Packages
Ord e rin g In fo rm a t io n
Decoupling capacitors are the only external compo-
nents needed for the power supply and reference. This
ADC operates with either an external reference, or an
internal reference that features an adjustment input for
trimming system gain errors.
ERROR
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
MAX191ACNG
MAX191BCNG
MAX191ACWG
MAX191BCWG
MAX191BC/D
MAX191AENG
MAX191BENG
0°C to +70°C 24 Narrow Plastic DIP ±1/2
0°C to +70°C 24 Narrow Plastic DIP ±1
The MAX191 provides three interface modes: two 8-bit
parallel modes, and a serial interface mode that is com-
patible with SPITM, QSPITM, and MICROWIRETM serial-
interface standards.
0°C to +70°C 24 Wide SO
0°C to +70°C 24 Wide SO
0°C to +70°C Dice*
±1/2
±1
±1
-40°C to +85°C 24 Narrow Plastic DIP ±1/2
-40°C to +85°C 24 Narrow Plastic DIP ±1
________________________Ap p lic a t io n s
Battery-Powered Data Logging
PC Pen Digitizers
MAX191AEWG -40°C to +85°C 24 Wide SO
MAX191BEWG -40°C to +85°C 24 Wide SO
±1/2
±1
MAX191AMRG
MAX191BMRG
-55°C to +125°C 24 Narrow CERDIP** ±1/2
-55°C to +125°C 24 Narrow CERDIP** ±1
High-Accuracy Process Control
Electromechanical Systems
Data-Acquisition Boards for PCs
Automatic Testing Systems
* Dice are specified at T = +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
A
Telecommunications
Digital Signal Processing (DSP)
P in Co n fig u ra t io n
TOP VIEW
Fu n c t io n a l Dia g ra m
PD
V
1
2
DD
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
24
CLK/SCLK
23
V
SS
CLK/SCLK
PAR
18
17
16
15
14
13
11
10
5
6
AIN+
D7/DOUT
D6/SCLK
3
VREF
OSC
3-STATE
OUTPUT
REFADJ
OUT
AIN-
HBEN
4
D5/SSTRB
D4
MAX191
VREF
REFADJ
AGND
BIP
CS
5
8-BIT
BUS
AND
SERIAL
I/O
D3/D11
D2/D10
D1/D9
D0/D8
RD
6
2.46V
REF
D7/DOUT
D6/SCLK
7
12
8
OUT
3
4
AIN +
AIN -
BUSY
D0/D8
D1/D9
DGND
D5/SSTRB
D4
9
20
CS
RD
BUSY
HBEN
10
11
12
IN REF OUT
19
9
21
CONTROL
LOGIC
12-BIT
D3/D11
D2/D10
MAX191
SAR ADC
1
PD
7
12
AGND DGND
2
V
SS
22
8
BIP
PAR
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
ABSOLUTE MAXIMUM RATINGS
V
to DGND............................................................-0.3V to +7V
Operating Temperature Ranges
DD
V
to AGND ............................................................-7V to +0.3V
to V ..............................................................................12V
SS
MAX191_C_ _ ................................................................0°C to +70°C
MAX191_E_ _ .............................................................-40°C to +85°C
MAX191_M_ _ ..........................................................-55°C to +125°C
Storage Temperature Range.....................................-65°C to +160°C
Lead Temperature (soldering, 10sec).....................................+300°C
SS
V
DD
AGND, VREF, REFADJ to DGND................-0.3V to (V + 0.3V)
AIN+, AIN-, PD to V .................................-0.3V to (V + 0.3V)
CS, RD, CLK, BIP, HBEN, PAR, to DGND....-0.3V to (V + 0.3V)
DD
SS
DD
DD
BUSY, D0–D7 to DGND..............................-0.3V to (V + 0.3V)
DD
MAX91
Continuous Power Dissipation (T = +70°C)
A
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW
Wide SO (derate 11.76mW/°C above +70°C) ......................941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C) ........1000mW
Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 5V ±5%, V = 0V or -5V ±5%, f = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
DD
SS
CLK
mode, reference compensation mode—external, synchronous operation, Figure 6, T = T
to T
, unless otherwise noted.) (Note 1)
A
MIN
MAX
PARAMETER
DC ACCURACY (Note 2)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
12
Bits
MAX191A
MAX191B
±1/2
LSB
±1
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
No missing codes over temperature
MAX191A
±1
±1
±2
±2
±3
LSB
LSB
MAX191B
MAX191A
Gain Error (Note 3)
LSB
MAX191B
Gain-Error Tempco (Note 4)
Excludes internal-reference drift
±0.2
ppm/°C
DYNAMIC ACCURACY (sample rate = 100kHz, V = 4Vp-p)
IN
Signal-to-Noise plus Distortion
Ratio
1kHz input signal, T = +25°C
SINAD
70
80
dB
A
Total Harmonic Distortion
(up to the 5th Harmonic)
1kHz input signal, T = +25°C
THD
-80
dB
dB
A
1kHz input signal, T = +25°C
Spurious-Free Dynamic Range
SFDR
A
CONVERSION RATE
Synchronous CLK (12 to 13 CLKs)
7.50
6
8.125
18
t
Conversion Time (Note 5)
µs
CONV
Internal CLK, C = 120pF
12
L
Track/Hold Acquisition Time
Aperture Delay
2
µs
ns
ps
25
50
Aperture Jitter
External Clock Frequency
Range (Note 6)
f
0.1
1.6
MHz
CLK
2
_______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%, V = 0V or -5V ±5%, f = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
DD
SS
CLK
mode, reference compensation mode—external, synchronous operation, Figure 6, T = T
to T
, unless otherwise noted.) (Note 1)
A
MIN
MAX
PARAMETER
ANALOG INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Input Voltage Range (Note 7)
Input Leakage Current
V
µA
SS
DD
V
= V to V
±10
80
IN
SS
DD
Input Capacitance (Note 6)
Small-Signal Bandwidth
INTERNAL REFERENCE
VREF Output Voltage
45
2
pF
MHz
T
= +25°C
4.076
4.096
4.116
50
60
80
2
V
A
MAX191_C
MAX191_E
MAX191_M
VREF Output Tempco (Note 8)
ppm/°C
T
= +25°C
Output Current Capability (Note 9)
Load Regulation
mA
mV
mA
µF
A
T
= +25°C, I
= 0mA to 2mA
4
A
OUT
Output Short-Circuit Current
Capacitive Load Required
Power-Supply Rejection
18
Reference compensation mode—external
= ±5%, V = ±5%
4.7
V
±300
µV
DD
SS
REFADJ Input Adjustment Range
(Note 10)
-60
4.5
30
60
mV
REFADJ Disable Threshold
REFADJ Output Voltage
REFADJ Input Current
REFERENCE INPUT
Input Voltage Range
Input Current
V
V
2.4
10
REFADJ = 5V
µA
External-reference mode
External-reference = 5V
External-reference mode
2.5
5
5.0
1
V
mA
kΩ
Input Resistance
LOGIC INPUTS
V
Input Low Voltage
0.8
V
V
CS, RD, CLK, HBEN, PAR, BIP
CS, RD, CLK, HBEN, PAR, BIP
IL
V
Input High Voltage
Input Current
2.4
IH
I
V = 0V to V
IN DD
±10
µA
IN
±200
PD = high/float
PD = low
I
Input Current CLK
µA
IN
±0.1
C
Input Capacitance (Note 6)
PD Input Low Voltage
PD Input High Voltage
PD Input Current
10
pF
V
IN
V
0.5
IL
V
4.5
V
IH
I
PD = 0V to V (Note 11)
±20
µA
IN
DD
PD External Leakage for Float
State (Note 12)
Maximum current allowed for “floating state”
Reference compensation mode—external
±100
nA
V
V
2.8
PD Floating-State Voltage
FLT
_______________________________________________________________________________________
3
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%, V = 0V or -5V ±5%, f = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
DD
SS
CLK
mode, reference compensation mode—external, synchronous operation, Figure 6, T = T
to T
, unless otherwise noted.) (Note 1)
A
MIN
MAX
PARAMETER
LOGIC OUTPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Low Voltage
V
I
= 1.6mA
0.4
V
V
OL
OUT
MAX91
Output High Voltage
V
OH
I
= -200µA
4.0
OUT
Three-State Leakage Current
I
D0/D8-D7/DOUT
±10
15
µA
L
Three-State Output
Capacitance (Note 6)
C
pF
OUT
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
V
4.75
5.25
0
V
V
DD
V
SS
-5.25
3
20
20
1
5
mA
µA
CS = RD = V
AIN = 5V, D0/D8–D7/
DOUT = 0V or V
,
PD = high/float
DD
Positive Supply Current
Negative Supply Current
I
DD
50
PD = low
,
DD
100
20
PD = high/float
PD = low
HBEN = PAR = BIP
= 0V or V
I
SS
µA
DD
Positive Supply Rejection (Note 13)
Negative Supply Rejection (Note 13)
FS change, V = 5V ±5%
±1/2
±1/2
LSB
LSB
DD
FS change, V = -5V ±5%
SS
TIMING CHARACTERISTICS (Figures 6–10)
(V =5V ±5%, V = 0V or -5V ±5%, T = T
to T
, unless otherwise noted.) (Note 14)
DD
SS
A
MIN
MAX
T
= +25°C
MAX191C/E
MIN TYP MAX
MAX191M
MIN TYP MAX
A
PARAMETER
SYMBOL CONDITIONS
UNITS
MIN TYP MAX
t
0
0
0
ns
ns
ns
ns
ns
CS to RD Setup Time
RD to BUSY Delay
1
t
t
t
t
C
C
= 50pF
120
120
150
0
140
140
150
0
160
160
150
0
2
3
4
5
L
L
Data Access Time (Note 15)
RD Pulse Width
= 100pF
CS to RD Hold Time
Data Setup Time After
BUSY (Note 15)
t
80
100
120
ns
6
Bus-Relinquish Time (Note 16)
HBEN to RD Setup Time
HBEN to RD Hold Time
t
t
t
100
110
120
ns
ns
ns
7
8
9
80
0
100
0
120
0
Delay Between Read
Operations (Note 6)
t
200
200
2
200
2
ns
10
Delay Between Conversions
Aperture Delay
t
t
t
2
µs
ns
ns
11
12
13
Jitter < 50ps
25
200
230
130
260
150
CLK to BUSY Delay (Note 6)
SCLK
to SSTRB
OUT
t
t
100
100
ns
ns
14
15
Rise Delay
SCLK
to SSTRB
OUT
130
150
Fall Delay
4
_______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
TIMING CHARACTERISTICS (Figures 6–10) (continued)
(V =5V ±5%, V = 0V or -5V ±5%, T = T
to T
, unless otherwise noted.) (Note 14)
DD
SS
A
MIN
MAX
T
= +25°C
MAX191C/E
MIN TYP MAX
MAX191M
MIN TYP MAX
A
PARAMETER
SYMBOL CONDITIONS
UNITS
MIN TYP MAX
t
10
10
10
ns
ns
ns
ns
ns
ns
ns
CS or RD Hold Time
CS or RD Setup Time
CS to DOUT Three-State
16
t
150
100
160
100
240
260
150
110
180
130
260
310
150
120
200
150
280
350
17
t
19
SCLK to SCLK
Delay
t
t
t
t
OUT
20
21
22
23
SCLK
to DOUT Delay
OUT
SCLK to DOUT Delay
SCLK to SSTRB Delay
Note 1: Performance at power-supply tolerance limits guaranteed by power-supply rejection test.
Note 2: = 5V, V = 0V, FS = VREF.
Note 3: FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB.
Note 4: Gain-Error Tempco = ∆GE is the gain-error change from T = +25°C to T
V
DD
SS
or T .
MAX
A
MIN
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Guaranteed by design, not production tested.
Note 7: AIN+, AIN- must not exceed supplies for specified accuracy.
Note 8: VREF TC = ∆T, where ∆VREF is reference-voltage change from T = +25°C to T
or T
.
A
MIN
MAX
Note 9: Output current should not change during conversion. This current is in addition to the current required by the internal DAC.
Note 10: REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V.
This will typically result in a 1.7 times larger change in the REF output (Figure 19a).
Note 11: This current is included in the PD supply current specification.
Note 12: Floating the PD pin guarantees external compensation mode.
Note 13: V
= 4.096V, external reference.
REF
Note 14: All input control signals are specified with t = t = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V.
r
f
Note 15: t and t are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
3
6
Note 16: t is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
7
_______________________________________________________________________________________
5
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
CLOCK FREQUENCY
vs. TIMING CAPACITOR
NEGATIVE SUPPLY CURRENT
vs. TEMPERATURE
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
25
20
25
20
10
SEE FIGURE 5
T = +25˚C
A
MAX91
I
DD
1
15
10
15
10
V
= +5V
= -5V
DD
V
SS
0.1
PD = 0V
5
0
5
0
I
SS
0.01
-60 -30
0
30 60
90
120 150
0.1
1
10
-60 -30
0
30 60
90
120 150
TEMPERATURE (°C)
TIMING CAPACITOR (nF)
TEMPERATURE (°C)
POSITIVE SUPPLY CURRENT
vs. TEMPERATURE
10kHz FFT PLOT
1kHz FFT PLOT
0
-20
-40
0
3.5
3.0
f
IN
= 10kHz
f
IN
= 1kHz
-20
f = 100kHz
S
f = 100kHz
S
SNR = 71.2dB
T = +25˚C
A
SNR = 72dB
T = +25˚C
A
2.5
2.0
1.5
1.0
-40
-60
-60
-86.0dB -90.8dB
-80
-100
-120
-80
-94.3dB -96.1dB-98.0dB -93.8dB
-100
-120
0.5
0
-140
-140
-60
-30
0
30
60 90 120 150
0
1
2
3
4
5
6
0
5
10 15 20 25 30 35 40
FREQUENCY (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
6
_______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
P in De s c rip t io n
FUNCTION
PIN
NAME
Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic
high selects normal operation, internal-reference compensation mode. An open-circuit condition selects
normal operation, external-reference compensation mode.
1
PD
2
3
4
V
Negative Supply, 0V to -5.25V
SS
AIN+
AIN-
Sampled Analog Input
Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section).
Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to
5
VREF
V
.
DD
6
7
REFADJ
AGND
Reference Adjust. Connect to V to use an extended reference at VREF.
DD
Analog Ground
BIP = low selects unipolar mode
BIP = high selects bipolar mode (see Gain and Offset Adjustment section)
8
BIP
9
BUSY
D0/D8
D1/D9
DGND
D2/D10
D3/D11
D4
BUSY Output is low during a conversion.
Three-State Data Outputs: LSB = D0
10
11
12
13
14
15
16
17
18
Three-State Data Outputs
Digital Ground
Three-State Data Outputs
Three-State Data Outputs: MSB = D11
Three-State Data Output
D5/SSTRB
Three-State Data Output/Serial Strobe Output in serial mode
Three-State Data Output/Serial Clock Output in serial mode
Three-State Data Output/Data Output in serial mode
Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory
D6/SCLK
OUT
D7/DOUT
19
20
RD
mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLK
and
OUT
SSTRB when CS is low. RD = high forces SCLK
and SSTRB into a high-impedance state.
OUT
Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling
CS
edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLK
, SSTRB, and
OUT
DOUT into a high-impedance state.
High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result
into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs
21
HBEN
onto the data bus. In serial mode, HBEN = low enables SCLK
to operate during the conversion only,
OUT
HBEN = high enables SCLK
to operate continuously, provided CS is low.
OUT
22
23
24
PAR
Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.
Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to
this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal
oscillator.
CLK/SCLK
V
DD
Positive Supply, +5V ±5%
_______________________________________________________________________________________
7
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
+5V
24
3k
1
PD
+5V
V
DD
OPEN
DN
23 C1
DN
CLK/SCLK
PAR
22
3
4
AIN+
AIN-
SERIAL/PARALLEL
INTERFACE MODE
21
20
19
C
C
L
3k
L
HBEN
CS
MAX91
5
6
7
µP CONTROL
INPUTS
VREF
MAX191
4.7µF
0.1µF
DGND
DGND
a. High-Z to V and V to V
RD
REFADJ
AGND
BIP
18
17
16
15
14
13
D7/DOUT
b. High-Z to V and V to V
OL
OH
OL
OH
OL
OH
0.1µF
8
D6/SCLK
OUT
9
OUTPUT
STATUS
Figure 1. Load Circuits for Access Time
BUSY
DO/DB
D1/D9
DGND
D5/SSTRB
10
11
12
D4
D3/D11
D2/D10
+5V
3k
V
SS
DN
DN
2
0V TO -5V
µP DATA BUS
10pF
10pF
3k
DGND
DGND
a. V to High-Z
NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK.
b. V to High-Z
OH
OL
Figure 3. Operational Diagram
Figure 2. Load Circuits for Bus-Relinquish Time
disconnects from the input during the conversion. In
unb uffe re d a p p lic a tions , a n inp ut filte r c a p a c itor
reduces conversion noise, but also may limit input
bandwidth.
_______________De t a ile d De s c rip t io n
The MAX191 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog input sig-
nal to a 12-bit digital output. Flexible control logic pro-
vides easy interface to microprocessors (µPs), so most
applications require only the addition of passive com-
ponents. No external hold capacitor is required for the
T/H. Figure 3 shows the MAX191 in its simplest opera-
tional configuration.
When converting a single-ended input signal, AIN-
should be connected to AGND. If a differential signal is
connected, consider that the configuration is pseudo
differential—only the signal side to the input channel is
held by the T/H. The return side (AIN-) must remain sta-
b le within ± 0.5LSB (± 0.1LSB for b e s t re s ults ) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- to AGND.
P s e u d o -Diffe re n t ia l In p u t
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). A capacitor switching between the AIN+
and AIN- inputs acquires the signal at the ADC’s ana-
log input. At the end of the conversion, the capacitor
reconnects to AIN+ and charges to the input signal.
An external input buffer is usually not needed for low-
bandwidth input signals (<100Hz) because the ADC
An a lo g In p u t —Tra c k /Ho ld
The T/H enters its tracking mode when the ADC is des-
elected (CS pin is held high and BUSY pin is high).
Hold mode starts approximately 25ns after a conver-
sion is initiated. The variation in this delay from one
conversion to the next (aperture jitter) is about 50ps.
Figures 6–10 detail the T/H and interface timing for the
8
_______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
AIN +
TRACK
COMPARATOR
C
HOLD
MAX191
+1.6V
HOLD
32pF
R
IN
C
CLK
C
SWITCH
10pF
PACKAGE
5pF
HOLD
CLOCK
C
EXT
AIN -
DGND
12-BIT DAC
NOTE: C = 120pF GENERATES 1MHz NOMINAL CLOCK
EXT
Figure 4. Equivalent Input Circuit
various interface modes.
Figure 5. Internal Clock Circuit
tection diodes are even slightly forward biased.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal-
culated by: tACQ = 10(RS + RIN)CHOLD (but never less
than 2µs), where RIN = 2kΩ, RS = source impedance of
the input signal, and CHOLD = 32pF (see Figure 4).
Dig it a l In t e rfa c e
S t a rt in g a Co n ve rs io n
In parallel mode, the ADC is controlled by the CS, RD,
a nd HBEN inp uts , a s s hown in Fig ure 6. The T/H
enters hold mode and a conversion starts at the falling
edge of CS and RD while HBEN (not shown) is low.
BUSY goes low as soon as the conversion starts. On
the falling edge of the 13th input clock pulse after the
conversion starts, BUSY goes high and the conversion
result is latched into three-state output buffers. In seri-
al mode, the falling edge of CS initiates a conversion,
and the T/H enters hold mode. Data is shifted out seri-
ally as the conversion proceeds (Figure 10). See the
Parallel Digital-Interface Mode and Serial-Interface
Mode sections for details.
In p u t Ba n d w id t h
The ADC’s input tracking circuitry has a 1MHz typical
large-signal bandwidth characteristic, and a 30V/µs
slew rate. It is possible to digitize high-speed transients
and measure periodic signals with bandwidths exceed-
ing the ADC’s sample rate of 100ksps by using under-
sampling techniques. Note that if undersampling is
used to measure high-frequency signals, special care
must be taken to avoid aliasing errors. Without ade-
quate input bandpass filtering, out-of-band signals and
noise may be aliased into the measurement band.
In t e rn a l/Ex t e rn a l Clo c k
Figure 5 shows the MAX191 clock circuitry. The ADC
includes internal circuitry to generate a clock with an
e xte rna l c a p a c itor. As ind ic a te d in the Typ ic a l
Operating Characteristics , a 120pF capacitor con-
nected between the CLK and DGND pins generates
a 1MHz nominal clock frequency (Figure 5).
In p u t P ro t e c t io n
Internal protection diodes, which clamp the analog input
to VDD and VSS , allow AIN+ to swing from (V - 0.3V) to
SS
(VDD + 0.3V) with no ris k of d a ma g e to the ADC.
However, for accurate conversions near full scale, AIN+
should not exceed the power supplies by more than
50mV because ADC accuracy is affected when the pro-
Alternatively, an external clock (between 100kHz and
1.6MHz) can be applied to CLK. When using an exter-
nal clock source, acceptable clock duty cycles are
_______________________________________________________________________________________
9
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
CLK
t
16
t
17
CS + RD
BUSY
t
13
t
2
MAX91
t
CONV
t
t
2
CONV
Figure 6. CS, RD, and CLK Synchronous Operation
between 45% and 55%.
restarted. BUSY remains low during the entire conver-
sion cycle.
Clo c k a n d Co n t ro l S yn c h ro n iza t io n
The timing diagrams of Figures 7–10 outline two paral-
lel-interface modes and one serial mode.
For best analog performance on the MAX191, the clock
should be synchronized to the conversion start signals
(CS and RD) as shown in Figure 6. A conversion should
not be started in the 50ns before a clock edge nor in
the 100ns after it. This ensures that CLK transitions are
not coupled to the analog input and sampled by the
T/H. The magnitude of this feedthrough can be a few
millivolts. When the clock and conversion start signals
are synchronized, small end-point errors (offset and
full-scale) are the most that can be generated by clock
feedthrough. Even these errors (which can be trimmed
out) can be avoided by ensuring that the start of a con-
version (RD or CS falling edge) does not occur close to
a clock transition (Figure 6), as described above.
S lo w -Me m o ry Mo d e
In slow-memory mode, the device appears to the µP as
a slow peripheral or memory. Conversion is initiated
with a read instruction (see Figure 7 and Table 2). Set
the PAR pin high for parallel interface mode. Beginning
with HBEN low, taking CS and RD low starts the con-
version. The analog input is sampled on the falling
edge of RD. BUSY remains low while the conversion is
in progress. The previous conversion result appears at
the digital outputs until the end of conversion, when
BUSY returns high. The output latches are then updat-
ed with the newest results of the 8 LSBs on D7–D0. A
second read operation with HBEN high places the 4
MSBs, with 4 leading 0s, on data outputs D7–D0. The
second read operation does not start a new conversion
because HBEN is high.
P a ra lle l Dig it a l-In t e rfa c e Mo d e
Output-Data Format
The data output from the MAX191 is straight binary in
the unipolar mode. In the bipolar mode, the MSB is
inverted (see Figure 22). The 12 data bits can be out-
put either in two 8-bit bytes or as a serial output. Table
1 shows the data-bus output format.
ROM Mo d e
As in slow-memory mode, D7–D0 are used for 2-byte
reads. A conversion starts with a read instruction with
HBEN and CS low. The T/H samples the input on the
falling edge of RD (see Figure 8 and Table 3). PAR is set
high. At this point the data outputs contain the 8 LSBs
from the previous conversion. Two more read operations
are needed to access the conversion result. The first
occurs with HBEN high, where the 4 MSBs with 4 leading
0s are accessed. The second read, with HBEN low, out-
puts the 8 LSBs and also starts a new conversion.
A 2-byte read uses outputs D7–D0. Byte selection is
controlled by HBEN. When HBEN is low, the lower 8
bits appear at the data outputs. When HBEN is high,
the upper 4 bits appear at D0-D3 with the leading 4 bits
low in locations D4–D7.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the HBEN, CS, and RD digital inputs. A logic
low is required on all three inputs to start a conversion,
and once the conversion is in progress it cannot be
Figure 9 and Table 4 show how to read output data
within one conversion cycle without starting another
conversion. Trigger the falling edge of a read on the ris-
10 ______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
HBEN
CS
t
8
t
9
t
8
t
9
t
1
t
5
t
1
t
4
t
5
RD
t
t
10
t
10
t
2
CONV
BUSY
t
11
t
3
t
6
t
7
t
3
t
7
OLD DATA
D7–D0
NEW DATA
D7–D0
NEW DATA
D11–D8
DATA
t
12
t
12
HOLD*
TRACK
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.
Figure 7. Slow-Memory Mode Timing
HBEN
t
8
t
9
t
8
t
9
t
8
t
9
CS
RD
t
1
t
4
t
5
t
1
t
4
t
5
t
1
t
4
t
5
t
2
t
t
10
t
2
CONV
BUSY
DATA
t
11
t
3
t
7
t
3
t
7
t
3
t
7
OLD DATA
D7–D0
NEW DATA
D11–D8
NEW DATA
D7–D0
t
12
t
12
HOLD*
TRACK
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.
Figure 8. ROM Mode Timing
______________________________________________________________________________________ 11
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
HBEN
t
8
t
9
t
8
CLK
CS
MAX91
t
1
t
4
t
5
RD
t
10
t
2
t
CONV
BUSY
DATA
t
7
t
3
t
7
t
3
t
7
t
3
OLD DATA
D7–D0
NEW DATA
D7–D0
NEW DATA
D11–D8
t
12
HOLD*
TRACK
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High
Figure 9. ROM Mode Timing, Reading Data without Starting a Conversion
SCLK
t
22
t
20
t
20
THREE STATE
THREE STATE
SCLK
OUT
t
17
t
16
CS
t
23
t
23
THREE STATE
THREE STATE
SSTRB
DOUT
t
15
t
14
t
21
t
12
t
22
t
19
HOLD
TRACK
12 SCLK CYCLES
Figure 10. Serial-Interface Mode Timing Diagram (RD = low)
12 ______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
Table 1. Data-Bus Output, CS = RD = Low
PIN NAME
D7/DOUT D6/SCLK
D5/SSTRB
D4
D3/D11
D2/D10
D1/D9
D0/D8
OUT
HBEN = 0, PAR = 1,
PARALLEL MODE
D7
D6
D5
D4
D3
D2
D1
D0
HBEN = 1, PAR = 1,
PARALLEL MODE
Low
Low
Low
Low
Low
Low
D11
Low
Low
D10
Low
Low
D9
D8
HBEN = X, PAR = 0,
SERIAL MODE, RD = 0
HBEN = X, PAR = 0,
SERIAL MODE, RD = 1
DOUT
DOUT
SCLK
SSTRB
Low
Low
Low
Low
OUT
Three-
Stated
Three-
Stated
Note: D7/DOUT–D0/D8 are the ADC data output pins.
D11–D0 are the 12-bit conversion results. D11 is the MSB.
DOUT = Three-state data output. Data output in serial mode.
SCLK
= Three-state data output. Clock output in serial mode.
OUT
SSTRB = Three-state data output. Strobe output in serial mode.
Table 2. Slow-Memory Mode, 2-Byte Read Data-Bus Status
PIN NAME
D7/DOUT D6/SCLK
D5/SSTRB
D4
D3/D11
D2/D10
D1/D9
D0/D8
OUT
FIRST READ (New Data)
D7
D6
D5
D4
D3
D2
D1
D0
SECOND READ (New Data)
Low
Low
Low
Low
D11
D10
D9
D8
Table 3. ROM Mode, 2-Byte Read Data-Bus Status
PIN NAME
D7/DOUT D6/SCLK
D5/SSTRB
D4
D3/D11
D2/D10
D1/D9
D0/D8
OUT
FIRST READ (Old Data)
D7
Low
D7
D6
Low
D6
D5
D4
D3
D2
D1
D0
SECOND READ (New Data)
THIRD READ (New Data)
Low
D5
Low
D4
D11
D3
D10
D2
D9
D1
D8
D0
Table 4. ROM Mode, 2-Byte Read Data-Bus Status without Starting a Conversion Cycle
PIN NAME
D7/DOUT D6/SCLK
D5/SSTRB
D4
D3/D11
D2/D10
D1/D9
D0/D8
OUT
FIRST READ (Old Data)
D7
D7
D6
D6
D5
D4
D3
D2
D1
D0
SECOND READ (New Data)
THIRD READ (New Data)
D5
D4
D3
D2
D1
D9
D0
D8
Low
Low
Low
Low
D11
D10
______________________________________________________________________________________ 13
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
+5V
+5V
3
4
23
20
19
Q
A
SCLK
CS
1
2
8
Q
B
A
18
17
5
Q
C
DOUT
B
RD
74HC164
6
Q
D
SCLK
MAX191
CLOCK
OUT
MAX91
10
11
12
13
21
Q
E
HBEN
Q
F
Q
G
16
9
Q
H
SSTRB
CLEAR
3
4
Q
A
1
2
8
+5V
Q
B
A
5
6
Q
C
B
74HC164
Q
D
CLOCK
10
11
Q
E
Q
F
12
13
Q
G
9
Q
H
CLEAR
LOGIC INPUT
CS
SCLK
SCLK
OUT
t
19
DOUT
DO
D11
SSTRB
NOTE: USE SSTRB TO GATE PARALLEL DATA TRANSFER FROM SHIFT REGISTER, OR TO CLEAR SHIFT REGISTERS IF DESIRED.
Figure 11. Simple Serial-to-Parallel Interface
14 ______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
ing edge of the first clock cycle after conversion end
c ontinuous s e ria l c loc k. If CS a nd HBEN a re low,
SCLK is output only during the conversion cycle,
while the converter internal clock runs continuously.
This is useful for creating a simple serial-to-parallel
interface without shift-register overflow (Figure 11).
(when BUSY goes high). As mentioned previously, two
more re a d op e ra tions (a fte r BUSY g oe s hig h) a re
needed to access the conversion results. The only dif-
ference is that now the low byte can be read first. This
happens by allowing the first read operation to occur
with HBEN low, where the 8 LSBs are accessed. The
second read, with HBEN high, accesses the 4 MSBs
with 4 leading 0s.
OUT
Maximum Clock Rate in Serial Mode
The maximum SCLK rate depends on the minimum
setup time required at the serial data input to the µP
and the ADC’s DOUT to SCLK delay (t22) (see Figure
S e ria l-In t e rfa c e Mo d e
12). The maximum f
is as follows:
SCLK
The serial mode is compatible with Microwire, SPI and
QSPI serial interfaces. In addition, a framing signal
(SSTRB) is provided that allows the devices to interface
with the TMS320 family of DSPs. Set PAR low for serial
mode. A falling edge on CS causes the T/H to sample
the input (Figure 10). Conversion always begins on the
next falling edge of SCLK, regardless of where CS
occurs. The DOUT line remains high-impedance until a
conversion begins. During the MSB decision, DOUT
remains low (leading 0), while SSTRB goes high to indi-
cate that a data frame is beginning. The data is avail-
able at DOUT on the rising edge of SCLK (SCLKOUT
when using an internal clock) and transitions on the
falling edge. DOUT remains low after all data bits have
been shifted out, inserting trailing 0s in the data stream
until CS returns high. The SCLKOUT signal is synchro-
nous with the internal or external clock.
CS
I/O
SCLK
DOUT
SCK
MISO
+5V
MAX191
SS
a. SPI
CS
CS
SCK
SCLK
DOUT
MISO
+5V
MAX191
For interface flexibility, DOUT, SCLKOUT and SSTRB
signals enter a high-impedance state when CS is high.
When CS is low, RD controls the status of SCLKOUT and
SSTRB outputs. A logic low RD enables SCLKOUT and
SSTRB, while a logic high forces both outputs into a
high-impedance state. Also, with CS low and HBEN
high, SCLKOUT drives continuously, regardless of con-
version status. This is useful with µPs that require a
SS
b. QSPI
I/O
CS
SK
SI
SCLK
DOUT
MAX191
SCLK
c. MICROWIRE
t
22
I/O
CS
DOUT
1
CLKX
SCLK
MAX191
t
(MIN)
SETUP
1
CLKR
f
(MAX) = –– –––––––––
SCLK
)
(
t (M) + t
SU 22
2
DOUT
DR
t
(M) IS THE SETUP TIME REQUIRED AT THE SERIAL DATA INPUT TO THE µP.
IS THE MAXIMUM SCLK TO DOUT DELAY.
SU
SSTRB
FSR
t
22
d. TMS320 SERIAL INTERFACE
Figure 12. f
the serial data input to the µP.
(MAX) is limited by the setup time required by
SCLK
Figure 13. Common Serial-Interface Connections to the MAX191
______________________________________________________________________________________ 15
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
fSCLK(MAX) = (1/2) x 1/ (t (M) + t
)
SPI (CPOL=1, CPHA=1)
su
22
whe re ts u(M) is the minimum d a ta -s e tup time re -
quired at the serial data input to the µP. For example,
Motorola’s MC68HC11A8 data book specifies a 100ns
minimum data-setup time. Using the worst case for a
milita ry g ra d e p a rt of t22 = 280ns (s e e Timing
Characteristics) and substituting in the above equation
indicates a maximum SCLK frequency of 1.3MHz.
Setting CPOL = 1 and CPHA = 1 starts the clock high
during a read instruction. The MAX191 will shift out a
leading 0 followed by the 12 data bits and three trailing
0s (Figure 14b).
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles required to clock in the
data (Figure 15).
MAX91
Us in g t h e MAX1 9 1 w it h S P I, QS P I a n d
MICROWIRE S e ria l In t e rfa c e s
Figure 13 shows interface connections to the MAX191
for common serial-interface standards.
TMS320 Serial Interface
Figure 13d shows the pin connections to interface the
MAX191 to the TMS320. Since the MAX191 makes data
available on the rising edge of SCLK and the TMS320
shifts data in on the falling edge of CLKR, use CLKX of the
DSP to drive SCLK, and CLKX to drive the DSP’s CLKR
input. The inverter’s propagation delay also provides more
data-setup time at the DSP. For example, with no inverter
delay, and using t22 = 280ns and fSCLK = 1.6MHz, the
available setup time before the SCLK transition is:
SPI and MICROWIRE (CPOL=0, CPHA=0)
The MAX191 is c omp a tib le with SPI, QSPI a nd
MICROWIRE serial-interface standards. When using SPI
or QSPI, two modes are available to interface with the
MAX191. You can set CPOL = 0 and CPHA = 0 (Figure
14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When
using CPOL = 0 and CPHA = 0, the conversion begins
on the first falling edge of SCLK following CS going low.
Data is available from DOUT on the rising edge of SCLK,
and transitions on the falling edge. Two consecutive
1-byte reads are required to get the full 12 bits from the
ADC. The first byte contains the following, in this order: a
leading unknown bit (DOUT will still be high-impedance
on the first bit), a 0, and the six MSBs. The second byte
contains the remaining six LSBs and two trailing 0s.
setup time = 1/ (2 x fSCLK) - t22 = 1/ (2 x 1.6E6) - 280ns = 32ns
This still exceeds the 13ns minimum DR setup time before
the CLKR goes low (tsu(DR)), however, a generic 74HC04
provides an additional 20ns setup time (see Figure 13d).
Figure 16 shows the DSP interface timing characteris-
tics. The DSP begins clocking data in on the falling
e d g e of CLKR a fte r the fa lling e d g e of SSTRB.
2ND BYTE READ
1ST BYTE READ
SCLK
CS
HIGH-Z
HIGH-Z
DOUT
LEADING MSB
ZERO
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
a. CPOL = 0, CPHA = 0
SCLK
CS
HIGH-Z
DOUT
HIGH-Z
LEADING MSB
ZERO
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
b. CPOL = 1, CPHA = 1
Figure 14. SPI/MICROWIRE Serial-Interface Timing
16 ______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
SCLK
CS
HIGH-Z
HIGH-Z
DOUT
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
a. CPOL = 0, CPHA = 0
SCLK
CS
HIGH-Z
HIGH-Z
DOUT
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
b. CPOL = 1, CPHA = 1
Figure 15. QSPI Serial-Interface Timing
SCLK
CLKR
CS
HIGH-Z
SSTRB
HIGH-Z
HIGH-Z
HIGH-Z
DOUT
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
Figure 16. TMS320 Interface Timing
______________________________________________________________________________________ 17
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
Following the data transfer, the DSP receive shift regis-
ter (RSR) contains a 16-bit word consisting of the 12
data bits, MSB first, followed by four trailing 0s.
nal reference compensation, drive PD between V
DD
a nd DGND with a µP I/O p in or othe r log ic d e vic e
(Fig ure 17a ). For e xte rna l-re fe re nc e c omp e ns a tion
mode, use the circuit in Figure 17b to drive PD between
DGND and the floating voltage of PD. An alternative is
to drive PD with three-state logic or a switch, provided
the off leakage does not exceed 100nA.
Ap p lic a t io n s In fo rm a t io n
P o w e r-On In it ia liza t io n
Whe n the +5V p owe r s up p ly is firs t a p p lie d to the
MAX191, perform a single conversion to initialize the
ADC (the BUSY signal status is undefined at power-on).
Disregard the data outputs.
MAX91
In t e rn a l Re fe re n c e
The internal 4.096V reference is available at VREF and
mus t b e b yp a s s e d to AGND with a 4.7µF low-ESR
capacitor (less than 1/2Ω) in parallel with a 0.1µF capaci-
tor, unless internal-reference compensation mode is
used (see the Internal Reference Compensation section).
This minimizes noise and maintains a low reference
impedance at high frequencies. The reference output
P o w e r-Do w n Mo d e
In some battery-powered systems, it is desirable to
power down or remove power from the ADC during
inactive periods. To power down the MAX191, drive PD
low. In this mode, all internal ADC circuitry is off except
the reference, and the ADC consumes less than 50µA
max (assuming all signals CS, RD, CLK, and HBEN are
static and within 200mV of the supplies). Figure 17
shows a practical way to drive the PD pin. If using inter-
can be disabled by connecting REFADJ to V
when
DD
using an external reference.
Re fe re n c e -Co m p e n s a t io n Mo d e s
Power-down performance can be optimized for a given
conversion rate by selecting either internal or external
reference compensation.
Internal Compensation
The connection for internal compensation is shown in
Figure 18a. In this mode, the reference stabilizes quick-
ly enough so that a conversion typically starts within
35µs after the ADC is reactivated (PD pulled high). In
this compensation mode, the reference buffer requires
longer recovery time from SAR transients, therefore
requiring a slower clock (and conversion time). With
internal reference compensation, the typical conversion
time rises to 25µs (Figure 18b). Figure 18c illustrates
the typical average supply current vs. conversion rate,
MAX191
1
PD
a. INTERNAL-REFERENCE COMPENSATION MODE
+5V
1
PD
MAX191
MAX191
5
VREF
6
REFADJ
1
PD
0.1µF
OPEN-DRAIN
BUFFER
b. EXTERNAL-REFERENCE COMPENSATION MODE
Figure 17. Drive Circuits for PD Pin
Figure 18a. Internal-Compensation Mode Circuit
18 ______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
10,000
1
0
PD
1000
100
VREF
RD
15µs
20µs
25µs
10
10
50
200
1k
5k
20k 100k
CONVERSIONS PER SECOND
Figure 18c. Average Supply Current vs. Conversion Rate,
Powering Down Between Conversions
Figure 18b. Low Average-Power Mode Operation (Internal
Compensation)
which can be achieved using power-down between
conversions.
1
PD
External Compensation
Figure 19a shows the connection for external compensa-
tion with reference adjustment. In this mode, an external
4.7µF c a p a c itor c ompe nsa te s the re fe re nc e output
amplifier, allowing for maximum conversion speed and
lowest conversion noise. However, when reactivating the
ADC after power-down, the reference takes typically 2ms
to fully charge the 4.7µF capacitor, so more time is
required before a conversion can start (Figure 19b).
Thus, the average current consumed in power-up/power-
down operations is higher in external compensation
mode than in internal compensation mode.
5
VREF
11k
MAX191
100k
4.7µF
0.1µF
6
REFADJ
5k
0.01µF
15k
Ga in a n d Offs e t Ad ju s t m e n t
Figure 19a. External-Compensation Mode with Internal
Reference Adjustment Circuit
Figure 20 depicts the nominal, unipolar input/output (I/O)
transfer function, and Figure 22 shows the bipolar I/O
transfer function. Code transitions occur halfway between
successive integer LSB values. Note that 1LSB = 1.00mV
(4.096V/4096) for unipolar operation and 1LSB = 1.00mV
((4.096V/2 - -4.096V/2)/4096) for bipolar operation.
ADCs, it is virtually impossible to null system negative
offset errors. However, the MAX191 input configuration
is pseudo-differential—only the difference in voltage
between AIN+ and AIN- will be converted into its digital
representation. By applying a small positive voltage to
AIN-, the 0 input voltage at AIN+ can be adjusted to
above or below AIN- voltage, thus nulling positive or
ne g a tive s ys te m offs e t e rrors . R9 a nd R10 c a n b e
removed for applications that require only positive sys-
tem errors to be nulled. To trim the offset error of the
MAX191, apply 1/2LSB to the analog input and adjust
R6 so the digital output code changes between 000
(hex) and 001 (hex). To adjust full scale, apply FS - 1
1/2LSBs and adjust R2 until the output code changes
Figures 19a and 21a show how to adjust the ADC gain
in applications that require full-scale range adjustment.
The connection shown in Figure 21a provides ±0.5%
for ±20LSBs of adjustment range and is recommended
for applications that use an external reference. On the
other hand, Figure 19a is recommended for applica-
tions that use the internal reference, because it uses
fewer external components.
If both offset and full scale need adjustment, the circuit
in Fig ure 21b is re c omme nd e d . For s ing le -s up p ly
______________________________________________________________________________________ 19
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
OUTPUT
CODE
FULL-SCALE
TRANSITION
OPEN CIRCUIT (FLOAT)
PD
0
11 . . . 111
11 . . . 110
11 . . . 101
MAX91
VREF
RD
2ms
200ms
12.5µs
FS = VREF
FS
1LSB =
4096
00 . . . 011
00 . . . 010
Figure 19b. Low Average-Power Mode Operation (External
Compensation)
00 . . . 001
00 . . . 000
0
1
2
3
between FFE (hex) and FFF (hex). Because interaction
occurs between adjustments, offset should be adjusted
before gain. For an input gain of two, remove R7 and R8.
FS
FS–1LSB
AIN INPUT VOLTAGE (LSB)
The MAX191 accepts input voltages from AGND to V
DD
Figure 20. Unipolar Transfer Function
while operating from a single supply, and V to V
SS
DD
when operating from dual supplies. Figure 22 shows
the bipolar input transfer function with AIN- connected
to midscale for single-supply operation and connected
to GND operating from dual supplies. When operating
from a single supply, the MAX191 can be configured
for bipolar operation on its pseudo-differential input.
Instead of using AIN- as an analog input return, AIN-
c a n b e s e t to a d iffe re nt p os itive p ote ntia l volta g e
above ground (BIP pin is set high). The sampled ana-
log input (AIN+) can swing to any positive voltage
above and below AIN-, and the ADC performs bipolar
conversions with respect to AIN-. When operating from
dual supplies, the MAX191 full-scale range is from
V
IN
MAX480
R2
49.9Ω
R1
100Ω
TO AIN+
R3
10k
R4
10k
-V
/2 to +V
/2.
REF
REF
Dig it a l Bu s No is e
If the data bus connected to the ADC is active during a
conversion, crosstalk from the data pins to the ADC
comparator may generate errors. Slow-memory mode
avoids this problem by placing the µP in a wait state
during the conversion. In ROM mode, if the data bus is
active during the conversion, it should be isolated from
the ADC using three-state drivers.
Figure 21a. Trim Circuit for Gain (±0.5%)
RD and CS should be active for less than one clock
cycle. If this is not possible, RD or CS should go high at
the rising edge of CLK, since the comparator output is
always latched on falling edges of CLK.
The ADC generates considerable digital noise in ROM
mode when RD or CS go high and the output data dri-
vers are disabled after a conversion has started. This
noise can cause large errors if it occurs when the SAR
latches a comparator decision. To avoid this problem,
La yo u t , Gro u n d in g , Byp a s s in g
Use printed circuit boards for best system performance.
20 ______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
R7
10k
MAX480
V
IN
AIN +
R8
10k
01 . . . 111
R1
01 . . . 110
10k
00 . . . 010
R2
100Ω
MAX191
D0–D11
00 . . . 001
00 . . . 000
11 . . . 111
11 . . . 110
11 . . . 101
VREF
R3
10k
R5
10k
R6
10k
R4
49.9Ω
VREF
10 . . . 001
10 . . . 000
R9*
20k
VREF
––––
0V
SINGLE SUPPLY
AIN -
VREF - 1LSB
VREF
2
AIN- = ––––
(
R10*
49.9Ω
)
0.1µF*
2
-VREF
––––
0V
DUAL SUPPLY
AIN- = 0V
VREF
–––– - 1LSB
2
2
* CONNECT AIN- TO AGND WHEN USING DUAL SUPPLIES
Figure 21b. Offset (±10mV) and Gain (±1%) Trim Circuit
Figure 22. Bipolar Transfer Function
Wire-wrap boards are not recommended. Board layout
should ensure that digital- and analog-signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
SUPPLIES
+5V
GND
-5V
Figure 23 shows the recommended system ground
connections. Establish a single-point ground (“star”
g round p oint) a t AGND, s e p a ra te from the log ic
ground. Connect all other analog grounds and DGND
to it. No other digital-system ground should be con-
nected to this single-point analog ground. The ground
return to the power supply for this star ground should
be low impedance and as short as possible for noise-
free operation.
R* = 10Ω
+5V
DGND
DGND
V
DD
AGND
V
SS
High-frequency noise in the V
power supply may
DD
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
DIGITAL
CIRCUITRY
MAX191
*OPTIONAL
Figure 23. Power-Supply Grounding Connection
______________________________________________________________________________________ 21
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
0.01µF and 10µF bypass capacitors. Minimize capaci-
tor lead lengths for best supply-noise rejection. If the
+5V power supply is very noisy, a 10Ω resistor can be
connected as a lowpass filter to filter out supply noise
(Figure 23).
The theoretical minimum A/D noise is caused by quan-
tization error and is a direct result of the ADC’s resolu-
tion: SNR = (6.02n + 1.76) dB, where n is the number of
bits of resolution. 74dB is the SNR of a perfect 12-bit
ADC.
By transposing the equation that converts resolution to
SNR we can compute the effective resolution or the
“effective number of bits” the ADC provides from the
measured SNR:
_____________Dyn a m ic P e rfo rm a n c e
High-speed sampling capability and throughput make
the MAX191 ideal for wideband signal processing. To
s up p ort the s e a nd othe r re la te d a p p lic a tions , Fa s t
Fourier Transform (FFT) test techniques guarantee the
ADC's dynamic frequency response, distortion, and
noise at the rated throughput. Specifically, this involves
applying a low-distortion sine wave to the ADC input
and recording the digital conversion results for a speci-
fied time. The data is then analyzed using an FFT algo-
rithm, whic h d e te rmine s its s p e c tra l c onte nt.
Conversion errors are then seen as spectral elements
outside the fundamental input frequency. FFT plots are
shown in the Typical Operating Characteristics.
MAX91
n = (SNR – 1.76)/6.02
To t a l Ha rm o n ic Dis t o rt io n
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal (in the frequen-
cy band above DC and below one-half the sample rate)
to the fundamental itself. This expressed as:
THD = 20log [ √(V 2 + V 2 + V 2 + V 2 + . . . + V 2) /V ]
2
3
4
5
n
1
where V is the fundamental RMS amplitude and V to
1
2
V are the amplitudes of the 2nd through nth harmonics.
n
ADCs have traditionally been evaluated by specifica-
tions such as zero and full-scale error, integral nonlin-
earity (INL), and differential nonlinearity (DNL). Such
parameters are widely accepted for specifying perfor-
mance with DC and slowly varying signals, but are less
us e ful in s ig na l-p roc e s s ing a p p lic a tions whe re the
ADC’s impact on the system transfer function is the
main concern. The significance of various DC errors
does not translate well to the dynamic case, so different
tests are required.
S p u rio u s -Fre e Dyn a m ic Ra n g e
Spurious-free dynamic range is the ratio of the funda-
mental RMS amplitude to the amplitude of the next
largest spectral component (in the frequency band
above DC and below one-half the sample rate). Usually
this peak occurs at some harmonic of the input fre-
quency. But if the ADC is exceptionally linear, it can
occur at a random peak in the ADC’s noise floor.
Signal-to-Noise Ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS a mp litud e of a ll othe r A/D outp ut signa ls,
except signal harmonics. Signal-to-Noise + Distortion
ratio (SINAD) is the same as the SNR, but includes sig-
nal harmonics.
Op t o -Is o la t e d A/D In t e rfa c e
Many industrial applications require isolation to prevent
excessive current flow where ground disparities exist
between the ADC and the rest of the system. In Figure
24, a MAX250 and four 6N136 opto-couplers create an
22 ______________________________________________________________________________________
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
MAX91
5V
T
1
602117970
(SCHOTT)
2
D1
IN
100µF
16V
5V
100µF
IC
74L05
14
13
4
V
OUT
CC
6V
GND
D2
IC
2-3
HCPL2630 (QUALITY TECHNOLOGIES)
1k
8
1
Q
2N3906
1
24
1k
2
0.1µF
V
DD
7
9
10
18
DOUT
IC
2
1k
TTL/CMOS
OUTPUTS
IC
MAX250
1
1k
4
3
3
AIN+
V
IN
1k
Q
2
6
12
11
2N3906
16
4
AIN-
SSTRB
1k
IC
MAX191
5
5
1
4
SHDN
1k
1k
8
7
1
2
21
19
22
8
HBEN
1k
1k
3
6
20
RD
PAR
BIP
CS
IC
3
TTL/CMOS
INPUTS
4
3
6
23
5
5
CLK
VREF
7
AGND
4.7µF
0.1µF
EN
GND
5
8
7
6
REFADJ
ISOLATION
BARRIER
DGND
12
V
SS
0.1µF
2
Figure 24. Isolated Data-Acquisition Circuit
______________________________________________________________________________________ 23
Lo w -P o w e r, 1 2 -Bit S a m p lin g ADC
w it h In t e rn a l Re fe re n c e a n d P o w e r-Do w n
___________________Ch ip To p o g ra p h y
HBEN
CS
RD
MAX91
VREF
REFADJ
0. 198"
(5. 0292mm)
AGND
D7/DOUT
D6/SCLK
OUT
BIP
0. 142"
(3. 6065mm)
SUBSTRATE CONNECTED TO V
DD
________________________________________________________P a c k a g e In fo rm a t io n
24 ______________________________________________________________________________________
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