MAX192BCWP+ [MAXIM]
ADC, Successive Approximation, 10-Bit, 1 Func, 8 Channel, Serial Access, CMOS, PDSO20, ROHS COMPLIANT, SOIC-20;
| 型号： | MAX192BCWP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 10-Bit, 1 Func, 8 Channel, Serial Access, CMOS, PDSO20, ROHS COMPLIANT, SOIC-20 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0247; Rev. 1; 4/97
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
♦ 8-Channel Single-Ended or 4-Channel Differential
________________Ge n e ra l De s c rip t io n
Inputs
The MAX192 is a low-cost, 10-bit data-acquisition system
that combines an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and ultra-low power consumption. The device
operates with a single +5V supply. The analog inputs are
software configurable for single-ended and differential
(unipolar/bipolar) operation.
♦ Single +5V Operation
♦ Low Power: 1.5mA (operating)
2µA (power-down)
♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference
♦ 4-Wire Serial Interface is Compatible
The 4-wire serial interface connects directly to SPI™,
QSPI™, and Microwire™ devices, without using external
logic. A serial strobe output allows direct connection to
TMS320 family digital signal processors. The MAX192
us e s e ithe r the inte rna l c loc k or a n e xte rna l s e ria l-
interface clock to perform successive approximation A/D
conversions. The serial interface can operate beyond
4MHz when the internal clock is used. The MAX192 has
an internal 4.096V reference with a drift of ±30ppm typi-
cal. A reference-buffer amplifier simplifies gain trim and
two sub-LSBs reduce quantization errors.
with SPI, QSPI, Microwire, and TMS320
♦ 20-Pin DIP, SO, SSOP Packages
♦ Pin-Compatible 12-Bit Upgrade (MAX186/MAX188)
_______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE PIN-PACKAGE INL (LSB)
MAX192ACPP
MAX192BCPP
MAX192ACWP
MAX192BCWP
MAX192ACAP
MAX192BCAP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 Plastic DIP ±1/2
20 Plastic DIP ±1
The MAX192 provides a hardwired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the device, and
the quick turn-on time allows the MAX192 to be shut
d own b e twe e n c onve rs ions . By p owe ring d own
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.
20 Wide SO
20 Wide SO
20 SSOP
±1/2
±1
±1/2
±1
20 SSOP
MAX192AEPP -40°C to +85°C
MAX192BEPP -40°C to +85°C
MAX192AEWP -40°C to +85°C
MAX192BEWP -40°C to +85°C
MAX192AEAP -40°C to +85°C
MAX192BEAP -40°C to +85°C
20 Plastic DIP ±1/2
20 Plastic DIP ±1
20 Wide SO
20 Wide SO
20 SSOP
±1/2
±1
The MAX192 is available in 20-pin DIP and SO pack-
ages, and in a shrink-small-outline package (SSOP)
that occupies 30% less area than an 8-pin DIP. The
data format provides hardware and software compati-
bility with the MAX186/MAX188. For anti-aliasing filters,
consult the data sheets for the MAX291–MAX297.
±1/2
±1
20 SSOP
MAX192AMJP -55°C to +125°C 20 CERDIP
MAX192BMJP -55°C to +125°C 20 CERDIP
±1/2
±1
________________________Ap p lic a t io n s
Automotive
___________________P in Co n fig u ra t io n
Pen-Entry Systems
Consumer Electronics
Portable Data Logging
Robotics
TOP VIEW
CH0
CH1
1
2
V
DD
20
19
18
17
SCLK
CS
Battery-Powered Instruments, Battery
Management
CH2
3
MAX192
CH3
4
DIN
Medical Instruments
5
CH4
16 SSTRB
15 DOUT
____________________________Fe a t u re s
CH5
6
CH6
14
13
12
11
DGND
AGND
7
8
CH7
See last page for Typical Operating Circuit.
AGND
SHDN
9
REFADJ
VREF
10
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Corp.
DIP/SO/SSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
ABSOLUTE MAXIMUM RATINGS
DD
V
to AGND........................................................... -0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
AGND to DGND.................................................... -0.3V to +0.3V
CH0–CH7 to AGND, DGND ...................... -0.3V to (V + 0.3V)
DD
CH0–CH7 Total Input Current.......................................... ±20mA
Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
SO (derate 10.00mW/°C above +70°C)...................... 800mW
SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
CERDIP (derate 11.11mW/°C above +70°C).............. 889mW
Operating Temperature Ranges
VREF to AGND .......................................... -0.3V to (V + 0.3V)
DD
REFADJ to AGND...................................... -0.3V to (V + 0.3V)
DD
Digital Inputs to DGND.............................. -0.3V to (V + 0.3V)
Digital Outputs to DGND........................... -0.3V to (V + 0.3V)
DD
Digital Output Sink Current .................................................25mA
MAX192_C_P ..................................................... 0°C to +70°C
MAX192_E_P .................................................. -40°C to +85°C
MAX192_MJP ............................................... -55°C to +125°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
DD
MAX192
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 5V ±5%, f
= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
unless otherwise noted. Typical values are at T = +25°C.)
DD
CLK
T
= T
to T
A
MIN
MAX, A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
10
Bits
MAX192A
MAX192B
±1/2
±1
Relative Accuracy (Note 2)
LSB
Differential Nonlinearity
Offset Error
DNL
No missing codes over temperature
±1
LSB
LSB
±2
Gain Error
External reference, 4.096V
External reference, 4.096V
±2
LSB
Gain Temperature Coefficient
±0.8
±0.1
ppm/°C
Channel-to-Channel
Offset Matching
LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock)
Signal-to-Noise + Distortion Ratio SINAD
66
dB
dB
Total Harmonic Distortion
THD
-70
(up to the 5th harmonic)
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
Full-Power Bandwidth
SFDR
70
-75
4.5
800
dB
dB
65kHz, V = 4.096Vp-p (Note 3)
IN
-3dB rolloff
MHz
kHz
CONVERSION RATE
Internal clock
5.5
6
10
Conversion Time (Note 4)
t
µs
CONV
External clock, 2MHz, 12 clocks/conversion
Track/Hold Acquisition Time
Aperture Delay
t
1.5
µs
ns
AZ
10
<50
1.7
Aperture Jitter
ps
Internal Clock Frequency
MHz
2
_______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%, f
= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
unless otherwise noted. Typical values are at T = +25°C.)
DD
CLK
T
= T
to T
A
MIN
MAX, A
PARAMETER
SYMBOL
CONDITIONS
External compensation, 4.7µF
Internal compensation (Note 5)
Used for data transfer only
MIN
0.1
TYP
MAX
2.0
UNITS
External Clock Frequency
0.1
0.4
MHz
10
ANALOG INPUT
Common-mode range (any input)
Single-ended range (unipolar only)
Unipolar
0
0
0
V
DD
V
REF
Analog Input Voltage
(Note 6)
V
REF
V
Differential range
Bipolar
-V
-2
+V
REF
REF
2
Multiplexer Leakage Current
Input Capacitance
On/off leakage current; V = 0V, 5V
IN
±0.01
16
±1
µA
pF
(Note 5)
INTERNAL REFERENCE (reference buffer enabled)
VREF Output Voltage
VREF Short-Circuit Current
VREF Tempco
T
= +25°C (Note 7)
4.066
4.096
4.126
30
V
mA
A
±30
2.5
ppm/°C
mV
Load Regulation (Note 8)
0mA to 0.5mA output load
Internal compensation
External compensation
Internal compensation
External compensation
0
Capacitive Bypass at VREF
µF
4.7
0.01
0.01
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
µF
%
±1.5
EXTERNAL REFERENCE AT VREF (buffer disabled, VREF = 4.096V)
V
50mV
+
DD
2.5
12
Input Voltage Range
V
Input Current
200
20
350
µA
kΩ
µA
Input Resistance
Shutdown VREF Input Current
1.5
10
V
50mV
-
Buffer Disable Threshold
REFADJ
DD
V
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode
Capacitive Bypass at VREF
0
µF
External compensation mode
4.7
Reference-Buffer Gain
REFADJ Input Current
1.678
V/V
µA
±50
_______________________________________________________________________________________
3
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%, f
= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
unless otherwise noted. Typical values are at T = +25°C.)
DD
CLK
T
= T
to T
A
MIN
MAX, A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
–—– –———–
DIGITALINPUTS(DIN,SCLK,CS,SHDN)
V
2.4
V
V
DIN,SCLK, CS Input High Voltage
DIN,SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN Input High Voltage
SHDN Input Low Voltage
INH
MAX192
V
INL
0.8
V
HYST
0.15
V
I
V
= 0V or V
DD
±1
15
µA
pF
V
IN
IN
C
(Note 5)
IN
V
INH
V
- 0.5
DD
V
INL
0.5
4.0
V
I
µA
µA
V
SHDN Input Current, High
SHDN Input Current, Low
SHDN Input Mid Voltage
SHDN = V
INH
DD
I
-4.0
1.5
SHDN = 0V
INL
V
V
- 1.5
IM
DD
V
2.75
V
SHDN Voltage, Floating
SHDN = open
SHDN = open
FLT
SHDN Max Allowed Leakage,
Mid Input
-100
100
0.4
nA
V
DIGITAL OUTPUTS (DOUT, SSTRB)
I
= 5mA
SINK
Output Voltage Low
V
OL
I
= 16mA
0.3
SINK
Output Voltage High
V
OH
I
= 1mA
4
V
SOURCE
Three-State Leakage Current
Three-State Leakage Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
I
±10
15
µA
pF
CS = 5V
L
C
CS = 5V (Note 5)
OUT
V
DD
5 ±5%
1.5
30
V
Operating mode
Fast power-down
Full power-down
2.5
70
10
mA
Positive Supply Current
I
DD
µA
2
Positive Supply Rejection
(Note 9)
V
= 5V ±5%; external reference, 4.096V;
DD
PSR
±0.06
±0.5
mV
full-scale input
Note 1: Tested at V = 5.0V; single-ended, unipolar.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Grounded on-channel; sine wave applied to all off channels.
Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: The common-mode range for the analog inputs is from AGND to V
.
DD
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured at V + 5% and V - 5% only.
SUPPLY
SUPPLY
4
_______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
TIMING CHARACTERISTICS
(V = 5V ±5%, T = T
to T , unless otherwise noted.)
MAX
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.5
TYP
MAX
UNITS
µs
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
t
AZ
DS
DH
DO
t
100
ns
t
0
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
t
C
C
C
= 100pF
= 100pF
= 100pF
20
150
100
100
ns
LOAD
LOAD
LOAD
t
ns
DV
t
TR
ns
t
t
100
0
ns
CSS
ns
CSH
t
200
200
ns
CH
t
ns
CL
t
C
= 100pF
200
200
ns
SSTRB
LOAD
CS Fall to SSTRB Output Enable
t
External clock mode only, C
External clock mode only, C
Internal clock mode only
= 100pF
= 100pF
ns
ns
ns
SDV
LOAD
LOAD
(Note 5)
CS Rise to SSTRB Output
Disable (Note 5)
t
200
STR
SSTRB Rise to SCLK Rise
(Note 5)
t
0
SCK
Note 5: Guaranteed by design. Not subject to production testing.
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
POWER-SUPPLY REJECTION
vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
0.16
0.30
V
= +5V ±5%
2.456
DD
0.14
0.12
0.10
0.08
0.06
0.04
0.25
0.20
2.455
2.454
2.453
2.452
0.15
0.10
0.05
0
0.02
0
-0.05
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADCs
P in De s c rip t io n
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to
analog ground.
9, 13
AGND
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-
rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-
er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external
compensation mode.
MAX192
10
SHDN
Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.
Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an
input when used with a precision external reference.
11
VREF
12
14
REFADJ
DGND
Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to V
.
DD
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is
high.
15
DOUT
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D
conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. SSTRB is high impedance when CS is high
(external mode).
16
SSTRB
17
18
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
CS
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
19
20
SCLK
V
DD
Positive Supply Voltage, +5V ±5%
+3V
+5V
3k
C
3k
C
DOUT
DOUT
DOUT
DOUT
3k
3k
C
LOAD
LOAD
C
LOAD
LOAD
DGND
DGND
DGND
a) High-Z to V and V to V
OH
DGND
b) High-Z to V and V to V
OL
OH
OL
OL
OH
a) V to High-Z
b) V to High-Z
OL
OH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disabled Time
6
________________________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
18
19
CS
SCLK
CAPACITIVE DAC
VREF
INPUT
SHIFT
REGISTER
INT
CLOCK
17
10
DIN
COMPARATOR
CONTROL
LOGIC
INPUT
MUX
C
HOLD
SHDN
ZERO
HOLD
–
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
1
CH0
15
16
16pF
OUTPUT
SHIFT
REGISTER
DOUT
2
3
4
CH1
CH2
CH3
10k
R
S
SSTRB
C
ANALOG
INPUT
MUX
SWITCH
T/H
5
6
CH4
CH5
CLOCK
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
IN
SAR
ADC
7
8
CH6
CH7
T/H
SWITCH
OUT
20
14
REF
13
9
V
DD
AGND
AGND
≈ 1.65
A
+2.46V
REFERENCE
DGND
20k
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.
DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
12
11
REFADJ
VREF
MAX192
+4.096V
Figure 4. Equivalent Input Circuit
Figure 3. Block Diagram
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- (the select-
ed analog input, respectively) to AGND.
De t a ile d De s c rip t io n
The MAX192 uses a successive-approximation conver-
sion technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
fle xib le s e ria l inte rfa c e p rovid e s e a s y inte rfa c e to
mic rop roc e s s ors . No e xte rna l hold c a p a c itors a re
required. Figure 3 shows the block diagram for the
MAX192.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
P s e u d o -Diffe re n t ia l In p u t
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Fig ure 4). In single-e nd e d mod e , IN+ is inte rna lly
switched to CH0–CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer
to Tables 1 and 2 to configure the channels.
on C
as a sample of the signal at IN+.
HOLD
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
ne g a tive inp ut (IN-). In s ing le -e nd e d mod e , IN- is
simply AGND. This unbalances node ZERO at the input
of the comparator. The capacitive DAC adjusts during
the remainder of the conversion cycle to restore its
node ZERO to 0V within the limits of its resolution. This
a c tion is e q uiva le nt to tra ns fe rring a c ha rg e of
In differential mode, IN- and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
b le within ± 0.5LSB (± 0.1LSB for b e s t re s ults ) with
16pF x (V + - V -) from C to the binary-weighted
IN
IN
HOLD
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
_______________________________________________________________________________________
7
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
band of interest, anti-alias filtering is recommended.
See the data sheets for the MAX291–MAX297 filters.
Tra c k /Ho ld
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for single-ended
inputs, IN- is connected to AGND, and the converter
samples the “+” input. If the converter is set up for differ-
ential inputs, IN- connects to the “-” input, and the differ-
ence of IN+ - IN- is sampled. At the end of the conver-
s ion, the p os itive inp ut c onne c ts b a c k to IN+, a nd
An a lo g In p u t Ra n g e a n d In p u t P ro t e c t io n
Internal protection diodes, which clamp the analog
input to V and AGND, allow the channel input pins to
DD
swing from AGND - 0.3V to V
+ 0.3V without dam-
DD
age. However, for accurate conversions near full scale,
MAX192
the inputs must not exceed V by more than 50mV, or
DD
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
C
charges to the input signal.
HOLD
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acquisi-
tion time lengthens and more time must be allowed
between conversions. Acquisition time is calculated by:
The MAX192 can be configured for differential (unipolar
or bipolar) or single-ended (unipolar only) inputs, as
selected by bits 2 and 3 of the control byte (Table 3).
In the single-ended mode, set the UNI/BIP bit to unipolar.
In this mode, analog inputs are internally referenced to
t
= 9 (R + R ) 16pF
S IN
AZ
AGND, with a full-scale input range from 0V to V
.
REF
where R = 5kΩ, R = the source impedance of the
IN
S
input signal, and tAZ is never less than 1.5µs. Note that
source impedances below 5kW do not significantly affect
the AC performance of the ADC. Higher source imped-
ances can be used if an input capacitor is connected to
the analog inputs, as shown in Figure 5. Note that the
input capacitor forms an RC filter with the input source
impedance, limiting the ADC’s signal bandwidth.
In differential mode, both unipolar and bipolar settings
can be used. Choosing unipolar mode sets the differen-
tial input range at 0V to V . The output code is invalid
REF
(code zero) when a negative differential input voltage is
applied. Bipolar mode sets the differential input range to
±V
/ 2. Note that in this differential mode, the com-
REF
mon-mode input range includes both supply rails. Refer
to Tables 4a and 4b for input voltage ranges.
In p u t Ba n d w id t h
The ADC’s inp ut tra c king c irc uitry ha s a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
ra te b y us ing und e rs a mp ling te c hniq ue s . To a void
high-frequency signals being aliased into the frequency
Qu ic k Lo o k
To evaluate the analog performance of the MAX192
quickly, use Figure 5’s circuit. The MAX192 requires a
c ontrol b yte to b e writte n to DIN b e fore e a c h
conversion. Tying DIN to +5V feeds in control bytes of
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
8
_______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
Table 2. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
–
+
–
+
–
+
+
Table 3. Control-Byte Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
Bit
Name
Description
7(MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion.
See Tables 1 and 2.
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar
mode, an analog input signal from 0V to VREF can be converted; in differential bipolar
mode, the differential signal can range from -VREF / 2 to +VREF / 2. Select differential
operation if bipolar mode is used.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In
single-ended mode, input signal voltages are referred to AGND. In differential mode,
the voltage difference between two channels is measured. Select unipolar operation
if single-ended mode is used. See Tables 1 and 2.
1
PD1
PD0
Selects clock and power-down modes.
0(LSB)
PD1
0
PD0
0
Mode
Full power-down (I = 2µA)
Q
0
1
Fast power-down (I = 30µA)
Q
1
1
0
1
Internal clock mode
External clock mode
_______________________________________________________________________________________
9
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
Example: Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
Table 4a. Unipolar Full Scale and Zero
Scale
ZERO
SCALE
REFERENCE
Internal Reference
FULL SCALE
1) Set up the control byte for external clock mode,
c a ll it TB1. TB1 s hould b e of the forma t:
1XXXXX11 binary, where the Xs denote the par-
ticular channel and conversion-mode selected.
0V
+4.096V
at REFADJ
at VREF
0V
V
(1.678)
REFADJ
External
Reference
MAX192
0V
V
REF
2) Use a general-purpose I/O line on the CPU to
pull CS on the MAX192 low.
Table 4b. Differential Bipolar Full Scale,
Zero Scale, and Negative Full Scale
NEGATIVE ZERO
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
REFERENCE
FULL SCALE
4) Tra ns mit a b yte of a ll ze ros ($00 HEX) a nd
simultaneously receive byte RB2.
FULL SCALE SCALE
Internal Reference
at
-4.096V / 2
0V
0V
0V
+4.096V / 2
5) Tra ns mit a b yte of a ll ze ros ($00 HEX) a nd
simultaneously receive byte RB3.
-1/2V
+1/2V
REFADJ
REFADJ
External
REFADJ
(1.678)
(1.678)
Reference
0.at VREF
6) Pull CS on the MAX192 high.
-1/2V
+1/2V
REF
REF
Figure 6 shows the timing for this sequence. Bytes RB2
a nd RB3 will c onta in the re s ult of the c onve rs ion
padded with one leading zero, two sub-LSB bits, and
three trailing zeros. The total conversion time is a func-
tion of the serial clock frequency and the amount of
dead time between 8-bit transfers. Make sure that the
total conversion time does not exceed 120µs, to avoid
excessive T/H droop.
$FF (HEX), which trigger single-ended conversions on
CH7 in external clock mode without powering down
b e twe e n c onve rs ions . In e xte rna l c loc k mod e , the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result comes
out of DOUT. Varying the analog input to CH7 should
alter the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs in differential mode, the
output is twos-complement (Figure 16). Data is clocked
out at the falling edge of SCLK in MSB-first format.
Ho w t o S t a rt a Co n ve rs io n
A conversion is started on the MAX192 by clocking
a control byte into DIN. Each rising edge on SCLK,
with CS low, clocks a bit from DIN into the MAX192’s
internal shift register. After CS falls, the first arriving
logic “1” bit defines the MSB of the control byte. Until
this first “start” bit arrives, any number of logic “0” bits
can be clocked into DIN with no effect. Table 3 shows
the control-byte format.
In t e rn a l a n d Ex t e rn a l Clo c k Mo d e s
The MAX192 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX192. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7 through 10
s how the timing c ha ra c te ris tic s c ommon to b oth
modes.
The MAX192 is compatible with Microwire, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 a nd CPHA = 0. Mic rowire a nd SPI b oth
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
10 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
V
DD
+5V
OSCILLOSCOPE
0.1µF
DGND
AGND
AGND
CS
SCLK
MAX192
SSTRB
DOUT*
0V TO
4.096V
ANALOG
INPUT
CH7
0.01µF
SCLK
DIN
CH4
2MHz
OSCILLATOR
CH3
CH1
CH2
+5V
DOUT
SSTRB
REFADJ
VREF
SHDN
N.C.
C2
0.01µF
C1
4.7µF
**
+2.5V
+2.5V
REFERENCE
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
**OPTIONAL. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.
Figure 5. Quick-Look Circuit
External Clock
Internal Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
p e riod a fte r the la s t b it of the c ontrol b yte .
Successive-approximation bit decisions are made and
appear at DOUT on each of the next 12 SCLK falling
edges (see Figure 6). The first 10 bits are the true data
bits, and the last two are sub-LSB bits.
In internal clock mode, the MAX192 generates its own
conversion clock internally. This frees the microproces-
sor from the burden of running the SAR conversion
clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
from zero to typically 10MHz. SSTRB goes low at the
start of the conversion and then goes high when the
conversion is complete. SSTRB will be low for a maxi-
mum of 10µs, during which time SCLK should remain
low for best noise performance. An internal register
stores data when the conversion is in progress. SCLK
clocks the data out at this register at any time after the
conversion is complete. After SSTRB goes high, the
next falling clock edge will produce the MSB of the
conversion at DOUT, followed by the remaining bits in
MSB-first format (Figure 9). CS does not need to be
held low once a conversion is started.
SSTRB and DOUT go into a high-impedance state when
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time, or
else droop on the sample -and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10µs, or if serial-clock interruptions
could cause the conversion interval to exceed 120µs.
______________________________________________________________________________________ 11
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
RB1
RB2
RB3
UNI/ SGL/
BIP DIF
DIN
START SEL2 SEL1 SEL0
PD1 PD0
MAX192
SSTRB
RB2
B6
RB3
RB1
FILLED WITH
ZEROS
B9
MSB
B0
LSB
DOUT
B8
B7
B5
B4
B3
B2
B1
S1
SO
ACQUISITION
CONVERSION
IDLE
IDLE
A/D STATE
1.5µs (CLK = 2MHz)
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
• • •
CS
t
t
CH
t
CSH
CSS
t
t
CL
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
DV
t
DO
t
TR
DOUT
• • •
Figure 7. Detailed Serial-Interface Timing
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as:
Pulling CS high prevents data from being clocked into
the MAX192 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
a lre a d y in p rog re s s . Whe n inte rna l c loc k mod e is
selected, SSTRB does not go into a high-impedance
state when CS goes high.
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after VDD is applied.
OR
The first high bit clocked into DIN after bit 3 of a
conversion in progress is clocked onto the DOUT pin.
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in
a nd out of the MAX192 a t c loc k ra te s e xc e e d ing
4.0MHz, provided that the minimum acquisition time,
If a falling edge on CS forces a start bit before bit 3
(B3) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX192 can run is 15 clocks per conver-
sion. Figure 11a shows the serial-interface timing nec-
essary to perform a conversion every 15 SCLK cycles
in external clock mode. If CS is low and SCLK is contin-
uous, guarantee a start bit by first clocking in 16 zeros.
t
, is kept above 1.5µs.
AZ
Da t a Fra m in g
The falling edge of CS does not start a conversion on
the MAX192. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on the falling edge of SCLK,
12 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
CS
• • •
• • •
t
t
STR
SDV
SSTRB
• • •
• • •
t
t
SSTRB
SSTRB
• • •
•
• • • •
SCLK
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
CS
SCLK
DIN
1
4
8
18
24
2
3
5
6
7
9
10
11
12
19
20
21
22
23
UNI/ SGL/
BIP DIF
START SEL2 SEL1 SEL0
PD1 PD0
SSTRB
t
CONV
FILLED WITH
ZEROS
B9
MSB
B0
LSB
DOUT
B8
B7
S1
S0
ACQUISITION CONVERSION
10µs MAX
IDLE
IDLE
A/D STATE
1.5µs (CLK = 2MHz)
Figure 9. Internal Clock Mode Timing
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX192. Figure 11b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
Re fe re n c e -Bu ffe r Co m p e n s a t io n
In addition to its shutdown function, the SHDN pin also
selects internal or external compensation. The compen-
sation affects both power-up time and maximum conver-
sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample-and-hold.
To select external compensation, float SHDN. See the
Typical Operating Circuit, which uses a 4.7µF capacitor
at VREF. A value of 4.7µF or greater ensures stability
and allows operation of the converter at the full clock
s p e e d of 2MHz. Exte rna l c omp e ns a tion inc re a s e s
power-up time (see the Choosing Power-Down Mode
section, and Table 5).
__________ Ap p lic a t io n s In fo rm a t io n
P o w e r-On Re s e t
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry will activate the
MAX192 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have been sta-
bilized, the internal reset time is 100µs and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT will shift out zeros.
Internal compensation requires no external capacitor at
VREF, and is selected by pulling SHDN high. Internal
compensation allows for shortest power-up times, but is
only available using an external clock and reduces the
maximum clock rate to 400kHz.
______________________________________________________________________________________ 13
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
CS
t
t
CONV
CSS
t
t
SCK
CSH
MAX192
SSTRB
t
SSTRB
SCLK
PD0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
CS
1
8
1
8
1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
DOUT
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
SCLK
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
B9 B8 B7 B6
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
14 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
CLOCK
MODE
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS FAST
POWER-DOWN
MODE
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
S X X X X X 0 1
S X X X X X 1 1
DOUT
DATA VALID
(10 + 2 DATA BITS)
DATA VALID
(10 + 2 DATA BITS)
VALID DATA INVALID
POWERED
UP
FULL
POWER-
DOWN
POWERED UP
POWERED UP
MODE
FAST
POWER-DOWN
Figure 12a. Timing Diagram Power-Down Modes, External Clock
CLOCK
MODE
INTERNAL CLOCK MODE
SETS FULL
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1 0
S X X X X X 0 0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
CONVERSION
FULL
POWER-DOWN
POWERED UP
POWERED
UP
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Fast power-down mode turns off all circuitry except the
bandgap reference. With the fast power-down mode, the
supply current is 30µA. Power-up time can be shortened
to 5µs in internal compensation mode.
P o w e r-Do w n
Choosing Power-Down Mode
You c a n s a ve p owe r b y p la c ing the c onve rte r in a
low-c urre nt s hutd own s ta te b e twe e n c onve rs ions .
Select full power-down or fast power-down mode via
bits 1 and 0 of the DIN control byte with SHDN either
high or floating (see Tables 3 and 6). Pull SHDN low at
any time to shut down the converter completely. SHDN
overrides bits 1 and 0 of DIN word (see Table 7).
In both software shutdown modes, the serial interface
remains operational, however, the ADC will not convert.
Table 5 illustrates how the choice of reference -buffer
c omp e ns a tion a nd p owe r-d own mod e a ffe c ts b oth
power-up delay and maximum sample rate.
Full power-down mode turns off all chip functions that
draw quiescent current, typically reducing IDD to 2µA.
In external compensation mode, the power-up time is
20ms with a 4.7µF compensation capacitor when the
capacitor is fully discharged. In fast power-down, you
can eliminate start-up time by using low-leakage capaci-
______________________________________________________________________________________ 15
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
Table 5. Worst-Case Power-Up Delay Times
Reference
Buffer
Reference-
Buffer
Compensation
Mode
VREF
Capacitor
(µF)
Power-
Down
Mode
Power-Up
Delay
(sec)
Maximum
Sampling
Rate (ksps)
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
External
Fast
Full
Fast
Full
Fast
Full
5µ
26
MAX192
300µ
26
4.7
4.7
See Figure 14c
133
133
133
133
See Figure 14c
2µ
2µ
Table 6. Software Shutdown and Clock
Mode
Table 7. Hard-Wired Shutdown and
Compensation Mode
PD1 PD0
Device Mode
SHDN
State
Device
Mode
Reference-Buffer
Compensation
1
1
0
0
1
0
1
0
External Clock Mode
Internal Clock Mode
Fast Power-Down Mode
Full Power-Down Mode
1
Floating
0
Enabled
Enabled
Internal Compensation
External Compensation
Full Power-Down N/A
tors that will not discharge more than 1/2LSB while shut
down. In shutdown, the capacitor has to supply the cur-
rent into the reference (1.5µA typ) and the transient cur-
rents at power-up.
Hardware Power-Down
The SHDN p in p la c e s the c onve rte r into the full
power-down mode. Unlike with the software shutdown
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low quies-
cent-current state. In internal clock mode, the interface
remains active and conversion results may be clocked
out while the MAX192 has already entered a software
power-down.
P o w e r-Do w n S e q u e n c in g
The MAX192 auto power-down modes can save con-
siderable power when operating at less than maximum
sample rates. The following discussion illustrates the
various power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following e xa mp le s illus tra te two d iffe re nt
power-down sequences. Other combinations of clock
rates, compensation modes, and power-down modes
may give lowest power consumption in other applica-
tions.
The first logical 1 on DIN will be interpreted as a start
bit, and powers up the MAX192. Following the start bit,
the data input word or control byte also determines
clock and power-down modes. For example, if the DIN
word contains PD1 = 1, then the chip will remain pow-
ered up. If PD1 = 0, a power-down will resume after
one conversion.
Figure 14a depicts the MAX192 power consumption for
one or e ig ht c ha nne l c onve rs ions utilizing full
power-down mode and internal reference compensa-
tion. A 0.01µF bypass capacitor at REFADJ forms an
16 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
COMPLETE CONVERSION SEQUENCE
2ms WAIT
0 1
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
1
1
1 1
1
0 0
FULLPD
1
0 1
FASTPD
FULLPD
2.5V
FASTPD
NOPD
REFADJ
VREF
0V
4V
0V
τ = RC = 20kΩ x C
REFADJ
t
≈ 15µs
BUFFEN
Figure 13. FULLPD/FASTPD Power-Up Sequence
FULL POWER-DOWN
FAST POWER-DOWN
1000
10,000
1 CHANNEL
8 CHANNELS
8 CHANNELS
100
1000
100
1 CHANNEL
10
2ms FASTPD WAIT
2MHz EXTERNAL CLOCK
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
EXTERNAL COMPENSATION
50µs WAIT
1
10
0
100
200
300
400
500
0
4k
8k
12k
16k
CONVERSIONS PER CHANNEL PER SECOND
CONVERSIONS PER CHANNEL PER SECOND
Figure 14a. Supply Current vs. Sample Rate/Second, FULLPD,
400kHz Clock
Figure 14b. Supply Current vs. Sample Rate/Second, FASTPD,
2MHz Clock
RC filter with the internal 20kΩ reference resistor with a
0.2ms time constant. To achieve full 10-bit accuracy,
10 time constants or 2ms are required after power-up.
Waiting 2ms in FASTPD mode instead of full power-up
will reduce the power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 13.
3.0
2.5
2.0
1.5
1.0
Lowest Power at Higher Throughputs
Fig ure 14b s hows the p owe r c ons ump tion with
external-reference compensation in fast power-down,
with one and eight channels converted. The external
4.7µF c omp e ns a tion re q uire s a 50µs wa it a fte r
p owe r-up , a c c omp lis he d b y 75 id le c loc ks a fte r a
d ummy c onve rs ion. This c irc uit c omb ine s fa s t
multi-channel conversion with lowest power consump-
tion p os s ib le . Full p owe r-d own mod e ma y p rovid e
increased power savings in applications where the
0.5
0
0.0001 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
______________________________________________________________________________________ 17
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
OUTPUT CODE
FULL-SCALE
OUTPUT CODE
TRANSITION
11 . . . 111
011 . . . 111
11 . . . 110
11 . . . 101
011 . . . 110
FS = +4.096
2
1LSB = +4.096
1024
MAX192
000 . . . 010
000 . . . 001
000 . . . 000
FS = +4.096V
1LSB = FS
1024
111 . . . 111
111 . . . 110
111 . . . 101
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0V
0
1
2
3
FS
-FS
+FS - 1LSB
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
DIFFERENTIAL INPUT VOLTAGE (LSBs)
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
Figure 16. Differential Bipolar Transfer Function,
±4.096V / 2 = Full Scale
MAX192 is inactive for long periods of time, but where
inte rmitte nt b urs ts of hig h-s p e e d c onve rs ions a re
required.
typ ic a lly 20kΩ. At VREF, the inp ut imp e d a nc e is a
minimum of 12kΩ for DC currents. During conversion,
an external reference at VREF must be able to deliver
up to 350µA DC loa d c urre nt a nd ha ve a n outp ut
impedance of 10Ω or less. If the reference has higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7µF capacitor.
Ex t e rn a l a n d In t e rn a l Re fe re n c e s
The MAX192 can be used with an internal or external
reference. Diode D1 shown in the Typical Operating
Circuit ensures correct start-up. Any standard signal
diode can be used. An external reference can either be
c onne c te d d ire c tly a t the VREF te rmina l or a t the
REFADJ pin.
Us ing the b uffe re d REFADJ inp ut a void s e xte rna l
buffering of the reference. To use the direct VREF input,
disable the internal buffer by tying REFADJ to VDD
.
The MAX192’s internally trimmed 2.46V reference is
buffered with a gain of 1.678 to scale an external 2.5V
reference at REFADJ to 4.096V at VREF.
Tra n s fe r Fu n c t io n a n d Ga in Ad ju s t
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the differ-
e ntia l b ip ola r inp ut/outp ut tra ns fe r func tion. Cod e
transitions occur halfway between successive integer
LS B va lu e s . O u tp u t c o d in g is b in a ry with
1LSB = 4.00mV (4.096V / 1024) for unipolar operation
and 1LSB = 4.00mV [(4.096V / 2 - -4.096V / 2)/1024]
for bipolar operation.
Internal Reference
The full-scale range of the MAX192 with internal reference
is 4.096V with unipolar inputs, and ±2.048V with differen-
tial bipolar inputs. The internal reference voltage is
adjustable to ±1.5% with the Reference-Adjust Circuit of
Figure 17.
Figure 17, the Reference-Adjust Circuit, shows how to
adjust the ADC gain in applications that use the internal
reference. The circuit provides ±1.5% (±15LSBs) of
gain adjustment range.
External Reference
An e xte rna l re fe re nc e c a n b e p la c e d a t e ithe r the
input (REFADJ) or the output (VREF) of the internal
b uffe r a mp lifie r. The REFADJ inp ut imp e d a nc e is
18 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
+5V
SUPPLIES
MAX192
REFADJ
+5V
GND
510k
100k
12
R* = 10Ω
0.01µF
24k
V
DD
AGND
DGND
+5V DGND
DIGITAL
CIRCUITRY
MAX192
* OPTIONAL
Figure 17. Reference-Adjust Circuit
Figure 18. Power-Supply Grounding Connection
La yo u t , Gro u n d in g , Byp a s s in g
For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Hig h -S p e e d Dig it a l In t e rfa c in g
The MAX192 can interface with QSPI at high through-
put rates using the circuit in Figure 19. This QSPI circuit
can be programmed to do a conversion on each of the
eight channels. The result is stored in memory without
ta xing the CPU s inc e QSPI inc orp ora te s its own
micro-sequencer.
Figure 18 shows the recommended system ground
c onne c tions . A s ing le -p oint a na log g round (“s ta r”
ground point) should be established at AGND, sepa -
rate from the logic ground. All other analog grounds
and DGND should be connected to this ground. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low imped-
ance and as short as possible for noise-free operation.
Fig ure 20 d e ta ils the c od e tha t s e ts up QSPI for
autonomous operation. In external clock mode, the
MAX192 performs a single-ended, unipolar conversion
on each of the eight analog input channels. Figure 21
shows the timing associated with the assembly code of
Figure 20. The first byte clocked into the MAX192 is the
control byte, which triggers the first conversion on CH0.
The last two bytes clocked into the MAX192 are all
zero, and clock out the results of the CH7 conversion.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
0.1µF a nd 4.7µF b yp a s s c a p a c itors c los e to the
MAX192. Minimize capacitor lead lengths for best sup-
ply-noise rejection. If the +5V power supply is very
noisy, a 10Ω resistor can be connected as a lowpass
filter, as shown in Figure 18.
______________________________________________________________________________________ 19
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
+5V
V
, V , V
, V
DDI DDE DDSYN STBY
1
2
20
19
18
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
SHDN
V
DD
0.1µF
4.7µF
SCLK
CS
SCK
3
4
PCS0
MOSI
MAX192
MC68HC16
ANALOG
INPUTS
DIN 17
16
MAX192
5
6
SSTRB
15
MISO
DOUT
7
DGND 14
13
8
AGND
9
12
11
REFADJ
VREF
0.01µF
10
+
4.7µF
0.1µF
V
SSI
V
SSE
* CLOCK CONNECTIONS NOT SHOWN
Figure 19. MAX192 QSPI Connection
TMS320 to MAX192 Interface
Figure 22 shows an application circuit to interface the
MAX192 to the TMS320 in external clock mode. The
timing diagram for this interface circuit is shown in
Figure 23.
4) The SSTRB output of the MAX192 is monitored via
the FSR input of the TMS320. A falling edge on the
SSTRB output indicates that the conversion is in
progress and data is ready to be received from
the MAX192.
Use the following steps to initiate a conversion in the
MAX192 and to read the results:
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10-bit conversion result and two sub-
LSBs, followed by four trailing bits, which should
be ignored.
1) The TMS320 s hould b e c onfig ure d with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR of the TMS320 are
tied together with the SCLK input of the MAX192.
6) Pull CS high to disable the MAX192 until the next
conversion is initiated.
2) The MAX192 CS is driven low by the XF_ I/O port
of the TMS320 to enable data to be clocked into
DIN of the MAX192.
3) An 8-bit word (1XXXXX11) should be written to the
MAX192 to initiate a conversion and place the
device into external clock mode. Refer to Table 3
to select the proper XXXXX bit values for your spe-
cific application.
20 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
* Description :
*
*
*
*
This is a shell program for using a stand-alone 68HC16 without any external memory. The internal 1K RAM
is put into bank $0F to maintain 68HC11 code compatibility. This program was written with software
provided in the Motorola 68HC16 Evaluation Kit.
* Roger J.A. Chen, Applications Engineer
* MAXIM Integrated Products
* November 20, 1992
*
******************************************************************************************************************************************************
INCLUDE
INCLUDE
INCLUDE
ORG $0200
‘EQUATES.ASM’ ;Equates for common reg addrs
‘ORG00000.ASM’ ;initialize reset vector
‘ORG00008.ASM’ ;initialize interrupt vectors
;start program after interrupt vectors
INCLUDE ‘INITSYS.ASM’
;set EK=F,XK=0,YK=0,ZK=0
;set sys clock at 16.78 MHz, COP off
INCLUDE ‘INITRAM.ASM’ ;turn on internal SRAM at $10000
;set stack (SK=1, SP=03FE)
MAIN:
JSR INITQSPI
MAINLOOP:
JSR READ192
WAIT:
LDAA SPSR
ANDA #$80
BEQ WAIT
BRA MAINLOOP
;wait for QSPI to finish
ENDPROGRAM:
INITQSPI:
;This routine sets up the QSPI microsequencer to operate on its own.
;The sequencer will read all eight channels of a MAX192 each time
;it is triggered. The A/D converter results will be left in the
;receive data RAM. Each 16 bit receive data RAM location will
;have a leading zero, 10 + 2 bits of conversion result and three zeros.
;
;Receive RAM Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
;A/D Result
0
MSB
LSB 0 0 0
***** Initialize the QSPI Registers ******
PSHA
PSHB
LDAA #%01111000
STAA QPDR
;idle state for PCS0-3 = high
LDAA #%01111011
STAA QPAR
LDAA #%01111110
STAA QDDR
;assign port D to be QSPI
;only MISO is an input
LDD #$8008
STD SPCR0
;master mode,16 bits/transfer,
;CPOL=CPHA=0,1MHz Ser Clock
LDD #$0000
STD SPCR1
;set delay between PCS0 and SCK,
;set delay between transfers
Figure 20. MAX192 Assembly-Code Listing
______________________________________________________________________________________ 21
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
LDD #$0800
STD SPCR2
;set ENDQP to $8 for 9 transfers
***** Initialize QSPI Command RAM *****
LDAA #$80
STAA $FD40
LDAA #$C0
STAA $FD41
STAA $FD42
STAA $FD43
STAA $FD44
STAA $FD45
STAA $FD46
STAA $FD47
LDAA #$40
STAA $FD48
;CONT=1,BITSE=0,DT=0,DSCK=0,PCS0=ACTIVE
;store first byte in COMMAND RAM
;CONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
MAX192
;CONT=0,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
***** Initialize QSPI Transmit RAM *****
LDD #$008F
STD $FD20
LDD #$00CF
LDD #$009F
LDD #$00DF
LDD #$00AF
LDD #$00EF
LDD #$00BF
LDD #$00FF
LDD #$0000
STD $FD22
STD $FD24
STD $FD26
STD $FD28
STD $FD2A
STD $FD2C
STD $FD2E
STD $FD30
PULB
PULA
RTS
READ192:
;This routine triggers the QSPI microsequencer to autonomously
;trigger conversions on all 8 channels of the MAX192. Each
;conversion result is stored in the receive data RAM.
PSHA
LDAA #$80
ORAA SPCR1
STAA SPCR1
PULA
;just set SPE
RTS
***** Interrupts/Exceptions *****
BDM: BGND
;exception vectors point here
;and put the user in background debug mode
Figure 20. MAX192 Assembly-Code Listing (continued)
22 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
MAX192
CS
• • • •
• • • •
SCLK
SSTRB
DIN
• • • •
• • • •
Figure 21. QSPI Assembly-Code Timing
XF
CLKX
CLKR
DX
CS
SCLK
TMS320
MAX192
DIN
DR
DOUT
SSTRB
FSR
Figure 22. MAX192 to TMS320 Serial Interface
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
HIGH
IMPEDANCE
DOUT
MSB
B10
S1
S0
Figure 23. TMS320 Serial-Interface Timing Diagram
______________________________________________________________________________________ 23
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 0 -Bit ADC
Typ ic a l Op e ra t in g Circ u it
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2278
+5V
V
DD
V
CH0
CH7
DD
C3
0.1µF
0V to
4.096V
DGND
C4
0.1µF
ANALOG
INPUTS
1
AGND
AGND
CPU
MAX192
I/O
CS
SCLK
SCK (SK)*
MOSI (SO)
MISO (SI)
VREF
DIN
C1
4.7µF
DOUT
SSTRB
SHDN
REFADJ
V
SS
C2
0.01µF
P a c k a g e In fo rm a t io n
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
ENGL ISH • ? ? ? ? • ? ? ? • ? ? ?
WH AT 'S NEW
PR OD UC TS
SO LUTI ONS
D ES IG N
A PPNOTES
SU PPORT
B U Y
COM PA N Y
M EMB ERS
M A X 1 9 2
Pa rt Nu m ber T abl e
N o t e s :
1 . S e e t h e M A X 1 9 2 Q u i c k V i e w D a t a S h e e t f o r f u r t h e r i n f o r m a t i o n o n t h i s p r o d u c t f a m i l y o r d o w n l o a d t h e M A X 1 9 2
f u l l d a t a s h e e t ( P D F , 2 1 6 k B ) .
2 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
3 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n o n e
b u s i n e s s d a y .
4 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e f u l l
d a t a s h e e t o r P a r t N a m i n g C o n v e n t i o n s .
5 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e p r o d u c t
u s e s .
P a r t N u m b e r
F r e e
S a m p l e
B u y
D i r e c t
T e m p
R o H S / L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : T Y P E P I N S S I Z E
D R A W I N G C O D E / V A R *
M A X 1 9 2 B C P P +
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 + 3 *
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A C P P +
M A X 1 9 2 B C P P
M A X 1 9 2 A C P P
M A X 1 9 2 B E P P +
M A X 1 9 2 A E P P
M A X 1 9 2 B E P P
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 + 3 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 - 3 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 - 3 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 + 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 - 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 - 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A E P P +
M A X 1 9 2 A C W P +
M A X 1 9 2 B C W P
P D I P ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 2 0 + 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 B C W P - T
M A X 1 9 2 A C W P + T
M A X 1 9 2 B C W P + T
M A X 1 9 2 A C W P - T
M A X 1 9 2 A C W P
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 B C W P +
M A X 1 9 2 B E W P +
M A X 1 9 2 B E W P + T
M A X 1 9 2 B E W P - T
M A X 1 9 2 B E W P
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A E W P +
M A X 1 9 2 A E W P + T
M A X 1 9 2 A E W P - T
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 + 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A E W P
S O I C ; 2 0 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 2 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : W 2 0 - 3 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A C A P - G 0 0 2
M A X 1 9 2 A C A P - T G 0 0 2
M A X 1 9 2 B C A P
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 B C A P + T
M A X 1 9 2 B C A P +
M A X 1 9 2 A C A P
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A C A P - T
M A X 1 9 2 B C A P - T
M A X 1 9 2 A C A P +
M A X 1 9 2 A C A P + T
M A X 1 9 2 B E A P + T
M A X 1 9 2 B E A P +
M A X 1 9 2 B E A P
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A E A P +
M A X 1 9 2 A E A P
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 9 2 A E A P - T
M A X 1 9 2 A E A P + T
M A X 1 9 2 B E A P - T
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S S O P ; 2 0 p i n ; . 2 0 9 "
D w g : 2 1 - 0 0 5 6 C ( P D F )
U s e p k g c o d e / v a r i a t i o n : A 2 0 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
D i d n ' t F i n d W h a t Y o u N e e d ?
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
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