MAX1937EEI [MAXIM]
Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change; 双相，台式机CPU核电源控制器，带有受控的VID调节
| 型号： | MAX1937EEI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change |
| 文件： | 总24页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2498; Rev 1; 10/02
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
General Description
Features
The MAX1937/MAX1938/MAX1939 comprise a family of
synchronous, two-phase, step-down controllers capable
of delivering load currents up to 60A. The controllers uti-
lize Quick-PWM™ control architecture in conjunction with
active load-current voltage positioning. Quick-PWM con-
trol provides instantaneous load-step response, while
programmable voltage positioning allows the converter
to utilize full transient regulation limits, reducing the out-
put capacitance requirement. The two phases operate
180° out-of-phase with an effective 500kHz switching fre-
quency, thus reducing input and output current ripple, as
well as reducing input filter capacitor requirements.
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The MAX1937/MAX1938/MAX1939 are compliant with
AMD Hammer, Intel ‚ Voltage-Regulator Module (VRM)
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9.0/9.1, and AMD Athlon™ Mobile VID code specifica-
tions (see Table 1 for VID codes). The internal DAC pro-
vides ultra-high accuracy of 0.75ꢀ. A controlled VID
voltage transition is implemented to minimize both
undervoltage and overvoltage overshoot during VID
input change.
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Remote sensing is available for high output-voltage
accuracy. The MOSFET switches are driven by a 6V
gate-drive circuit to minimize switching and crossover
conduction losses to achieve efficiency as high as
90ꢀ. The MAX1937/MAX1938/MAX1939 feature cycle-
by-cycle current limit to ensure that the current limit is
not exceeded. Crowbar protection is available to pro-
tect against output overvoltage.
Ordering Information
PꢂRT
TEMP%RꢂNGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PꢂCKꢂGE
28 QSOP
MꢂX193.EEI
MꢂX1938EEI
MꢂX1939EEI
28 QSOP
28 QSOP
Applications
Notebook and Desktop Computers
Servers and Workstations
Blade Servers
Pin Configuration
TOP VIEW
VID0
VID1
TIME
VID2
VID3
VID4
VPOS
1
2
3
4
5
6
7
8
9
28 V
CC
High-End Switches
27 BST1
26 DH1
25 LX1
High-End Routers
Macro Base Stations
24 CS1
23 DL1
22 VLG
21 PGND
20 DL2
19 CS2
18 LX2
MAX1937
MAX1938
MAX1939
V
DD
ILIM
Typical Application Circuits and Functional Diagram appear
at end of data sheet.
GND 10
GNDS 11
REF 12
EN 13
17 DH2
16 BST2
15 PWRGD
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Athlon is a trademark of Advanced Micro Devices, Inc.
Intel is a registered trademark of Intel Corp.
FB 14
QS P
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
ꢂBS LUTE%MꢂXIMUM%RꢂTINGS
V
V
to GND............................................................-0.3V to +28V
, PWRGD, ILIM, FB to GND ...............................-0.3V to +6V
EN, GNDS, VPOS, REF, VID_,
DH1 to LX1.................................................-0.3V to V
DH2 to LX2.................................................-0.3V to V
DL1, DL2 to PGND ......................................-0.3V to V
+ 0.3V
+ 0.3V
+ 0.3V
CC
DD
BST1
BST2
VLG
TIME to GND ............................................0.3V to V
+ 0.3V
Continuous Power Dissipation (T = +70°C)
A
VDD
PGND to GND .......................................................-0.3V to +0.3V
CS1, CS2 to GND......................................................-2V to +28V
VLG to GND..............................................................-0.3V to +7V
BST1, BST2 to GND ...............................................-0.3V to +35V
LX1 to BST1..............................................................-7V to +0.3V
LX2 to BST2..............................................................-7V to +0.3V
28-Pin QSOP (derate 20.8mW/°C above +70°C)......860.2mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICꢂL%CHꢂRꢂCTERISTICS
(V
= 12V, V
= V
= 5V, PGND = GNDS = GND = 0, VID_ = GND, C
= 47pF, C
= 0.1µF, V = 1V, T =%±°C%uV
ILIM ꢂ
CC
EN
VDD
VPOS
REF
+87°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
GENERAL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1937
6
8
24
24
V
V
Operating Range
Operating Range
V
CC
MAX1938/MAX1939
4.5
4.5
5
5.5
6.5
40
V
V
DD
VLG Operating Range
V
> V
VLG VDD
V
V
Operating Supply Current
Operating Supply Current
FB above threshold (no switching)
FB above threshold (no switching)
FB above threshold (no switching)
EN = GND
20
µA
mA
µA
µA
µA
µA
V
CC
DD
1.4
2.5
60
VLG Operating Supply Current
20
V
V
Shutdown Current
Shutdown Current
<1
50
5
CC
DD
EN = GND, VID_ not connected
EN = GND
100
5
VLG Shutdown Current
TIME Output Voltage
ILIM Input Bias
<1
1.96
-250
2.00
2.04
+250
V
= 1.5V
nA
ILIM
CS_= GND, VPOS connected to REF through a 75kΩ
resistor
VPOS Output Voltage
1.96
2.0
2.04
V
V
REFERENCE
Reference Voltage
SOFT-START
-50µA ≤ I
≤ 50µA
1.987
2.000
2.013
REF
MAX1937
MAX1938
MAX1939
1.1
1.5
1.3
5.5
6.2
6.5
Ramp Period
ms
mV
Soft-Start Voltage Step
ERROR AMPLIFIER
FB Input Resistance
25
Resistance from FB to GND
180
kΩ
GNDS Input Bias Current
-5
+5
µA
Output Regulation Voltage
Accuracy
-0.75
+0.75
%
2
_______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
ELECTRICAL CHARACTERISTICS (continued)
(V
= 12V, V
= V
= 5V, PGND = GNDS = GND = 0, VID_ = GND, C
= 47pF, C
= 0.1µF, V = 1V, T = 0°C to
ILIM A
CC
EN
VDD
VPOS
REF
+85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
4.45
4.45
UNITS
FAULT PROTECTION
V
Undervoltage Lockout
(UVLO) Threshold
DD
Rising or falling V
4.00
4.00
4.25
V
DD
V
UVLO Hysteresis
80
mV
V
DD
VLG UVLO Threshold
VLG UVLO Hysteresis
Thermal Shutdown
Rising or falling VLG
4.25
40
mV
°C
Rising temperature, typical hysteresis = 15°C
160
Rising edge
Falling edge
1.600
1.584
2.00
2.250
Reference UVLO Threshold
V
V
MAX1937/MAX1938
Rising and falling
1.97
2.03
Output Overvoltage Fault
Threshold
MAX1939
2.215
2.285
Rising and falling percentage of the nominal
regulation voltage
Output UVLO Threshold
65
70
75
%
CURRENT LIMIT
PGND to CS_, V
PGND to CS_, V
PGND to CS_, V
CS_ = GND
= 1.5V
= 1V
135
90
45
-3
150
100
50
165
110
55
ILIM
ILIM
ILIM
Current-Limit Threshold
mV
= 0.5V
CS Input Offset Voltage
CS_ Input Bias Current
VOLTAGE POSITIONING
VPOS Input Offset Voltage
VPOS Gain
+3
mV
µA
CS_ = GND
-5
+5
-3
+3
mV
From CS_ to FB; V
, V
CS1 CS2
= 0, -100mV; R
= 75kΩ
VPOS
72.5
75.0
75
77.5
%/V
From CS1, CS2 to FB; V
, V
= +13mV, -113mV;
CS1 CS2
VPOS Gain
68
82
%/V
R
= 75kΩ
VPOS
TIMER AND DRIVERS
On-Time
LX1 = LX2 = CS1 = CS2 = GND, V = 1.5V
FB
420
260
525
325
60
630
390
ns
ns
Minimum Off-Time
DH1 low to DH2 high, and DH2 low to DH1 high
MAX1937/MAX1938
DH_ low to DL_ high
MAX1939
60
Break-Before-Make Time
ns
MAX1937/MAX1938
DL_ low to DH_ high
85
MAX1939
70
_______________________________________________________________________________________
3
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
ELECTRICAL CHARACTERISTICS (continued)
(V
= 12V, V
= V
= 5V, PGND = GNDS = GND = 0, VID_ = GND, C
= 47pF, C
= 0.1µF, V = 1V, T = 0°C to
ILIM A
CC
EN
VDD
VPOS
REF
+85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
DH_ On-Resistance in Low State
DH_ On-Resistance in High State
DL_ On-Resistance in Low State
DL_ On-Resistance in High State
BST_ Leakage Current
LX_ Leakage Current
CONDITIONS
= 6V, LX1 = LX2 = GND
BST2
MIN
TYP
MAX
3.0
3.0
1.7
3.0
50
UNITS
Ω
V
V
= V
1.5
1.5
0.5
1.5
BST1
BST_
= 6V, LX_ = GND
Ω
Ω
Ω
V
V
= 30V, V
= 30V, V
= 24V
= 24V
µA
µA
BST_
BST_
LX_
50
LX_
EN AND VID
Low Level Threshold
0.8
V
V
High Level Threshold
1.6
Pullup Resistance
Internally pulled up to V
50
100
200
kΩ
DD
PWRGD
PWRGD Upper Trip Level
PWRGD Lower Trip Level
Output Low Level
10.0
-15
12.5
15.0
-10
0.4
1
%
%
V
-12.5
Output High Leakage
CONTROLLED VID CHANGE
µA
R
R
R
= 120kΩ
= 47kΩ
6.17
2.35
23.5
38
6.67
2.63
26.3
7.25
2.99
29.9
380
350
TIME
TIME
TIME
On-the-Fly VID Change Slew
Rate
25mV per step
µs
= 470kΩ
VID_ Change Frequency Range
PWRGD Blanking Time
kHz
µs
V
= 4.5V to 5.5V
125
200
VDD
4
_______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
ELECTRICAL CHARACTERISTICS
(V
= 12V, V = V
= 5V, PGND = GNDS = GND, VID_= GND, C
= 47pF, C
= 0.1µF, V = 1V, T = -40°C to +85°C,
ILIM A
VCC
EN
VDD
VPOS
REF
unless otherwise noted.) (Note 1)
PARAMETER
GENERAL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1937
6
24
24
V
V
Operating Range
Operating Range
V
CC
MAX1938/MAX1939
8
4.5
4.5
5.5
6.5
40
V
V
DD
VLG Operating Range
V
≥ V
VLG VDD
V
V
Operating Supply Current
Operating Supply Current
FB above threshold (no switching)
FB above threshold (no switching)
FB above threshold (no switching)
EN = GND
µA
mA
µA
µA
µA
µA
V
CC
DD
2.5
60
VLG Operating Supply Current
20
V
V
Shutdown Current
Shutdown Current
5
CC
DD
EN = GND, VID_ not connected
EN = GND
100
5
VLG Shutdown Current
TIME Output Voltage
ILIM Input Bias
1.96
-250
2.04
+250
V
= 1V
nA
ILIM
CS_ = GND, VPOS connected to REF through a 75kΩ
resistor
VPOS Output Voltage
1.96
2.04
V
V
REFERENCE
Reference Voltage
SOFT-START
-50µA ≤ I
≤ 50µA
REF
1.98
2.02
MAX1937
MAX1938
MAX1939
1.1
1.5
1.3
5.5
6.6
7.0
Ramp Period
ms
ERROR AMPLIFIER
GNDS Input Bias Current
-5
-1
+5
+1
µA
%
Output Regulation Voltage
Accuracy
FAULT PROTECTION
V
UVLO Threshold
Rising or falling V
4.00
4.45
V
V
V
DD
DD
VLG UVLO Threshold
Rising or falling VLG
Rising and falling
4.00
1.97
4.45
2.03
MAX1937/MAX1938
MAX1939
Output Overvoltage Fault
Threshold
2.215
2.285
Rising and falling percentage of the nominal
regulation voltage
Output UVLO Threshold
65
75
%
CURRENT LIMIT
PGND to CS_, V
PGND to CS_, V
PGND to CS_, V
= 1.5V
= 1V
135
90
165
110
55
ILIM
ILIM
ILIM
Current-Limit Threshold
mV
= 0.5V
45
_______________________________________________________________________________________
5
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
ELECTRICAL CHARACTERISTICS (continued)
(V
= 12V, V = V
= 5V, PGND = GNDS = GND, VID_= GND, C
= 47pF, C
= 0.1µF, V = 1V, T = -40°C to +85°C,
ILIM A
VCC
EN
VDD
VPOS
REF
unless otherwise noted.) (Note 1)
PARAMETER
CS Input Offset Voltage
CS_ Input Bias Current
VOLTAGE POSITIONING
VPOS Input Offset Voltage
VPOS Gain
CONDITIONS
MIN
-5
TYP
MAX
+5
UNITS
mV
CS_ = GND
CS_ = GND
-5
+5
µA
-5
+5
mV
From CS_ to FB; V
, V
= 0, -100mV; R
= 75kΩ
VPOS
72.5
77.5
%/V
CS1 CS2
From CS1, CS2 to FB; V
, V
CS1 CS2
= +13mV, -113mV;
VPOS Gain
68
82
%/V
R
= 75kΩ
VPOS
TIMER AND DRIVERS
On-Time
LX1 = LX2 = CS1 = CS2 = GND, V = 1.5V
FB
420
260
630
390
3
ns
ns
Ω
Minimum Off-Time
DH1 low to DH2 high, and DH2 low to DH1 high
DH_ On-Resistance in Low State
DH_ On-Resistance in High State
DL_ On-Resistance in Low State
DL_ On-Resistance in High State
BST_ Leakage Current
LX_ Leakage Current
V
V
= V
= 6V, LX1 = LX2 = GND
BST2
BST1
BST_
= 6V, LX_ = GND
3
Ω
1.7
3
Ω
Ω
V
V
= 30V, V
= 30V, V
= 24V
= 24V
50
50
µA
µA
BST_
BST_
LX_
LX_
EN AND VID_
Low Level Threshold
0.8
V
V
High Level Threshold
Pullup Resistance
1.6
50
Internally pulled up to V
200
kΩ
DD
PWRGD
PWRGD Upper Trip Level
PWRGD Lower Trip Level
Output Low Level
10
15
-10
0.4
1
%
%
V
-15
Output High Leakage
CONTROLLED VID CHANGE
µA
R
R
R
= 120kΩ
= 47kΩ
6.17
2.35
23.5
38
7.25
2.99
29.9
380
350
TIME
TIME
TIME
On-the-Fly VID Change Slew
Rate
25mV per step
µs
= 470kΩ
VID_ Change Frequency Range
PWRGD Blanking Time
kHz
µs
V
= 4.5V to 5.5V
125
VDD
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
6
_______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Typical Operating Characteristics
(V = 12V, V
IN
= 1.45V, T = +25°C, unless otherwise noted.)
A
OUT
EFFICIENCY vs. LOAD CURRENT
AT 1.85V OUTPUT
EFFICIENCY vs. LOAD CURRENT
AT 1.45V OUTPUT
FREQUENCY vs. LOAD CURRENT
350
300
250
200
150
100
50
90
80
70
60
50
90
80
70
60
50
V
= 8V
IN
V
= 12V
IN
V
= 14V
IN
V
= 12V
IN
V
= 14V
IN
V
IN
= 8V
V
V
= 12V
IN
V
= 1.45V
V
= 1.85V
OUT
OUT
= 1.45V
OUT
0
0
10
20
30
40
50
60
1
10
100
1
10
LOAD CURRENT (A)
100
LOAD CURRENT (A)
LOAD CURRENT (A)
FREQUENCY vs. INPUT VOLTAGE
FREQUENCY vs. TEMPERATURE
325
300
275
250
225
200
175
260
255
250
245
240
235
230
225
220
I
= 46A
LOAD
I
= 1A
LOAD
V
V
I
= 12V
IN
= 1.45V
= 10A
OUT
LOAD
V
= 1.45V
9
OUT
150
8
10
11
12
13
14
-40 -20
0
20
40
60
80 100
INPUT VOLTAGE (V)
TEMPERATURE (°C)
V
INPUT CURRENT
CC
vs. INPUT VOLTAGE
V
CURRENT vs. V VOLTAGE
DD DD
25
20
15
10
5
1.80
1.75
1.70
1.65
1.60
1.55
1.50
V
= 1.45V
OUT
0
8
9
10
11
12
13
14
4.5
4.7
4.9
5.1
5.3
5.5
INPUT VOLTAGE (V)
V
VOLTAGE (V)
DD
_______________________________________________________________________________________
7
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Typical Operating Characteristics (continued)
(V = 12V, V
IN
= 1.45V, T = +25°C, unless otherwise noted.)
A
OUT
OUTPUT VOLTAGE vs. LOAD CURRENT
AT 1.45V OUTPUT
V
CURRENT vs. V VOLTAGE
DD
DD
IN SHUTDOWN
1.450
1.425
1.400
1.375
1.350
70
65
60
55
50
45
40
35
30
R
= 90.9kΩ
VPOS
R
= 120kΩ
VPOS
VID_ NOT CONNECTED
V
= 12V
10
IN
0
20
30
40
50
4.5
4.7
4.9
5.1
5.3
5.5
LOAD CURRENT (A)
V
VOLTAGE (V)
DD
CURRENT SHARING
CURRENT SHARING
30
25
20
15
10
5
30
25
20
15
10
5
V
V
A
= 12V
OUT
= +25°C
V
= 12V
IN
OUT
= +80°C
IN
= 1.45V
V
= 1.45V
0
0
T
T
A
-5
-5
0
10
20
30
40
50
0
10
20
30
40
50
LOAD CURRENT (A)
LOAD CURRENT (A)
INDUCTOR CURRENT WAVEFORMS
WITH 0A LOAD
INDUCTOR CURRENT WAVEFORMS
WITH 40A LOAD
MAX1937 toc12
MAX1937 toc13
OUTPUT RIPPLE
VOLTAGE:
20mV/div
OUTPUT RIPPLE
VOLTAGE:
20mV/div
OUTPUT INDUCTOR
CURRENTS:
10A/div
OUTPUT INDUCTOR
CURRENTS:
0A
0A
10A/div
V
= 12V
IN
V
= 1.45V
OUT
= 40A
V
V
= 12V
OUT
= 0A
IN
I
OUT
= 1.45V
I
OUT
2µs/div
2µs/div
8
_______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Typical Operating Characteristics (continued)
(V = 12V, V
IN
= 1.45V, T = +25°C, unless otherwise noted.)
OUT
A
LOAD TRANSIENT
1A TO 40A TO 1A
SOFT-START WAVEFORMS
WITH NO LOAD
MAX1937 toc14
MAX1937 toc15
POK SIGNAL
OUTPUT VOLTAGE:
50mV/div
OUTPUT VOLTAGE:
0.5V/div
INDUCTOR CURRENTS:
10A/div
INDUCTOR CURRENT:
10A/div
TRANSIENT CONTROL
SIGNAL:
C6 = 47pF
ENABLE SIGNAL
R2 = 91.1kΩ
40µs/div
1ms/div
SHUTDOWN WAVEFORM
WITH NO LOAD
SOFT-START WAVEFORMS
WITH 40A LOAD
MAX1937 toc16
MAX1937 toc17
POK SIGNAL
POK SIGNAL
OUTPUT VOLTAGE:
0.5V/div
OUTPUT VOLTAGE:
0.5V/div
INDUCTOR CURRENT:
10A/div
INDUCTOR CURRENT:
10A/div
ENABLE SIGNAL
ENABLE SIGNAL
1ms/div
20ms/div
SHUTDOWN WAVEFORM
WITH 40A LOAD
CURRENT-SENSE THRESHOLD vs. V
ILIM
MAX1937 toc18
160
140
120
100
80
POK SIGNAL
T
= +80°C
A
OUTPUT VOLTAGE:
0.5V/div
INDUCTOR CURRENT:
10A/div
T
= +25°C
A
60
V
V
= 12V
OUT
IN
ENABLE SIGNAL
= 1.45V
40
20ms/div
0.5
0.7
0.9
1.1
1.3
1.5
V
(V)
ILIM
_______________________________________________________________________________________
9
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Typical Operating Characteristics (continued)
(V = 12V, V
IN
= 1.45V, T = +25°C, unless otherwise noted.)
A
OUT
VID CODE CHANGE ON-THE-FLY WITH 1A
VID CODE CHANGE ON-THE-FLY WITH 40A
LOAD 1.2V TO 1.45V TO 1.2V
LOAD 1.2V TO 1.45V TO 1.2V
MAX1937 toc21
MAX1937 toc20
POK SIGNAL
POK SIGNAL
OUTPUT VOLTAGE:
200mV/div
OUTPUT VOLTAGE:
200mV/div
VID CODE CHANGE
CONTROL SIGNAL
VID CONTROL
SIGNAL
40µs/div
40µs/div
REFERENCE VOLTAGE vs. TEMPERATURE
FB VOLTAGE vs. TEMPERATURE
2.000
1.998
1.996
1.994
1.992
1.990
0.810
0.805
0.800
0.795
0.790
V
= 0.8V
OUT
V
V
= 12V
OUT
NO LOAD
IN
= 1.45V
V
= 12V
IN
NO LOAD
-40 -20
0
20
40
60
80 100
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FB VOLTAGE vs. TEMPERATURE
1.465
1.460
1.455
1.450
1.445
V
= 1.45V
OUT
V
= 12V
IN
NO LOAD
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
10 ______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Pin Description
PIN
1
NAME
VID0
VID1
TIME
VID2
VID3
VID4
FUNCTION
Voltage Identification Input Bit 0. See Table 1. Internal 100kΩ pullup resistor to V
Voltage Identification Input Bit 1. See Table 1. Internal 100kΩ pullup resistor to V
.
.
DD
2
DD
3
Connect to an external resistor (47kΩ to 470kΩ) for VID change slew-rate control.
4
Voltage Identification Input Bit 2. See Table 1. Internal 100kΩ pullup resistor to V
Voltage Identification Input Bit 3. See Table 1. Internal 100kΩ pullup resistor to V
Voltage Identification Input Bit 4. See Table 1. Internal 100kΩ pullup resistor to V
.
.
.
DD
DD
DD
5
6
Voltage Positioning. Connect a resistor between VPOS and REF to set the output voltage-positioning
droop, or connect directly to REF for no output voltage positioning. Connect a 47pF capacitor from
VPOS to GND.
7
8
9
VPOS
V
IC Analog Power-Supply Input. Connect a 5V supply to V
.
DD
DD
Current-Limit Threshold per Phase. Connect ILIM to V
to set a default current limit of 120mV, or
DD
ILIM
connect to a voltage-divider from REF to GND to adjust the current limit. See the Setting the Current
Limit section.
10
11
GND
Ground
Remote Ground Sense. Connect GNDS to the output ground at the load. For VRM applications, also
connect a 100Ω resistor from GNDS to PGND locally.
GNDS
12
13
REF
EN
Reference Output. Connect a 0.1µF capacitor from REF to GND.
Enable Input. Leave unconnected or drive high for normal operation. Drive low for shutdown.
Remote Feedback Sense. Connect FB to the output at the load. For VRM applications, also connect
a 100Ω resistor from FB to the output locally.
14
FB
Power-Good Output. Open-drain output is high impedance when the output is in regulation and
pulled low when the output deviates more than 12.5% from the voltage set by the VID code. PWRGD
is also low in shutdown or during any fault condition. To use as a logic output, connect a pullup
resistor from PWRGD to the logic supply.
15
PWRGD
High-Side MOSFET Gate-Driver Bootstrap Input. Connect 0.22µF or higher value bypass capacitor
from BST2 to LX2. Keep trace length as short as possible. Connect a Schottky diode between BST2
and VLG. See the Selecting a BST Capacitor section.
16
BST2
High-Side MOSFET Gate-Drive Output. Connect to the high-side MOSFET gate. DH2 is pulled low in
shutdown.
17
18
19
DH2
LX2
CS2
Inductor Connection. Connect to the switched side of the inductor.
Negative Current-Sense Input. Connect to a current-sense resistor in series with the low-side
MOSFET, or connect to LX2 to use the low-side MOSFET’s on-resistance for current sensing.
Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL2 is pulled low in
shutdown.
20
21
DL2
Power Ground. Connect to power ground at the point where the current-sense resistors or low-side
MOSFET sources connect. PGND is used as the positive current-sense connection.
PGND
______________________________________________________________________________________ 11
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Pin Description (continued)
PIN
NAME
FUNCTION
DL_ Driver Power-Supply Input. Connect to a 4.5V to 6.5V supply for powering the low-side MOSFET
gate drive, and the bootstrap circuit for driving the high-side MOSFETs. Ensure that V
is greater
22
VLG
VLG
than or equal to V
.
VDD
Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL1 is pulled low in
shutdown.
23
DL1
Negative Current-Sense Input. Connect to a current-sense resistor in series with the low-side
MOSFET or connect to LX1 to use the low-side MOSFET’s on-resistance for current sensing.
24
25
26
CS1
LX1
DH1
Inductor Connection. Connect to the switched side of the inductor.
High-Side MOSFET Gate-Drive Output. Connect to the high-side MOSFET gate. DH1 is pulled low in
shutdown.
High-Side MOSFET Gate-Driver Bootstrap Input. Connect 0.22µF or higher value bypass capacitor
from BST1 to LX1. Keep trace length as short as possible. Connect a Schottky diode between BST1
and VLG. See the Selecting a BST Capacitor section.
27
28
BST1
Input Voltage Sense. Connect to the input supply at the high-side MOSFET drain. The voltage
V
CC
sensed at V
is used to set the on-time.
CC
On-Time One-Shot
The heart of the Quick-PWM core is the one-shot that
sets the high-side switch on-time. This fast, low-jitter,
one-shot circuitry varies the on-time in response to the
input and output voltages. The high-side switch on-time
Detailed Description
The MAX1937/MAX1938/MAX1939 is a family of syn-
chronous, two-phase step-down controllers capable of
delivering load currents up to 60A. The controllers use
Quick-PWM control architecture in conjunction with
active load current voltage positioning. Quick-PWM
control provides instantaneous load-step response,
while programmable voltage positioning allows the con-
verter to utilize full transient regulation limits, reducing
the output capacitance requirement. Furthermore, the
two phases operate 180° out-of-phase with an effective
500kHz switching frequency, thus reducing input and
output current ripple, as well as reducing input filter
capacitor requirements.
is inversely proportional to the voltage applied to V
CC
and directly proportional to the output voltage. This
algorithm results in a nearly constant switching fre-
quency, despite the lack of a fixed-frequency clock
generator. The benefits of a constant switching fre-
quency are twofold: the frequency selected avoids
noise-sensitive regions, and the inductor ripple current
operating point remains relatively constant, resulting in
easy design methodology and predictable output volt-
age ripple:
The MAX1937/MAX1938/MAX1939 are compliant with
the AMD Hammer, Intel VRM 9.0/VRM 9.1, and AMD
Athlon Mobile VID code specifications (see Table 1 for
VID codes). The internal DAC provides ultra-high accu-
racy of 0.75%. A controlled VID voltage transition is
implemented to minimize both undervoltage and over-
voltage overshoot during VID input change.
K V
+ V
(
OUT
DROP
)
t
=
ON
V
VCC
where the constant K is 4µs and V
drop across the low-side MOSFET’s on-resistance plus
the drop across the current-sense resistor (V
75mV), if used.
is the voltage
DROP
≈
DROP
Remote sensing is available for high output-voltage
accuracy. The MOSFET switches are driven by with a
6V gate-drive circuit to minimize switching and
crossover conduction losses to achieve efficiency as
high as 90%. The MAX1937/MAX1938/ MAX1939 fea-
ture cycle-by-cycle current limit to ensure current limit
is not exceeded. Crowbar protection is available to pro-
tect against output overvoltage.
The on-time one-shot has good accuracy at the operat-
ing point specified in the Electrical Characteristics. On-
times at operating points far removed from the
conditions specified in the Electrical Characteristics can
vary over a wide range. For example, the regulators run
slower with input voltages greater than 12V because of
the very short on-times required.
12 ______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Table 1. VID Programmed Output Voltage
V
(V)
OUT
VID4
VID3
VID2
VID1
VID0
MAX1937
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
MAX1938
1.850
1.825
1.800
1.775
1.750
1.725
1.700
1.675
1.650
1.625
1.600
1.575
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
Shutdown
MAX1939
2.000
1.950
1.900
1.850
1.800
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
Shutdown
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
Shutdown
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Note: In the above table, a zero indicates the VID_ pin is connected to GND or driven low, indicates the VID_ pin is driven high or
not connected.
While the on-time is set by the input and output voltage,
other factors contribute to the switching frequency. The
on-time guaranteed in the Electrical Characteristics is
influenced by switching delays in the external high-side
MOSFET. Resistive losses in the inductor, both MOSFETs,
output capacitor ESR, and PC board copper losses in
the output and ground, tend to raise the switching fre-
quency at higher output currents. Switch dead-time can
also increase the effective on-time, reducing the
switching frequency. This effect occurs when the
inductor current reverses at light or negative load cur-
rents. With reversed inductor current, the inductor’s
______________________________________________________________________________________ 13
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
EMF causes LX to go high earlier than normal, extend-
ing the on-time by a period equal to the DH rising
dead-time.
Once regulation is achieved, the controller returns to
180° out-of-phase operation. A minimum current-adap-
tive phase-selection algorithm is used to determine which
phase is used to start the first out-of-phase cycle. Once
the output voltage returns to the nominal output voltage
regulation value, the subsequent cycle starts with the
phase that has the lowest inductor current. For example,
if the current-sense inputs indicate that phase 2 has
lower inductor current than phase 1, the controller turns
on phase 2’s high-side MOSFET first when returning to
normal operation.
When the controller operates in continuous mode, the
dead-time is no longer a factor, and the actual switch-
ing frequency is:
V
+ V
+ V
OUT
DROP1
− V
f
=
SW
t
V
(
)
ON VCC DROP1 DROP2
Differential Voltage Sensing and Error
Comparator
where V
is the sum of the parasitic voltage drops
DROP1
in the inductor discharge path, including the synchro-
The MAX1937/MAX1938/MAX1939 use differential
sensing of the output voltage to achieve the highest
possible accuracy of the output voltage. This allows the
error comparator to sense the actual voltage at the
load, so that the controller can compensate for losses
in the power output and ground lines.
nous rectifier, inductor, and PC board resistances;
V
is the sum of the resistances in the charging
DROP2
path, including the high-side MOSFET, inductor, and
PC board resistances.
Synchronized 2-Phase Operation
The two phases of the MAX1937/MAX1938/MAX1939
operate 180° out-of-phase to reduce input filtering
requirements, reduce electromagnetic interference
(EMI), and improve efficiency. This effectively lowers
cost and saves board space, making the MAX1937/
MAX1938/MAX1939 ideal for cost-sensitive applica-
tions.
FB and GNDS are used for the differential output voltage
sensing. The controller triggers the next cycle (turn on
the high-side MOSFET) when the error comparator is low
(V - V
is less than the VID regulation voltage),
GNDS
FB
CS
V
is below the current-limit threshold, and the mini-
mum off-time one-shot has timed out.
Traces from FB and GNDS should be routed close to
each other and as far away as possible from sources of
noise (such as the inductors and high di/dt traces). If
noise on these connections cannot be prevented, then
use RC filters. To filter FB, connect a 100Ω series resistor
from the positive sense trace to FB, and connect a
1000pF capacitor from FB to GND right at the FB pin. For
GNDS, connect a 100Ω series resistor from the negative
sense trace to GNDS, and connect a 1000pF capacitor
from GNDS to GND at the GNDS pin.
With dual synchronized out-of-phase operation, the
MAX1937/MAX1938/MAX1939s’ high-side MOSFETs turn
on 180° out-of-phase. The instantaneous input current
peaks of both regulators do not overlap, resulting in
reduced input voltage ripple and RMS ripple current.
This reduces the input capacitance requirement, allowing
fewer or less expensive capacitors, and reduces shield-
ing requirements for EMI. The 180° out-of-phase wave-
forms are shown in the Typical Operating Characteristics.
Each phase operates with a 250kHz switching frequen-
cy. Since the two regulators operate 180° out-of-phase,
an effective switching of 500kHz is seen at the input
and output. In addition to being at a higher frequency
(compared to a single-phase regulator), both the input
and output ripple have lower amplitude.
For VRM applications, connect a 10kΩ resistor from FB
to the output locally (on the VRM board), and connect a
10kΩ resistor from GNDS to PGND locally (on the VRM
board). FB and GNDS also connect to the output at the
load (off the VRM board, at the microprocessor). This
provides the benefits of differential output voltage sens-
ing mentioned above and the safety of regulating the
output voltage on the board in case the external sense
connections get disconnected.
Phase Overlap
To minimize the crosstalk noise in the two phases, the
maximum duty cycle of the MAX1937/MAX1938/
MAX1939 is less than 50%. To provide a fast transient
response, these devices have a phase-overlap mode
that allows the two phases to operate in phase when a
heavy-load transient is detected. In-phase operation
continues until the output voltage returns to the nominal
output voltage regulation value.
External Linear Regulator
A 6V linear regulator (U2) is used to step down the
main supply. The output of this linear regulator is con-
nected to VLG to provide power for the low-side gate
drive and bootstrap circuit. Using 6V for this supply
improves efficiency by providing a stronger gate drive
than a 5V supply. To reduce switching noise on VLG,
14 ______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
V
IN
INPUT: 8V TO 14V
6 × 10µF CERAMIC CAPACITORS
TAIYO YUDEN TMK432BJ106MM
AND 2 × 100µF OS-CON
C
C
IN
VDD
VLG
1µF
U2
KA78M06
R1
N3
SANYO 16SP100M
2
D1
10Ω
3
1
1
2
IN
OUT
GND
2
N1
3
IR: 2 × IRLR7811W
1
28
8
26
25
CENTRAL
CMHD4448
V
V
CC
DD
DH1
LX1
C1
2.2µF
L1
0.66µH
C2
2.2µF
C3
2.2µF
C
VDD
0.01µF
C
V
OUT
BST1
SUMIDA CDEP134-6
0.22µF N3
2
OUTPUT
27
23
BST1
DL1
1
2
4
FAIRCHILD
2 × ISL9N303AS3ST
0.8V TO 1.55V
46A
VID0
VID1
VID2
VID0
1
3
VID1
VID2
24
22
CS1
VLG
2
1mΩ
R
CS1
5
D2
3
VID3
VID4
EN
VID3
VID4
EN
CENTRAL CMPSH-3A
U1
6
1
1mΩ
MAX1937
21
19
20
16
R
CS2
PGND
CS2
13
R
TIME
120kΩ
3
1
DL2
3
7
FAIRCHILD
2 × ISL9N303AS3ST
TIME
L2
0.66µH
C
VPOS
47pF
BST2
C
2
BST2
N4
N2
0.22µF
18
17
VPOS
SUMIDA CDEP134-6
R
LX2
VPOS
C
REF
0.47µF
51.1kΩ
3 IR: 2 × 1RLR7811W
12
DH2
REF
1
R3
V
IN
200kΩ
R4
68kΩ
2
14
13
9
FB
BF
ILIM
GND
R6
10kΩ
10
11
VDD
GNDS
GNDS
PWRGD
C
OUT
R5
6 × 390µF SP-CAP
10kΩ
PANASONIC EEFUE0D391XR
AND 4 × 1µF CERAMIC CAPACITORS
TAIYO YUDEN LMK212BJ105MG
R2
100kΩ
PWRGD
Figure 1. MAX1937 Application Circuit
connect a capacitor (C
) from VLG to PGND. Place
High-Side Gate-Drive Supply (BST_)
The drive voltage for the high-side MOSFETs is gener-
ated using a bootstrap circuit. The capacitor, C
should be sized properly to minimize the ripple voltage
for switching. The ripple voltage should be less than
200mV. For more information on selecting capacitors
for the BST circuit, see the Selecting a BST Capacitor
section. To minimize the forward voltage drop across
the bootstrap diodes (D2), use Schottky diodes. The
VLG
this capacitor as close as possible to the VLG pin.
,
BST_
The MAX1937/MAX1938/MAX1939 also require an exter-
nal 5V supply connected to V . A diode with a forward
DD
voltage drop of about 1V (D1) is used to stepdown the
6V supply to power the IC, as shown in Figure 1. The
diode connects between the linear regulator output and
the RC filter used to filter the voltage at V
(R1, C
,
DD
VDD
as close as
and C3). In the PC board layout, place C
VDD
recommended value for the boost capacitors (C
0.22µF.
) is
BST_
possible to the V pin.
DD
______________________________________________________________________________________ 15
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
MOSFET Drivers
The DH_ and DL_ drivers are optimized for driving large
high-side (N1 and N2) and larger low-side MOSFETs
(N3 and N4). This is consistent with the low duty-cycle
operation of the controller. The DL_ low-side drive wave-
form is always the complement of the DH_ high-side
drive waveform, with a fixed dead-time between one
MOSFET turning off and the other turning on to prevent
cross-conduction or shoot-through current.
Current Balancing
The DC current balancing between phases depends on
the accuracy of the current-sense elements and the off-
set of the current-balance amplifier.
The maximum offset of the current-balance amplifier
(V
) is 3mV. The current-balance accuracy
CBOFFSET
can be calculated from:
✕
Current-balance accuracy = V
/ (I
R
)
CS
CBOFFSET
L
where I is the peak inductor current and R
L
value of the current-sense resistor.
is the
CS
The internal transistor that drives DL_ low is robust with
a 0.5Ω (typ) on-resistance. This helps prevent DL_ from
being pulled up during the fast rise time of the LX_
node due to capacitive coupling from the drain to the
gate of the low-side synchronous-rectifier MOSFET.
However, some combinations of high-side and low-side
MOSFETs may cause excessive gate-drain coupling,
leading to poor efficiency, EMI, and shoot-through cur-
rents. This is often remedied by adding a resistor (typi-
cally less than 5Ω) in series with BST_, which increases
the turn-on time of the high-side MOSFET without
degrading the turn-off time.
The current-balance accuracy is most important at full
load. With a load current of 50A (I = 25A) and 2mΩ
L
current-sense resistors, the worst-case current-balance
accuracy is:
✕
Current-balance accuracy = 0.003 / (25 0.002) = 6%
If the on-resistance of the low-side MOSFETs is used
for current sensing, the part-to-part variation of the
MOSFET on-resistance is a significant factor in the cur-
rent balance. The matching between MOSFETs should
be on the order of 15%, worst case. Thus, even if the
current-balance amplifier has no offset, the DC-current
balance could be as bad as 15%. In practice, a little
help is received from the thermal ballasting of the
MOSFETs. That is to say, the positive temperature coef-
ficient of the on-resistance of MOSFETs reduces the
mismatch current between the two phases.
Current-Limit Circuit
The MAX1937/MAX1938/MAX1939 use either the on-
resistance of the low-side MOSFETs or a current-sense
resistor to monitor the inductor current. Using the low-
side MOSFETs’ on-resistance as the current-sense ele-
ment provides a lossless and inexpensive solution ideal
for high-efficiency or cost-sensitive applications. The dis-
advantage to this method is that the on-resistance of
MOSFETs vary from part to part, and overtemperature,
which means it cannot be counted on for high accuracy.
If high accuracy is needed, use current-sense resistors,
which provide an accurate current limit under all condi-
tions but reduce efficiency slightly because of the power
lost in the resistors.
Voltage Positioning (VPOS)
During a load transient, the output voltage instantly
changes by the ESR of the output capacitors times the
✕
change in load current (∆V
= -ESR
∆I
LOAD
).
OUT
COUT
Conventional DC-DC converters respond by regulating
the output voltage back to its nominal state after the
load transient occurs (Figure 3). However, the CPU
requires that the output voltage remain within a specific
voltage band. Dynamically positioning the output volt-
age allows the use of fewer output capacitors and
reduces power consumption under heavy load.
The current-limit circuit employs a “valley” current-
sensing algorithm to monitor the inductor current. If the
current-sense signal does not drop below the current-
limit threshold, the controller does not initiate a new
For a conventional (nonvoltage-positioned) circuit, the
total output voltage deviation from light load to full load
and back to light load is:
cycle. This limits the maximum value of I
to the
VALLEY
current set by the current-limit threshold (Figure 2).
The current-limit threshold is adjustable over a wide
range, allowing for a range of current-sense resistor
values. The voltage on ILIM sets the current-limit
✕
✕
✕
V
P-P1
= 2 (ESR
∆I ) + V + V
LOAD SAG SOAR
COUT
where V
and V
are defined in the Output
SOAR
SAG
threshold between PGND and CS_ to 0.1
V . The
ILIM
Capacitor Selection section. Setting the converter to
regulate at a lower voltage when under load allows a
larger voltage step when the output current suddenly
decreases. The total voltage change for a voltage-posi-
tioned circuit is:
10mV to 200mV adjustment range corresponds to ILIM
voltages from 100mV to 2V. The ILIM voltage is set by a
resistor-divider between REF and GND. See the Setting
the Current Limit section for details.
✕
V
P-P2
= (ESR
∆I
LOAD
) + V
+V
COUT
SAG SOAR
16 ______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
VOLTAGE POSITIONING THE OUTPUT
I
I
I
PEAK
A
B
1.4V
1.4V
LOAD
VALLEY
A. CONVENTIONAL CONVERTER (50mV/div)
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
TIME
Figure 2. Inductor Current Waveform
Figure 3. Voltage-Positioning and Nonvoltage-Positioning
Waveforms
The maximum allowable voltage change during a tran-
sient is fixed by the supply range of the CPU (V
P-P2
tolerates twice the ESR in the output capacitors.
Because the ESR specification is achieved by parallel-
ing several capacitors, fewer capacitors are needed for
the voltage-positioned circuit. Figure 4 shows transient
response regions.
In the case of shutdown by VID code, only DL_ and
DH_ are held low. The rest of the controller is enabled.
=
P-P1
V
). This means that the voltage-positioned circuit
When EN is driven high, the startup sequence begins.
Once the reference voltage rises above its 1.6V UVLO
threshold, the controller begins switching and starts to
ramp up the output voltage. The output voltage is
ramped up in 25mV steps every 50µs until the output
reaches the nominal output voltage.
An additional benefit of voltage positioning is reduced
power consumption at high-load currents. Because the
output voltage is lower under heavy load, the CPU
draws less current. The result is lower power dissipa-
tion in the CPU.
Fault Conditions
The MAX1937/MAX1938/MAX1939 contain internal cir-
cuitry to protect themselves and surrounding circuitry
from damage from output overvoltage and output
undervoltage conditions. When either of these condi-
tions occurs, DH_ is pulled low, DL_ is driven high, and
PWRGD is pulled low. These pins remain in this state
Voltage Reference (REF)
A 2V reference is provided on the MAX1937/MAX1938/
MAX1939 through the REF pin. REF is capable of
sourcing or sinking up to 50µA. In addition to providing
a reference for the IC, REF is used for setting the cur-
rent limit and voltage positioning. Connect a 0.47µF
capacitor from REF to GND. This capacitor should be
placed as close as possible to the REF pin.
until either power is cycled on V
high-low-high.
or EN is toggled
DD
Setting the Output Voltage (VID_)
An internal DAC is used to set the output regulation
voltage. A 5-bit code on inputs VID0–VID4 is used to
specify the output voltage. Some codes disable the
output. There is an internal 100kΩ pullup resistor to
VDD on each of the VID_ inputs. Connecting VID_ to
GND sets the bit to logic low (0); connecting VID_ to
VDD or leaving it unconnected sets the bit to logic high
(1). Use external pullup resistors to speed the low-to-
high logic transition, or for lower logic voltages. See
Table 1 for a list of codes and corresponding output
regulation voltages for each of the parts.
A UVLO is provided for the reference voltage. The ref-
erence voltage must rise above 1.600V to activate the
controller. The controller is disabled if the reference
voltage falls below 1.584V.
Enable Input (EN) and Soft-Start
When EN is low, DL_ and DH_ are held low (turning off
the MOSFETs), leaving LX_ high impedance. In addi-
tion, the reference is turned off and PWRGD is pulled
low. In shutdown, total current consumption is about
50µA (typ).
The VID_ codes for the MAX1937 comply with AMD
Hammer code. The VID_ codes on the MAX1938 are
______________________________________________________________________________________ 17
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Design Procedure
CAPACITIVE SOAR
(dV/dt = I /C
)
OUT OUT
Output Inductor Selection
For most applications, an inductor value of 0.5µH to
1µH is recommended. The inductance is set by the
desired amount of inductor current ripple (LIR). A larger
inductance value minimizes output ripple current and
increases efficiency, but slows transient response. For
the best compromise of size, cost, and efficiency, a LIR
of 30% to 40% is recommended (LIR = 0.3 to 0.4). The
inductor value is found from:
ESR VOLTAGE STEP
(I x R
)
ESR
STEP
V
OUT
CAPACITIVE SAG
(dV/dt = I /C
)
RECOVERY
OUT OUT
V
× V − V
OUT
(
IN
OUT
)
L =
V
× f ×I
×LIR
IN SW LOAD(MAX)
I
LOAD
where f is the actual switching frequency of a phase.
sw
The selected inductor should have the lowest possible
equivalent DC resistance and a saturation current
Figure 4. Transient Response Regions
greater than the peak inductor current (I
). I
is
PEAK PEAK
set for Intel VRM 9.0/9.1 and AMD Athlon. The
MAX1939 is set for AMD Athlon Mobile.
found from:
VID_ Change Slew Rate (TIME)
The MAX1937/MAX1938/MAX1939 allow the VID_ code
to be changed while the converter is operating (on-the-
fly). The slew rate at which the output voltage is chang-
ing is controlled through TIME. The slew rate is
adjusted externally by connecting a 47kΩ to 470kΩ
LIR
2
I
=I
× 1+
PEAK LOAD(MAX)
Output Capacitor Selection
The output capacitor must have low enough ESR to
meet output ripple and load-transient requirements.
Also, the capacitance value must be high enough to
absorb the inductor energy going from a full-load to a
no-load condition without tripping the OVP circuit.
resistor (R
) from TIME to GND. To set the slew rate,
TIME
select the R
resistor using the following equation:
TIME
521
SR
R
=
(Ω)
TIME
In CPU core power supplies and other applications
where the output is subject to large load transients, the
output capacitor’s size typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to
finite capacitance:
where SR is the slew rate of the output voltage in V/µs.
The output voltage is stepped up or down in 25mV
steps until it reaches the voltage set by the new VID
code.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that is pulled low when
the output voltage deviates more than 12.5% from its
regulation voltage (set by VID_ inputs). PWRGD is
pulled low in shutdown, input UVLO, and during start-
up. Any fault condition forces PWRGD low until the fault
R
ESR
= V
/ ∆I
STEP(MAX) LOAD(MAX)
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of OS-
CONs, SP capacitors, POSCAPs, and other electrolytic
capacitors). Generally, ceramic capacitors are not rec-
ommended for bulk output capacitance but make
excellent high-frequency decoupling capacitors.
is cleared, and the IC is reset by cycling power at V
DD
or momentarily toggling EN. For logic-level output volt-
ages, connect an external pullup resistor between
PWRGD and the logic power supply. A 100kΩ resistor
works well in most applications.
Once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
18 ______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
(V
) is no longer a problem. The amount of overshoot
tems that may be powered from very low impedance
sources.
SAG
from stored inductor energy can be calculated as:
Multiple smaller value capacitors can be used in paral-
lel to satisfy the ESR and capacitance requirements.
2
I
×L
PEAK
V
=
SOAR
2×C
× V
OUT
OUT
Selecting a BST Capacitor
The BST capacitors must be large enough to handle
the gate-charging requirements of the high-side
MOSFETs. For most applications, 0.22µF ceramic
capacitors are recommended.
where I
is the peak inductor current.
PEAK
The undershoot at the rising load edge of a load tran-
sient is calculated from:
BST capacitors are needed to keep the voltage on the
BST_ pins from dropping too much when the high-side
MOSFET gates are charged. A capacitor value that
V
×K
2
OUT
V
L × ∆I
×
+ t
OFF(MIN)
LOAD
IN
V
=
SAG
prevents V
_ from dropping more than 100mV to
BST
(V − V
)×K
IN
OUT
200mV is adequate. The capacitance needed for the
BST_ capacitor is calculated from:
2×C
× V
×
− t
OFF(MIN)
OUT
OUT
V
IN
Q
GH
C
=
where ∆I
is the change in load current, and K is
BST_
LOAD
∆V
BST_
4µs.
To ensure stability, make sure that the zero frequency
created by the output capacitance, and the ESR of the
output capacitor do not exceed 50kHz. The zero fre-
quency is found from:
where Q
is the total gate charge of the high-side
GH
MOSFET and ∆V
is the amount that the voltage on
BST_
the BST_ pin drops when the gate is charged. If using
multiple MOSFETs in parallel, use the sum of all the
gate charges for Q
.
GH
1
f
=
zESR
Setting the Current Limit
2π ×ESR
×C
OUT
COUT
Current limit sets the maximum value of the inductor
“valley” current. I
equation:
is calculated from the following
VALLEY
Currently, aluminum electrolytic, Sanyo POSCAP, and
Panasonic SP capacitors have ESR zero frequencies
well below 50kHz. When using ceramic capacitors, it
might be necessary to use a series resistance to
ensure that the ESR zero is below 50kHz.
I
LIR
2
LOAD(MAX)
I
=
× 1−
VALLEY
2
Input Capacitor Selection
The input capacitor reduces peak currents drawn from
the power source and reduces noise and voltage ripple
on the input caused by the circuit’s switching. The input
capacitor must meet the ripple current requirement
The current-limit threshold (I
than the valley current:
) must be set higher
LIMIT
I
>I
LIMIT VALLEY
(I
) imposed by the switching currents as defined by
RMS
The current-limit threshold is set by the voltage at ILIM
and the value of the current-sense resistors:
the following equation:
V
V
× V − V
(
)
ILIM
I
OUT
IN
OUT
LOAD
2
I
=
LIMIT
I
=
RMS
10×R
V
CS
IN
where V
is the voltage on the ILIM pin (0.1V to 2V)
ILIM
I
has a maximum value when the input voltage
and R is the value of the current-sense resistor. If the
RMS
CS
equals twice the output voltage (V = 2V
), so
OUT
on-resistance of the low-side MOSFET is used for cur-
rent sensing, then the maximum value of the on-resis-
tance (overtemperature and part-to-part variation) must
IN
I
= I
/ 2. For most applications, nontanta-
RMS(MAX)
LOAD
lum capacitors (ceramic, aluminum electrolytic, poly-
mer, or OS-CON) are preferred at the input because of
their robustness with high inrush currents typical of sys-
be used for R
.
CS
______________________________________________________________________________________ 19
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
V
is set from 0.5V to 2V by connecting ILIM to a
ILIM
2
V
×I
×R
LOADMAX
DS(ON)
OUT
resistor-divider from REF to GND. Select resistors R3
and R4 such that the current through the divider is at
least 5µA:
P
=
D(HS)COND
4× V
IN
where R
is the on-resistance of the high-side
DS(ON)
R3 + R4 ≤ 400kΩ
MOSFET and V is the input voltage. To minimize con-
IN
duction losses, select a MOSFET with a low R
.
DS(ON)
A typical value for R3 is 200kΩ; then solve for R4 using:
Switching losses are also a major contributor to power
dissipation in the high-side MOSFET. Switching losses
are difficult to precisely calculate and should be mea-
sured in the circuit. To estimate the switching losses,
use the following equation:
V
ILIM
R4 =R3×
2− V
ILIM
Setting the Voltage Positioning
Voltage positioning dynamically changes the output-
voltage set point in response to the load current. When
the output is loaded, the signals fed back from the cur-
rent-sense inputs adjust the output voltage set point,
thereby decreasing power dissipation. The load-tran-
sient response of this control loop is extremely fast yet
well controlled, so the amount of voltage change can
be accurately confined within the limits stipulated in the
microprocessor power-supply guidelines. To under-
stand the benefits of dynamically adjusting the output
voltage, see the Voltage Positioning (VPOS) section.
V
× f
IN SW
2
P
≅ (I
× t +I
× t
)
D(HS)SW
PEAK fall VALLEY rise
where I
valley inductor currents, t
and I
are the maximum peak and
VALLEY
PEAK
and t
are the fall and
RISE
FALL
rise times of the high-side MOSFET, and f
switching frequency (about 250kHz).
is the
SW
The total power dissipated in the high-side MOSFET is
then found from:
P
= P
+ P
D(HS)
D(HS)COND D(HS)SW
The amount of output voltage change is adjusted by an
The power dissipation in the low-side MOSFET is high-
est at low duty cycles (high input voltage, low output
voltage), and is mainly because of conduction losses:
external gain resistor (R
). Connect R
between
VPOS
VPOS
REF and VPOS. The output voltage changes in response
to the load current as follows:
2
V
V
I
LOADMAX
4
OUT
P
= 1−
×
×R
DS(ON)
D(LS)COND
I
×R
OUT
CS
V
= V
−g
×R
×
IN
OUT
VID
m(VPOS)
VPOS
2
Switching losses in the low-side MOSFET are small
because of its voltage being clamped by the body
diode. Switching losses can be estimated from:
where V
is the programmed output voltage set by
VID
the VID code (Table 1), and the voltage-positioning
transconductance (g ) is typically 20µS. R is
m(VPOS)
CS
the value of the current-sense resistor connected from
CS_ to PGND. If the on-resistance of the low-side
MOSFETs is used instead of current-sense resistors for
current sensing, then use the maximum on-resistance
I
LOADMAX
P
≅
× t × V × f
DT DF SW
D(LS)SW
2
where I
is the maximum average inductor
current, t is the time/cycle that the low-side MOSFET
conducts through its body diode, and V
ward voltage drop across the body diode.
LOADMAX/2
DT
of the low-side MOSFETs for R
above.
in the equation
CS
is the for-
DF
MOSFET Power Dissipation
Power dissipation in the high-side MOSFET is worst at
high duty cycles (maximum output voltage, minimum
input voltage). Two major factors contribute to the high-
side power dissipation, conduction losses, and switch-
ing losses. Conduction losses are because of current
flowing through a resistance, and can be calculated
from:
The total power dissipation in the low-side MOSFET is:
= P + P
P
D(LS)
D(LS)COND
D(LS)SW
IC Power Dissipation
During normal operation, power dissipation in the con-
troller is mostly from the gate drivers. This can be cal-
culated from the following equation:
✕
✕
✕
P
GATE
= 2
V
VLG
f
( Q
+ Q
)
SW
GH
GL
20 ______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
where f
is approximately 250kHz, Q
is the gate
is the gate
rent traces short and wide to reduce the resistance in
these traces. Also make the gate-drive connections (DH_
and DL_) short and wide, measuring 10 to 20 squares
(50mils to 100mils wide if the MOSFET is 1in from the
controller IC).
SW
GH
GL
charge of the high-side MOSFET, and Q
charge of the low-side MOSFET. The values used for
the gate charge are at the gate drive voltage (V ).
The “2” in the above equation is due to the two phases
of the converter. If multiple MOSFETs are used in paral-
lel, add the gate charges of each MOSFET to find the
total gate charge used in the above equation.
VLG
Use Kelvin sense connections for the current-sense
resistors.
Place the REF capacitor, the V
capacitor, and the
DD
Make sure that the maximum power dissipation of the IC
is not exceeded (see the Absolute Maximum Ratings).
BST_ diode and capacitor as close as possible to the IC.
If the IC is far from the input capacitors, bypass V to
CC
GND with an additional 0.1µF or greater ceramic capaci-
Applications Information
tor close to the V pin.
CC
PC Board Layout Guidelines
A properly designed PC board layout is important in any
switching DC-DC converter circuit. If possible, mount
the MOSFETs, inductor, input/output capacitors, and
current-sense resistor on the top side of the PC board.
Connect the ground for these devices close together on
a power ground plane. Make all other ground connec-
tions to a separate analog ground plane. Connect the
analog ground plane to power ground at a single point.
For an example PC board layout, refer to the MAX1937
or MAX1938 evaluation kit.
Chip Information
TRANSISTOR COUNT: 6243
PROCESS: BiCMOS
To help dissipate heat, place high-power components
(MOSFETs, inductor, and current-sense resistor) on a
large PC board area, or use a heat sink. Keep high cur-
______________________________________________________________________________________ 21
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Functional Diagram
EN
VDD
VCC
ENABLE/
SHUTDOWN
ON-TIME
BIAS
CS1
CS2
FB
ONE-SHOT
ON-TIME
COMPUTE
MIN OFF
TIME
ONE-SHOT
BST1
DH1
REF - 12.5%
REF + 12.5%
LX1
VLG
PWRGD
CONTROL
LOGIC
DL1
CS1
PGND
BST2
CS2
g
m
DH2
LX2
DL2
VLG
VPOS
CURRENT
BALANCE
REF
FB
ERROR AMP
DL2
DL2
2V
UVLO/
OVLO
∑
CURRENT
LIMIT
∑
VID DAC
GNDS
GND
VID0–VID4
TIME
ILIM
22 ______________________________________________________________________________________
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
MAX1938 Typical Application Circuit
V
IN
INPUT: 8V TO 14V
10 × 10µF CERAMIC CAPACITORS
TAIYO YUDEN TMK432BJ106MM
AND 4 × 330µF
C
CVLG
1µF
IN
VDD
U2
KA78M06
R1
N3
SANYO 25MV330WX
2
D1
10Ω
3
1
1
2
IN
OUT
GND
2
N1
3
1
28
8
26
25
CENTRAL
CMHD4448
V
V
CC
DD
DH1
LX1
IR: 3X1RLR7811W
C1
2.2µF
L1
0.5µH
C2
2.2µF
C3
2.2µF
C
VDD
0.01µF
CBST1
V
OUT
BI TECHNOLOGIES HM73-40R50
0.22µF N3
2
OUTPUT
0.8V TO 1.55V
60A
27
23
BST1
DL1
FAIRCHILD
2 × 1SL9N303AS3ST
1
2
4
VID0
VID1
VID2
VID0
1
3
VID1
VID2
24
22
CS1
VLG
2
1mΩ
R
CS1
5
D2
3
VID3
VID4
EN
VID3
VID4
EN
CENTRAL CMPSH-3A
U1
6
1
1mΩ
MAX1938
21
19
20
16
R
CS2
PGND
CS2
13
R
TIME
120kΩ
3
1
DL2
3
7
FAIRCHILD
2 × 1SL9N303AS3ST
TIME
L2
0.5µH
C
VPOS
47pF
BST2
C
2
BST2
N4
0.22µF
18
17
VPOS
BI TECHNOLOGIES HM73-40R50
R
LX2
VPOS
C
REF
0.47µF
51.1kΩ
IR: 3 × 1RLR7811W
3 IR: 2 × 1RLR7811W
12
DH2
REF
1
R3
V
IN
200kΩ
R4
82.5kΩ
N2
2
14
13
9
FB
R6
BF
ILIM
GND
10
10kΩ
11
VDD
GNDS
GNDS
PWRGD
R5
6 × 560µF/4V OS-CAN CAPACITORS
SANYO SP560M
AND 2 × 1µF CERAMIC CAPACITORS
TAIYO YUDEN: LMK212BJ105MG
10kΩ
R2
100kΩ
PWRGD
______________________________________________________________________________________ 23
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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