MAX19542EGK [MAXIM]
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications; 12位，170Msps ADC ，CMOS输出，适用于宽带系统
| 型号： | MAX19542EGK |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications |
| 文件： | 总23页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3464; Rev 1; 10/10
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
General Description
Features
The MAX19542 monolithic 12-bit, 170Msps analog-to-
digital converter (ADC) is optimized for outstanding
dynamic performance at high-IF frequencies of
300MHz and beyond. This device operates with con-
version rates up to 170Msps while consuming only
907mW.
o 170Msps Conversion Rate
o SNR = 64.3dB, f = 100MHz at 170Msps
o SFDR = 73dBc, f = 100MHz at 170Msps
IN
IN
o
0.7 LSB INL, 0.25 DNL (typ)
o 907mW Power Dissipation at 170Msps
o On-Chip Selectable Divide-by-2 Clock Input
o Parallel or Demux Parallel Digital CMOS Outputs
o Reset Option for Synchronizing Multiple ADCs
o Data Clock Output
o Offset Binary or Two’s-Complement Output
o Evaluation Kit Available (MAX19542EVKIT)
At 170Msps and an input frequency of 240MHz, the
MAX19542 achieves a spurious-free dynamic range
(SFDR) of 76.4dBc. The MAX19542 features an excel-
lent signal-to-noise ratio (SNR) of 65dB at 10MHz that
remains flat (within 3dB) for input tones up to 250MHz.
This makes the MAX19542 ideal for wideband applica-
tions such as power-amplifier predistortion in cellular
base-station transceiver systems.
The MAX19542 operates in either parallel mode where
the data outputs appear on a single parallel port at the
sampling rate, or in demux parallel mode, where the out-
puts appear on two separate parallel ports at one-half
the sampling rate. See the Mode of Operation section.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
The MAX19542 operates on a single 1.8V supply. The
analog input is differential and can be AC- or DC-cou-
pled. The ADC also features a selectable on-chip
divide-by-2 clock circuit that allows clock frequencies
as high as 340MHz. This helps to reduce the phase
noise of the input clock source, allowing for higher
dynamic performance. For best performance, a differ-
ential LVPECL sampling clock is recommended. The
digital outputs are CMOS compatible and the data for-
mat can be selected to be either two’s complement or
offset binary.
MAX19542EGK+
-40°C to +85°C
68 QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A pin-compatible, 12-bit, 125Msps version of the
MAX19542 is also available. Refer to the MAX19541
data sheet for more information.
+
AVCC
AGND
REFIO
REFADJ
AGND
AVCC
AGND
INP
1
2
3
4
5
6
7
8
9
51 DA4
50 DA3
49 DA2
48 DA1
47 DA0
46 ORB
45 OGND
44 OVCC
43 DCLKP
42 DCLKN
41 OVCC
40 DB11
39 DB10
38 DB9
37 DB8
36 DB7
35 DB6
The MAX19542 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the extended
(-40°C to +85°C) temperature range.
Applications
INN
MAX19542
AGND 10
AVCC 11
AVCC 12
AVCC 13
AVCC 14
RESET 15
DEMUX 16
CLKDIV 17
Base-Station Power Amplifier Linearization
Cable Head-End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
EP
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
NOTE: EXPOSED PAD CONNECTED TO AGND.
QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ABSOLUTE MAXIMUM RATINGS
AV
to AGND ......................................................-0.3V to +2.1V
to OGND .....................................................-0.3V to +2.1V
ESD on All Pins (Human Body Model)............................. 2000V
CC
OV
Continuous Power Dissipation (T = +70°C)
CC
A
AV
to OV .......................................................-0.3V to +2.1V
68-Pin QFN (derate 41.7mW/°C above +70°C) ........ 3333mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
CC
CC
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs (INP, INN) to AGND..........-0.3V to (AV
All Digital Inputs to AGND........................-0.3V to (AV
REFIO, REFADJ to AGND........................-0.3V to (AV
All Digital Outputs to OGND....................-0.3V to (OV
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
CC
CC
CC
CC
Maximum Current into Any Pin ....................................... 50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX19542
ELECTRICAL CHARACTERISTICS
(V
= V
= 1.8V, V
= V
= 0V, f
OGND
= 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
SAMPLE
AGND
AVCC
OVCC
itor on REFIO, internal reference, T = T
guaranteed by design and characterization. Typical values are at T = +25°C.)
to T
, unless otherwise noted. T ≥ +25°C guaranteed by production test, T < +25°C
A
MIN
MAX A A
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
12
-2.5
-0.75
-3
Bits
LSB
Integral Nonlinearity
INL
f
f
= 10MHz (Note 1)
0.7
+2.5
+0.75
+3
IN
Differential Nonlinearity
Transfer Curve Offset
Offset Temperature Drift
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
DNL
= 10MHz, no missing codes (Note 1)
0.25
LSB
IN
V
(Note 1)
mV
OS
40
mV/°C
V
(Note 1)
1300
1410
130
1510
mV
P-P
FS
Full-Scale Range Temperature
Drift
ppm/°C
V
1.365
0.15
Common-Mode Input Range
V
CM
Input Capacitance
C
3
pF
kΩ
IN
Differential Input Resistance
Full-Power Analog Bandwidth
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
Reference Temperature Drift
R
3.00
1.22
4.3
900
6.25
1.27
IN
FPBW
MHz
V
1.245
90
V
REFIO
ppm/°C
V
AVCC
- 0.3
REFADJ Input High Voltage
V
Used to disable the internal reference
V
REFADJ
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
Minimum Sampling Rate
Clock Duty Cycle
f
f
170
MHz
MHz
%
SAMPLE
20
40 to 60
620
SAMPLE
Set by clock-management circuit
Figure 4
Aperture Delay
t
ps
AD
Aperture Jitter
t
AJ
0.2
ps
RMS
2
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
ELECTRICAL CHARACTERISTICS (continued)
= 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
SAMPLE
(V
= V
= 1.8V, V
= V
A
= 0V, f
OGND
AGND
AVCC
OVCC
itor on REFIO, internal reference, T = T
guaranteed by design and characterization. Typical values are at T = +25°C.)
to T
, unless otherwise noted. T ≥ +25°C guaranteed by production test, T < +25°C
MIN
MAX
A
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input
Amplitude
(Note 2)
200
500
mV
P-P
Clock Input Common-Mode
Voltage Range
1.15
0.25
V
Clock Differential Input
Resistance
11
25%
R
C
kΩ
CLK
Clock Differential Input
Capacitance
5
pF
CLK
DYNAMIC CHARACTERISTICS (at -2dBFS)
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 10MHz
62.3
62.3
65
64.3
63.5
63.3
64.8
63.6
62.6
63
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 100MHz
= 180MHz
= 240MHz
= 10MHz
Signal-to-Noise Ratio
SNR
SINAD
SFDR
dB
dB
61.9
61.7
= 100MHz
= 180MHz
= 240MHz
= 10MHz
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
68.3
68.3
82
= 100MHz
= 180MHz
= 240MHz
= 10MHz
73
dBc
72.4
76.4
-85
-69.1
-68.7
= 100MHz
= 180MHz
= 240MHz
-73
Worst Harmonics
(HD2 or HD3)
dBc
dBc
-72.4
-76.4
Two-Tone Intermodulation
Distortion
f
f
= 207.5MHz at -7dBFS,
= 211.5MHz at -7dBFS, f
IN1
IN2
IMD
-69
100
= 170MHz
SAMPLE
CMOS DIGITAL OUTPUTS (DA0–DA11, DB0–DB11, ORA, ORB)
V
- 0.1
OVCC
Logic-High Output Voltage
V
V
V
OH
Logic-Low Output Voltage
V
0.1
OL
LVCMOS DIGITAL INPUTS (CLKDIV, T/B, DEMUX, ITL)
0.2 x
Digital Input-Voltage Low
Digital Input-Voltage High
V
V
V
IL
V
AVCC
0.8 x
V
IH
V
AVCC
_______________________________________________________________________________________
3
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
= 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
SAMPLE
(V
= V
= 1.8V, V
= V
A
= 0V, f
OGND
AGND
AVCC
OVCC
itor on REFIO, internal reference, T = T
guaranteed by design and characterization. Typical values are at T = +25°C.)
to T
, unless otherwise noted. T ≥ +25°C guaranteed by production test, T < +25°C
MIN
MAX A A
A
PARAMETER
Input Resistance
SYMBOL
CONDITIONS
MIN
TYP
46.5
5
MAX
UNITS
kΩ
R
IN
C
IN
Input Capacitance
pF
TIMING CHARACTERISTICS
MAX19542
CLKP-to DA0–DA11 Propagation
Delay
t
Figures 5, 6, and 7
2.5
2.1
ns
ns
ns
PDL
CLKP-to-DCLKP Propagation
Delay
t
Figures 5, 6, and 7
CPDL
DCLKP Rising Edge to
DA0–DA11
t
t
-
PDL
Figures 5, 6, and 7 (Note 2)
180
400
710
CPDL
CMOS Output Rise Time
CMOS Output Fall Time
RESET Hold
t
20% to 80%, C = 5pF
1
ns
ns
ps
ps
RISE
L
t
20% to 80%, C = 5pF
L
1
FALL
t
Figure 4
Figure 4
100
500
HR
RESET Setup
t
SR
Clock
cycles
Output Data Pipeline Delay
t
Figure 4
11
LATENCY
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
AVCC
OVCC
1.7
1.7
1.8
1.8
480
24
1.9
1.9
520
31
V
V
I
f
f
f
= 100MHz
= 100MHz
= 100MHz
mA
AVCC
IN
IN
IN
Digital Supply Current
I
mA
OVCC
Analog Power Dissipation
P
907
1.8
1.5
992
mW
mV/V
%FS/V
DISS
Offset (Note 3)
Gain (Note 3)
Power-Supply Rejection Ratio
PSRR
Note 1: Static linearity and offset parameters are computed from a straight line drawn between the end points of the code transition
transfer function. The full-scale range (FSR) is defined as 4096 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; T = T
to T
.
A
MIN
MAX
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
Typical Operating Characteristics
(V
= V
= 1.8V, V
= V
= 0V, f
OGND
= 170MHz, A = -1dBFS; see TOCs for detailed information on test condi-
SAMPLE IN
AGND
AVCC
OVCC
tions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs dif-
ferential R = 100Ω, T = +25°C.)
L
A
FFT PLOT
(16,384-POINT DATA RECORD)
FFT PLOT
(16,384-POINT DATA RECORD)
FFT PLOT
(16,384-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
A
= 12.9599243MHz
f
f
A
= 64.9863939MHz
f
f
A
= 190.186111MHz
IN
IN
IN
SAMPLE
= 170.0043234MHz
= -1.05dBFS
= 170.0043234MHz
= 170.0043234MHz
= -1.03dBFS
SAMPLE
IN
SAMPLE
= -1.068dBFS
IN
IN
SNR = 65.923dB
SINAD = 65.822dB
SFDR = 88.137dBc
HD2 = -92.278dBc
HD3 = -88.96dBc
SNR = 65.921dB
SINAD = 65dB
SFDR = 74.007dBc
HD2 = -82.197dBc
HD3 = -79.515dBc
SNR = 64.664dB
SINAD = 63.513dB
SFDR = 71.34dBc
HD2 = -77.559dBc
HD3 = -71.34dBc
7
3
3
7
2
2
6
5
2
4
4
3
5
5
4
6
6
7
0
10 20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
SFDR vs. ANALOG INPUT FREQUENCY
= 170.0043MHz, A = -1dBFS)
FFT PLOT
(16,384-POINT DATA RECORD)
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
(f
= 170.0043MHz, A = -1dBFS)
SAMPLE
IN
SAMPLE
IN
90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
70
67
64
61
58
55
f
f
A
= 241.008937MHz
IN
SAMPLE
IN
85
80
75
70
65
60
55
50
45
40
= 170.0043234MHz
SNR
= -1.035dBFS
SNR = 64.01dB
SINAD = 63.521dB
SFDR = 74.963dBc
HD2 = -74.963dBc
HD3 = -82.606dBc
SINAD
2
4
3
5
7
6
0
25 50 75 100 125 150 175 200 225 250
(MHz)
0
10 20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
0
25 50 75 100 125 150 175 200 225 250
(MHz)
f
f
IN
IN
HD2/HD3 vs. ANALOG INPUT FREQUENCY
THD vs. ANALOG INPUT FREQUENCY
= 170.0043MHz, A = -1dBFS)
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(f
= 170.0043MHz, A = -1dBFS)
(f
(f
= 170.0043MHz, f = 64.9864MHz)
SAMPLE
IN
SAMPLE
IN
SAMPLE
IN
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-60
-65
-70
-75
-80
-85
-90
-95
-100
68
SNR
62
56
50
44
38
32
HD3
SINAD
HD2
0
25 50 75 100 125 150 175 200 225 250
(MHz)
0
25 50 75 100 125 150 175 200 225 250
(MHz)
-30
-25
-20
-15
-10
-5
0
f
f
IN
A
(dBFS)
IN
IN
_______________________________________________________________________________________
5
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, V
= V
= 0V, f
OGND
= 170MHz, A = -1dBFS; see TOCs for detailed information on test condi-
SAMPLE IN
AGND
AVCC
OVCC
tions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs dif-
ferential R = 100Ω, T = +25°C.)
L
A
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
SFDR vs. ANALOG INPUT AMPLITUDE
= 170.0043MHz, f = 64.9864MHz)
THD vs. ANALOG INPUT AMPLITUDE
= 170.0043MHz, f = 64.9864MHz)
(f
-50
= 170.0043MHz, f = 64.9864MHz)
(f
90
SAMPLE
IN
(f
-50
SAMPLE
IN
SAMPLE
IN
85
80
75
70
65
60
55
50
45
40
HD2
-60
-70
-60
-70
MAX19542
-80
-90
-80
HD3
-100
-110
-120
-90
-100
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
A
(dBFS)
A
(dBFS)
IN
A
(dBFS)
IN
IN
HD2/HD3 vs. f
(f = 65.0165MHz, A = -1dBFS)
SNR/SINAD vs. f
(f = 65.0165MHz, A = -1dBFS)
SFDR vs. f
(f = 65.0165MHz, A = -1dBFS)
SAMPLE
IN
SAMPLE
IN
SAMPLE
IN
IN
IN
IN
-50
-55
68
67
66
65
64
63
62
61
60
90
85
80
75
70
65
60
55
50
SNR
-60
HD3
-65
-70
-75
-80
-85
SINAD
-90
-95
HD2
-100
-105
-110
20 40 60 80 100 120 140 160 180 200
(MHz)
20 40 60 80 100 120 140 160 180 200
20 40 60 80 100 120 140 160 180 200
(MHz)
f
f
(MHz)
f
SAMPLE
SAMPLE
SAMPLE
TWO-TONE IMD
(16,384-POINT DATA RECORD)
INL vs. DIGITAL OUTPUT CODE
(512k-POINT DATA RECORD)
THD vs. f
(f = 65.0165MHz, A = -1dBFS)
SAMPLE
IN
IN
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
1.0
0.8
-60
-65
-70
-75
-80
-85
-90
f
f
f
= 207.4936801MHz
= 211.5611664MHz
= 170.00432MHz
IN1
IN2
f = 13.008646MHz
IN
SAMPLE
0.6
A
= A = -7dBFS
IN2
IN1
IMD = -69dBc
0.4
f
f
0.2
IN1
IN2
0
2f - f
IN2 IN1
-0.2
-0.4
-0.6
-0.8
-1.0
2f - f
IN1 IN2
20 40 60 80 100 120 140 160 180 200
(MHz)
0
10 20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
f
SAMPLE
6
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, V
= V
= 0V, f
OGND
= 170MHz, A = -1dBFS; see TOCs for detailed information on test condi-
SAMPLE IN
AGND
AVCC
OVCC
tions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs dif-
ferential R = 100Ω, T = +25°C.)
L
A
DNL vs. DIGITAL OUTPUT CODE
(512k-POINT DATA RECORD)
SNR/SINAD vs. TEMPERATURE
= 170MHz, A = -2dBFS)
GAIN BANDWIDTH PLOT
(f
(f
= 170.0043MHz, A = -1dBFS)
SAMPLE
IN
SAMPLE
IN
1.0
0.8
67
66
65
64
63
62
61
1
0
f
= 13.008646MHz
IN
f
= 100MHz
IN
0.6
-1
-2
-3
-4
-5
-6
-7
SNR
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
SINAD
10
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
-40
-15
35
60
85
10
100
ANALOG INPUT FREQUENCY (MHz)
1000
TEMPERATURE (°C)
FULL-SCALE ADJUSTMENT RANGE
vs. FULL-SCALE ADJUSTMENT RESISTANCE
1.34
SFDR vs. TEMPERATURE
TOTAL POWER DISSIPATION vs. f
SAMPLE
(f
= 170MHz, A = -2dBFS)
SAMPLE
IN
(f = 65.0165MHz, A = -1dBFS)
IN
IN
78
77
76
75
74
73
72
71
70
69
68
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
f
= 100MHz
IN
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
R
BETWEEN REFADJ AND REFIO
BETWEEN REFADJ AND GND
ADJ
R
ADJ
0
200
400
R
600
(kΩ)
800
1000
-40
-15
10
35
60
85
20 40 60 80 100 120 140 160 180
(MHz)
TEMPERATURE (°C)
ADJ
f
SAMPLE
SNR/SINAD vs. SUPPLY VOLTAGE
(f = 64.9864MHz, A = -1dBFS)
INTERNAL REFERENCE
vs. SUPPLY VOLTAGE
IN
IN
68
66
64
62
60
58
1.250
1.249
1.248
1.247
1.246
1.245
1.244
AVCC = OVCC
SNR
SINAD
1.6
1.7
1.8
1.9
2.0
2.1
1.6
1.7
1.8
1.9
2.0
2.1
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Pin Description
PIN
NAME
FUNCTION
1, 6, 11–14,
20, 25, 62,
63, 65
Analog Supply Voltage. Bypass each AVCC pin with a 0.1µF capacitor for best decoupling results.
Additional board decoupling might be required. See the Grounding, Bypassing, and Layout
Considerations section.
AVCC
2, 5, 7, 10,
18, 19, 21,
24, 64, 66
AGND
REFIO
Analog Converter Ground. Connect the converter’s exposed pad (EP) to AGND.
MAX19542
Reference Input/Output. Drive REFADJ high to allow an external reference source to be connected to
the MAX19542. Drive REFADJ low to activate the internal 1.23V bandgap reference. Connect a 0.1µF
capacitor from REFIO to AGND.
3
4
Reference Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and REFIO (increases
FS range). If REFADJ is connected to AVCC, the internal reference can be overdriven with an external
source connected to REFIO. If REFADJ is connected to AGND, the internal reference is used to
determine the full-scale range of the data converter.
REFADJ
8
9
INP
INN
Positive Analog Input Terminal
Negative Analog Input Terminal
Active-High RESET Input. RESET controls the latency of the MAX19542. RESET has an internal
pulldown resistor. See the Reset Operation section.
15
RESET
Output-Mode-Select Input. Drive DEMUX low for the parallel output mode (full-rate CMOS outputs on
A ports only). Drive DEMUX high for the demux parallel or demux interleaved modes (half-rate outputs
on both ports A and B) depending on the state of the ITL input. See the Modes of Operation section.
16
DEMUX
Clock-Divider Input. CLKDIV is an LVCMOS-compatible input that controls the sampling frequency
relative to the input clock frequency. CLKDIV has an internal pulldown resistor:
CLKDIV = 0: sampling frequency is 1/2 the input clock frequency.
17
22
CLKDIV
CLKN
CLKDIV = 1: sampling frequency is equal to the input clock frequency.
Complementary Clock Input. CLKN ideally requires an LVPECL-compatible input level to maintain the
converter’s excellent performance.
True Clock Input. CLKP ideally requires an LVPECL-compatible input level to maintain the converter’s
excellent performance.
23
CLKP
OGND
OVCC
26, 45, 61
Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41,
44, 60
Digital Supply Voltage. Bypass OVCC with a 0.1µF capacitor for best decoupling results. Additional board
decoupling might be required. See the Grounding, Bypassing, and Layout Considerations section.
29
30
31
32
33
34
35
36
37
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
Port B CMOS Digital Output Bit 0 (LSB)
Port B CMOS Digital Output Bit 1
Port B CMOS Digital Output Bit 2
Port B CMOS Digital Output Bit 3
Port B CMOS Digital Output Bit 4
Port B CMOS Digital Output Bit 5
Port B CMOS Digital Output Bit 6
Port B CMOS Digital Output Bit 7
Port B CMOS Digital Output Bit 8
8
_______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
Pin Description (continued)
PIN
38
NAME
DB9
FUNCTION
Port B CMOS Digital Output Bit 9
39
DB10
DB11
Port B CMOS Digital Output Bit 10
40
Port B CMOS Digital Output Bit 11 (MSB)
Inverted CMOS Digital Clock Output. DCLKN provides a CMOS-compatible output level and can be
used to synchronize external devices to the converter clock. When DEMUX is high, the frequency at
DCLKN is half the sampling clock’s frequency.
42
43
DCLKN
DCLKP
True CMOS Digital Clock Output. DCLKP provides a CMOS-compatible output level and can be used
to synchronize external devices to the converter clock. When DEMUX is high, the frequency at DCLKP is
half the sampling clock’s frequency.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
ORB
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
ORA
Port B CMOS Digital Output Overrange
Port A CMOS Digital Output Bit 0 (LSB)
Port A CMOS Digital Output Bit 1
Port A CMOS Digital Output Bit 2
Port A CMOS Digital Output Bit 3
Port A CMOS Digital Output Bit 4
Port A CMOS Digital Output Bit 5
Port A CMOS Digital Output Bit 6
Port A CMOS Digital Output Bit 7
Port A CMOS Digital Output Bit 8
Port A CMOS Digital Output Bit 9
Port A CMOS Digital Output Bit 10
Port A CMOS Digital Output Bit 11 (MSB)
Port A CMOS Digital Output Overrange
Interleaved/Parallel-Select Input. Drive ITL low for the demux parallel mode. Drive ITL high for the demux
interleaved mode.
67
68
—
ITL
T/B
EP
Output-Format-Select Input. T/B is an LVCMOS-compatible input that controls the digital output format
of the MAX19542. T/B has an internal pulldown resistor:
T/B = 1: binary output format.
T/B = 0: two’s-complement output format.
Exposed Pad. Connect EP to analog ground (AGND) for optimum performance. The exposed pad is
located on the backside of the chip. EP is internally connected to the die substrate.
_______________________________________________________________________________________
9
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ADC following the first T/H stage then digitizes the sig-
Detailed Description—
Theory of Operation
The MAX19542 uses a fully differential, pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy and linearity, while minimizing power
consumption. Both positive (INP) and negative/comple-
mentary analog input terminals (INN) are centered
around a 1.365V common-mode voltage, and accept a
350mV differential analog input voltage swing each,
nal, and controls a digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 12-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital
correction logic to generate the final output code. The
result is a 12-bit parallel digital output word in user-
selectable two’s complement or binary output formats
with CMOS-compatible output levels. See the functional
diagram (Figure 1) for a more detailed view of the
MAX19542’s architecture.
MAX19542
resulting in a 1.41V
signal swing.
typical differential full-scale
P-P
Inputs INP and INN are buffered prior to entering each
track-and-hold (T/H) stage and are sampled when the
differential sampling clock signal transitions high. The
CLKDIV
RESET
CLKP
CLOCK-
DIVIDER
CONTROL
CLOCK
MANAGEMENT
DEMUX
ITL
CLKN
INP
12 BITS
BUFFER
CMOS
DATA
PORTS
12-BIT PIPELINE
QUANTIZER
CORE
DA0–DA11, ORA
DB0–DB11, ORB
T/H
INN
12 BITS
2.15kΩ
2.15kΩ
CM
BUFFER
DCLKP
DCLKN
CLK
GENERATOR
REFERENCE
MAX19542
REFIO REFADJ
Figure 1. MAX19542 Functional Diagram
10 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
ADC FULL SCALE = REFT - REFB
REFERENCE-
SCALING
AMPLIFIER
REFT
REFB
G
AVCC
REFERENCE
BUFFER
REFIO
1V
INP
INN
0.1µF
MAX19542
2.15kΩ
2.15kΩ
REFADJ*
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
TO COMMON-MODE
INPUT
TO COMMON-MODE
INPUT
AGND
AVCC
AVCC/2
*REFADJ CAN BE SHORTED TO AGND THROUGH A 1kΩ
RESISTOR OR POTENTIOMETER.
Figure 2. Simplified Analog Input Architecture
Figure 3. Simplified Reference Architecture
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX19542. Differential inputs usually feature good
rejection of even-order harmonics, which allows for
enhanced AC performance as the signals are pro-
gressing through the analog stages. The MAX19542
analog inputs are self-biased at a 1.365V common-
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX19542 differentially
with an LVPECL-compatible clock to achieve the best
dynamic performance. The clock signal source must be
high-quality, low phase noise to avoid any degradation
in the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to typically 1.15V,
mode voltage and allow a 1.41V
differential input
accept a typical 0.5V
differential signal swing, and
P-P
P-P
voltage swing. Both inputs are self-biased through
2.15kΩ resistors, resulting in a typical differential input
resistance of 4.3kΩ (Figure 2). It is recommended dri-
ving the analog inputs of the MAX19542 in an AC-cou-
pled configuration to achieve the best dynamic
performance. See the Transformer-Coupled, Differential
Analog Input Drive section for a detailed discussion of
this configuration.
are usually driven in an AC-coupled configuration. See
the Differential, AC-Coupled Clock Input section for
more circuit details on how to drive CLKP and CLKN
appropriately.
The MAX19542 features an internal clock-management
circuit (duty-cycle equalizer). The clock-management
circuit ensures that the clock signal applied to inputs
CLKP and CLKN is processed to provide a near 50%
duty-cycle clock signal. This desensitizes the perfor-
mance of the converter to variations in the duty cycle of
the input clock source. Note that the clock duty-cycle
equalizer cannot be turned off externally.
On-Chip Reference Circuit
The MAX19542 features an internal 1.24V bandgap ref-
erence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determine the full-
scale range of the MAX19542. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain errors
or increase the ADC’s full-scale range, the voltage of this
bandgap reference can be indirectly adjusted by adding
an external resistor (e.g., 100kΩ trim potentiometer)
between REFADJ and AGND or REFADJ and REFIO.
See Figure 7 and the Applications Information section for
a detailed description of this process.
Clock Outputs (DCLKP, DCLKN)
The MAX19542 features CMOS-complementary clock
outputs (DCLKP, DCLKN) to latch the digital output
data with an external latch or receiver. Additionally, the
clock outputs can be used to synchronize external
devices (e.g., FPGAs) to the ADC. There is a 2.1ns
delay time between the rising (falling) edge of CLKP
(CLKN) and the rising (falling) edge of DCLKP
(DCLKN). See Figure 4 for timing details.
______________________________________________________________________________________ 11
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Divide-by-Two Clock Control (CLKDIV)
RESET Operation
The MAX19542 offers a clock control line (CLKDIV) that
allows the reduction of clock jitter and phase noise in a
system as higher frequency oscillators usually exhibit
better phase noise and jitter characteristics. Connect
CLKDIV to OGND to enable the ADC’s internal divide-
by-2 clock divider, which allows the user to use an
oscillator of twice the maximum sampling frequency.
The sampling frequency now becomes 1/2 of the input
clock frequency. CLKDIV has an internal pulldown
resistor and can be left open for applications that
require this divide-by-2 mode. Connecting CLKDIV to
The RESET input defines the pipeline latency of the
MAX19542. Drive RESET high to place the MAX19542
in reset mode with the CMOS outputs tri-stated. During
the time when RESET is high, no sample information is
available at the outputs. For pipeline latency, the first
sample is defined at the first rising edge of CLKP after
RESET goes low. The conversion information is avail-
able at the outputs after 11 clock cycles. Synchronize
RESET with the input clock of the device by observing
MAX19542
the minimum RESET hold (t ) and RESET setup (t
)
HR
SR
times (Figure 4). RESET is only used to control the
latency of the device and, in applications where this is
not critical, drive RESET low or leave unconnected.
RESET has an internal pulldown resistor.
OV
disables the divide-by-2 mode.
CC
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
t
AD
CLKN
N
N + 1
N + 11
N + 12
CLKP
t
t
CL
CH
t
SR
RESET
t
HR
Figure 4. RESET Timing Diagram
12 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
Parallel Mode
Drive DEMUX low to place the MAX19542 in the parallel
mode. In this mode, the output clock has the same fre-
quency as the sampling frequency and conversion
data is output at full rate on parallel ports DA0–DA11.
Note that the sampling frequency may not be the same
as the input clock frequency. See the Divide-by-Two
Clock Control (CLKDIV) section. In parallel mode, sam-
ples are taken on the rising edge of CLKP. Conversion
data appears at the outputs on the rising edge of
DCLKP after the latency period of 11 clock cycles and
is stable for one clock period (Figure 5). If an overrange
condition occurs, it is reflected on the ORA port.
System Timing Requirements
Figures 5, 6, and 7 depict the relationship between the
clock input and output, analog input, sampling event,
and data output. The MAX19542 samples on the rising
(falling) edge of CLKP (CLKN). In all these figures,
CLKDIV is assumed to be high; otherwise, the sampling
events would occur at every other rising edge of CLKP.
Output data is latched on the next rising (falling) edge
of the DCLKP (DCLKN) clock, but has an internal laten-
cy of 11 input clock cycles.
Modes of Operation
The MAX19542 features three modes of operation. In
each mode of operation, the conversion data is output
in a different format.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
t
AD
CLKN
N
N + 1
N + 11
N + 12
CLKP
t
t
CL
CH
RESET
t
CPDL
DCLKN
DCLKP
N - 11
N - 10
N
N + 1
t
LATENCY
t
PDL
N - 11
N - 10
N - 1
N
N + 1
DA0–DA11, ORA
Figure 5. Parallel Mode Timing Diagram
______________________________________________________________________________________ 13
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Demux Parallel Mode
Drive DEMUX high and ITL low to place the MAX19542
in the demux parallel mode. In this mode, the output
clock’s frequency is 1/2 the sampling frequency. The
sampling frequency may not be the same as the input
clock frequency. See the Divide-by-Two Clock Control
(CLKDIV) section. Each conversion starts with a sam-
pling event on the rising edge of CLKP. Conversion
data now appears on both DA0–DA11 and DB0–DB11.
The first conversion result is output on the A ports on
the rising edge of DCLKP after 12 input clock cycles
from the initial sampling event. The second conversion
result is output on the B ports on the rising edge of
DCLKP after 11 input clock cycles from the initial sam-
pling event. Both conversion results are output simulta-
neously (Figure 6). The conversion results on ports A
and B remain stable for one period of DCLKP after they
become valid. Thus, the overall throughput rate is the
same as in parallel mode; however, now each data line
is allowed to be valid for a longer time (two sampling
periods, one digital clock period). Overrange condi-
tions are reflected on the appropriate output port, ORA
or ORB, depending on which conversion they occur.
The demux interleaved mode is the recommended
demux mode of operation due to the fact that output
bus switching is more evenly distributed over sample
clock edges.
MAX19542
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
t
AD
CLKN
N
N + 12
t
CLKP
t
t
CL
CPDL
CH
RESET
DCLKP
DCLKN
N
N + 2
t
LATENCY
t
PDL
DA0–DA11, ORA
DB0–DB11, ORB
N
N + 2
N + 3
N + 1
DEMUX PARALLEL MODE
Figure 6. Demux Parallel Mode Timing Diagram
14 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
Demux Interleaved Mode
Drive DEMUX high and ITL high to place the
MAX19542 in the demux interleaved mode of operation.
In this mode, the output clock’s frequency is 1/2 the
sampling frequency. The sampling frequency may not
be the same as the input clock frequency. See the
Divide-by-Two Clock Control (CLKDIV) section. Each
conversion starts with a sampling event on the rising
edge of CLKP. Conversion data now appears on both
DA0–DA11 and DB0–DB11. The first conversion result
is output on the A ports on the rising edge of DCLKP
after 12 input clock cycles from the initial sampling
event. The second conversion result is output on the B
ports on the rising edge of DCLKN after 12 input clock
cycles from the initial sampling event. In this way, the two
conversion results are interleaved with respect to each
other (Figure 7). The conversion results on ports A and B
remain stable for one period of DCLKP and DCLKN,
respectively, after they become valid. Overrange condi-
tions are reflected on the appropriate output port, ORA
or ORB, depending on which conversion they occur.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
t
AD
CLKN
N
N + 12
t
CLKP
t
t
CL
CPDL
CH
RESET
DCLKP
DCLKN
N
N + 2
t
LATENCY
t
PDL
DA0–DA11, ORA
DB0–DB11, ORB
N
N + 2
N + 1
N + 3
DEMUX INTERLEAVED MODE
Figure 7. Demux Interleaved Mode Timing Diagram
______________________________________________________________________________________ 15
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
The MAX19542 offers an additional differential output
Digital Outputs
(DA0–DA11, DCLKP, DCLKN, ORA,
pair (ORA, ORB) to flag overrange conditions, where
overrange is above positive or below negative full scale.
An overrange condition is identified with ORA/ORB tran-
sitioning high.
DB0–DB11, ORB) and Control Input T/B
Digital outputs DA0/DB0–DA11/DB11, DCLKP, DCLKN,
ORA/ORB are CMOS compatible, and data on DA0/DB
DA11/DB11 are presented in either binary or two’s-
complement format (Table 1). The T/B control line is an
LVCMOS-compatible input that allows the user to select
the desired output format. Drive T/B high to select data
to be output in offset binary format and drive it low to
select data to be output in two’s complement format on
the 12-bit parallel bus. T/B has an internal pulldown
resistor and can be left unconnected in applications
using only two’s-complement output format. The CMOS
outputs are powered from a separate power supply that
can be operated between 1.7V and 1.9V.
Note: Keep the capacitive load on the digital outputs as
low as possible. Use digital buffers on the digital out-
puts of the ADC when driving larger loads to improve
overall performance and reduce system timing con-
straints. Further improvements in dynamic performance
can be achieved by adding small series resistors
(100Ω) to the digital output paths, close to the ADC.
MAX19542
Table 1. MAX19542 Digital Output Coding
BINARY
DIGITAL OUTPUT CODE
(D_11–D_0)
TWO’S-COMPLEMENT
DIGITAL OUTPUT CODE
(D_11–D_0)
INP ANALOG INPUT
VOLTAGE LEVEL
INN ANALOG INPUT
VOLTAGE LEVEL
OVERRANGE
ORA/ORB
1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
> V
+ 0.35V
< V
- 0.35V
REF
1
0
REF
1111 1111 1111
(+FS)
0111 1111 1111
(+FS)
V
+ 0.35V
V
- 0.35V
REF
REF
V
1000 0000 0000 or
0111 1111 1111
(FS/2)
0000 0000 0000 or
1111 1111 1111
(FS/2)
V
0
REF
REF
0000 0000 0000
(-FS)
1000 0000 0000
(-FS)
V
- 0.35V
V
+ 0.35V
0
1
REF
REF
00 0000 0000
(exceeds -FS, OR set)
10 0000 0000
(exceeds -FS, OR set)
< V
+ 0.35V
> V
- 0.35V
REF
REF
16 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
overall full-scale range adjustment of the MAX19542.
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
Do not use resistor values of less than 13kΩ to avoid
instability of the internal gain regulation loop for the
bandgap reference. Use the following formula to calcu-
late the percentage change of the reference voltage:
The MAX19542 supports a full-scale adjustment range
of 10%. To decrease the full-scale range, an external
resistor value ranging from 13kΩ to 1MΩ can be added
between REFADJ and AGND. A similar approach can
be taken to increase the ADCs full-scale range. Add a
variable resistor, potentiometer, or predetermined resis-
tor value between REFADJ and REFIO to increase the
full-scale range of the data converter. Figure 8 shows
the two possible configurations and their impact on the
100kΩ
V
REF
(%) = 1.25% x
R
ADJ
The percentage change is positive when R
is
ADJ
added between REFADJ and REFIO, and is negative
when R is added between REFADJ and GND.
ADJ
ADC FULL SCALE = REFT - REFB
ADC FULL SCALE = REFT-REFB
REFERENCE-
SCALING
AMPLIFIER
REFERENCE-
SCALING
AMPLIFIER
REFT
REFB
REFT
REFB
G
G
REFERENCE
BUFFER
REFERENCE
BUFFER
1V
REFIO
1V
REFIO
0.1µF
0.1µF
13kΩ TO
100kΩ
MAX19542
MAX19542
REFADJ
REFADJ
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
13kΩ TO 100kΩ
AVCC
AVCC/2
AVCC
AVCC/2
Figure 8. Circuit Suggestions to Adjust the ADC’s Full-Scale Range (Simplified Schematic)
______________________________________________________________________________________ 17
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
tion to convert a single-ended source signal to a fully
differential signal, required by the MAX19542 for opti-
mum dynamic performance.
Differential, AC-Coupled, LVPECL-
Compatible Clock Input
The MAX19542 dynamic performance depends on a
very clean clock source. The phase noise floor of the
clock source has a negative impact on the SNR perfor-
mance. Spurious signals on the clock signal source
also affect the ADC’s dynamic range. The preferred
method of clocking the MAX19542 is differentially with
LVPECL-compatible input levels. The fast data transition
rates of these logic families minimize the clock-input cir-
cuitry’s transition uncertainty, thereby improving the SNR
performance. Apply a 50Ω reverse-terminated clock
signal source with low phase noise AC-coupled into a
fast differential receiver such as the MC100LVEL16
(Figure 9). The receiver produces the necessary
LVPECL output levels to drive the clock inputs of the
data converter.
A secondary-side termination of a 1:1 transformer (e.g.,
Mini-Circuit’s ADT1-1WT) into two separate 24.9Ω
0.1% resistors (use tight resistor tolerances to mini-
mize effects of imbalance; 0.1% would be an ideal
choice) placed between top/bottom and center tap of
the transformer is recommended to maximize the
ADC’s dynamic range. This configuration optimizes
THD and SFDR performance of the ADC by reducing
the effects of transformer parasitics. However, the
source impedance combined with the shunt capaci-
tance provided by a PC board and the ADC’s parasitic
capacitance limit the ADC’s full-power input bandwidth
to approximately 600MHz.
MAX19542
To further enhance THD and SFDR performance at high
input frequencies (>100MHz), a second transformer
(Figure 10) should be placed in series with the single-
ended-to-differential conversion transformer. This trans-
former reduces the increase of even-order harmonics
at high frequencies.
Transformer-Coupled,
Differential Analog Input Drive
The MAX19542 provides the best SFDR and THD with
fully differential input signals and it is not recommend-
ed driving the ADC inputs in single-ended configura-
tion. In differential input mode, even-order harmonics
are usually lower since INP and INN are balanced, and
each of the ADC inputs requires only half the signal
swing compared to a single-ended configuration.
Wideband RF transformers provide an excellent solu-
For more detailed information on transformer termina-
tion methods, refer to the Application Note: Secondary-
Side Transformer Termination Improves Gain Flatness
in High-Speed ADCs from the Maxim website:
www.maxim-ic.com.
V
CLK
0.1µF
SINGLE-ENDED
INPUT TERMINAL
8
0.1µF
0.1µF
2
3
7
6
150Ω
0.1µF
MC100LVEL16
AVCC OVCC
50Ω
510Ω
150Ω
510Ω
CLKN CLKP
INP
INN
D_0–D_11, OR_
12
4
5
0.01µF
MAX19542
V
GND
AGND
OGND
Figure 9. Differential, AC-Coupled, LVPECL-Compatible Clock Input Configuration
18 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
AVCC
OVCC
10Ω
SINGLE-ENDED
INP
INPUT TERMINAL
0.1µF
ADT1-1WT
ADT1-1WT
D_0–D_11, OR_
25Ω
MAX19542
25Ω
12
INN
10Ω
0.1µF
AGND
OGND
Figure 10. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
ranges. Although both supply types can be combined
and supplied from one source, it is recommended
using separate sources to cut down on performance
degradation caused by digital switching currents that
can couple into the analog supply network. Isolate ana-
log and digital supplies (AVCC and OVCC) where they
enter the PC board with separate networks of ferrite
beads and capacitors to their corresponding grounds
(AGND, OGND).
AVCC
OVCC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
0.1µF
INP
INN
D_0–D_11, OR_
50Ω
MAX19542
12
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 12). Locate these capacitors directly at the
ADC supply pins or as close as possible to the
MAX19542. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter, to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
25Ω
AGND
OGND
Figure 11. Single-Ended AC-Coupled Analog Input Configuration
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX19542 can be
used in single-ended mode (Figure 11). Analog signals
can be AC-coupled to the positive input INP through a
0.1µF capacitor and terminated with a 49.9Ω resistor to
AGND. Terminate the negative input with a 24.9Ω resis-
tor and AC ground it with a 0.1µF capacitor.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long dis-
tances before they are recombined at a common
source ground, resulting in large and undesirable
Grounding, Bypassing, and Board
Layout Considerations
The MAX19542 requires board layout design tech-
niques suitable for high-speed data converters. This
ADC provides separate analog and digital power sup-
plies. The analog and digital supply voltage inputs
AVCC and OVCC accept 1.7V to 1.9V input voltage
______________________________________________________________________________________ 19
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Take considerable care when routing the digital output
traces for a high-speed, high-resolution data converter.
It is essential to keep trace lengths at a minimum and
place minimal capacitive loading—less than 5pF—on
any digital trace to prevent coupling to sensitive analog
sections of the ADC. Route high-speed digital signal
traces away from sensitive analog traces, and remove
digital ground and power planes from underneath digital
outputs. Keep all signal lines short and free of 90° turns.
Alternatively, all ground pins could share the same
ground plane if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sec-
tions of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
Static Parameter Definitions
MAX19542
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX19542 are mea-
sured using the histogram method with a 10MHz input
frequency.
The MAX19542 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the board with standard infrared (IR)
flow-soldering techniques.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX19542’s DNL specification is measured with the
histogram method based on a 10MHz input tone.
Thermal efficiency is one of the factors for the selection
of a package with an exposed pad for the MAX19542.
The exposed pad improves thermal dissipation and
ensures a solid ground connection between the ADC
and the PC board’s analog ground layer.
BYPASSING-ADC LEVEL
BYPASSING-BOARD LEVEL
AVCC
OVCC
AVCC
0.1µF
0.1µF
ANALOG POWER-
SUPPLY SOURCE
10µF
47µF
1µF
D_0–D_11, OR_
OVCC
MAX19542
12
DIGITAL/OUTPUT
DRIVER POWER-
SUPPLY SOURCE
10µF
47µF
1µF
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
AGND
OGND
Figure 12. Grounding, Bypassing, and Decoupling Recommendations for the MAX19542
20 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
Spurious-Free Dynamic Range (SFDR)
Dynamic Parameter Definitions
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion compo-
nent. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Aperture Jitter
Figure 13 depicts the aperture jitter (t ), which defines
AJ
the sample-to-sample variation in the aperture delay.
Aperture jitter is measured in ps
.
RMS
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
620ps rising edge of the sampling clock and the instant
when an actual sample is taken (Figure 13).
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 2nd-order (or higher) inter-
modulation products. The individual input tone levels
are usually set to 7dB below full scale and intermodula-
tion products IM2 through IM5 are considered for the
IMD calculation. The various intermodulation products
are defined as follows:
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
•
•
•
•
2nd-order intermodulation distortion (IM2):
+ f , f - f
f
IN1
IN2 IN2 IN1
3rd-order intermodulation distortion (IM3):
2f + f , 2f - f , 2f + f , 2f - f
IN2 IN1
IN1
IN2
IN1 IN2
IN2
IN1
SNR
= 6.02 x N + 1.76
dB dB
dB[max]
4th-order intermodulation distortion (IM4):
3f + f , 3f - f , 3f + f , 3f - f
IN2 IN1
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calcula-
tion and should be considered when determining the
SNR of an ADC.
IN1
IN2
IN1 IN2
IN2
IN1
5th-order intermodulation distortion (IM5):
4f + f , 4f - f , 4f + f , 4f - f
IN2 IN1
IN1
IN2
IN1 IN2
IN2
IN1
Full-Power Bandwidth
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components excluding the fundamen-
tal and the DC offset. In the case of the MAX19542,
SINAD is computed from a curve fit.
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB point is defined as
the full-power input bandwidth frequency of the ADC.
CLKN
CLKP
ANALOG
INPUT
t
AD
t
AJ
SAMPLED
DATA (T/H)
HOLD
TRACK
TRACK
T/H
Figure 13. Aperture Jitter/Delay Specifications
______________________________________________________________________________________ 21
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
LAND
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0122
PATTERN NO.
90-0245
68 QFN-EP
G6800+4
MAX19542
22 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
MAX19542
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
11/04
10/10
Initial release
Updated Ordering Information and Electrical Characteristics
—
1, 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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