MAX195BC/D [MAXIM]
16-Bit, 85ksps ADC with 10レA Shutdown; 16位85ksps ADC，具有10μA停机
| 型号： | MAX195BC/D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit, 85ksps ADC with 10レA Shutdown |
| 文件： | 总28页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0377; Rev 1; 12/97
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 16 Bits, No Missing Codes
♦ 90dB SINAD
The MAX195 is a 16-bit successive-approximation ana-
log -to-d ig ita l c onve rte r (ADC) tha t c omb ine s hig h
speed, high accuracy, low power consumption, and a
10µA shutdown mode. Internal calibration circuitry cor-
rects linearity and offset errors to maintain the full rated
performance over the operating temperature range with-
out external adjustments. The capacitive-DAC architec-
ture provides an inherent 85ksps track/hold function.
♦ 9.4µs Conversion Time
♦ 10µA (max) Shutdown Mode
♦ Built-In Track/Hold
♦ AC and DC Specified
♦ Unipolar (0V to V
) and Bipolar (-V
to V
)
REF
REF
REF
The MAX195, with an external reference (up to +5V),
Input Range
offers a unipolar (0V to V ) or bipolar (-V
to V
)
REF
REF
REF
pin-selectable input range. Separate analog and digital
supplies minimize digital-noise coupling.
♦ Three-State Serial-Data Output
♦ Small 16-Pin DIP, SO, and Ceramic SB Packages
The chip select (CS) input controls the three-state serial-
data output. The output can be read either during conver-
sion as the bits are determined, or following conversion at
up to 5Mbps using the serial clock (SCLK). The end-of-
conversion (EOC) output can be used to interrupt a
processor, or can be connected directly to the convert
input (CONV) for continuous, full-speed conversions.
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Wide SO
MAX195BCPE
MAX195BCWE
MAX195ACDE
MAX195BC/D
MAX195BEPE
MAX195BEWE
MAX195AEDE
MAX195AMDE
MAX195BMDE
0°C to +70°C
The MAX195 is available in 16-pin DIP, wide SO, and
ceramic sidebraze packages.
0°C to +70°C
16 Ceramic SB
Dice*
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
16 Plastic DIP
16 Wide SO
________________________Ap p lic a t io n s
Portable Instruments
16 Ceramic SB
16 Ceramic SB**
16 Ceramic SB**
Audio
Industrial Controls
Robotics
* Dice are specified at T = +25°C, DC parameters only.
A
** Contact factory for availability and processing to MIL-STD-883.
Multiple Transducer Measurements
Medical Signal Acquisition
Vibrations Analysis
________________Fu n c t io n a l Dia g ra m
Digital Signal Processing
13
__________________P in Co n fig u ra t io n
4
6
11
16
AIN
REF
VDDD
DGND
MAIN DAC
12
Σ
VSSD
VDDA
AGND
VSSA
TOP VIEW
14
15
BP/UP/SHDN
CLK
VDDA
VSSA
AGND
AIN
1
2
3
4
5
6
7
8
COMPARATOR
MAX195
16
15
14
13
12
11
10
9
CALIBRATION
DACs
SCLK
SAR
VDDD
MAX195
2
CLK
SCLK
DOUT
DGND
EOC
REF
3
9
1
8
5
7
DOUT
EOC
VSSD
RESET
CONV
CONV
THREE-STATE BUFFER
CONTROL LOGIC
BP/UP/SHDN
CS
CS
10
RESET
DIP/Wide SO/Ceramic SB
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
ABSOLUTE MAXIMUM RATINGS
VDDD to DGND .....................................................................+7V
VDDA to AGND......................................................................+7V
VSSD to DGND.........................................................+0.3V to -6V
VSSA to AGND .........................................................+0.3V to -6V
VDDD to VDDA, VSSD to VSSA..........................................±0.3V
AIN, REF ....................................(VSSA - 0.3V) to (VDDA + 0.3V)
AGND to DGND..................................................................±0.3V
Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V)
Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V)
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 10.53mW/°C above +70°C) ............842mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
Ceramic SB (derate 10.53mW/°C above +70°C)...........842mW
Operating Temperature Ranges
MAX195_C_E ........................................................0°C to +70°C
MAX195_E_E .....................................................-40°C to +85°C
MAX195_MDE..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
MAX195
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
= 1.7MHz, V
= +5V, T = T
to T , unless otherwise noted. Typical
MAX
CLK
REF
A
MIN
values are at T = +25°C.)
A
PARAMETER
ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
16
Bits
MAX195A
±1
±2
Differential Nonlinearity
Integral Nonlinearity
DNL
LSB
MAX195B
MAX195A
MAX195B
±0.003
±0.004
±3
INL
%FSR
MAX195A, V
= 4.75V
= 4.75V
REF
Unipolar/Bipolar Offset Error
LSB
MAX195B, V
±4
REF
Unipolar/Bipolar Offset Tempco
Unipolar Full-Scale Error
Bipolar Full-Scale Error
Full-Scale Tempco
0.4
0.1
ppm/°C
V
= 4.75V
±0.0075 %FSR
REF
V
REF
= 4.75V
±0.018
%FSR
ppm/°C
VDDA = 4.75V to 5.25V, V
= 4.75V
65
65
REF
Power-Supply Rejection
Ratio (VDDA and VSSA only)
dB
VSSA = -5.25V to -4.75V, V
= 4.75V
REF
ANALOG INPUT
Unipolar
Bipolar
Unipolar
Bipolar
0
V
REF
Input Range
V
-V
REF
V
REF
250
125
Input Capacitance
pF
DYNAMIC PERFORMANCE (f = 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1)
s
Signal-to-Noise plus Distortion
Ratio (Note 2)
SINAD
THD
T
= +25°C
87
90
dB
dB
A
Total Harmonic Distortion (up to
the 5th harmonic) (Note 2)
T
A
= +25°C
= +25°C
-97
-90
-90
Peak Spurious Noise (Note 2)
Conversion Time
T
A
dB
µs
t
16 (t
)
9.4
CONV
CLK
Clock Frequency
(Notes 3, 4)
f
1.7
5
MHz
MHz
CLK
Serial Clock Frequency
f
SCLK
2
_______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
= 1.7MHz, V
= +5V, T = T
to T , unless otherwise noted. Typical
MAX
CLK
REF
A
MIN
values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN)
CLK, CS, CONV, RESET, SCLK
Input High Voltage
V
VDDD = 5.25V
VDDD = 4.75V
2.4
V
V
IH
CLK, CS, CONV, RESET, SCLK
Input Low Voltage
V
IL
0.8
10
CLK, CS, CONV, RESET, SCLK
Input Capacitance (Note 3)
pF
µA
V
CLK, CS, CONV, RESET, SCLK
Input Current
Digital inputs = 0 or 5V
±10
BP/UP/SHDN
Input High Voltage
V
IH
VDDD - 0.5
BP/UP/SHDN
Input Low Voltage
V
0.5
4.0
V
IL
BP/UP/SHDN
Input Current, High
I
IH
µA
µA
V
BP/UP/SHDN = VDDD
BP/UP/SHDN = 0V
BP/UP/SHDN
Input Current, Low
I
IL
-4.0
1.5
BP/UP/SHDN
Mid Input Voltage
V
IM
VDDD - 1.5
BP/UP/SHDN Voltage,
Floating
V
2.75
V
BP/UP/SHDN = open
BP/UP/SHDN = open
FLT
BP/UP/SHDN Max Allowed
Leakage, Mid Input
-100
+100
0.4
nA
DIGITAL OUTPUTS (DOUT, EOC)
Output Low Voltage
Output High Voltage
DOUT Leakage Current
Output Capacitance (Note 2)
POWER REQUIREMENTS
VDDD
V
VDDD = 4.75V, I
VDDD = 4.75V, I
DOUT = 0 or 5V
= 1.6mA
V
V
OL
SINK
V
OH
= 1mA
VDDD - 0.5
SOURCE
I
±10
10
µA
pF
LKG
4.75
-5.25
4.75
5.25
-4.75
5.25
-4.75
4
V
V
VSSD
VDDA
By supply-rejection test
By supply-rejection test
V
VSSA
-5.25
V
VDDD Supply Current
VSSD Supply Current
VDDA Supply Current
VSSA Supply Current
I
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
2.5
0.9
3.8
3.8
mA
mA
mA
mA
DDD
I
2
SSD
I
5
DDA
I
5
SSA
_______________________________________________________________________________________
3
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
= 1.7MHz, V
= +5V, T = T
to T , unless otherwise noted. Typical
MAX
CLK
REF
A
MIN
values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
POWER REQUIREMENTS (cont.)
Power Dissipation
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
80
5
mW
µA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VDDD Shutdown Supply Current
(Note 5)
MAX195
I
1.6
0.1
0.1
0.1
DDD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VSSD Shutdown Supply Current
VDDA Shutdown Supply Current
VSSA Shutdown Supply Current
I
5
5
5
µA
µA
µA
SSD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
I
DDA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
I
SSA
Note 1: Accuracy and dynamic performance tests performed after calibration.
Note 2: Guaranteed by design, not tested.
Note 3: Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable.
Note 4: See External Clock section.
Note 5: Measured in shutdown mode with CLK and SCLK low.
TIMING CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.)
T
= 0°C to
+70°C
T
= -40°C to
+85°C
T
A
= -55°C to
+125°C
A
A
T
= +25°C
TYP
A
PARAMETER
CONV Pulse Width
SYMBOL CONDITIONS
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
t
20
30
35
ns
ns
CW
CONV to CLK Falling
Synchronization (Note 2)
t
10
40
10
40
10
40
CC1
CC2
CONV to CLK Rising
Synchronization (Note 2)
t
ns
Data Access Time
t
C
C
C
C
C
C
= 50pF
= 10pF
= 50pF
= 50pF
= 50pF
= 50pF
80
80
90
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
DV
L
L
L
L
L
L
Bus Relinquish Time
CLK to EOC High
t
40
40
40
DH
t
300
300
350
140
300
300
375
160
350
350
400
160
CEH
t
CLK to EOC Low
CEL
CLK to DOUT Valid
SCLK to DOUT Valid
CS to SCLK Setup Time
CS to SCLK Hold Time
Acquisition Time
t
100
20
100
20
100
20
CD
t
SD
t
t
75
75
75
CSS
-10
2.4
8.2
-40
120
-10
2.4
8.2
-40
120
-10
2.4
8.2
-40
120
CSH
t
AQ
Calibration Time
t
14,000 x t
CLK
CAL
RCS
t
t
RESET to CLK Setup Time
RESET to CLK Hold Time
RCH
Exiting
shutdown
Start-Up Time (Note 6)
t
50
µs
SU
Note 6: Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
4
_______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown.
0V = shutdown, +5V = unipolar, floating = bipolar.
1
BP/UP/SHDN
2
3
4
5
6
CLK
SCLK
VDDD
DOUT
DGND
Conversion Clock Input
Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK.
+5V Digital Power Supply
Serial Data Output, MSB first
Digital Ground
End-of-Conversion/Calibration Output—normally low. Rises one clock cycle after the beginning of conversion
or calibration and falls one clock cycle after the end of either. May be used as an output framing signal.
7
8
9
EOC
CS
Chip-Select Input—active low. Enables the serial interface and the three-state data output (DOUT).
Convert-Start Input—active low. Conversion begins on the falling edge after CONV goes low if the input
signal has been acquired; otherwise, on the falling clock edge after acquisition.
CONV
Reset Input. Pulling RESET low places the ADC in an inactive state. Rising edge resets control logic and
begins calibration.
10
RESET
11
12
13
14
15
16
VSSD
REF
-5V Digital Power Supply
Reference Input, 0 to 5V
AIN
Analog Input, 0 to V
unipolar or ±V
bipolar range
REF
REF
AGND
VSSA
VDDA
Analog Ground
-5V Analog Power Supply
+5V Analog Power Supply
disconnected from AIN, trapping a charge proportional
to the input voltage on the capacitor array.
_______________De t a ile d De s c rip t io n
The MAX195 uses a successive-approximation register
(SAR) to convert an analog input to a 16-bit digital
code, which outputs as a serial data stream. The data
bits can be read either during the conversion, at the
CLK clock rate, or between conversions asynchronous
with CLK at the SCLK rate (up to 5Mbps).
The free terminal of the MSB (largest) capacitor is con-
nected to the reference (REF), which pulls the common
te rmina l (c onne c te d to the c omp a ra tor) p os itive .
Simultaneously, the free terminals of all other capaci-
tors in the array are connected to AGND, which drives
the comparator input negative. If the analog input is
The MAX195 includes a capacitive digital-to-analog
converter (DAC) that provides an inherent track/hold
input. The interface and control logic are designed for
easy connection to most microprocessors (µPs), limiting
the need for external components. In addition to the
SAR and DAC, the MAX195 includes a serial interface, a
sampling comparator used by the SAR, ten calibration
DACs, and control logic for calibration and conversion.
near V , connecting the MSB’s free terminal to REF
REF
only p ulls the c omp a ra tor inp ut s lig htly p os itive .
However, connecting the remaining capacitor’s free ter-
mina ls to g round d rive s the c omp a ra tor inp ut we ll
below ground, so the comparator input is negative, the
comparator output is low, and the MSB is set high. If
the analog input is near ground, the comparator output
is high and the MSB is low.
The DAC consists of an array of 16 capacitors with
binary weighted values plus one “dummy LSB” capaci-
tor (Fig ure 1). During inp ut a c q uis ition in unip ola r
mode, the array’s common terminal is connected to
AGND and all free terminals are connected to the input
signal (AIN). After acquisition, the common terminal is
disconnected from AGND and the free terminals are
Following this, the next largest capacitor is disconnect-
ed from AGND and connected to REF, and the com-
parator determines the next bit. This continues until all
bits have been determined. For a bipolar input range,
the MSB capacitor is connected to REF rather than AIN
during input acquisition, which results in an input range
of V
to -V
.
REF
REF
_______________________________________________________________________________________
5
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MSB
LSB
DUMMY
32,768C
16,384C
4C
2C
C
C
MAX195
AIN
REF
AGND
Figure 1. Capacitor DAC Functional Diagram
t
CAL
CLK
t
RCH
t
RCS
RESET
EOC
CALIBRATION
BEGINS
CALIBRATION
ENDS
MAX195
OPERATION HALTS
Figure 2. Initiating Calibration
output and offset the main DAC’s output according to
the value on their digital inputs. During calibration, the
correct digital code to compensate for the error in each
MSB capacitor is determined and stored. Thereafter,
the stored code is input to the appropriate calibration
DAC whenever the corresponding bit in the main DAC
is hig h, c omp e ns a ting for e rrors in the a s s oc ia te d
capacitor.
Ca lib ra t io n
In an ideal DAC, each of the capacitors associated with
the data bits would be exactly twice the value of the
next smaller capacitor. In practice, this results in a
range of values too wide to be realized in an economi-
cally feasible size. The capacitor array actually consists
of two arrays, which are capacitively coupled to reduce
the LSB array’s effective value. The capacitors in the
MSB array are production trimmed to reduce errors.
Sma ll va ria tions in the LSB c a p a c itors c ontrib ute
insignificant errors to the 16-bit result.
The MAX195 calibrates automatically on power-up. To
reduce the effects of noise, each calibration experiment
is performed many times and the results are averaged.
Ca lib ra tion re q uire s a b out 14,000 c loc k c yc le s , or
8.2ms at the highest clock (CLK) speed (1.7MHz). In
addition to the power-up calibration, bringing RESET
low halts MAX195 operation, and bringing it high again
initiates a calibration (Figure 2).
Unfortunately, trimming alone does not yield 16-bit per-
formance or compensate for changes in performance
due to changes in temperature, supply voltage, and
other parameters. For this reason, the MAX195 includes
a calibration DAC for each capacitor in the MSB array.
These DACs are capacitively coupled to the main DAC
6
_______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
t
CC1
t
CC2
CLK
EOC
t
t
CEH
CEL
*
CONV
t
CW
TRACK/HOLD
t
AQ
CONVERSION
ENDS
CONVERSION
BEGINS
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.
If the power supplies do not settle within the MAX195’s
power-on delay (500ns minimum), power-up calibration
may begin with supply voltages that differ from the final
values and the converter may not be properly calibrat-
ed. If so, recalibrate the converter (pulse RESET low)
b e fore us e . For b e s t DC a c c ura c y, c a lib ra te the
MAX195 any time there is a significant change in sup-
ply voltages, temperature, reference voltage, or clock
characteristics (see External Clock section) because
these parameters affect the DC offset. If linearity is the
only concern, much larger changes in these parame-
ters can be tolerated.
input (AIN = 0V to V
places the MAX195 in its 10µA shutdown mode.
). Bringing BP/UP/SHDN low
REF
A logic low on RESET halts MAX195 operation. The ris-
ing edge of RESET initiates calibration as described in
the Calibration section above.
Begin a conversion by bringing CONV low. After con-
ve rs ion b e g ins , a d d itiona l c onve rt s ta rt p uls e s a re
ignored. The convert signal must be synchronized with
CLK. The falling edge of CONV must occur during the
period shown in Figures 3 and 4. When CLK is not
directly controlled by your processor, two methods of
ensuring synchronization are to drive CONV from EOC
(continuous conversions) or to gate the conversion-start
signal with the conversion clock so that CONV can go
low only while CLK is low (Figure 5). Ensure that the
maximum propagation delay through the gate is less
than 40ns.
Because the calibration data is stored digitally, there is
no need either to perform frequent conversions to main-
tain accuracy or to recalibrate if the MAX195 has been
held in shutdown for long periods. However, recalibra-
tion is recommended if it is likely that ambient tempera-
ture or sup ply volta g e s ha ve signific a ntly c ha ng e d
since the previous calibration.
The MAX195 automatically ensures four CLK periods
for track/hold acquisition. If, when CONV is asserted, at
least three clock (CLK) cycles have passed since the
end of the previous conversion, a conversion will begin
on CLK’s next falling edge and EOC will go high on the
following falling CLK edge (Figure 3). If, when convert
is asserted, less than three clock cycles have passed,
a conversion will begin on the fourth falling clock edge
Dig it a l In t e rfa c e
The digital interface pins consist of BP/UP/SHDN, CLK,
SCLK, EOC, CS, CONV, and RESET.
BP/UP/SHDN is a three-level input. Leave it floating to
configure the MAX195’s analog input in bipolar mode
(AIN = -V
to V ) or connect it high for a unipolar
REF
REF
_______________________________________________________________________________________
7
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
t
CC1
t
CC2
CLK
MAX195
t
t
CEH
CEL
EOC
*
CONV
t
CW
t
TRACK/HOLD
AQ
CONVERSION
ENDS
CONVERSION
BEGINS
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
Output Data
after the end of the previous conversion and EOC will
The conversion result, clocked out MSB first, is avail-
able on DOUT only when CS is held low. Otherwise,
DOUT is in a high-impedance state. There are two ways
to read the data on DOUT. To read the data bits as they
are determined (at the CLK clock rate), hold CS low
during the conversion. To read results between conver-
sions, hold CS low and clock SCLK at up to 5MHz.
go high on the following CLK falling edge (Figure 4).
External Clock
The conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the min-
imum high and low times exceed 150ns. The minimum
clock rate for accurate conversion is 125Hz for temper-
atures up to +70°C or 1kHz at +125°C due to leakage
of the s a mp ling c a p a c itor a rra y. In a d d ition, CLK
should not remain high longer than 50ms at tempera-
tures up to +70°C or 500µs at +125°C. If CLK is held
high longer than this, RESET must be pulsed low to initi-
ate a recalibration because it is possible that state
information stored in internal dynamic memory may be
lost. The MAX195’s clock can be stopped indefinitely if
it is held low.
If you read the serial data bits as they are determined,
EOC frames the data bits (Figure 6). Conversion begins
with the first falling CLK edge, after CONV goes low
and the input signal has been acquired. Data bits are
shifted out of DOUT on subsequent falling CLK edges.
Clock data in on CLK’s rising edge or, if the clock
speed is greater than 1MHz, on the following falling
edge of CLK to meet the maximum CLK-to-DOUT tim-
ing s p e c ific a tion. Se e the Op e ra ting Mod e s a nd
SPI™/QSPI™ Interfaces section for additional informa-
tion. Reading the serial data during the conversion
re s ults in the ma ximum c onve rs ion throug hp ut,
because a new conversion can begin immediately after
the input acquisition period following the previous con-
version.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by cou-
pling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
SPI/QSPI are trademarks of Motorola Corp.
8
_______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
START
MAX195
CONV
CLK
START
CLK
CONV
SEE DIGITAL INTERFACE SECTION
Figure 5. Gating CONV to Synchronize with CLK
CS
CONV
t
CW
CLK
(CASE 1)
CLK
(CASE 2)
t
t
CEH
CEL
EOC
t
DV
t
CD
B15 FROM PREVIOUS
CONVERSION
DOUT
B15
MSB
B14
B13
B12
B2
B1
B0
B15
t
DH
LSB
CONVERSION
BEGINS
CONVERSION
ENDS
CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
If you read the data bits between conversions, you can:
1) count CLK cycles until the end of the conversion, or
Note that the MSB conversion result appears at DOUT
after CS goes low, but before the first SCLK pulse.
Each subsequent SCLK pulse shifts out the next con-
version bit. The 15th SCLK pulse shifts out the LSB.
Additional clock pulses shift out zeros.
2) p oll EOC to d e te rmine whe n the c onve rs ion is
finished, or
3) generate an interrupt on EOC’s falling edge.
_______________________________________________________________________________________
9
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
t
CONV
EOC
CS
t
CSS
t
CSH
MAX195
SCLK
(CASE 1)
SCLK
(CASE 2)
SCLK
(CASE 3)
DOUT
B15
MSB
B14
B13
B12
B11
B3
B2
B1
B0
LSB
t
DV
t
SD
t
DH
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0)
NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
Data is clocked out on SCLK’s falling edge. Clock
data in on SCLK’s rising edge or, for clock speeds
above 2.5MHz, on the following falling edge to meet
the ma ximum SCLK-to-DOUT timing s p e c ific a tion
(Figure 7). The maximum SCLK speed is 5MHz. See
the Operating Modes and SPI/QSPI Interfaces section
for additional information. When the conversion clock
is near its maximum (1.7MHz), reading the data after
each conversion (during the acquisition time) results
in lower throughput (about 70ksps max) than reading
the data during conversions, because it takes longer
than the minimum input acquisition time (four cycles
at 1.7MHz) to clock 16 data bits at 5Mbps. After the
data has been clocked in, leave some time (about
1µs) for any coupled noise on AIN to settle before
beginning the next conversion.
+5V
10µF
-5V
10µF
0.1µF
BP/UP/
0.1µF
1
2
3
4
16
15
14
VDDA
VSSA
AGND
AIN
SHDN
CLK
CONVERSION
CLOCK
MAX195
SCLK
VDDD
ANALOG
INPUT
13
12
11
5
6
DOUT
DGND
REF
VSSD
RESET
CONV
REFERENCE
(0V TO VDDA)
10
9
7
8
EOC
CS
Whichever method is chosen for reading the data, con-
versions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX195 in its simplest
operational configuration.
Figure 8. MAX195 in the Simplest Operating Configuration
10 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
Table 1. Low-ESR Capacitor Suppliers
COMPANY
Sprague
AVX
CAPACITOR
FACTORY FAX [COUNTRY CODE]
1-603-224-1430
USA TELEPHONE
603-224-1961
800-282-4975
619-661-6835
708-843-7500
595D series,
592D series
TPS series
1-207-283-1941
OS-CON series,
MVGX series
Sanyo
81-7-2070-1174
Nichicon
PL series
1-708-843-2798
+5V
BRIDGE
INSTRUMENTATION
AMPLIFIER
VDDA
MAX195
AIN
REF
47µF
0.1µF
LOW ESR
CERAMIC
AGND
Figure 9. Ratiometric Measurement Without an Accurate Reference
DACs, all of which may be switching between GND and
REF a t the c onve rs ion c loc k fre q ue nc y. The tota l
capacitive load presented can exceed 1000pF and,
unlike the analog input (AIN), REF is sampled continu-
ously throughout the conversion.
__________Ap p lic a t io n s In fo rm a t io n
Re fe re n c e
The MAX195 reference voltage range is 0V to VDDA.
When choosing the reference voltage, the MAX195’s
e quiva le nt inp ut noise (40µV
in unip ola r mod e ,
RMS
The firs t s te p in c hoos ing a re fe re nc e c irc uit is to
decide what kind of performance is required. This often
suggests compromises made in the interests of cost
and size. It is possible that a system may not require an
accurate reference at all. If a system makes a ratiomet-
ric measurement such as Figure 9’s bridge circuit, any
relatively noise-free voltage that presents a low imped-
ance at the REF input will serve as a reference. The
+5V analog supply suffices if you use a large, low-
impedance bypass capacitor to keep REF stable dur-
ing switching of the capacitor arrays. Do not place a
resistance between the +5V supply and the bypass
capacitor, because it will cause linearity errors due to
the dynamic REF input current, which typically ranges
from 300µA to 400µA.
80µV
in bipolar mode) should be considered. Also, if
exceeds VDDA, errors will occur due to the internal
RMS
V
REF
protection diodes that will begin to conduct, so use cau-
tion when using a reference near VDDA (unless V
and VDDA are virtually identical). V
REF
must never
REF
exceed its absolute maximum rating (VDDA + 0.3V).
The MAX195 needs a good reference to achieve its
rated performance. The most important requirement is
that the reference must present a low impedance to the
REF input. This is often achieved by buffering the refer-
ence through an op amp and bypassing the REF input
with a large (1µF to 47µF), low-ESR capacitor in parallel
with a 0.1µF ceramic capacitor. Low-ESR capacitors
are available from the manufacturers listed in Table 1.
The reference must drive the main conversion DAC
capacitors as well as the capacitors in the calibration
Figure 10 shows a more typical scheme that provides
good AC accuracy. The MAX874’s initial accuracy can
______________________________________________________________________________________ 11
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
+15V
+5V
0.1µF
2
0.1µF
1k
16
V
VDDA
IN
2k
1N914
8
6
COMP
0.1µF
10Ω
MAX195
2
7
MAX195
1000pF
4.096V
MAX874
6
12
REF
MAX427
10Ω
1N914
3
V
OUT
47µF
LOW ESR
0.1µF
4
0.1µF
VSSA AGND
15 14
GND
0.1µF
4
-15V
-5V
Figure 10. Typical Reference Circuit for AC Accuracy
V
IN
≥ 8V
2
IN
MAX195
MAX6241
12
6
OUT
REF
2.2µF
3
5
10k
0.1µF
2.2µF
TRIM
NR
AGND
14
GND
4
1µF
Figure 11. High-Accuracy Reference
be improved by trimming, but the drift is too great to
provide good stability over temperature. The MAX427
buffer provides the necessary drive current to stabilize
the REF input quickly after capacitance changes.
of 1ppm/°C (typ). This allows reasonable temperature
c ha ng e s with le s s tha n 1LSB e rror. While the
MAX6241’s initia l-a c c ura c y s p e c ific a tion (0.02%)
results in an offset error of about ±14LSB, the reference
voltage can be trimmed or the offset can be corrected
in software if absolute DC accuracy is essential. Figure
11’s circuit provides outstanding temperature stability
and also provides excellent DC accuracy if the initial
error is corrected.
The reference inaccuracies contribute additional full-
1
16
scale error. A reference with less than
⁄
total error
2
(15 parts per million) over the operating temperature
range is required to limit the additional error to less
than 1LSB. The MAX6241 achieves a drift specification
12 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
+5V
+15V
VDDA
MAX195
10Ω
AIN
INPUT
SIGNAL
1N914
DIODE
VSSA
CLAMPS
-15V
-5V
Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence
Input Acquisition and Settling
REF a n d AIN In p u t P ro t e c t io n
Four conversion-clock periods are allocated for acquir-
ing the input signal. At the highest conversion rate, four
clock periods is 2.4µs. If more than three clock cycles
have occurred since the end of the previous conver-
sion, conversion begins on the next falling clock edge
after CONV goes low. Otherwise, bringing CONV low
begins a conversion on the fourth falling clock edge
after the previous conversion. This scheme ensures the
minimum input acquisition time is four clock periods.
The REF a nd AIN s ig na ls s hould not e xc e e d the
MAX195 supply rails. If this can occur, diode clamp the
signal to the supply rails. Use silicon diodes and a 10Ω
current-limiting resistor (Figures 10 and 12) or Schottky
diodes without the resistor.
When using the current-limiting resistor, place the resis-
tor between the appropriate input (AIN or REF) and any
bypass capacitor. While this results in AC transients at
the input due to dynamic input currents, the transients
settle quickly and do not affect conversion results.
Improperly placing the bypass capacitor directly at the
input forms an RC lowpass filter with the current-limiting
resistor, which averages the dynamic input current and
causes linearity errors.
Most applications require an input buffer amplifier. If
the input signal is multiplexed, the input channel should
be switched near the beginning of a conversion, rather
than near the end of or after a conversion (Figure 13).
This allows time for the input buffer amplifier to respond
to a large step change in input signal. The input amplifi-
er must have a high enough slew rate to complete the
required output voltage change before the beginning of
the acquisition time.
An a lo g In p u t
The MAX195 uses a capacitive DAC that provides an
inherent track/hold function. The input impedance is
typically 30Ω in series with 250pF in unipolar mode and
50Ω in series with 125pF in bipolar mode.
At the beginning of acquisition, the capacitive DAC is
connected to the amplifier output, causing some output
disturbance. Ensure that the sampled voltage has set-
tled to within the required limits before the end of the
acquisition time. If the frequency of interest is low, AIN
can be bypassed with a large enough capacitor to
charge the capacitive DAC with very little change in
voltage (Figure 14). However, for AC use, AIN must be
driven by a wideband buffer (at least 10MHz), which
must be stable with the DAC’s capacitive load (in paral-
lel with any AIN bypass capacitor used) and also must
settle quickly (Figure 15 or 16).
Input Range
The analog input range can be either unipolar (0V to
V
REF
) or bipolar (-V
to V
), depending on the
REF
REF
state of the BP/UP/SHDN pin (see Digital Interface sec-
tion). The reference range is 0V to VDDA. When choos-
ing the reference voltage, the equivalent MAX195 input
noise (40µV
in unipolar mode, 80µV
in bipolar
RMS
RMS
mode) should be considered.
______________________________________________________________________________________ 13
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
A0
A1
IN1
IN2
4-TO-1
MUX
MAX195
MAX195
IN3
IN4
AIN
OUT
EOC
CLK
CONVERSION
ACQUISITION
EOC
A0
A1
CHANGE MUX INPUT HERE
Figure 13. Change multiplexer input near beginning of conversion to allow time for slewing and settling.
1k
+5V
+15V
7
1000pF
0.1µF
0.1µF
1N914
10Ω
2
3
6
AIN
MAX400
100Ω
IN
4
1N914
1.0µF
-15V
-5V
Figure 14. MAX400 Drives AIN for Low-Frequency Use
14 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
Digital Noise
Digital noise can easily be coupled to AIN and REF. The
conversion clock (CLK) and other digital signals that are
active during input acquisition contribute noise to the con-
version result. If the noise signal is synchronous to the
sampling interval, an effective input offset is produced.
Asynchronous signals produce random noise on the input,
whose high-frequency components may be aliased into
the frequency band of interest. Minimize noise by present-
ing a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN to
AGND, or buffering the input with an amplifier that has a
small-signal bandwidth of several megahertz, or prefer-
ably both. AIN has a bandwidth of about 16MHz.
ing. Also, to reduce linearity errors due to finite amplifier
gain, use an amplifier circuit with sufficient loop gain at
the frequencies of interest (Figures 14, 15, 16).
DC Accuracy
If DC accuracy is important, choose a buffer with an
offset much less than the MAX195’s maximum offset
(±3LSB = ±366µV for a ±4V input range), or whose
offset can be trimmed while maintaining good stability
over the required temperature range.
Recommended Circuits
Figure 14 shows a good circuit for DC and low-frequen-
cy use. The MAX400 has very low offset (10µV) and
drift (0.2µV/°C), and low voltage noise (10nV/ Hz) as
√
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX195’s cali-
bration scheme. However, because the magnitude of
the offset produced by a synchronous signal depends
on the signal’s shape, recalibration may be appropriate
if the shape or relative timing of the clock or other digi-
tal signals change, as might occur if more than one
clock signal or frequency is used.
well. However, its gain-bandwidth product (GBW) is
much too low to drive AIN directly, so the analog input
is bypassed to present a low impedance at high fre-
quencies. The large bypass capacitor is isolated from
the amplifier output by a 100Ω resistor, which provides
a d d itiona l nois e filte ring . Sinc e the ± 15V s up p lie s
exceed the AIN range, add protection diodes at AIN
(see REF and AIN Input Protection section).
Figure 15 shows a wide-bandwidth amplifier (MAX427)
driving a wideband video buffer, which is capable of
driving AIN and a small bypass capacitor (for noise
re d uc tion) d ire c tly. The vid e o b uffe r is ins id e the
MAX427’s feedback loop, providing good DC accura-
cy, while the buffer’s low output impedance and high-
current capability provide good AC performance. AIN is
diode-clamped to the ±5V rails to prevent overvoltage.
The MAX427’s 15µV maximum offset voltage, 0.8µV/°C
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX195’s
THD (-97dB, or 0.0014%) at frequencies of interest. If
the chosen amplifier has insufficient common-mode
rejection, which results in degraded THD performance,
use the inverting configuration (positive input ground-
ed) to eliminate errors from this source. Low tempera-
ture-coefficient, gain-setting resistors reduce linearity
errors caused by resistance changes due to self-heat-
maximum drift, and less than 5nV/ Hz noise specifica-
√
tions make this an excellent choice for AC/DC use.
1k
+5V
+15V
1
+15V
100pF
0.1µF
0.1µF
1N914
2
3
7
10Ω
2
6
7
ELANTEC
EL2003
AIN
MAX427
1k
IN
4
4
1N914
0.0033µF
0.1µF
0.1µF
-15V
-15V
-5V
Figure 15. AIN Buffer for AC/DC Use
______________________________________________________________________________________ 15
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
If ±15V supplies are unavailable, Figure 16’s circuit
works very well with the ±5V analog supplies used by
the MAX195. The MAX410 has a minimum ±3.5V com-
mon-mode input range, with a similar output voltage
swing, which allows use of a reference voltage up to
3.5V. The offset voltage (250µV) is about 2LSB. The
drift (1µV/°C), unity-gain bandwidth (28MHz), and low
voltage noise (2.4nV/√Hz) are appropriate for 16-bit
performance.
Op e ra t in g Mo d e s a n d S P I/QS P I In t e rfa c e s
The two basic interface modes are defined according
to whether serial data is received during the conversion
(clocked with CLK, SCLK unused) or in bursts between
conversions (clocked with SCLK). Each mode is pre-
sented interfaced to a QSPI processor, but is also com-
patible with SPI.
MAX195
Mode 1 (Simultaneous
Conversion and Data Transfer)
In this mode, each data bit is read from the MAX195
during the conversion as it is determined. SCLK is
grounded and CLK is used as both the conversion
clock and the serial data clock. Figure 17 shows a
QSPI processor connected to the MAX195 for use in
this mode and Figure 18 is the associated timing dia-
gram.
510Ω
+5V
0.1µF
2
3
7
4
22Ω
In addition to the standard QSPI interface signals, gen-
eral I/O lines are used to monitor EOC and to drive
BP/UP/SHDN and RESET. The two general output pins
may not be necessary for a given application and, if I/O
lines are unavailable, the EOC connection can be omit-
ted as well.
6
AIN
MAX410
IN
0.01µF
0.1µF
-5V
The EOC s ig na l is monitore d d uring c a lib ra tion to
d e te rmine whe n c a lib ra tion is finis he d a nd b e fore
beginning a conversion to ensure the MAX195 is not in
mid-conversion, but it is possible for a system to ignore
EOC completely. On power-up or after pulsing RESET
low, the µP must provide 14,000 CLK cycles to com-
plete the calibration sequence (Figure 2). One way to
do this is to toggle CLK and monitor EOC until it goes
low, b ut it is p os s ib le to s imp ly c ount 14,000 CLK
c yc le s to c omp le te the c a lib ra tion. Simila rly, it is
unnecessary to check the status of EOC before begin-
ning a conversion if you are sure the last conversion is
complete. This can be done by ensuring that every
conversion consists of at least 20 CLK cycles.
Figure 16. ±5V Buffer for AC/DC Use Has ±3.5V Swing
QSPI
PCS0
CS
CONV
MAX195
SCK
CLK
MISO
DOUT
SCLK
Data is clocked out of the MAX195 on CLK’s falling
edge and can be clocked into the µP on the rising
edge or the following falling edge. If you clock data in
on the rising edge (SPI/QSPI with CPOL = 0 and CPHA
= 0; standard MicroWire™: Hitachi H8), the maximum
CLK rate is given by:
GPT
*OC3
BP/UP/SHDN
*IC1
EOC
1
1
*OC2
RESET
f
=
/
2
CLK(max)
t
+ t
CD
SD
where t
is the MAX195’s CLK-to-DOUT valid delay
* THE USE OF THESE SIGNALS ADDS FLEXIBILITY AND FUNCTIONALITY
BUT IS NOT REQUIRED TO IMPLEMENT THE INTERFACE.
CD
and t is the data setup time for your µP.
SD
Figure 17. MAX195 Connection to QSPI Processor Clocking
Data Out During Conversions
MicroWire is a trademark of National Semiconductor Corp.
16 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
CS, CONV
CLK
EOC
B15 FROM PREVIOUS
B15
t
B14
B2
B1
B0
B15
DOUT
CONVERSION
t
DH
t
DV
CD
DATA LATCHED:
Figure 18. Timing Diagram for Circuit of Figure 17 (Mode 1)
If c loc king d a ta in on the fa lling e d g e (CPOL = 0,
CPHA = 1), the maximum CLK rate is given by:
1
f
=
CLK(max)
t
+ t
SD
CD
QSPI
Do not exceed the maximum CLK frequency given in
the Electrical Characteristics table. To clock data in on
the falling edge, your processor hold time must not
PCS0
SCK
MISO
OC3
CS
MAX195
SCLK
DOUT
exceed t
minimum (100ns).
CD
While QSPI can provide the required 20 CLK cycles as
two continuous 10-bit transfers, SPI is limited to 8-bit
transfers. This means that with SPI, a conversion must
consist of three 8-bit transfers. Ensure that the pauses
between 8-bit operations at your selected clock rate
are short enough to maintain a 20ms or shorter conver-
sion time, or the leakage of the capacitive DAC may
cause errors.
BP/UP/SHDN
GPT
IC1
EOC
OC2
RESET
CONV
CLK
Complete source code for the Motorola 68HC16 and
the MAX195 evaluation kit (EV kit) using this mode is
available with the MAX195 EV kit.
IC3
74HC32
Mode 2 (Asynchronous Data Transfer)
This mode uses a conversion clock (CLK) and a serial
clock (SCLK). The serial data is clocked out between
conversions, which reduces the maximum throughput
for high CLK rates, but may be more convenient for
some applications. Figure 19 is a block diagram with a
QSPI processor (Motorola 68HC16) connected to the
MAX195. Figure 20 shows the associated timing dia-
gram. Figure 21 gives an assembly language listing for
this arrangement.
1.7MHz
1.3µs
START
Figure 19. MAX195 Connection to QSPI Processor Clocking
Data Out with SCLK Between Conversions
______________________________________________________________________________________ 17
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
588ns
CLK
START
MAX195
EOC
CS
239ns
4.19MHz
SCLK
DOUT
B15 B14 B13
B3 B2 B1 B0
CONVERSION TIME
4µs
1.3µs
9.4µs
17µs*
5.1µs
* INTERRUPT LATENCY OF THE PROCESSOR
Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2)
An OR gate is used to synchronize the “start” signal to
the asynchronous CLK, as described in the External
Clock section. As with Mode 1, the QSPI processor must
run CLK during calibration and either count CLK cycles
or, as is done here, monitor EOC to determine when cal-
ibration is complete. Also, EOC is polled by the µP to
determine when a conversion result is available. When
EOC goes low, data is clocked out at the highest QSPI
data rate (4.19Mbps). After the data is transferred, a
new conversion can be initiated whenever desired.
S u p p lie s , La yo u t , Gro u n d in g
a n d Byp a s s in g
For b e s t s ys te m p e rforma nc e , us e p rinte d c irc uit
boards with separate analog and digital ground planes.
Wire -wra p b oa rd s a re not re c omme nd e d . The two
g round p la ne s s hould b e tie d tog e the r a t the low-
impedance power-supply source and at the MAX195
(Figure 22.) If the analog and digital supplies come
from the same source, isolate the digital supply from
the analog supply with a low-value resistor (10Ω).
The timing specification for SCLK-to-DOUT valid (t
)
SD
Constraints on sequencing the four power supplies are
as follows.
imposes some constraints on the serial interface. At
SCLK rates up to 2.5Mbps, data is clocked out of the
MAX195 b y a fa lling e d g e of SCLK a nd ma y b e
clocked into the µP by the next rising edge (CPOL = 0,
CPHA = 0). For data rates greater than 2.5Mbps (or for
lower rates, if desired) it is necessary to clock data out
of the MAX195 on SCLK’s falling edge and to clock it
into the µP on SCLK’s next falling edge (CPOL = 0,
CPHA = 1). Also, your processor hold time must not
•
•
•
•
Apply VDDA before VDDD.
Apply VSSA before VSSD.
Apply AIN and REF after VDDA and VSSA are present.
The p owe r s up p lie s s hould s e ttle within the
MAX195’s power-on delay (minimum 500ns) or you
should recalibrate the converter (pulse RESET low)
before use.
exceed t
minimum (20ns). As with CLK in mode 1,
SD
maximum SCLK rates may not be possible with some
interface specifications that are subsets of SPI.
18 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19
______________________________________________________________________________________ 19
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)
20 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)
Be sure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV, or about 2LSBs error with a
±4V full-scale system.
is long enough that the supply voltages or ambient tem-
perature may have changed.
The time required for the converter to “wake up” and
settle depends heavily on the amount of additional error
acceptable. For 0.5LSB additional error, 3.2µs is suffi-
cient settling time and also allows enough time for reac-
quisition of the analog input signal. 50µs settling is
re q uire d for le s s tha n 0.1LSB e rror. Fig ure 23 is a
graph of theoretical power consumption vs. conver-
sions per second for the MAX195 that assumes the
conversion clock is 1.7MHz and the converter is shut
down as much as possible between conversions.
The board layout should ensure as much as possible
that digital and analog signal lines are kept separate.
Do not run analog and digital (especially clock) lines
parallel to one another. If you must cross one with the
other, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the VDDA and VSSA power sup -
plie s. Byp a ss the se supp lie s to the a na log g round
plane with 0.1µF in parallel with 1µF or 10µF low-ESR
capacitors. Keep capacitor leads short for best supply-
noise rejection.
Stop CLK before shutting down the MAX195. CLK must
be stopped without generating short clock pulses. Short
CLK pulses (less than 150ns), or shutting down the
MAX195 without stopping CLK, may adversely affect the
MAX195’s inte rna l c a lib ra tion d a ta . In a p p lic a tions
where CLK is free-running and asynchronous, use the
circuit of Figure 24 to stop CLK cleanly.
S h u t d o w n
The MAX195 ma y b e s hut d own b y p ulling BP/UP/
SHDN low. In addition to lowering power dissipation to
10µW (100µW max) when the device is not in use, you
can save considerable power by shutting the converter
down for short periods between conversions. There is
no need to perform a reset (calibration) after the con-
verter has been shut down unless the time in shutdown
To minimize the time required to settle and perform a
conversion, shut the converter down only after a con-
version is finished and the desired mode (unipolar or
bipolar) has been set. This ensures that the sampling
capacitor array is properly connected to the input sig-
nal. If shut down in mid-conversion, when awakened,
______________________________________________________________________________________ 21
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
10Ω
VDDD
100
50µs WAKE-UP DELAY
0.01LSB ERROR
VDDA
10µF
5V
10
0.1µF
MAX195
20µs WAKE-UP DELAY
0.25LSB ERROR
0.1µF
10µF
MAX195
DGND
AGND
1
10µF
0.1
5V
0.1µF
3.2µs WAKE-UP DELAY
0.5LSB ERROR
0.1µF
10µF
VSSA
VSSD
0.01
1
10
100
1000 10,000 100,000
CONVERSIONS PER SECOND
10Ω
Figure 23. Power Dissipation vs. Conversions/sec When
Shutting the MAX195 Down Between Conversions
Figure 22. Supply Bypassing and Grounding
the MAX195 finishes the old conversion, allows four
clock (CLK) cycles for input acquisition, then begins
the new conversion.
The theoretical minimum ADC noise is caused by quan-
tization error and is a direct result of the ADC’s resolu-
tion: SNR = (6.02N + 1.76)dB, where N is the number
of bits of resolution. A perfect 16-bit ADC can, there-
fore, do no better than 98dB. An FFT plot of the output
shows the output level in various spectral bands. Figure
25 shows the result of sampling a pure 1kHz sinusoid at
85ksps with the MAX195.
_____________Dyn a m ic P e rfo rm a n c e
High-speed sampling capability, 85ksps throughput,
and wide dynamic range make the MAX195 ideal for
AC applications and signal processing. To support
the s e a nd othe r re la te d a p p lic a tions , Fa s t Fourie r
Transform (FFT) test techniques are used to guarantee
the ADC’s dynamic frequency response, distortion, and
noise at the rated throughput. Specifically, this involves
applying a low-distortion sine wave to the ADC input
a nd re c ord ing the d ig ita l c onve rs ion re s ults for a
specified time. The data is then analyzed using an FFT
a lg orithm, whic h d e te rmine s its s p e c tra l c onte nt.
Conversion errors are then seen as spectral elements
other than the fundamental input frequency.
By transposing the equation that converts resolution to
SNR, we can, from the measured SNR, determine the
effective resolution or the “effective number of bits” the
ADC provides: N = (SNR - 1.76) / 6.02. Substituting
SINAD for SNR in this formula results in a better mea-
sure of the ADC’s usefulness. Figure 26 shows the
effective number of bits as a function of the MAX195’s
input frequency calculated from the SINAD.
If your intended sample rate is much lower than the
MAX195’s maximum of 85ksps, you can improve your
noise performance by taking more samples than neces-
sary (oversampling) and averaging them in software.
Figure 27 is a histogram showing 16,384 samples for
the MAX195 without averaging, with an ideal “noiseless
conversion,” and with a running average of five sam-
ples. The standard deviation is 0.621LSB without aver-
aging and 0.382LSB with the running average. If fewer
data points are needed, normal averaging (e.g., five
data points averaged to produce one data point) can be
used instead of a running average, with similar results.
S ig n a l-t o -No is e Ra t io a n d
Effe c t ive Nu m b e r o f Bit s
Signal-to-Noise Ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other ADC output signals. The
output band is limited to frequencies above DC and
below one-half the ADC sample rate. This usually (but
not always) includes distortion as well as noise compo-
nents. For this reason, the ratio is sometimes referred to
as Signal-to-Noise + Distortion (SINAD).
22 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
1
/
74HC73
2
MAX195
J
CLOCK SHUTDOWN
+5V
CLK
Q
K
BP/UP/SHDN
CK
2 x CLK
CK
(2 x CLK)
Q
(CLK)
J
(CLOCK SHUTDOWN)
Figure 24. Circuit to Stop Free-Running Asynchronous CLK
Even better than oversampling and averaging is over-
sampling and digital filtering. Averaging is just a rough
(but computationally simple) type of digital filter. Finite
impulse response (and other) digital filter algorithms are
readily available, and are useful even with slow proces-
sors if the data rate is low or the data does not need to
be processed in real-time. When using averaging, be
sure to average an odd number of samples to avoid
small offset errors caused by asymmetrical rounding.
-10
f
= 1kHz
IN
f = 85kHz
-30
-50
S
T = +25°C
A
-70
Whether simple averaging or more complex digital fil-
tering is used, the effect of oversampling is to spread
the noise across a wider bandwidth. Digital filtering or
averaging then eliminates the portion of this noise that
lies above the filter’s passband, leaving less noise in
the passband than if oversampling was not used. An
additional benefit of oversampling is that it simplifies
the design or choice of an anti-aliasing pre-filter for the
input. You can use a filter with a more gradual rolloff,
because the sample rate is much higher than the fre-
quency of interest.
-90
-110
-130
-150
0
5
10
15
20
25
30
35
40
FREQUENCY (kHz)
Figure 25. MAX195 FFT Plot
______________________________________________________________________________________ 23
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
16
15
14
100
95
90
85
80
f = 85kHz
S
T = +25°C
A
f = 85kHz
S
T = +25°C
A
13
12
11
10
MAX195
75
70
65
60
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 28. Signal-to-Noise + Distortion vs. Frequency
Figure 26. Effective Bits vs. Input Frequency
This is expressed as follows:
18
2
N
2
2
2
V
= +4.5V
= +2.25V
IDEAL
CONVERSION
REF
V2 + V3 + V4 + ...+ V
16
14
12
V
AIN
THD = 20log
UNIPOLAR MODE
85ksps
V1
where V is the fundamental RMS amplitude, and V
NO AVERAGING
1
2
10
8
through V are the amplitudes of the 2nd through Nth
N
RUNNING
AVERAGE OF
5 SAMPLES
ha rmonic s . The THD s p e c ific a tion in the Ele c tric a l
Characteristics includes the 2nd through 5th harmon-
ics. In the MAX195, this distortion is caused primarily
by the changes in on-resistance of the AIN sampling
switches with changing input voltage. These resis-
tance changes, together with the DAC’s capacitance
(whic h c a n a ls o va ry with inp ut volta g e ), c a us e a
varying time delay for AC signals, which causes sig -
nific a nt d is tortion a t mod e ra te ly hig h fre q ue nc ie s
(Figure 28).
6
4
2
0
8021 8022 8023 8024 8025 8026 8027
OUTPUT CODE (HEXADECIMAL)
Figure 27. Histogram of 16,384 Conversions Shows Effects of
Noise and Averaging
S p u rio u s -Fre e Dyn a m ic Ra n g e
Spurious-free dynamic range is the ratio of the funda-
mental RMS amplitude to the amplitude of the next
largest spectral component (in the frequency band
a b ove DC a nd b e low one -ha lf the s a mp le ra te ).
Usually, this peak occurs at some harmonic of the input
frequency. However, if the ADC is exceptionally linear,
it may occur only at a random peak in the ADC’s noise
floor.
To t a l Ha rm o n ic Dis t o rt io n
If a pure sine wave is input to an ADC, AC integral non-
linearity (INL) of an ADC’s transfer function results in
harmonics of the input frequency being present in the
sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not includ-
ing the DC component) to the RMS amplitude of the
fundamental frequency.
Tra n s fe r Fu n c t io n
Figures 29 and 30 show the MAX195’s transfer func-
tions. In unipolar mode, the output data is in binary for-
mat and in bipolar mode it is offset binary.
24 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
___________________Ch ip To p o g ra p h y
11 . . . 111
11 . . . 110
11 . . . 101
11 . . . 100
11 . . . 011
11 . . . 010
BP/UP/SHDN
CLK
VSSA
VDDA
SCLK
AGND
00 . . . 110
00 . . . 101
00 . . . 100
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
AIN
REF
0. 273"
(6. 93mm)
VDDD
0V
V
REF
- (1LSB)
Figure 29. MAX195 Unipolar Transfer Function
DOUT
DGND
11 . . . 111
11 . . . 110
11 . . . 101
VSSD
EOC
CS
CONV
RESET
10 . . . 010
10 . . . 001
10 . . . 000
01 . . . 111
01 . . . 110
0. 144"
(3. 66mm)
TRANSISTOR COUNT: 7966
SUBSTRATE CONNECTED TO VDDA
00 . . . 010
00 . . . 001
00 . . . 000
-V
REF
0V
V
REF
- (1LSB)
Figure 30. MAX195 Bipolar Transfer Function
______________________________________________________________________________________ 25
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
________________________________________________________P a c k a g e In fo rm a t io n
MAX195
26 ______________________________________________________________________________________
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
MAX195
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
______________________________________________________________________________________ 27
1 6 -Bit , 8 5 k s p s ADC w it h 1 0 µA S h u t d o w n
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
MAX195
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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