MAX1961EEP+T [MAXIM]
Switching Controller, Voltage-mode, 1120kHz Switching Freq-Max, BICMOS, PDSO20, 0.150 INCH, MO-137, QSOP-20;
| 型号： | MAX1961EEP+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Voltage-mode, 1120kHz Switching Freq-Max, BICMOS, PDSO20, 0.150 INCH, MO-137, QSOP-20 控制器 |
| 文件： | 总29页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2740; Rev 0; 1/03
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
General Description
Features
The MAX1960/MAX1961/MAX1962 high-current, high-
efficiency voltage-mode step-down DC-DC controllers
operate from a 2.35V to 5.5V input and generate output
voltages down to 0.8V at up to 20A. An on-chip charge
pump generates a regulated 5V for MOSFET drive.
Additionally, adaptive dead-time drivers allow a
wide variety of MOSFETs to be used without risking
shoot-through.
o 0.5% Accurate Output
o Operates from 2.35V to 5.5V Supply
o Generates Low Output Voltage Down to 0.8V
o On-Chip Charge Pump Provides 5V Gate Drive
o Ceramic or Electrolytic Capacitors
o 94% Efficiency
o External Synchronization from 450kHz to 1.2MHz
o 500kHz/1MHz Fixed-Frequency PWM Operation
o Fast Transient Response
Fixed-frequency PWM operation and external synchro-
nization make these controllers suitable for telecom
and datacom applications. The operating frequency is
programmable to either 500kHz or 1MHz, or from
450kHz to 1.2MHz with an external clock. A clock output
is provided to synchronize another converter for 180°
out-of-phase operation. A high closed-loop bandwidth
provides excellent transient response for applications
with dynamic loads.
o Two Converters Can Operate 180° Out-of-Phase
o
4% Voltage Margining for System Test
o 10% Accurate Current Sensing (MAX1962)
o Adaptive Dead Time Prevents Shoot-Through
Lossless current sensing in the MAX1960 and
MAX1961 is achieved by monitoring the drain-to-source
voltage of the low-side external FET. The current limit is
scalable to accommodate a wide variety of MOSFETs
and load currents. The MAX1962 has 10% accurate
sense-resistor-based current limiting.
Ordering Information
PART
MAX1960EEP
MAX1961EEP
MAX1962EEP
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 QSOP
20 QSOP
20 QSOP
The MAX1960 and MAX1962 have an adjustable output
voltage from 0.8V to 4.95V. The MAX1961 and
MAX1962 have four preset output voltages (1.5V, 1.8V,
2.5V, and 3.3V) and feature 0.5% voltage accuracy
over temperature, line, and load variations. The
MAX1960 and MAX1961 also feature voltage-margining
control inputs that shift the output voltage up or down
by 4% for system testing.
Typical Operating Circuit
C+
C-
AV
INPUT
2.35V TO 5.5V
V
DD
CC
MAX1960
V
DD
CTL1
VOLTAGE
MARGINING
AND ON/OFF
BST
DH
Applications
ASIC, FPGA, DSP, and CPU Core and I/O Voltages
CTL2
COMP
OUTPUT
IN
UP TO 20A
0.8 TO 0.87 ✕ V
Cellular Base Stations
LX
REF
Telecom and Network Equipment
Server and Storage Systems
DL
GND
PGND
ILIM
FB
FSET/SYNC
CLKOUT
OPTIONAL
SYNCHRONIZATION
CLKOUT
180° OUT-OF-PHASE
Pin Configurations and Selector Guide appear at the end
of the data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ABSOLUTE MAXIMUM RATINGS
CC
V
, CTL_, CS, FSET/SYNC, SEL, EN,
Continuous Power Dissipation (T = +70°C)
A
OUT to GND ..........................................................-0.3V to +6V
20-Pin QSOP (derate up to +70°C)..............................727mW
20-Pin QSOP (derate above +70°C)........................9.1mW/°C
Operating Temperature Range (Extended).........-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ILIM, COMP, REF, FB, CLKOUT,
C- to GND ..............................................-0.3V to V
C+ to GND.............-0.3V to higher of V
+ 0.3V
+ 0.3V
AVDD
+ 1V or V
VCC
VDD
V
, AV
to GND..............-0.3V to higher of V
- 0.3V or 6V
DD
DD
VCC
DL to PGND ................................................-0.3V to V
+ 0.3V
VDD
BST to GND............................................................-0.3V to +12V
DH to LX ...................................................................-0.3V to +6V
LX to BST..................................................................-6V to +0.3V
PGND to GND, or V
to AV
............................-0.3V to +0.3V
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3.3V, Circuits of Figures 9–12, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A A
VCC
PARAMETER
Input Voltage Range
Input Voltage UVLO
Input Voltage UVLO
CONDITIONS
MIN
2.35
1.95
3.9
TYP
MAX
5.5
UNITS
V
V
V
V
V
V
V
CC
CC
DD
Rising or falling, hysteresis = 33mV (typ)
Rising or falling, hysteresis = 44mV (typ)
2.3
4.45
Output Voltage
0.8
MAX1960/MAX1962 (measured at FB)
SEL = GND
0.796
1.492
1.791
2.487
3.272
+3.8
-3.8
0.800
1.500
1.800
2.500
3.300
+4
0.804
1.508
1.809
2.514
3.336
+4.2
MAX1961/
DC Output Accuracy
SEL = REF
V
MAX1962 (FB = V ),
DD
measured at output
SEL not connected
SEL = V
DD
Positive Voltage-Margining Shift
Negative Voltage-Margining Shift
Load Regulation Error
MAX1960/MAX1961
MAX1960/MAX1961
0V to full load
%
%
-4
-4.2
0.08
0.1
%
Line Regulation Error
V
= 2.7V to 5.5V
%
VCC
FB Input Bias Current
-0.2
1
+0.2
3
µA
mS
Ω
Feedback Transconductance
COMP Discharge Resistance
DC-DC Soft-Start Time
2
In shutdown
10
100
1280
500
1000
cycles
FSET/SYNC = GND
450
880
450
80
550
1120
1200
Switching Frequency
kHz
FSET/SYNC = V
CC
SYNC Frequency Range
Maximum Duty Cycle
kHz
%
f = 1MHz
83
92
11
Maximum Duty Cycle
f = 500kHz
90
%
Quiescent Supply Current
Shutdown Supply Current
15
15
mA
µA
2
_______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, Circuits of Figures 9–12, T = 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A A
VCC
PARAMETER
CONDITIONS
≤ 5.5V, I = 1mA to 50mA
MIN
TYP
MAX
UNITS
2.7V ≤ V
4.75
5.25
V
VCC
LOAD
2.35V ≤ V
= 4.7µF, C6 = 22µF (Note 1)
≤ 2.7V, I
= 1mA to 35mA, C1
LOAD
VCC
4.45
5.25
V
V
V
Output Voltage
DD
2.35V ≤ V ≤ 3.6V with tripler, I
50mA (circuit of Figure 12) (Note 1)
= 1 to
LOAD
VCC
4.75
5.25
Reference Voltage (No Load)
Reference Load Regulation
1.269
1.280
3
1.291
V
-50µA to +50µA
mV
V
V
V
= 0.8V
= 2.0V
= 3.3V
44
45
38
53
62
55
58
OUT
OUT
OUT
Positive Current-Limit Threshold
MAX1962
50
mV
(V
PGND
- V )
LX
48
Negative Current-Limit Threshold
(V - V
MAX1962, V
= 0.8V to 3.3V
38
50
68
mV
OUT
)
PGND
LX
CS Bias Current
MAX1962, V = 3.3V
CS
20
30
50
50
µA
µA
OUT Bias Current
MAX1961/MAX1962, V
= 3.3V
OUT
Current-Limit Threshold (Positive
MAX1960/MAX1961, ILIM = V
MAX1960/MAX1961, ILIM = V
58
50
74
67
90
85
mV
mV
mV
mV
DD
Direction, Fixed, V
- V )
LX
PGND
Current-Limit Threshold (Negative
Direction, Fixed, V - V
DD
)
PGND
LX
MAX1960/MAX1961, R
= 160kΩ
= 160kΩ
100
250
90
114
279
107
271
135
306
125
296
ILIM
ILIM
Current-Limit Threshold (Positive
Direction, Adjustable, V - V
)
)
PGND
LX
R
= 400kΩ
ILIM
MAX1960/MAX1961, R
= 400kΩ
Current-Limit Threshold (Negative
Direction, Adjustable, V - V
LX
PGND
R
245
ILIM
Thermal-Shutdown Threshold
DH Gate-Driver On-Resistance
DL Gate-Driver On-Resistance (Pullup)
15°C hysteresis
- V = 5V, pulling up or down
DL high state
+160
1.8
1.8
0.5
35
°C
Ω
Ω
V
3.5
3.5
1.6
BST
LX
DL Gate-Driver On-Resistance (Pulldown) DL low state
Ω
DH falling to DL rising
Minimum Adaptive Dead Time
FSET/SYNC Pulse Width
ns
DH rising to DL falling
Minimum high time (Note 1)
Minimum low time (Note 1)
(Note 1)
26
200
200
ns
FSET/SYNC Rise/Fall Time
100
ns
V
CTL_, FSET/SYNC, EN Input High Voltage
CTL_, FSET/SYNC, EN Input Low Voltage
CTL_, FSET/SYNC, EN Input Current
V
V
= 2.35V to 5.5V
= 2.35V to 5.5V
2.0
-1
VCC
VCC
0.8
+1
0.1
V
µA
V
CLKOUT V
Sinking 1mA
0.01
OL
V
0.2V
-
V
-
VCC
VCC
CLKOUT V
Sourcing 1mA
V
OH
0.01V
CLKOUT Rise/Fall Time
C
= 100pF (Note 1)
40
ns
LOAD
_______________________________________________________________________________________
3
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ELECTRICAL CHARACTERISTICS
(V
= 3.3V, Circuits of Figures 9–12, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
VCC
PARAMETER
Input Voltage Range
Input Voltage UVLO
Input Voltage UVLO
CONDITIONS
MIN
2.35
TYP
MAX
5.50
2.3
UNITS
V
V
V
V
V
V
V
CC
CC
DD
Rising or falling
Rising or falling
1.95
3.90
4.45
Output Voltage
0.8
MAX1960/MAX1962 (measured at FB)
SEL = GND
0.795
1.492
1.789
2.482
3.272
0.805
1.508
1.809
2.517
3.339
4.2
MAX1961/MAX1962
DC Output Accuracy
SEL = REF
V
(FB = V ),
DD
measured at output
SEL not connected
SEL = V
DD
Positive Voltage-Margining Shift
Negative Voltage-Margining Shift
FB Input Bias Current
MAX1960/MAX1961
MAX1960/MAX1961
3.8
-3.8
-0.2
1
%
%
-4.2
+0.2
3
µA
µS
Ω
Feedback Transconductance
COMP Discharge Resistance
In shutdown
100
FSET/SYNC = GND
450
880
450
80
550
Switching Frequency
kHz
FSET/SYNC = V
1120
1200
CC
SYNC Frequency Range
Maximum Duty Cycle
kHz
%
f = 1MHz
Maximum Duty Cycle
f = 500kHz
90
%
Quiescent Supply Current
Shutdown Supply Current
15
15
mA
µA
2.7V ≤ V
≤ 5.5V, I
= 1mA to 50mA
4.75
4.45
5.25
VCC
LOAD
2.35V ≤ V
C1 = 4.7µF, C6 = 22µF
≤ 2.7V, I
= 1mA to 35mA,
VCC
LOAD
5.25
V
Output Voltage
V
DD
2.35V ≤ V ≤ 3.6V with tripler, I
to 50mA (circuit of Figure 12)
= 1mA
LOAD
VCC
4.75
1.267
45
5.25
1.291
56
Reference Voltage (No Load)
Positive Current-Limit Threshold
V
MAX1962, V
MAX1962, V
= 2V
= 2V
mV
OUT
(V - V
)
CS
OUT
Negative Current-Limit Threshold
(V - V
42
64
mV
OUT
)
CS
OUT
CS Bias Current
MAX1962, V = 3.3V
CS
50
50
µA
µA
OUT Bias Current
MAX1961/MAX1962, V
= 3.3V
OUT
Current-Limit Threshold (Positive
MAX1960/MAX1961, ILIM = V
MAX1960/MAX1961, ILIM = V
58
50
90
85
mV
mV
mV
DD
Direction, Fixed, V
- V )
LX
PGND
Current-Limit Threshold (Negative
Direction, Fixed, V - V
DD
)
PGND
LX
MAX1960/MAX1961, R
= 160kΩ
100
250
135
306
ILIM
Current-Limit Threshold (Positive
Direction, Adjustable, V - V
)
PGND
LX
R
= 400kΩ
ILIM
4
_______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, Circuits of Figures 9–12, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
VCC
PARAMETER
Current-Limit Threshold (Negative
Direction, Adjustable, V - V
CONDITIONS
MAX1960/MAX1961, R = 160kΩ
MIN
90
TYP
MAX
125
296
3.5
UNITS
ILIM
mV
)
LX
PGND
R
= 400kΩ
245
ILIM
DH Gate-Driver On-Resistance
DL Gate-Driver On-Resistance (Pullup)
DL Gate-Driver On-Resistance (Pulldown) DL low state
V
- V = 5V, pulling up or down
LX
Ω
Ω
Ω
BST
DL high state
3.5
1.6
Minimum high time
Minimum low time
200
200
FSET/SYNC Pulse Width
ns
FSET/SYNC Rise/Fall Time
100
ns
V
CTL_, FSET/SYNC, EN Input High Voltage
CTL_, FSET/SYNC, EN Input Low Voltage
CTL_, FSET/SYNC, EN Input Current
V
V
= 2.35V to 5.5V
= 2.35V to 5.5V
2.0
-1
VCC
VCC
0.8
+1
0.1
V
µA
V
CLKOUT V
Sinking 1mA
OL
V
0.2V
-
VCC
CLKOUT V
Sourcing 1mA
V
OH
CLKOUT Rise/Fall Time
C
= 100pF
40
ns
LOAD
Note 1: Guaranteed by design.
Note 2: Specifications at -40°C are guaranteed by design, and not production tested.
_______________________________________________________________________________________
5
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Typical Operating Characteristics
(Circuit of Figure 9, T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. LOAD CURRENT WITH
15A 1MHz CIRCUIT, 3.3V INPUT
EFFICIENCY vs. LOAD CURRENT WITH
15A 1MHz CIRCUIT, 5V INPUT
EFFICIENCY vs. LOAD CURRENT WITH
15A 500kHz CIRCUIT, 3.3V INPUT
100
90
80
70
60
50
100
90
80
70
60
50
100
90
80
70
60
50
V
= 2.5V
V
= 3.3V
OUT
OUT
V
= 2.5V
OUT
V
= 1.8V
OUT
V
= 1.8V
V
V
V
= 2.5V
= 1.8V
= 1.5V
OUT
OUT
OUT
OUT
V
= 1.5V
OUT
V
= 1.5V
OUT
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT WITH
15A 500kHz CIRCUIT, 5V INPUT
OUTPUT VOLTAGE
vs. INPUT VOLTAGE, 1MHz
OUTPUT VOLTAGE
vs. INPUT VOLTAGE, 500kHz
100
90
80
70
60
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 3.3V
OUT
3.3V OUTPUT
3.3V OUTPUT
2.5V OUTPUT
DROPOUT
2.5V OUTPUT
DROPOUT
V
V
= 2.5V
= 1.8V
OUT
OUT
1.8V OUTPUT
1.5V OUTPUT
1.2V OUTPUT
1.8V OUTPUT
1.5V OUTPUT
1.2V OUTPUT
V
= 1.5V
OUT
15A LOAD
15A LOAD
0.1
1
10
100
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
INPUT VOLTAGE (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
INPUT VOLTAGE (V)
LOAD CURRENT (A)
FB REGULATION VOLTAGE
vs. LOAD CURRENT
FREQUENCY
vs. INPUT VOLTAGE
0.803
0.802
0.801
0.800
0.799
0.798
0.797
1200
1100
1000
900
FSET/SYNC = V
CC
800
700
600
FSET/SYNC = GND
500
400
0
5
10
15
20
3.0
3.5
4.0
4.5
5.0
5.5
LOAD CURRENT (A)
INPUT VOLTAGE (V)
6
_______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Typical Operating Characteristics (continued)
(Circuit of Figure 9, T = +25°C, unless otherwise noted.)
A
CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 1MHz
CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 500kHz
FREQUENCY vs. TEMPERATURE
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
5.2
1100
1000
900
800
700
600
500
400
300
200
100
0
C1 = 1µF
C6 = 4.7µF
C1 = 0.47µF
C6 = 2.2µF
5.1
5.0
4.9
4.8
4.7
4.6
4.5
FSET/SYNC = V
CC
V
= 3.3V
IN
V
= 2.5V
IN
FSET/SYNC = GND
V
= 2.5V
IN
V
= 3.3V
IN
0
50
100
150
200
0
50
100
150
200
-40
-15
10
35
60
85
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP LOAD CURRENT (mA)
TEMPERATURE (°C)
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 1MHz
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 500kHz
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
5.2
C10, C11, C12 = 1µF
C6 = 4.7µF
C10, C11, C12 = 0.47µF
C6 = 2.2µF
5.1
5.0
4.9
4.8
4.7
4.6
4.5
V
= 2.5V
V = 2.5V
IN
IN
CIRCUIT OF FIGURE 12
10 20
CIRCUIT OF FIGURE 12
10 20
0
30
40
50
0
30
40
50
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP LOAD CURRENT (mA)
MAX1960/MAX1961
CURRENT-LIMIT THRESHOLD
VOLTAGE vs. TEMPERATURE
MAX1962
CURRENT-LIMIT THRESHOLD
VOLTAGE vs. TEMPERATURE
350
52.0
51.5
51.0
50.5
50.0
49.5
49.0
48.5
48.0
47.5
47.0
R
= 390kΩ
300
250
200
150
100
50
ILIM
ILIM = V
DD
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Typical Operating Characteristics (continued)
(Circuit of Figure 9, T = +25°C, unless otherwise noted.)
A
VOLTAGE-MARGINING STEP RESPONSE
7.5A TO 15A TO 7.5A LOAD TRANSIENT
MAX1960 toc17
MAX1960 toc16
CTL1
CTL2
5V/div
5V/div
50mV/div
V
OUT
I
200mA/div
200mV/div
IN
I
LOAD
5A/div
V
OUT
CIRCUIT OF FIGURE 13
50µs/div
20µs/div
MAX1960/MAX1961
SHORT-CIRCUIT WAVEFORMS
STARTUP/SHUTDOWN WAVEFORMS
MAX1960 toc18
MAX1960 toc19
CIRCUIT OF FIGURE 13
V
OUT
2V/div
I
10A/div
10A/div
IN
I
L
I
20A/div
5A/div
L
V
OUT
1V/div
I
IN
1ms/div
50µs/div
MAX1962
SHORT-CIRCUIT WAVEFORMS
SYNC TIMING WAVEFORMS
MAX1960 toc21
MAX1960 toc20
DH
MASTER
I
IN
10A/div
10A/div
DL
MASTER
CLKOUT
MASTER/
SYNC
I
L
SLAVE
DH
SLAVE
V
OUT
2V/div
V
OUT
= 5V
IN
= 3.3V
DL
SLAVE
V
200ns/div
50µs/div
8
_______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Pin Description
PIN
NAME
FUNCTION
MAX1960 MAX1961 MAX1962
Clock Output. Connect to FSET/SYNC of a second converter to operate 180° out-of-
1
2
1
2
1
2
CLKOUT
phase. CLKOUT swings from V to GND. CLKOUT is low in shutdown (see the
CC
Operating Frequency and Synchronization section).
Frequency Set and Synchronization. Connect to GND for 500kHz operation,
connect to V
for 1MHz operation, or drive with clock signal to synchronize
FSET/SYNC
CC
(between 450kHz and 1200kHz).
Current Limit. Connect a resistor from ILIM to GND to set the current-sense
3
3
—
ILIM
EN
threshold voltage. Connect ILIM to V
to select the default threshold of 75mV.
DD
—
—
3
Enable. Drive high for normal operation. Drive low or connect to GND for shutdown mode.
Preset Output Voltage Select. Allows the output to be set to one of four preset
voltages (1.5V, 1.8V, 2.5V, and 3.3V). For the MAX1962, FB must be connected to
—
4
4
SEL
V
if SEL is to be used (see the Setting the Output Voltage section).
DD
4
—
—
N.C.
OUT
No Connection. Not internally connected.
Output. Connect to the output. Used to sense the output voltage for internal
feedback and current sense.
—
8
5
Control Pins. Controls voltage margining and shutdown. Connect both CTL1 and
CTL2 high for normal operation. Connect both CTL1 and CTL2 low for shutdown.
Connect CTL1 high and CTL2 low for +4% voltage margining. Connect CTL1 low
and CTL2 high for -4% voltage margining. If voltage margining is not to be used,
connect CTL1 and CTL2 together and use to enable/shutdown the device.
5
6
5
6
—
—
CTL1
CTL2
CS
Current-Sense Input. Connect to the junction of the current-sense resistor and the
inductor. The MAX1962 current-sense threshold is 50mV measured from CS to OUT.
—
—
6
7
Filtered Supply from V . Connect a 1µF bypass capacitor. AV
is forced to V
CC
DD
DD
7
7
AV
DD
in shutdown. Do not apply an external load to AV
.
DD
Feedback Input. The feedback threshold is 0.8V. Connect to the center of a resistive
voltage-divider from the output to GND to set the output voltage to 0.8V or greater. On
8
—
8
FB
the MAX1962, connect FB to V to select preset output voltages (see SEL).
DD
9
9
9
COMP
REF
Compensation Pin. COMP is forced to GND in shutdown, UVLO, or thermal fault.
10
10
10
Reference Output. V
= 1.28V. Bypass with a 0.22µF capacitor to GND.
REF
Analog Ground. Connect to the PC board analog ground plane. Connect the PC
board analog ground plane and power ground planes with a single connection.
11
12
11
12
11
12
GND
Charge-Pump Output. Provides regulated 5V to power the IC and gate drivers.
Bypass with a 4.7µF ceramic capacitor for operating frequencies between 450kHz
V
DD
and 950kHz. Bypass with a 2.2µF ceramic capacitor for 1MHz operation. V is
DD
internally forced to V
in shutdown. Do not apply an external load to V
.
DD
CC
Low-Side MOSFET Synchronous Rectifier Gate-Driver Output. DL is high in
shutdown.
13
14
13
14
13
14
DL
PGND
Power Ground. Connect to the PC board power ground plane.
_______________________________________________________________________________________
9
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1960 MAX1961 MAX1962
Charge-Pump Flying Capacitor Negative Connection. Use a 0.47µF ceramic
capacitor at 1MHz, and 1µF between 450kHz and 950kHz.
15
16
15
16
15
16
C-
Charge-Pump Flying Capacitor Positive Connection. Use a 0.47µF ceramic
capacitor at 1MHz and 1µF between 450kHz and 950kHz.
C+
17
18
19
20
17
18
19
20
17
18
19
20
V
Input Supply to Charge Pump
CC
BST
DH
LX
Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor from BST to LX.
High-Side MOSFET Gate-Driver Output. DH is low in shutdown.
Inductor Connection
where I
is the current supplied to the IC through
AVDD
(typically 2mA), f
Detailed Description
AV
is the PWM switching
OSC
DD
The MAX1960/MAX1961/MAX1962 are high-current,
high-efficiency voltage-mode step-down DC-DC con-
trollers that operate from 2.35V to 5.5V input and gener-
ate adjustable voltages down to 0.8V at up to 20A. An
on-chip charge pump generates a regulated 5V for dri-
ving a variety of external N-channel MOSFETs.
frequency, Q
MOSFET, and Q
is the gate charge of the high-side
G2
G1
is the gate charge of the low-side
MOSFET. The MOSFETs must be chosen such that
does not exceed 50mA. For example, with 1MHz
I
TOTAL
operation, Q + Q should be less than 48nC.
G1
G2
Voltage Margining and Shutdown
The voltage-margining feature on the MAX1960/
MAX1961 shifts the output voltage up or down by 4%.
This is useful for the automatic testing of systems at high
and low supply conditions to find potential hardware fail-
ures. CTL1 and CTL2 control voltage margining as out-
lined in Table 1.
Constant frequency PWM operation and external syn-
chronization make these controllers suitable for telecom
and datacom applications. The operating frequency is
programmed externally to either 500kHz or 1MHz, or
from 450kHz to 1.2MHz with an external clock. A clock
output is provided to synchronize another converter for
180° out-of-phase operation.
A shutdown feature is included on all three parts, which
stops switching the output drivers and the charge
pump, reducing the supply current to less than 15µA.
For the MAX1962, drive EN high for normal operation,
or low for shutdown. For the MAX1960/MAX1961, drive
both CTL1 and CTL2 high for normal operation, or drive
CTL1 and CTL2 low for shutdown. For a simple
enable/shutdown function with no voltage margining,
connect CTL1 and CTL2 together and drive as one
input.
A high closed-loop bandwidth provides excellent tran-
sient response for applications with dynamic loads.
Internal Charge Pump
An on-chip regulated charge pump develops 5V at
50mA (max) with input voltages as low as 2.35V. The
output of this charge pump provides power for the
internal circuitry, bias for the low-side driver (DL), and
the bias for the boost diode, which supplies the high-
side MOSFET gate driver (DH). The charge pump is
synchronized with the DL driver signal and operates at
1/2 the PWM frequency.
The external MOSFET gate charge is the dominant load
for the charge pump and is proportional to the PWM
switching frequency. The charge pump must supply
chip-operating current plus adequate gate current for
both MOSFETs at the selected operating frequency.
The required charge-pump output current is given by
the formula:
Table 1. Voltage Margining Truth Table
CTL1
High
High
Low
CTL2
High
Low
FUNCTION
Normal operation
+4% output-voltage shift
-4% output-voltage shift
Shutdown
High
Low
Low
I
= I
+ f
(Q + Q
)
TOTAL
AVDD
OSC
G1
G2
10 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
ILIM
CS
(MAX1960/MAX1961)
(MAX1962)
CURRENT
SENSE
LX
OUT
PGND
BST
DH
LX
CLKOUT
S
R
OSC
Q
Q
FSET/SYNC
UVLO
OSC
V
DD
COMP
DL
COMP
PGND
OUT
(MAX1961/MAX1962)
SOFT-START
DAC
REF
AV
DD
ERROR
AMP
REF
FEEDBACK
SELECT
FB
V
DD
(MAX1960/MAX1962)
C+
CHARGE
PUMP
VSEL
OSC
MAX1960/
MAX1961/
MAX1962
(MAX1961/MAX1962)
C-
V
CC
CTL1
SHUTDOWN
AND VOLTAGE
MARGINING
(MAX1960/MAX1961)
CTL2
(MAX1960/MAX1961)
GND
EN
(MAX1962)
Figure 1. Functional Diagram
MOSFET Gate Drivers
Undervoltage Lockout and Soft-Start
There are two undervoltage lockout (UVLO) circuits on
the MAX1960/MAX1961/MAX1962. The first UVLO cir-
The DH and DL drivers are designed to drive logic-level
N-channel MOSFETs to optimize system cost and effi-
ciency. MOSFETs with R
rated at V
4.5V are
GS
cuit monitors V , which must be above 2.15V (typ) in
CC
DSON
recommended. An adaptive dead-time circuit monitors
the DL output and prevents the high-side MOSFET from
turning on until DL is fully off. There must be a low-resis-
tance, low-inductance path from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
properly. Otherwise, the internal sense circuitry could
interpret the MOSFET gate as “off” while there is actually
still charge left on the gate. Use very short, wide traces
measuring no more than 20 squares (50mils to 100mils
wide if the MOSFET is 1in from the IC).
order for the charge pump to operate. The second
UVLO circuit monitors the output of the charge pump.
The charge-pump output, V , must be above 4.2V
DD
(typ) in order for the PWM converter to operate. Both
UVLO circuits inhibit switching and force DL high and DH
low when either V
or V
are below their threshold.
CC
DD
When the monitored voltages are above their thresh-
olds, an internal soft-start timer ramps up the error-
amplifier reference voltage. The ramp occurs in eighty
10mV steps. Full output voltage is reached 1.28ms after
activation with a 1MHz operating frequency.
______________________________________________________________________________________ 11
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
increases until it reaches its maximum value, where the
part enters dropout. With a switching frequency of
1MHz, the maximum duty cycle is about 83%. At
500kHz, the duty cycle can increase to about 92%,
resulting in a lower dropout voltage. The duty cycle is
Operating Frequency and Synchronization
The MAX1960/MAX1961/MAX1962 operating frequency
is set externally to either 500kHz or 1MHz. For 500kHz
operation, connect FSET/SYNC to GND, or for 1MHz
operation, connect FSET/SYNC to V . Alternately, an
DD
dependent on the input voltage (V ), the output volt-
IN
external clock from 450kHz to 1.2MHz can be applied
to SYNC.
age (V
), and the parasitic voltage drops in the
OUT
MOSFETs and the inductor (V
, V
,
DROP(N2)
DROP(N1)
A clock output (CLKOUT) that is 180° out-of-phase with
the internal clock is also provided. This allows a second
converter to be synchronized, and operate 180° out-of-
phase with the first. To do this, simply connect CLKOUT
of the first converter to FSET/SYNC of the second con-
verter. The first converter can be set internally to 500kHz
or 1MHz for this mode of operation. When the first con-
verter is synchronized to an external clock, CLKOUT is
the inverse of external clock. See the SYNC Timing
Waveform in the Typical Operating Characteristics.
V
). Note that V
includes the voltage
DROP(L)
DROP(L)
drop due to the inductor’s resistance, the drop across
the current-sense resistor (if used), and any other resis-
tive voltage drop from the LX switching node to the
point where the output voltage is sensed. The duty
cycle is found from:
VOUT + VDROP(L)
- VDROP(N1) - VDROP(N2)
D =
V
IN
Lossless Current Limit
(MAX1960/MAX1961)
Adaptive Dead Time
The MAX1960/MAX1961/MAX1962 DL and DH MOSFET
drivers have an adaptive dead-time circuit to prevent
shoot-through current caused by high- and low-side
MOSFET overlap. This allows a wide variety of MOSFETs
to be used without matching FET dynamic characteris-
tics. The DL driver will not go high until DH drives the
high-side MOSFET gate to within 1V of its source (LX).
The DH output will not go high until DL drives the low-side
MOSFET gate to within 1V of ground.
To prevent damage in the case of excessive load cur-
rent or a short circuit, the MAX1960/MAX1961 use the
low-side MOSFET’s on-resistance (R
) for current
DS(ON)
sensing. The current is monitored during the on-time of
the low-side MOSFET. If the current-sense voltage
(V
- V ) rises above the current-limit threshold for
LX
PGND
more than 128 clock cycles, the controller turns off. The
controller remains off until the input voltage is removed
or the device is re-enabled with CTL1 and CTL2 (see
the Setting the Current Limit section).
Design Procedure
Component selection is primarily dictated by the following
criteria:
Current-Sense Resistor (MAX1962)
The MAX1962 uses a standard current-sense resistor in
series with the inductor for a 10% accurate current-limit
measurement. The current-sense threshold is 50mV. This
provides accurate current sensing at all duty cycles with-
out relying on MOSFET on-resistance. CS connects to
the high-side (inductor side) of the current-sense resistor
and OUT connects to the low-side (output side) of the
current-sense resistor.
Input voltage range. The maximum value
(V
) must accommodate the worst-case high
IN(MAX)
input voltage. The minimum value (V
) must
IN(MIN)
account for the lowest input voltage after drops due
to connectors, fuses, and selector switches are con-
sidered.
Maximum load current. There are two values to con-
The current-sense resistor for the MAX1962 may also be
replaced with a series RC network across the inductor.
This method uses the parasitic resistance of the inductor
for current sensing. This method is less accurate than
using a current-sense resistor, but is lower cost and pro-
vides slightly higher efficiency. See the Design
Procedure section for instructions on using this method.
sider: The peak load current (I ) determines
LOAD(MAX)
the instantaneous component stresses and filtering
requirements and is key in determining output capac-
itor requirements. I
also determines the
LOAD(MAX)
inductor saturation rating and the design of the cur-
rent-limit circuit. The continuous load current (I
)
LOAD
determines the thermal stresses and is key in deter-
mining input capacitor requirements, MOSFET
requirements, as well as those of other critical heat-
contributing components.
Dropout Performance
The MAX1960/MAX1961/MAX1962 enter dropout when
the input voltage is not sufficiently high to maintain output
regulation. As input voltage is lowered, the duty cycle
12 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Inductor operating point. This choice provides
Table 2. Preset Voltages—
MAX1961/MAX1962
tradeoffs between size, transient response, and effi-
ciency. Choosing higher inductance values results
in lower inductor ripple current, lower peak current,
lower switching losses, and, therefore, higher effi-
ciency at the cost of slower transient response and
larger size. Choosing lower inductance values
results in large ripple currents, smaller size, and
poorer efficiency, but have faster transient response.
PRESET OUTPUT VOLTAGE
SEL
GND
1.5V
1.8V
2.5V
3.3V
REF
No connection
V
DD
Setting the Output Voltage
The MAX1961 has four output voltage presets selected
by SEL. Table 2 shows how each of the preset voltages
are selected. The MAX1962 also has four preset output
voltages, but also is adjustable down to 0.8V. To use the
preset voltages on the MAX1962, FB must be connected
D2
D3
D4
D5
C11
C10
C12
V
CC
C-
to V . SEL then selects the output voltage as shown in
DD
Table 2.
C+
MAX1960/
MAX1961/
MAX1962
Both the MAX1960/MAX1962 feature an adjustable out-
put that can be set down to 0.8V. To set voltages greater
than 0.8V, Connect FB to a resistor-divider from the out-
put (Figures 9 and 11). Use a resistor up to 10kΩ for R2
and select R1 according to the following equation:
V
DD
C6
R5
10Ω
AV
DD
C4
1µF
V
V
OUT
R1= R2 ×
- 1
FB
500kHz
1µF
1MHz
0.47µF
2.2µF
C10, C11, C12
C6
where the feedback threshold, V = 0.8V, and V
FB
the output voltage.
is
OUT
4.7µF
Input Voltage Range
The MAX1960/MAX1961/MAX1962 have an input volt-
age range of 2.35V to 5.5V but cannot operate at both
extremes with one application circuit. The standard
charge-pump doubler application circuit operates with
an input range of 2.7V to 5.5V (Figures 9, 10, and 11).
In order to operate down to 2.35V, the charge pump
must be configured as a tripler. This circuit, however,
limits the maximum input voltage to 3.6V. The schematic
for the tripler charge pump is shown in Figure 2. Note
that the flying capacitor between C+ and C- has been
removed and C+ is not connected.
Figure 2. Tripler Charge-Pump Configuration.
vides a good compromise between efficiency and
economy. Choose a low-loss inductor having the lowest
possible DC resistance. Ferrite core type inductors are
often the best choice for performance. The inductor
saturation current rating must exceed I
:
PEAK
LIR
2
I
= I
+
× I
LOAD(MAX)
PEAK
LOAD(MAX)
Inductor Selection
Determine an appropriate inductor value with the fol-
lowing equation:
Setting the Current Limit
Lossless Current Limit (MAX1960/MAX1961)
The MAX1960/MAX1961 use the low-side MOSFET’s on-
resistance (R ) for current sensing. This method of
current limit sets the maximum value of the inductor’s
“valley” current (Figure 3). If the inductor current is higher
than the valley current-limit setting at the end of the
clock period, the controller skips the DH pulse. When
the first current-limit event is detected, the controller initi-
V
- V
OUT
× LIR × I
IN
L = V
×
DS(ON)
OUT
V
× f
IN
OSC LOAD(MAX)
The inductor current ripple, LIR, is the ratio of peak-to-
peak inductor ripple current to the average continuous
inductor current. An LIR between 20% and 40% pro-
______________________________________________________________________________________ 13
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
0.22µH, 2.8mW,
I
= 18A
DH
LX
DL
LIMIT
R
I
I
I
L
L
PEAK
LOAD
R
C
MAX1962
R = 33Ω
C = 4.7µF
VALLEY
CS
OUT
TIME
Figure 3. Inductor Current Waveform
Figure 4. Using the Inductor Resistance as a Current-Sense
Resistor with the MAX1962
ates a 128 clock cycle counter. If the current limit is pre-
sent at the end of this count, the controller remains off
until the input voltage is removed and re-applied, or the
device is re-enabled with CTL1 and CTL2. The 128-cycle
counter is reset when four successive DH pulses are
observed, without activating the current limit.
accuracy is needed, use the MAX1962 with a current-
sense resistor.
Current-Sense Resistor (MAX1962)
The MAX1962 uses a current-sense resistor connected
from the inductor to the output with Kelvin sense connec-
tions. The current-sense voltage is measured from CS to
OUT, and has a fixed threshold of 50mV. The MAX1962
current limit is triggered when the peak voltage across
At maximum load, the low excursion of inductor current,
I
, is:
VALLEY(MAX)
the current-sense resistor, I
× R
, exceeds
SENSE
PEAK
LIR
2
I
= I
-
× I
LOAD(MAX)
50mV. Once current sense is triggered, the controller
does not turn off, but continues to operate at the current
limit. This method of current sensing is more precise due
to the accuracy of the current-sense resistor. The cost of
this precision is that it requires an extra component and
is slightly less efficient due to the loss in the current-
sense resistance.
VALLEY(MAX)
LOAD(MAX)
The current-limit threshold (V
) is set by connecting a
CLT
resistor (R
) from ILIM to GND. The range for this
ILIM
resistor is 100kΩ to 400kΩ. Set current-limit threshold as
follows:
V
= R
× 0.714µA
ILIM
sets the threshold to a default
CLT
Inductor Resistance Current Sense (MAX1962)
Alternately, the inductor resistance can be used to
sense current in place of a current-sense resistor. To
do this, connect a series RC network in parallel with the
inductor (Figure 4). Choose a resistor value less than
40Ω to avoid offsets due to CS input current. Calculate
Connecting ILIM to V
value of 75mV.
DD
To prevent the current limit from falsely triggering, V
divided by the low-side MOSFET R
the maximum value of I
low-side MOSFET R
CLT
must exceed
DS(ON)
. The maximum value of
should be used:
VALLEY
DS(ON)
the capacitor value from the formula C = 2L / (R × R).
L
The effective current-sense resistance (R
L
) equals
SENSE
V
CLT
> R
x I
DS(ON)MAX VALLEY(MAX)
R . Current-sense accuracy then depends on the accu-
A limitation of sensing current across MOSFET on-resis-
tance is that the MOSFET on-resistance varies signifi-
cantly from MOSFET to MOSFET and over temperature.
Consequently, this current-sensing method may not be
suitable if a precise current limit is required. If better
racy of the inductor resistance. Note that the current-
sense signal is delayed due to the RC filter time
constant. Consequently, inductor current may over-
shoot (by as much as 2x) when a fast short occurs.
14 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
The RMS input ripple current is given by:
Output Capacitor Selection
The output filter capacitor must have low enough effective
series resistance (ESR) to meet output ripple and load
transient requirements. In addition, the capacitance value
must be high enough to absorb the inductor energy
during load steps.
VOUT × (V - VOUT
)
IN
IRMS = ILOAD
×
V
IN
For optimal circuit reliability, choose a capacitor that
has less than 10°C temperature rise at the peak ripple
current.
In applications where the output is subject to large load
transients, low ESR is needed to prevent the output
from dipping too low (V ) during a load step:
DIP
Compensation and Stability
V
DIP
LOADSTEP(MAX)
Compensation with Ceramic Output Capacitors
The high switching frequency range of the
MAX1960/MAX1961/MAX1962 allows the use of ceramic
output capacitors. Since the ESR of ceramic capacitors
is very low typically, the frequency of the associated
transfer function zero is higher than the unity-gain
crossover frequency and the zero cannot be used to
compensate for the double pole created by the output
inductor and capacitor. The solution is Type 3 compen-
sation (Figure 5), which takes advantage of local feed-
back to create two zeros and three poles (Figure 6). The
frequency of the poles and zeros are described below:
R
≤
ESR
I
In applications with less severe load steps, maximum
ESR may be governed by what is needed to maintain
acceptable output voltage ripple:
V
RIPPLE P−P
(
)
R
≤
ESR
LIR × I
LOAD(MAX)
To satisfy both load step and ripple requirements,
select the lowest value from the above two equations.
The capacitor is usually selected by physical size, ESR,
and voltage rating, rather than by capacitance value.
With current tantalum, electrolytic, and polymer capaci-
tor technology, the bulk capacitance will also be suffi-
cient once the ESR requirement is satisfied.
f
= 0
P1
1
f
=
P2
2π × R2 × C3
When using low-capacity filter capacitors such as
ceramic, capacitor size is usually determined by the
capacitance needed to prevent voltage undershoot
and overshoot during load transients. The overshoot
1
f
=
P3
C1 × C2
C1 + C2
2π × R1 ×
voltage (V
) is given by:
SOAR
1
f
=
LC
2
2π L × C
L × I
(
)
0
0
PEAK
V
=
SOAR
2 × V
× C
OUT
OUT
1
f
=
Z1
2π × R1 × C1
Generally, once enough capacitance is in place to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem.
1
f
=
Z2
2π × (R2+R3) × C3
Input Capacitor Selection
The input capacitor (C ) reduces the current peaks
IN
drawn from the input supply and reduces noise injec-
tion. The source impedance to the input supply largely
1
f
=
ZESR
2π × R
× C
0
ESR
determines the value of C . High source impedance
IN
requires high input capacitance. The input capacitor
Unity-gain crossover frequency:
must meet the ripple current requirement (I
imposed by the switching currents.
)
RMS
V
1
IN(MAX)
f =R1 × C3 ×
×
0
V
2π × L × C
0 0
RAMP
______________________________________________________________________________________ 15
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
V
IN
GAIN (dB)
DH
LX
DL
L
O
V
OUT
C
0
MAX1960
R3
R2
FB
C3
R4
R1
COMP
FREQUENCY
fp3
fz1
fz2
fp2
fp1
C2
C1
Figure 5. Type 3 Compensation Network
Figure 6. Transfer Function for Type 3 Compensation
where:
If C2 < 10pF, it can be omitted.
V
= Maximum input voltage
IN(MAX)
2π × f × L × C × V
6
0
0
0
RAMP
V
= Oscillator ramp voltage = 0.85 x 10 /f ,
RAMP
C3≤
S
R1 × V
where f = switching frequency
IN
S
L
= Output inductance
= Output capacitance
O
Place the second pole after the ESR zero:
C
O
1
The goal is to place the two zeros below crossover and
the two poles above crossover so that crossover
occurs with a single-pole slope. The compensation pro-
cedure is as follows:
R2≤
2π × f
× C3
ZESR
If:
Select the crossover frequency such that:
1
f < f
0
and f <1/5 ✕ f
R2 <
(= 550Ω),
ZESR
0
S
g
M
Select R1 such that:
increase R1 and recalculate C1, C2, and C3.
2
gmEA
Place the second zero at the double-pole frequency:
R1>>
1
where g
= 2mS.
R3≥
- R2
mEA
2π × f
× C3
LC
Place the first zero before the double pole:
Set the output voltage:
1
C1≥
2π × 0.75 × f
× R1
V
FB
LC
R4 =
× R3, V = 0.8V
FB
V
- V
OUT
FB
Place the third pole at half the switching frequency:
1
C2≥
2π × 0.5 × f × R1
S
16 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Compensation with Electrolytic Output Capacitors
The MAX1960/MAX1961/MAX1962 use a voltage-mode
control scheme that regulates the output voltage by
comparing the error-amplifier output (COMP) with a
fixed internal ramp to produce the required duty cycle.
The inductor and output capacitor create a double pole
at the resonant frequency, which has gain drop of 40dB
per decade, and phase shift of 180°. The error amplifier
must compensate for this gain drop and phase shift in
order to achieve a stable high-bandwidth, closed-loop
system.
The transconductance error amplifier has DC gain
GEA(dc) of 80dB. A dominant pole is set by the com-
pensation capacitor (C ), the amplifier output resis-
C
tance (R ), and the compensation resistor (R ):
O
C
1
f
=
PEA
2π × C × (R + R )
C
0
C
A zero is set by the compensation resistor and the
compensation capacitor:
1
The basic regulator loop consists of a power modulator,
an output feedback divider and an error amplifier. The
f
=
ZEA
2π × C × R
C
C
power modulator has DC gain set by V /V
, with a
IN RAMP
double pole set by the inductor and output capacitor,
and a single zero set by the output capacitor (C ) and
O
its equivalent series resistance (ESR). Below are equa-
tions that define the power modulator:
The total closed-loop gain must equal to unity at the
crossover frequency, where the crossover frequency
should be higher than f
, so that the -1 slope is
ZESR
used to cross over at unity gain. Also, the crossover
frequency should be less than or equal to 1/5 the
switching frequency.
The DC gain of the power modulator is:
V
IN
G
=
f
5
MOD(DC)
S
f
< f
≤
V
ZESR
C
RAMP
where V
= 0.85 × 106 / f . The pole frequency due
S
RAMP
The loop-gain equation at the crossover frequency is:
to the inductor and output capacitor is:
V
FB
1
× G
× G
=1
MOD(f )
C
EA(f )
C
fPMOD
=
V
OUT
2π LOCO
where:
and:
The zero frequency due to the output capacitor’s ESR
is:
G
= g
× R
C
EA(f )
mEA
C
1
f
=
ZESR
2π × R
× C
O
ESR
(f
)2
× f
C
PMOD
G
= G
×
MOD(f )
MOD(DC)
C
The output capacitor is usually comprised of several
same value capacitors connected in parallel. With n
capacitors in parallel, the output capacitance is:
f
ESR
The compensation resistor, R , is calculated from:
C
C
= n × C
EACH
O
V
OUT
R
=
C
g
× V × G
FB MOD(f )
mEA
C
The total ESR is:
where g
= 2mS.
mEA
R
ESR(EACH)
n
R
=
Due to the under-damped (Q > 1) nature of the output
LC double pole, the error-amplifier compensation zero
should be approximately 0.2f
phase boost. C is calculated from:
ESR
to provide good
PMOD
The ESR zero (f
) for a parallel combination of
capacitors is the same as for an individual capacitor.
ZESR
C
The feedback divider has a gain of G = V /V
,
FB OUT
FB
5
C
=
C
where V is 0.8V.
FB
2π × R × f
C
PMOD
______________________________________________________________________________________ 17
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
A small capacitor C , can also be added from COMP to
The power modulator gain at f is:
C
F
GND to provide high-frequency decoupling. C will add
F
2
another high-frequency pole (f
) to the error-amplifier
V
(f
)
PHF
IN
PMOD
G
=
×
MOD(fc)
response. This pole should be greater than 100 times
the error-amplifier zero frequency to have negligible
impact on the phase margin. This pole should also be
less than half the switching frequency for effective
decoupling:
V
f
× f
RAMP
ZESR C
2
3
0.85
(9201)
29.3kΩ × 100kΩ
=
×
= 0.102
Choose R = 8.06kΩ, then R = 10kΩ (see the Setting
1
2
100f
< f
< 0.5f
ZEA
PHF S
the Output Voltage section):
Select a value for f
in the range given above, then
PHF
V
1.8
OUT
solve for C using the following equation:
F
=
=
C
g
× V × G
0.002 × 0.8 × 0.102
mEA
FB
MOD(f )
C
1
=11kΩ
C =
F
2π × R × f
C
PHF
5
5
C
=
=
= 7863pF
C
2π × R × f
2π × 11kΩ × 9201
Below is a numerical example to calculate compensa-
tion values:
C
PMOD
V
V
V
V
= 3.3V
Select C = 8200pF (nearest standard capacitor
C
IN
value).
= 0.85V
= 1.8V
RAMP
Select f
in the range 100f
< f < 0.5f .
PHF S
PHF
PHF
ZEA
OUT
184kHz < f
< 500kHz
PHF
= 0.8V
FB
Select f
= 250kHz, then solve for C :
F
I
= 15A
OUT(max)
C
= 2 x 680µF = 1360µF
O
1
1
C =
=
= 58pF
F
ESR = 0.008Ω / 2 = 0.004Ω
= 0.22µH
2π × R × f
2π × 11kΩ × 250kHz
C
PHF
L
O
Select the nearest standard capacitor value C = 56pF.
F
g
mEA
= 2mS
Summary of feedback divider and compensation com-
ponents:
f = 1MHz
S
1
R = 8.06kΩ
1
f
=
=
PMOD
2π ×
L
× C
O O
R = 10kΩ
2
1
R
C
= 11kΩ
−6
−6
C
C
= 8200pF
2π × 0.22 × 10
= 9.201kHz
× 1360 × 10
C = 56pF
F
Power MOSFET Selection
When selecting a MOSFET, essential parameters
include:
1
f
=
ZESR
2π × C × R
O
ESR
1
(1) Total gate charge (Q )
G
=
(2) Reverse transfer capacitance (C
)
−6
RSS
2π × 1360 × 10
= 29.3kHz
× 0.004
(3) On-resistance (R
)
DS(ON)
(4) Gate threshold voltage (V
(5) Turn-on/turn-off times
(6) Turn-on/turn-off delays
)
TH(MIN)
Choose the crossover frequency (f ) in the range f
C
ZESR
< f < f /5:
C
S
29.3kHz < f < 200kHz
C
Select f = 100kHz, this meets the criteria above, and the
C
bandwidth is high enough for good transient response.
18 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
FEEDBACK DIVIDER
ERROR AMPLIFIER
MODULATOR
OUTPUT FILTER
V
1
0.8V
R1
R2
V
/V
Gm
IN RAMP
R
S
R3
L1
C9
V
2
R
ESR
R
LOAD
C
OUT
Figure 7. Open-Loop Transfer Model
At high switching rates, dynamic characteristics (para-
meters 1, 2, 5, and 6) that predict switching losses may
MOSFET RC Snubber Circuit
Fast-switching transitions can cause ringing due to res-
onating circuit parasitic inductance and capacitance at
the switching nodes. This high-frequency ringing
occurs at LX rising and falling transitions, and may
introduce current-sensing errors and generate EMI. To
dampen this ringing, a series RC snubber circuit can
be added across each MOSFET switch (Figure 8).
have more impact on efficiency than R
, which pre-
DS(ON)
dicts DC losses. Q includes all capacitance associated
G
with charging the gate, and best performance is
achieved with a low total gate charge. Q also helps
G
predict the current needed to drive the gate at the
selected operating frequency. This is very important
because the output current from the charge pump is
finite (50mA, max) and is used to drive the gates of the
Typical values for the snubber components are C
SNUB
= 4700pF and R
= 1Ω, however, the ideal values
SNUB
MOSFETs as well as provide bias for the IC. R
is
for snubber components will depend on circuit para-
sitics. Below is the procedure for selecting the compo-
nent values of the series RC snubber circuit:
DS(ON)
important as well, as it is used for current sensing in the
MAX1960/MAX1961. R also causes power dissi-
DS(ON)
pation during the on-time of the MOSFET.
1) Connect a scope probe to measure V to GND,
LX
Choose Q to be as low as possible. Ensure that:
G
and observe the ringing frequency, f .
R
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
50mA
fS
QG1 +QG2
≤
3) The circuit parasitic capacitance, C , at LX is then
PAR
equal to 1/3 of the value of the added capacitance
above.
Choose R
to provide the desired I
at
LOAD(MAX)
DS(ON)
the desired current-limit threshold voltage (see the
Setting the Current Limit section).
______________________________________________________________________________________ 19
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
where V
FALL
MOSFET, I
is the maximum value of the input volt-
IN(MAX)
INPUT
age, t
and t
are the fall and rise time of the
RISE
and I
are the maximum
L(VALLEY)
L(PEAK)
peak and valley inductor current, and f is the PWM
switching frequency:
S
R
SNUB
DH
N1
I
= I
× (1 + 0.5 × LIR) and I
=
L(VALLEY)
L(PEAK)
OUT(MAX)
C
SNUB
L1
MAX1960
I
× (1 - 0.5 × LIR)
OUT(MAX)
LX
DL
where LIR is the peak-to-peak inductor ripple current
divided by the load current.
R
SNUB
N2
The total power dissipation in the high-side MOSFET is
the sum of these two power losses:
C
SNUB
PGND
P
D(N1)
= P
+ P
D(N1RESISTIVE) D(N1SWITCHING)
For the low-side MOSFET, the worst-case power dissi-
pation occurs at maximum input voltage:
Figure 8. RC Snubber Circuit
V
4) The circuit parasitic inductance, L , is calculated
PAR
by:
OUT
2
P
= 1 -
× I
× R
DS(ON)
D(N2RESISTIVE)
LOAD
V
IN(MAX)
1
2
L
=
PAR
Applications Information
(2π × f ) × C
R
PAR
PC Board Layout Guidelines
5) The resistor for critical dampening, R
= 2π x
SNUB
A properly designed PC board layout is important in
any switching DC-DC converter circuit. If possible,
mount the MOSFETs, inductor, input/output capacitors,
and current-sense resistor on the top side. Connect the
ground for these devices close together on a power-
ground trace. Make all other ground connections to a
separate analog ground plane. Connect the analog
ground plane to power ground at a single point.
f
x L
. The resistor value can be adjusted up
R
PAR
or down to tailor the desired damping and the
peak voltage excursion.
6) The capacitor, C
, should be at least 2 to 4
PAR
SNUB
times the value of the C
to be effective.
7) The snubber circuit power loss is dissipated in the
resistor, P
, and can be calculated as:
RSNUB
To help dissipate heat, place high-power components
(MOSFETs, inductor, and current-sense resistor) on a
large PC board area. Keep high-current traces short and
wide to reduce the resistance in these traces. Also make
the gate drive connections (DH and DL) short and wide,
measuring 10 to 20 squares (50mils to 100mils wide if the
MOSFET is 1in from the controller IC).
2
P
= C
× (V ) × f
SNUB IN S
RSNUB
where V is the input voltage, and f is the
IN
S
switching frequency. Choose R
power rating
SNUB
that exceeds the calculated power dissipation.
MOSFET Power Dissipation
Worst-case power dissipation occurs at duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
For the MAX1960/MAX1961, connect LX and PGND to
the low-side MOSFET using Kelvin sense connections.
For the MAX1962, connect CS and OUT to the current-
sense resistor using Kelvin sense connections.
input voltage (V
):
IN(MIN)
V
Place the REF capacitor, the BST diode and capacitor,
and the charge-pump components as close as possible
to the IC. If the IC is far from the input capacitors, bypass
OUT
2
PD
=
× I
× R
DS(ON)
(N1RESISTIVE)
LOAD
V
IN(MIN)
V
to GND with a 0.1µF or greater ceramic capacitor
CC
The following formula calculates switching losses for
the high-side MOSFET, but is only an approximation
and not a substitute for evaluation:
close to the V pin.
CC
For an example PC board layout, see the MAX1960
evaluation kit.
P
=
D(N1SWITCHING)
V
IN(MAX)
I
× t
+ I
× t
×
× f
S
L(PEAK)
FALL
L(VALLEY)
RISE
2
20 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Table 3. Component List for Application Circuits
PART
APP. CIRCUIT
1, 2, 3
15A OUTPUT 1MHz
0.47µF ceramic capacitor
15A OUTPUT 500kHz
1µF ceramic capacitor
C1
C2
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
4
5 × 10µF ceramic capacitors
2 x 680µF POSCAPs Sanyo 2R5TPD680M8
1µF ceramic capacitor
5 × 10µF ceramic capacitors
2 x 680µF POSCAPs Sanyo 2R5TPD680M8
1µF ceramic capacitor
C3
C4
C5
C6
0.1µF ceramic capacitor
2.2µF ceramic capacitor
0.22µF ceramic capacitor
(Table 4)
0.1µF ceramic capacitor
4.7µF ceramic capacitor
0.22µF ceramic capacitor
(Table 5)
C8
C9
C10, C11, C12
C13, C14
0.47µF ceramic capacitors
4700pF ceramic capacitors
1µF ceramic capacitors
4700pF ceramic capacitors
1, 2, 3, 4
Schottky diode
Central CMSSH-3
Schottky diode
Central CMSSH-3
D1
D2–D5
L1
1, 2, 3, 4
4
Schottky diodes
Central CMHSH5-2L
Schottky diodes
Central CMHSH5-2L
0.22µH, 1.7mΩ inductor
Sumida CDEP1040R2NC-50
0.45µH inductor
Sumida CDEP1040R4MC-50
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
N-channel MOSFET
International Rectifier IRLR7821
N-channel MOSFET
International Rectifier IRLR7821
N1
N-channel MOSFET
International Rectifier IRLR7833
N-channel MOSFET
International Rectifier IRLR7833
N2
R1
R2
R3
R4
R5
1, 3
1, 3
Sets output voltage
10kΩ 1% resistor
(Table 4)
Sets output voltage
10kΩ 1% resistor
(Table 5)
1, 2, 3, 4
1, 2
390kΩ 5% resistor
10Ω 5% resistor
390kΩ 5% resistor
10Ω 5% resistor
1, 2, 3, 4
1.5mΩ 5%, 1W resistor
Panasonic ERJM1WTJ1M5U
1.5mΩ 5%, 1W resistor
Panasonic ERJM1WTJ1M5U
R6
3, 4
R7, R8
1, 2, 3, 4
1Ω 5% resistors
1Ω 5% resistors
______________________________________________________________________________________ 21
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Table 4. R1, R3, and C9 Component Values for 1MHz Operation
V
= 3.3V
V
= 2.5V
V
= 1.8V
V
= 1.5V
OUT
OUT
OUT
OUT
V
IN
R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (Ω) R3 (kΩ) C9 (µF)
5V
3.12
—
1.2
—
0.0068
—
2.13
—
9.1
—
0.01
—
1.24
1.24
1.24
6.8
2.7
3.9
0.01
0.01
0.01
876
876
876
5.5
2.4
3.3
0.01
0.01
0.01
3.3V
2.5V
—
—
—
—
—
—
Table 5. R1, R3, and C9 Component Values for 500kHz Operation
V
= 3.3V
V
= 2.5V
V
= 1.8V
V
= 1.5V
OUT
OUT
OUT
OUT
V
IN
R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (Ω) R3 (kΩ) C9 (µF)
5V
3.12
—
36
—
—
0.0033
—
2.13
2.13
—
27
47
—
0.0047
0.0033
—
1.24
1.24
1.24
20
30
39
0.0068
0.0047
0.0033
876
876
876
16
27
33
0.0068
0.0047
0.0033
3.3V
2.5V
—
—
Table 6. Component Suppliers
Selector Guide
SUPPLIER
Central Semiconductor
International Rectifier
Kamaya
PHONE
WEBSITE
VOLTAGE
MARGINING
CURRENT
LIMIT
OUTPUT
VOLTAGE
PART
631-435-1110 www.centralsemi.com
310-322-3331 www.irf.com
MAX1960
MAX1961
Adjustable
4 Presets
FET V
DS
4%
Sensing
260-489-1533 www.kamaya.com
814-237-1431 www.murata.com
714-373-7939 www.panasonic.com
619-661-6835 www.sanyo.com
847-956-0666 www.sumida.com
408-573-4150 www.t-yuden.com
Murata
10% with
4 Presets or
Adjustable
MAX1962
No
R
Panasonic
SENSE
Sanyo
Sumida
Taiyo Yuden
22 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
C1
INPUT
2.7V TO 5.5V
C4
C+
C-
V
AV
V
CC
DD
C2
R5
CTL1
CTL2
DD
C6
D1
BST
DH
LX
R7
MAX1960
N1
N2
COMP
REF
OUTPUT
DOWN TO 0.8V
C5
C13
L1
C9
C3
R8
DL
C8
R3
C14
PGND
ILIM
GND
R1
FSET/SYNC
CLKOUT
CLKOUT
R4
FB
N.C.
R2
Figure 9. Application Circuit 1—MAX1960 Adjustable Output Voltage
______________________________________________________________________________________ 23
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
C1
INPUT
2.7V TO 5.5V
C4
C+
C-
V
AV
V
CC
DD
C2
R5
CTL1
CTL2
DD
C6
D1
BST
DH
LX
R7
MAX1961
N1
N2
COMP
REF
C5
C13
L1
OUTPUT 2.5V
C3
C9
R8
DL
C8
R3
C14
PGND
ILIM
GND
FSET/SYNC
CLKOUT
CLKOUT
R4
OUT
VSEL
Figure 10. Application Circuit 2—MAX1961 Preset Output Voltage
24 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
C1
INPUT
2.7V TO 5.5V
C4
C+
C-
V
AV
CC
DD
DD
C2
R5
V
C6
D1
BST
DH
LX
EN
R7
MAX1962
N1
N2
COMP
REF
OUTPUT
C5
C13
L1
R6
DOWN TO 0.8V
C9
C3
R8
DL
C8
R3
C14
PGND
CS
GND
FSET/SYNC
CLKOUT
CLKOUT
OUT
R1
R2
FB
VSEL
Figure 11. Application Circuit 3—MAX1962 Adjustable Output Voltage
______________________________________________________________________________________ 25
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
D2
D3
D4
D5
C11
C10
C12
INPUT
2.35V TO 3.6V
C4
C+
C-
V
AV
V
CC
DD
C2
R5
DD
C6
D1
BST
DH
LX
EN
R7
MAX1962
N1
COMP
REF
C5
C13
L1
R6
OUTPUT 1.5V
C3
C9
R8
DL
N2
C8
R3
C14
PGND
CS
GND
FSET/SYNC
CLKOUT
CLKOUT
OUT
FB
V
VSEL
DD
Figure 12. Application Circuit 4—MAX1962 Tripler Configuration, Preset Output
26 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
C1
0.47µF
C4
INPUT
1µF
C+
C-
2.7V TO 5.5V
V
AV
V
CC
DD
C2
5 x 10µF
R5
10Ω
C6
2.2µF
CTL1
CTL2
DD
D1
BST
DH
LX
R7
1Ω
MAX1960
N1
N2
COMP
REF
C5
0.1µF
C13
4700pF
L1
OUTPUT 2.5V, 15A
C10
C9
820pF
33pF
C3
R8
1Ω
4 x 47µF
C8
0.22µF
DL
TAIYO-YUDEN
R3
10kΩ
C14
4700pF
JMK325BJ476MN
PGND
ILIM
GND
R9
680Ω
FSET/SYNC
CLKOUT
CLKOUT
R4
390kΩ
C7
560pF
R1
6.84kΩ
FB
N.C.
R2
3.22kΩ
N1 – IRLR7821
N2 – IRLR7833
Figure 13. Application Circuit—Ceramic Output Capacitors with Type 3 Compensation
______________________________________________________________________________________ 27
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Pin Configurations
TOP VIEW
TOP VIEW
CLKOUT
FSET/SYNC
EN
1
2
3
4
5
6
7
8
9
20 LX
19 DH
18 BST
CLKOUT
FSET/SYNC
ILIM
1
2
3
4
5
6
7
8
9
20 LX
19 DH
18 BST
SEL
17 V
CC
N.C. (SEL)
CTL1
17 V
CC
MAX1962
MAX1960
MAX1961
OUT
16 C+
15 C-
16 C+
15 C-
14
CS
CTL2
AV
DD
14
AV
DD
PGND
13 DL
12
11 GND
PGND
FB
FB (OUT)
COMP
13 DL
12
COMP
V
V
DD
DD
REF 10
REF 10
11 GND
QSOP
QSOP
( ) ARE FOR MAX1961.
Chip Information
TRANSISTOR COUNT: 4476
PROCESS: BiCMOS
28 ______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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