MAX19692EVKIT [MAXIM]
On-Board 1.25V Reference Circuitry;
| 型号： | MAX19692EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | On-Board 1.25V Reference Circuitry |
| 文件： | 总16页 (文件大小：974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
General Description
Features
● Evaluates the MAX19692/MAX19693
The MAX19692 and MAX19693 evaluation kits (EV kits)
include either a MAX19692 2.3Gsps or MAX19693 4.0Gsps
12-bit, direct RF synthesis digital-to-analog converter
(DAC). The evaluation board includes a transformer circuit
used to convert the differential DAC output to a single-
ended 50Ω signal. An on-board 3-transformer circuit is also
provided to convert a single-ended 50Ω clock source into
the well balanced, 50% duty cycle, 100Ω differential source
required by the MAX19692/MAX19693.
● Supports Maximum Update Rates
• 2.3Gsps for MAX19692
• 4.0Gsps for MAX19693
● Proven 12-Layer PCB Design
● Single-Ended Clock Interface
• 2.3GHz Maximum Clock Rate (MAX19692)
• 2.0GHz Maximum Clock Rate (MAX19693)
● Single-Ended DAC Output Interface
• Selectable Frequency Response (MAX19692)
• Wideband Output Transformer
The MAX19692/MAX19693 evaluation board employs
two SAMTECH Q Strip (QSH) connectors for the
digital interface. The EV Kit includes an adapter board
that converts the QSH interface to an FPGA Mezzanine
Connector (FMC). The FMC connector is commonly
available on Commercial Off-the-Shelf (COTS) FPGA
®
• Supports from 50MHz to >2GHz
● On-Board 1.25V Reference Circuitry
● Fully Assembled and Tested
©
®
evaluation boards such as the Xilinx Virtex -7 VC707
EV kit.
The MAX19692/MAX19693 EV Kit is supported by the
MUXDAC Data Source based on a VC707 FPGA board
which provides a useful tool for supplying the digital
signals required to evaluate the MAX19692/MAX19693.
Refer to the MUXDAC Data Source User’s Guide for more
information.
Ordering Information appears at end of data sheet.
19-0703; Rev 3; 10/20
Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
Figure 1. MAX19692/MAX19693 EV Kit and MUXDAC Data Source Test Setup
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
2) Setup and connect the MAX19692/MAX19693 EV kit
board.
Quick Start
Required Equipment
a. Install the two 1-1/4” stand-offs included with the
MAX19692/MAX19693 EV kit. Stand-offs should
be installed on the DAC output side of the board.
●
Window PC (Windows 7/10 operating system), with
two available USB2.0 ports
●
●
Spectrum analyzer – Agilent PXA or equivalent
b. Mate the MAXDACFMCADP1 board to the
MAX19692/MAX19693 EV kit.
RF signal generator – Rohde & Schwarz SMF100A
or equivalent
i. Secure the two boards using the supplied
screws/nuts/washers.
●
●
One 3.3V/0.5A power supply (AVDD3.3)
c. Verify all jumpers on the MAX19692/MAX19693
EV kit board are in the default position; refer to
Table 1 and Table 2.
One or two 1.8V power supplies (AVDD1.8 and
AVCLK)
• Total current capability should be 0.5A per supply
connection
d. Connect the MAX19692/MAX19693 EV kit board
to the VC707 board, HPC1 as shown in Figure 1.
●
Xilinx VC707 EV kit – user supplied
• VC707 board
• 12V/5A power cube
e. Connect the power supplies to the MAX19692/
MAX19693 EV kit and enable the output.
• 1 each USB-A to Mini-B cable for interfacing and
programming
• 1 each USB-A to Micro-B cable for interfacing and
programming
f. Connect the RF generator to the clock input with
a low-loss SMA cable and set the frequency to
2.0GHz (50% duty-cycle) with output power at
+10dBm.
●
●
Low-Loss SMA/SMA cables as needed for connections
to the spectrum analyzer and signal generator
g. Connect the DAC Output to the spectrum
analyzer with a low-loss SMA cable.
Included in the MAX19692/MAX19693 EV Kit
• MAX19692/MAX19693 EV kit board
• MAXDACFMCADP1 adapter Board
• Mounting hardware
h. Turn on the VC707 by sliding switch SW12 to the
ON (left) position.
i. Connect the USB A to Micro-B cable from the
VC707 JTAG port to the PC.
Required Installed Software and Drivers
j. Connect the USB A to Mini-B cable from the
VC707 USB2.0 port to the PC.
●
Maxim Integrated MUXDAC data source and
associated components
3) Start the MUXDACEVKITSoftwareController.exe
a. Wait for the program to initialize.
Procedure
1) Install the MUXDAC Data Source software
4) Load the FPGA configuration
a. Click on the Xilinx Impact Tool Installed checkbox.
Reference the MUXDAC Data Source User’s Guide
for detailed installation and operating instructions. The
MUXDAC Data Source User’s Guide and software are
available for download from www.maximintegrated.com.
Search for ‘MUXDAC Data Source’, then download the
User’s Guide and follow the link to download the software.
You will be prompted to accept Maxim’s End User License
Agreement to complete the download process.
b. Click the <Load FPGA Configuration File> button.
i. A file browser will open in the C:\
maximintegrated\MUXDACEVKIT\
VC707Files folder. Double click the
MUXDAC_DSS_vNpM.bit file. (N and M are
the revision numbers, i.e., v1p3 is Version 1.3)
c. A progress bar will display while the FPGA is
configured, should take < 2 minutes.
Please ensure that all the USB device drivers are installed and ‘ready for use’ before proceeding to the next step. This preparation
may take up to 20 minutes to complete. The Windows OS reports new device arrivals in the Notification Area of the Task Bar. Device
Manager can also be used to verify the USB connections.
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
Table 1. General MAX19692/MAX19693 EV Kit Jumper Settings
JUMPER
POSITION
EVKIT FUNCTION
Installed*
Not Installed
MAX19692/MAX19693 external reference connected
MAX19692/MAX19693 using internal reference
JU1
Installed*
Not Installed
Power for U3 – MAX6161 – external reference
MAX6161 NOT powered
JU2
JU3
(DELAY)
1-2*
2-3
Logic High (VDD3.3) – Delay of 1/2 Input Data Period
Logic low (GND) – No Delay Added
JU5
(CLKDIV)
1-2*
2-3
Logic High (VDD3.3) – DDR Mode: DATACLK = input data rate/2 (f
/4)
CLK
/8)
Logic low (GND) – QDR Mode: DATACLK = input data rate/4 (f
CLK
JU8
(CAL)
Installed*
Not Installed
External RESET (CAL Enable) Connected
Float CAL Input
*Default position.
Table 2. MAX19692 Frequency-Response Selection (JU4, JU9)
SHUNT POSITION
OPERATING MODE
JU4 → RZ
JU9 → RF
2-3*
2-3*
NRZ mode
RZ mode
RF mode
2-3
1-2
1-2
2-3
*Default position.
Table 3. MAX19693 Modulation Mode Selection (JU4)
SHUNT POSITION
OPERATING MODE
1-2
Enable fDAC/2 Modulation Mode
Disable Modulation Mode
2-3*
*Default position.
Table 4. MAX19693 Input Register Scan Enable (JU7)
CONNECTION
SE PIN
SCAN FUNCTION
Installed*
Connected to GND
Scan Disabled
Not connected (SE pin
internally pulled down to
ground GND)
User must supply a
1.8V CMOS logic signal to pin 1 of jumper JU7 to enable scan
Not Installed
*Default position.
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
5) Select the DAC in use
Power Supplies
a. Click on the text box in the DAC Selection section
of the window.
b. Select MAX19692 or MAX19693 from the list.
Each evaluation board operates from two 1.8V and one
3.3V power supplies. The two separate 1.8V power supplies
can be driven from the same source. Each power plane on
the PCB is filtered for optimum dynamic performance.
6) Load Test Patterns
a. Click the Load Pattern List button.
b. A file browser will open in the C:\maximintegrated\
MUXDACEVKIT\TestPatterns folder. Select the
CW or Two-Tone list for 12-bit devices.
Clock Signal
Each DAC requires a differential clock input signal with
minimal jitter. The evaluation boards feature single-ended-
to-differential-conversion circuitry. Supply a single ended
clock signal at the SMA connector labeled CLK. The
power applied to the SMA should be between +10dBm
and +15dBm when measured at the connector. Insertion
losses due to the interconnecting cable decrease the
power seen at the board input. Account for these losses
when setting the signal generator amplitude.
7) Wait for the patterns to load.
8) Select a Pattern from the List
a. Click on the Select Pattern text.
b. Select a pattern from the populated list.
i. The format of the CW pattern’s name is
FO_FNumxFS_AO_ANumdBFS_12-Bit and
the format of the two-tone pattern’s name
is FCent_FNumxFS_FSpcSNUMxFS_AO_
ANumdBFS_12-BIT, where the variables are
FNum, ANum, and SNum for the frequency,
amplitude, and spacing, respectively. The
DAC output frequency of the patterns will be
Reference Voltage Options
The DAC requires a reference voltage to set its output
power. The DAC features a stable on-chip bandgap refer-
ence of 1.2V. The internal reference can be overdriven
by an external reference to enhance accuracy and drift
performance or for gain control.
at or around FNum * f
.
DAC
9) Start the Pattern
The evaluation board features three reference options.
Use the DAC’s internal voltage reference by removing the
shunts from jumpers JU1 and JU2. Use an external refer-
ence by removing the shunts from jumpers JU1 and JU2
and connecting a stable voltage reference at the REFIO
pad. Install shunts on jumpers JU1 and JU2 to use the
on-board reference (MAX6161). See Table 1 to configure
the shunts across jumpers JU1 and JU2 and select the
source of the reference voltage.
a. Click the Start button.
10) Observe the DAC output.
Refer to the Test Patterns and Lists section of the
MUXDAC User’s Guide for details regarding the creation
of custom patterns and lists.
Detailed Description of Hardware
The MAX19692 and MAX19693 EV kits are designed to
simplify the evaluation of the MAX19692 2.3Gsps and
MAX19693 4.0Gsps 12-bit, direct RF synthesis DACs.
Each EV Kit operates with LVDS data inputs, a single-
ended clock input signal, and 1.8V/3.3V power supplies
for simple board operation.
The full-scale continuous-wave (CW) output power is
dependent on the value of the reference voltage and
resistor R6. Use the equation below to calculate the DAC
full-scale output power:
V
The evaluation board features on-board QSH connec-
tors that interface to the MAXDACFMCADP1 board that
allows direct connection to a VC707 FMC connector, cir-
cuitry that converts the differential 50Ω output to a single-
ended 50Ω signal, and circuitry to convert a user-supplied
single-ended clock signal to a differential clock required
by the DAC. The evaluation board also includes jumpers
that configure frequency response, modulation, scan, ref-
erence voltage, calibration, and data clock modes.
REFIO
R6
P
= 73.1+ 20×log
dBm
[
]
OUT
where:
P
= DAC full-scale output power,
OUT
V
= Voltage present at the REFIO pad in volts
(1.2V if using the device’s internal reference),
REFIO
R6 = Value of resistor R6 in ohms (2kΩ default).
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
JU4 to configure the MOD pin. Refer to the MAX19693 IC
data sheet for more details on the MOD pin. See Table 3
for jumper JU4 configuration.
Clock Division
The data clock output differential signal (DATACLK)
frequency is scaled down from the DAC clock input.
Jumper JU5 controls the division factor. See Table 2 for
shunt settings. Refer to the IC data sheet for details on
synchronizing the DAC to an external pattern generator.
Install resistors R2, R3, and R4 to access the differential
output data clock signal at the DATA-CLKP and DATA-
CLKN SMA connectors on the evaluation board when not
using the MUXDAC Data Source System.
Output Resistor Calibration
The evaluation board circuit features an on-board µP
supervisor (U2) to generate the CAL signal required to
calibrate the integrated output termination resistors. At
power-up, the supervisor applies a logic-high to the CAL
pin 140ms after the final supply voltage is within its speci-
fied range. Pressing switch SW1 recalibrates the inte-
grated termination resistors by creating a logic-low pulse
on the CAL pin. The shunt on jumper JU8 can be removed
to apply an external logic signal to pin 1 of jumper JU8
and initiate a CAL operation. See Table 1 for jumper JU8
configuration. Refer to the IC data sheet for details on the
CAL operation.
Data Clock Delay
Jumper JU3 adjusts the delay of the data clock output.
Refer to the Data Timing Relationships section in the IC
data sheet for more details. See Table 1 for shunt settings.
Differential Output
The DAC features a differential output with built-in self-
calibrated output termination resistors. The evaluation
board circuit pulls the outputs up to AVDD3.3 through
bias inductors L4 and L5 to optimize performance of the
device. Balun transformer T1 converts the differential sig-
nal to a single-ended signal. Measure the resulting DAC
output at the SMA connector labeled OUT.
Input Register Scan (MAX19693)
The MAX19693 scan function can be enabled or disabled
by configuring the SE pin. When the scan function is
enabled, the contents of the input register are shifted out
on the SO pin. Connect a digital sampling device to pin 1
of JU6 to access the scan output data on the SO pin. The
EV kit circuit provides jumper JU7, which is used to enable
or disable the scan function. During normal operation,
install the shunt across jumper JU7 to disable the scan
function. Refer to the MAX19693 IC data sheet for more
details. See Table 4 for jumper JU7 configuration.
Impulse/Frequency Response
(MAX19692)
The MAX19692 DAC has three impulse/frequency
response modes: NRZ, RZ, and RF. These modes are
set with the RZ and RF input pins. The MAX19692 EV kit
provides jumpers JU4 and JU9 to configure these pins.
See Table 2 for jumpers JU4 and JU9 configuration. Refer
to the DAC Impulse/Frequency Response Mode section
in the MAX19692 IC data sheet for more details.
Operation with the MUXDAC
Data Source
The device’s LVDS-level data clock outputs (DATACLKP,
DATACLKN) synchronize the data source and the DAC
during normal operation of the EV Kit. Install a shunt
on JU5:1-2 to configure the DAC for DDR mode which
produce the correct DATACLK frequency for operation
with the MUXDAC Data Source System.
Modulation (MAX19693)
The MAX19693 f
/2 (or f
) modulation mode can be
DAC
CLK
enabled or disabled by connecting the MOD pin to 3.3V
or to ground. The evaluation board circuit provides jumper
Ordering Information
PART
TYPE
EV KIT
EV KIT
MAX19692EVKIT
MAX19693EVKIT
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAX19692/MAX19693 EV Kit Bill of Materials
ITEM REFERENCE QTY VALUE TOLERANCE
DESCRIPTION
PART NUMBER
MANUFACTURER
0402 Ceramic
Capacitor, SMT, 50V
C1005C0G1H101J
GRM1555C1H101J
TDK
Murata
1
2
3
4
5
C1, C2
2
4
100pF
0.1μF
1.0μF
-
±5%
±20%
±20%
-
C3, C4, C12,
C13
0402 Ceramic
Capacitor, SMT, 10V
C1005X5R1A104M
TDK
C5-C8,
C24-C31
0402 Ceramic
Capacitor, SMT, 6.3V
12
0
EEEFTV151XAP
-
PANASONIC
-
0603 Capacitors, SMT,
Not Installed
C9, C10, C11
C14, C15,
C16
C-Case Tantalum
Capacitor, SMT, 16V
TPSC476M016R0350
594D476X0016C2T
AVX
Vishay
3
47μF
±20%
0805 Ceramic
Capacitor, SMT, 6.3V
C2012X5R0J106M
GRM21BR60J106M
TDK
Murata
6
7
C17-C23
7
10μF
±20%
±20%
0201 Ceramic
Capacitor, SMT, 6.3V
C32 – C47
16
0.1μF
C0603X5R0J104M
TDK
SMA PC Mount
Connector, Vertical,
Not installed
DATA-CLKP,
DATA-CLKN
8
9
0
2
2
4
-
-
-
-
-
-
-
-
PC edge mount 0.92”
SMA Connector
CLK, OUT
H1, H2
32K243-40ML5
QSH-060-01-L-D-A
Rosenberger
Samtec
Vertical 2x60 surface
mount high speed
socket connectors
10
JU1, JU2,
JU7, JU8
2x4 pin header(Cut to
Fit)
Sullins Electronic
Corp.
11
12
-
-
-
-
PEC36SAAN
PEC36SAAN
JU3, JU4,
JU5, JU9*
4
(3*)
3 Pin Headers (Cut to
Fit)
Sullins Electronic
Corp.
2-pin headers,
No Installed
Sullins Electronic
Corp.
13
14
15
16
JU6
L1, L2, L3
L4, L5
R1
0
3
2
1
-
-
-
PEC36SAAN
EXC-CL4532U1
1008CS-222XJLB
1812 Chip bead cores,
SMT
-
PANASONIC
Coilcraft
2520 wire-wound chip
inductors, SMT, 0.47A
2.2uH
±5%
±1%
10.0
kOhm
0603 chip resistor, SMT
0402 chip resistor,
SMT,
Not Installed
0603 chip resistor,
SMT,
17
18
R2, R3
R4
0
0
-
-
-
-
Not Installed
49.9
Ohm
2.0
0402 chip resistors,
SMT
19
20
R5, R6
R7
2
1
±1%
±0.1%
0603 chip resistor, SMT
kOhm
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAX19692/MAX19693 EV Kit Bill of Materials (continued)
ITEM REFERENCE QTY VALUE TOLERANCE
DESCRIPTION
PART NUMBER
MANUFACTURER
499
Ohm
21
22
23
R8
1
2
2
±1%
±1%
±1%
0402 chip resistor, SMT
174
kOhm
R9, R11
R10, R12
0603 chip resistor, SMT
0603 chip resistor, SMT
100k
Ohm
Switch, Momentary,
Push-Button, SMT
24
25
26
SW1
T1 - T4
TP1
1
4
0
-
-
-
-
-
-
B3S-1000
Omron Electronics
Mini-Circuits
1:1 3000MHz RF
Transformers
TC1-1-13M+
Test point, Not Installed
PC Test Point, Red
PC Test point, black
VDD1.8,
AVDD3.3,
AVCLK
Keystone
Electronics
27
28
3
3
-
-
-
-
5000
5001
Keystone
Electronics
GND
12-Bit, 2.3Gsps, Digital-
to-Analog Converter,
169 CSBGA
U1
29
30
1
1
-
-
-
-
MAX19692EXW-D
MAX19693EXW-D
Maxim
Maxim
(MAX19692)
12-Bit, 4Gsps, Digital-
to-Analog Converter,
169 CSBGA
U1
(MAX19693)
High-Accuracy
Supervisory Circuit,
6-SOT23
MAX6710LUT+
(Top Mark: AAZL)
31
32
33
U2
U3
-
1
1
-
-
-
-
-
-
1.25V precision voltage
reference, 8 SO
MAX6161AESA+ or
MAX6161BESA+
Maxim
8
(7*)
Shunts (JU1-JU5, JU7-
JU9*)
Sullins Electronic
Corp.
STC02SYAN
MAX19692 /
MAX19693 Evaluation
Kit
PCB, 1 Oz Impedance
Controlled
34
35
1
1
-
-
Maxim
Maxim
FMC ADAPTER CARD
MAXDACFMCADP1
*MAX19693EVKIT Excludes JU9
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAX19692 Kit Schematic
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAX19692 Kit Schematic (continued)
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAX19693 Kit Schematic
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAX19693 Kit Schematic (continued)
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAXDACFMCADP1 Bill of Materials
ITEM
REFERENCE
QTY
DESCRIPTION
PART NUMBER
QTH-060-01-L-D-A
ASP-134488-01
EEEFTV151XAP
MANUFACTURER
SAMTEC
1
2
3
J1, J2
2
1
1
120 pin high-speed connector, SMT
High pin count FMC connector, SMT
PCB:EPCBMAXADAPTDACFMC1
J3
SAMTEC
PCB
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Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAXDACFMCADP1 Schematic
J1-A
QTH-060-01-L-D-A
J2-A
QTH-060-01-L-D-A
1
2
1
2
1
3
5
7
2
4
6
1
3
5
7
2
4
6
3
4
3
4
CLKBN0 IN
CLKBP0 IN
IN CLKAN0
IN CLKAP0
CLKCN0 IN
CLKCP0 IN
OUT
OUT
CLKDN0
CLKDP0
5
6
5
6
7
8
7
8
8
8
9
10
12
14
16
18
20
22
24
26
28
30
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60
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60
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50
52
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60
DB_N(0) IN
IN DA_N(0)
DC_N(0) IN
IN DD_N(0)
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
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57
59
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29
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55
57
59
IN
IN
IN
IN
DB_P(0)
DA_P(0)
DC_P(0)
DD_P(0)
DB_N(1) IN
IN DA_N(1)
DC_N(1) IN
OUT
OUT
DD_N(1)
DD_P(1)
IN
IN
IN
DB_P(1)
DA_P(1)
DC_P(1)
DB_N(2) IN
IN DA_N(2)
DC_N(2) IN
IN DD_N(2)
IN
IN
IN
IN
DB_P(2)
DA_P(2)
DC_P(2)
DD_P(2)
DB_N(3) IN
IN DA_N(3)
DC_N(3) IN
IN DD_N(3)
IN
IN
IN
IN
DB_P(3)
DA_P(3)
DC_P(3)
DD_P(3)
DB_N(4) IN
IN DA_N(4)
DC_N(4) IN
IN DD_N(4)
IN
IN
IN
IN
DB_P(4)
DA_P(4)
DC_P(4)
DD_P(4)
DB_N(5) IN
IN DA_N(5)
DC_N(5) IN
IN DD_N(5)
IN
IN
IN
IN
DB_P(5)
DA_P(5)
DC_P(5)
DD_P(5)
DB_N(6) IN
IN DA_N(6)
DC_N(6) IN
IN DD_N(6)
IN
IN
IN
IN
DB_P(6)
DA_P(6)
DC_P(6)
DD_P(6)
DB_N(7) IN
IN DA_N(7)
DC_N(7) IN
IN DD_N(7)
IN
IN
IN
IN
DB_P(7)
DA_P(7)
DC_P(7)
DD_P(7)
JI-B
QTH-060-01-L-D-A
J2-B
QTH-060-01-L-D-A
61
62
61
62
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
63
64
63
64
DB_N(8)
IN
DA_N(8)
IN
DC_N(8)
IN
DD_N(8)
IN
IN DD_P(8)
65
66
65
66
DB_P(8)
IN
DC_P(8)
IN
IN DA_P(8)
67
68
67
68
69
70
69
70
DB_N(9)
IN
DA_N(9)
IN DA_P(9)
DA_N(10)
DC_N(9)
IN
DD_N(9)
IN DD_P(9)
DD_N(10)
IN DD_P(10)
IN
IN
71
72
71
72
DB_P(9)
IN
DC_P(9)
IN
73
74
73
74
75
76
75
76
DB_N(10)
IN
DC_N(10)
IN
IN
IN
77
78
77
78
DB_P(10)
IN
DC_P(10)
IN
IN DA_P(10)
79
80
79
80
81
82
81
82
83
84
83
84
DB_N(11)
IN
DC_N(11)
IN
DD_N(11)
DD_P(11)
IN
IN
IN
IN
DA_N(11)
85
86
85
86
DB_P(11)
DC_P(11)
IN
IN
DA_P(11)
87
88
87
88
89
90
89
90
DB_N(12)
DB_P(12)
DA_N(12)
IN DA_P(12)
DA_N(13)
IN DA_P(13)
DC_N(12)
DC_P(12)
DD_N(12)
IN DD_P(12)
IN
IN
IN
IN
IN
IN
91
92
91
92
93
94
93
94
93
95
97
99
93
95
97
99
95
96
95
96
DB_N(13)
DB_P(13)
96
98
DC_N(13)
DC_P(13)
96
98
DD_N(13)
IN DD_P(13)
IN
IN
IN
IN
IN
IN
97
98
97
98
99
100
102
104
106
108
110
112
114
116
118
120
99
100
102
104
106
108
110
112
114
116
118
120
100
102
104
106
108
110
112
114
116
118
120
100
102
104
106
108
110
112
114
116
118
120
101
103
105
107
109
111
113
115
117
119
101
103
105
107
109
111
113
115
117
119
101
103
105
107
109
111
113
115
117
119
101
103
105
107
109
111
113
115
117
119
DB_N(14)
DB_P(14)
DA_N(14)
IN DA_P(14)
DC_N(14)
DC_P(14)
DD_N(14)
IN DD_P(14)
IN
IN
IN
IN
IN
IN
DB_N(15)
DB_P(15)
DA_N(15)
DA_P(15)
DC_N(15)
DC_P(15)
DD_N(15)
DD_P(15)
IN
IN
IN
IN
IN
IN
IN
IN
CLKBN1
CLKBP1
CLKAN1
CLKAP1
CLKCN1
CLKCP1
CLKDN1
CLKDP1
IN
IN
IN
IN
IN
IN
IN
IN
J1-C
QTH-060-01-L-D-A
J2-3
QTH-060-01-L-D-A
121
123
125
127
122
124
126
128
121
123
125
127
122
124
126
128
121
123
125
127
122
124
126
128
121
123
125
127
122
124
126
128
Maxim Integrated
│ 14
www.maximintegrated.com
Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
MAXDACFMCADP1 Schematic (continued)
J3-A
J3-B
J3-C
J3-D
J3-E
ASP-134488-01
ASP-134488-01
ASP-134488-01
ASP-134488-01
ASP-134488-01
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
1
1
1
1
1
2
2
2
2
2
A3
B3
C3
D3
E3
3
3
3
3
3
A4
B4
C4
D4
E4
4
4
4
4
4
A5
B5
C5
D5
E5
5
5
5
5
5
A6
A7
A8
A9
B6
B7
B8
B9
C6
C7
C8
C9
D6
D7
D8
D9
E6
E7
E8
E9
6
6
6
6
6
DD_P(6) OUT
DD_N(6) OUT
7
7
7
7
7
8
8
8
8
8
DA_P(0) OUT
DA_N(0) OUT
9
9
9
9
9
DD_P(13) OUT
DD_N(13) OUT
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DA_P(3) OUT
DA_N(3) OUT
DA_P(14) OUT
DA_N(14) OUT
DD_P(11) OUT
DD_N(11) OUT
DA_P(9) OUT
DA_N(9) OUT
DA_P(15) OUT
DA_N(15) OUT
DD_P(12) OUT
DD_N(12) OUT
DA_P(13) OUT
DA_N(13) OUT
DA_P(11) OUT
DA_N(11) OUT
DD_P(7) OUT
DD_N(7) OUT
CLKBP1 OUT
CLKBN1 OUT
DC_P(2) OUT
DC_N(2) OUT
DB_P(0) OUT
OUT
DB_P(7) OUT
DB_N(7) OUT
DB_N(0)
DC_P(10) OUT
DC_N(10) OUT
DB_P(13) OUT
OUT
DB_P(4) OUT
DB_N(4) OUT
DB_N(13)
DC_P(14) OUT
DC_N(14) OUT
OUT
DC_P(6)
DC_N(6) OUT
IN
DC_P(0)
DC_N(0) IN
J3-F
J3-G
J3-H
J3-J
J3-K
ASP-134488-01
ASP-134488-01
ASP-134488-01
ASP-134488-01
ASP-134488-01
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
K1
K2
K3
K4
K5
K6
K7
K8
K9
1
1
1
1
1
2
2
2
2
2
CLKBP0 IN
CLKBN0 IN
3
3
3
3
3
4
4
4
4
4
CLKDP1 OUT
CLKDN1 OUT
CLKAP0 OUT
CLKAN0 OUT
5
5
5
5
5
6
6
6
6
6
CLKAP1 OUT
CLKAN1 OUT
DD_P(10) OUT
DD_N(10) OUT
7
7
7
7
7
DD_P(8) OUT
DD_N(8) OUT
DA_P(10) OUT
DA_N(10) OUT
DD_P(2) OUT
DD_N(2) OUT
8
8
8
8
8
9
9
9
9
9
DA_P(7) OUT
DA_N(7) OUT
DD_P(4) OUT
DD_N(4) OUT
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DD_P(3) OUT
DD_N(3) OUT
DA_P(1) OUT
DA_N(1) OUT
DD_P(9) OUT
DD_N(9) OUT
DA_P(12) OUT
DA_N(12) OUT
DD_P(5) OUT
DD_N(5) OUT
DA_P(5) OUT
DA_N(5) OUT
DD_P(14) OUT
DD_N(14) OUT
DA_P(8) OUT
DA_N(8) OUT
DD_P(15) OUT
DD_N(15) OUT
DA_P(4) OUT
DA_N(4) OUT
CLKDP0 OUT
CLKDN0 OUT
DA_P(2) OUT
DA_N(2) OUT
DD_P(0) OUT
DD_N(0) OUT
DA_P(6) OUT
DA_N(6) OUT
DB_P(2) OUT
DB_N(2) OUT
DD_P(1) OUT
DD_N(1) OUT
DC_P(3) OUT
DC_N(3) OUT
DB_P(3) OUT
DB_N(3) OUT
DB_P(5) OUT
DB_N(5) OUT
DC_P(4) OUT
DC_N(4) OUT
DC_P(5) OUT
DC_N(5) OUT
DB_P(11) OUT
DB_N(11) OUT
CLKCP1 IN
CLKCN1 IN
DB_P(9) OUT
DB_N(9) OUT
DC_P(12) OUT
DC_N(12) OUT
DC_P(7) OUT
DC_N(7) OUT
DB_P(15) OUT
DB_N(15) OUT
DB_P(10) OUT
DB_N(10) OUT
DC_P(8) OUT
DC_N(8) OUT
DB_P(1) OUT
DB_N(1) OUT
DC_P(11) OUT
DC_N(11) OUT
DB_P(12) OUT
DB_N(12) OUT
DC_P(13) OUT
DC_N(13) OUT
DC_P(9) OUT
DC_N(9) OUT
DB_P(6) OUT
DB_N(6) OUT
DC_P(15) OUT
DC_N(15) OUT
DB_P(8) OUT
DB_N(8) OUT
DC_P(1) OUT
DC_N(1) OUT
DB_P(14) OUT
DB_N(14) OUT
CLKCP0 IN
CLKCN0 IN
Maxim Integrated
│ 15
www.maximintegrated.com
Evaluates: MAX19692/MAX19693
MAX19692/MAX19693
Evaluation Kit User’s Guide
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
12/06
Initial release
—
The EV kit board was redesigned. The same data sheet is now used for both the
MAX19692 and MAX19693 EV kits
1
5/08
1–16
Extensive changes to flow and content of document. Changes include matching
newer format. Also details new tools and adapters provided for the MAX19692
and MAX19693 EV kits
2
3/19
1–16
Updated Procedure, Detailed Description of Hardware, Power Supplies, Clock
Division, Operation with the MUXDAC Data Source sections, Table 1 and
Ordering Information table
3
10/20
3–6
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2020 Maxim Integrated Products, Inc.
│ 16
相关型号：
MAX1969EUI+T
Switching Regulator, Current-mode, 9A, 1000kHz Switching Freq-Max, BICMOS, PDSO28, 4.40 MM, EXPOSED PAD, TSSOP-28
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