MAX196AENI+ [MAXIM]
Analog Circuit, 1 Func, PDIP28, PLASTIC, DIP-28;
| 型号： | MAX196AENI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, PDIP28, PLASTIC, DIP-28 光电二极管 |
| 文件： | 总16页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0435; Rev 0; 9/95
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 12-Bit Resolution, 1/2LSB Linearity
♦ Single +5V Supply Operation
♦ Software-Selectable Input Ranges:
±10V, ±5V, 0V to +10V, 0V to +5V (MAX196)
The MAX196/MAX198 multirange, 12-bit data-acquisi-
tion systems (DAS) require only a single +5V supply for
operation, yet convert analog signals at their inputs up
to ±10V (MAX196) and ±4V (MAX198). These systems
provide six analog input channels that are indepen-
dently software programmable for a variety of ranges:
±10V, ±5V, 0V to +10V, and 0V to +5V for the MAX196;
±V
, ±V
/2, 0V to +V
, 0V to +V /2
REF
REF
REF
REF
(MAX198)
♦ Internal 4.096V or External Reference
♦ Fault-Protected Input Multiplexer
♦ 6 Analog Input Channels
♦ 6µs Conversion Time, 100ksps Sampling Rate
♦ Internal or External Acquisition Control
♦ Two Power-Down Modes
±V
, ±V
/2, 0V to +V
, and 0V to +V
/2 for
REF
REF
REF
REF
the MAX198. This range switching increases the effec-
tive dynamic range to 14 bits and provides the flexibility
to interface ±12V, ±15V, and 4mA to 20mA powered
sensors to a single +5V system. In addition, these con-
verters are fault protected to ±16.5V; a fault condition
on any channel will not affect the conversion result of
the selected channel. Other features include a 5MHz
bandwidth track/hold, 100ksps throughput rate, soft-
ware-selectable internal/external clock, internal/external
acquisition control, 12-bit parallel interface, and internal
4.096V or external reference.
♦ Internal or External Clock
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
MAX196ACNI
MAX196BCNI
MAX196ACWI
MAX196BCWI
MAX196ACAI
MAX196BCAI
Two p rog ra mma b le p owe r-d own mod e s (STBYPD,
FULLPD) provide low-current shutdown between con-
ve rs ions . In STBYPD mod e , the re fe re nc e b uffe r
remains active, eliminating start-up delays.
28 Wide SO
28 SSOP
The MAX196/MAX198 employ a standard microproces-
sor (µP) interface. A three-state data I/O port is config-
ure d to op e ra te with 16-b it d a ta b us e s , a nd d a ta -
access and bus-release timing specifications are com-
patible with most popular µPs. All logic inputs and out-
puts are TTL/CMOS compatible.
28 SSOP
Ordering Information continued at end of data sheet.
__________________P in Co n fig u ra t io n
TOP VIEW
These devices are available in 28-pin DIP, wide SO,
SSOP (55% smaller in area than wide SO), and ceramic
SB packages. For 8+4 bus interface, see the MAX197
and the MAX199 data sheets. An evaluation kit will be
available after December 1995 (MAX196EVKIT-DIP).
CLK
CS
28 DGND
1
2
V
27
26
25
24
23
DD
WR
RD
D11
D10
D9
3
4
INT
REF
5
________________________Ap p lic a t io n s
Industrial-Control Systems
Robotics
MAX196
MAX198
D8
6
D7
7
22 REFADJ
21 CH5
D6
8
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
D5
CH4
CH3
CH2
CH1
CH0
AGND
9
20
19
18
17
16
15
D4
10
D3 11
D2 12
Telecommunications
13
14
D1
D0
DIP/SO/SSOP/Ceramic SB
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -7 2 2 -8 2 6 6 fo r fre e s a m p le s o r lit e ra t u re .
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
to AGND............................................................-0.3V to +7V
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C) ......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
DD
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (V + 0.3V)
REFADJ to AGND.......................................-0.3V to (V + 0.3V)
DD
DD
Digital Inputs to DGND...............................-0.3V to (V + 0.3V)
MAX196_C_ I/MAX198_C_ I .................................0°C to +70°C
MAX196_E_ I/MAX198_E_ I ...............................-40°C to +85°C
MAX196_MYI/MAX198_MYI.............................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
Digital Outputs to DGND............................-0.3V to (V + 0.3V)
DD
CH0–CH5 to AGND ..........................................................±16.5V
Continuous Power Dissipation (T = +70°C)
A
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
DD
= 4.096V; 4.7µF at REF pin; external clock, f
= 2.0MHz
REF
CLK
with 50% duty cycle; T = T
to T ; unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
6/MAX198
PARAMETER
ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
MAX196A/MAX198A
MAX196B/MAX198B
±1/2
±1
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
±1
MAX196A/MAX198A
±3
Unipolar
Bipolar
MAX196B/MAX198B
MAX196A/MAX198A
MAX196B/MAX198B
±5
Offset Error
LSB
LSB
±5
±10
Unipolar
Bipolar
±0.1
±0.5
Channel-to-Channel Offset
Error Matching
MAX196A/MAX198A
MAX196B/MAX198B
MAX196A/MAX198A
MAX196B/MAX198B
±7
±10
±7
Unipolar
Bipolar
Gain Error
(Note 2)
LSB
±10
Unipolar
Bipolar
3
5
Gain Temperature Coefficient
(Note 2)
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p (MAX196) or ±4.096Vp-p (MAX198), f
= 100ksps)
-78
SAMPLE
MAX196A/MAX198A
MAX196B/MAX198B
Up to the 5th harmonic
70
69
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
SINAD
THD
dB
dB
dB
-85
Spurious-Free Dynamic Range
SFDR
80
50kHz, V = ±5V (MAX196) or ±4V (MAX198)
IN
(Note 3)
Channel-to-Channel Crosstalk
Aperture Delay
-86
dB
External CLK mode/external acquisition control
External CLK mode/external acquisition control
15
ns
ps
<50
Aperture Jitter
Internal CLK mode/internal acquisition
control (Note 4)
10
ns
2
_______________________________________________________________________________________
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f = 2.0MHz
CLK
DD
REF
with 50% duty cycle; T = T
to T ; unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Track/Hold Acquisition Time
f
= 2.0MHz
3
µs
CLK
±10V or ±V
range
5
REF
±5V or ±V /2 range
2.5
2.5
1.25
REF
-3dB
rolloff
Small-Signal Bandwidth
MHz
0V to 10V or 0V to V
range
REF
0V to 5V or 0V to V /2 range
REF
0
0
10
5
MAX196
MAX198
MAX196
MAX198
Unipolar
0
V
REF
0
V
/2
REF
Input Voltage Range
(see Table 3)
V
IN
V
-10
-5
10
5
Bipolar
Unipolar
Bipolar
-V
REF
V
REF
-V /2
REF
V
/2
REF
0V to 10V range
MAX196
720
360
10
0V to 5V range
MAX198
0.1
Input Current
I
IN
±10V range
MAX196
-1200
-600
720
360
10
µA
±5V range
±V
REF
range
-1200
-600
MAX198
±V /2 range
REF
10
Unipolar
Bipolar
21
16
∆V
∆I
IN
IN
Input Resistance
kΩ
Input Capacitance
(Note 5)
40
pF
INTERNAL REFERENCE
REF Output Voltage
V
T
= +25°C
4.076
4.096
15
4.116
V
REF
A
REF Output Tempco
MAX196_C/MAX198_C
MAX196_E/MAX198_E
MAX196_M/MAX198_M
(Contact Maxim Applications for
guaranteed temperature drift
specifications)
TC V
30
ppm/°C
REF
40
Output Short-Circuit Current
Load Regulation
30
10
mA
mV
µF
0mA to 0.5mA output current (Note 6)
With recommended circuit (Figure 1)
Capacitive Bypass at REF
REFADJ Output Voltage
REFADJ Adjustment Range
Buffer Voltage Gain
4.7
2.465
2.500
±1.5
2.535
V
%
1.6384
V/V
_______________________________________________________________________________________
3
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f
= 2.0MHz
DD
REF
CLK
with 50% duty cycle; T = T
to T ; unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT (buffer disabled, reference input applied to REF pin)
Input Voltage Range
2.4
4.18
400
1
V
Normal, or STANDBY
power-down mode
V
4.18V
=
REF
Input Current
µA
FULL power-down mode
Normal, or STANDBY power-down mode
FULL power-down mode
10
5
kΩ
Input Resistance
MΩ
REFADJ Threshold for
Buffer Disable
V
DD
- 50mV
V
POWER REQUIREMENTS
6/MAX198
Supply Voltage
V
DD
4.75
5.25
V
Normal mode, bipolar ranges
Normal mode, unipolar ranges
STANDBY power-down mode
FULL power-down mode (Note 7)
External reference = 4.096V
Internal reference
18
10
mA
6
700
60
Supply Current
I
DD
850
120
1
µA
±0.1
1
± /
2
Power-Supply Rejection Ratio
(Note 8)
PSRR
LSB
± /
2
TIMING
Internal Clock Frequency
External Clock Frequency Range
f
C
= 100pF
CLK
1.25
0.1
3.0
3.0
3.0
1.56
2.00
2.0
MHz
MHz
CLK
f
CLK
External CLK
Internal CLK
t
Internal acquisition
ACQI
ACQE
CONV
5.0
Acquisition Time
µs
External acquisition (Note 9)
After FULLPD or STBYPD
External CLK
t
5
6.0
6.0
Conversion Time
Throughput Rate
t
µs
Internal CLK, C
External CLK
= 100pF
7.7
10.0
100
CLK
ksps
Internal CLK, C
= 100pF
62
CLK
Bandgap Reference
Start-Up Time
Power-up (Note 10)
200
µs
C
C
= 4.7µF
= 33µF
8
To 0.1mV REF bypass
capacitor fully discharged
REF
REF
Reference Buffer Settling
ms
60
DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS) (Note 11)
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
V
2.4
V
V
INH
V
INL
0.8
±10
15
I
V
= 0V or V
DD
µA
pF
IN
IN
C
(Note 5)
IN
4
_______________________________________________________________________________________
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f
= 2.0MHz
DD
REF
CLK
with 50% duty cycle; T = T
to T ; unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (D11–D0, INT)
Output Low Voltage
V
V
= 4.75V, I
= 4.75V, I
= 1.6mA
0.4
15
V
V
OL
DD
SINK
Output High Voltage
V
OH
V
DD
= 1mA
V
DD
- 1
SOURCE
Three-State Output Capacitance
C
(Note 5)
pF
OUT
TIMING CHARACTERISTICS
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
DD
= 4.096V; 4.7µF at REF pin; external clock, f = 2.0MHz
CLK
REF
with 50% duty cycle; T = T
to T ; unless otherwise noted.)
MAX
A
MIN
PARAMETER
CS Pulse Width
SYMBOL
CONDITIONS
MIN
80
80
0
TYP
MAX
UNITS
ns
t
CS
WR Pulse Width
t
ns
WR
CS to WR Setup Time
CS to WR Hold Time
CS to RD Setup Time
CS to RD Hold Time
CLK to WR Setup Time
CLK to WR Hold Time
Data Valid to WR Setup
Data Valid to WR Hold
t
ns
CSWS
CSWH
t
0
ns
t
0
ns
CSRS
t
0
ns
CSRH
t
100
50
ns
CWS
t
ns
CWH
t
60
0
ns
DS
DH
DO
t
ns
RD Low to Output Data Valid
RD High to Output Disable
RD Low to INT High Delay
t
Figure 2, C = 100pF (Note 12)
L
120
70
ns
t
TR
(Note 13)
ns
t
120
ns
INT1
Note 1: Accuracy specifications tested at V = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
DD
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
Note 2: External reference: V
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
REF
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale.
Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD
= high control byte.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t = t = 5ns from a voltage level of 0.8V to 2.4V.
R
F
Note 12: t
is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
DO
Note 13: t is defined as the time required for the data lines to change by 0.5V.
TR
_______________________________________________________________________________________
5
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
vs. DIGITAL CODE
FFT PLOT
0
-20
0.250
12.0
11.5
11.0
10.5
f
= 100kHz
SAMPLE
f
= 10kHz
= 100kHz
TONE
0.200
0.150
0.100
0.050
0
f
SAMPLE
-40
-60
-80
-0.050
-0.100
-0.150
-100
-120
6/MAX198
10.0
0
1000
2000
3000
4000
0
25
FREQUENCY (kHz)
50
1
10
INPUT FREQUENCY (kHz)
100
DIGITAL CODE
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE
REFERENCE OUTPUT VOLTAGE (V
)
REF
vs. TEMPERATURE
0.4
4.100
V
DD
= 5V ±0.25V
120Hz
0.2
0
4.095
100Hz
4.090
-0.2
-0.4
A = 1.6384
V
+2.5V
INTERNAL
REFERENCE
4.085
4.080
REF
REFADJ
-0.6
-70 -50
110
130
-30 -10 10 30 50 70 90
TEMPERATURE (°C)
-55 -35
5
25 45 65
-15
85 105 125
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING vs. TEMPERATURE
GAIN-ERROR MATCHING vs. TEMPERATURE
0.33
0.20
0.32
0.31
0.30
0.18
0.16
0.14
0.12
0.10
0.29
0.28
0.27
130
130
-70 -50 -30 -10 10 30 50 70 90 110
-70 -50 -30 -10 10 30 50 70 90 110
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode,
1
CLK
place a capacitor (C
) from this pin to ground to set the internal clock frequency; f
= 1.56MHz typical
CLK
CLK
with C
= 100pF.
CLK
2
CS
Chip Select, active low
3–14
15
D11–D0
AGND
Three-State Digital I/O, D11 = MSB
Analog Ground
16–21 CH0–CH5
Analog Input Channels
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect
to V when using an external reference at the REF pin.
DD
22
REFADJ
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
23
REF
buffer by pulling REFADJ to V
.
DD
24
25
INT
RD
INT goes low when conversion is complete and output data is ready.
If CS is low, a falling edge on RD will enable a read operation on the data bus.
In the internal acquisition mode, when CS is low, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR
starts an acquisition, and a second rising edge on WRends acquisition and starts a conversion cycle.
26
WR
27
28
V
+5V Supply. Bypass with 0.1µF capacitor to AGND.
Digital Ground
DD
DGND
_______________De t a ile d De s c rip t io n
+5V
Co n ve rt e r Op e ra t io n
The MAX196/MAX198 multirange, fault-tolerant ADCs
510k
100k
24k
REFADJ
us e s uc c e s s ive a p p roxima tion a nd inte rna l inp ut
track/hold (T/H) circuitry to convert an analog signal to
a 12-bit digital output. The 12-bit parallel-output format
p rovid e s e a s y inte rfa c e to mic rop roc e s s ors (µPs ).
Figure 3 shows the MAX196/MAX198 in the simplest
operational configuration.
0.01µF
MAX196
MAX198
Figure 1. Reference-Adjust Circuit
An a lo g -In p u t Tra c k /Ho ld
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo-
lar mode and unipolar mode (MAX196 only), a low-
impedance input source, which settles in less than
1.5µs, is required to maintain conversion accuracy at
the maximum conversion rate.
+5V
3k
D
OUT
D
OUT
C
LOAD
3k
C
LOAD
When the MAX198 is configured for unipolar mode, the
input does not need to be driven from a low-impedance
a) High-Z to V and V to V
OH
b) High-Z to V and V to V
OL
OH
OL
OL
OH
source. The acquisition time (t ) is a function of the
AZ
source output resistance (R ), the channel input resis-
S
Figure 2. Load Circuits for Enable Time
tance (R ), and the T/H capacitance.
IN
_______________________________________________________________________________________
7
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
Acquisition time is calculated as follows:
In p u t Ba n d w id t h
The ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
For 0V to V : t = 9 x (R + R ) x 16pF
REF AZ
S
IN
For 0V to V /2: t = 9 x (R + R ) x 32pF
REF
AZ
S
IN
where R = 7kΩ and t is never less than 2µs (0V to
IN
AZ
V
range) or 3µs (0V to V /2 range).
REF
REF
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second
WR rising edge with D5 = 0 (see External Acquisition
section).
In p u t Ra n g e a n d P ro t e c t io n
Figure 4 shows the equivalent input circuit. The full-
scale input voltage depends on the voltage at the refer-
1
28
CLK
DGND
100pF
ence (V ). The MAX196 uses a scaling factor, which
REF
27
23
22
MAX196
MAX198
V
REF
+5V
DD
allows input voltage ranges of ±10V, ±5V, 0V to +10V,
or 0V to +5V with a 4.096V voltage reference (Table 1).
Program the desired range by setting the appropriate
control bits (D3, D4) in the control byte (Tables 2 and
3). The MAX198 does not use a scaling factor, so its
input voltage range directly corresponds with the refer-
ence voltage. It can be programmed for input voltages
of ±V , ±V /2, 0V to V , or 0V to V /2 (Table
25
26
2
6/MAX198
µP
CONTROL
INPUTS
RD
WR
CS
4.7µF
4.7µF
REFADJ
3
4
5
0.01µF
0.01µF
D11
D10
D9
24
INT
OUTPUT STATUS
6
7
8
9
D8
REF
REF
REF
REF
21
20
19
18
17
16
D7
D6
D5
CH5
CH4
3). When an external reference is applied at REFADJ,
the voltage at REF is given by V = 1.6384 x V
REF
REFADJ
ANALOG
INPUTS
CH3
CH2
CH1
CH0
10
11
(2.4V < V
< 4.18V).
D4
REF
D3
D2
The inp ut c ha nne ls a re ove rvolta g e p rote c te d to
±16.5V. This protection is active even if the device is in
power-down mode.
12
13
14
D1
D0
15
AGND
Even with V = 0V, the input resistive network provides
DD
current-limiting that adequately protects the device.
µP DATA BUS
Dig it a l In t e rfa c e
Input data (control byte) and output data are multi-
plexed on a three-state parallel interface. This parallel
I/O can easily be interfaced with a µP. CS, WR, and RD
control the write and read operations. CS is the stan-
dard chip-select signal, which enables a µP to address
the MAX196/MAX198 as an I/O port. When high, it dis-
ables the WR and RD inputs and forces the interface
into a high-Z state.
Figure 3. Operational Diagram
BIPOLAR
VOLTAGE
REFERENCE
S1
UNIPOLAR
OFF
5.12k
R1
CH_
C
HOLD
S2
R2
T/H
OUT
Table 1. Full Scale and Zero Scale
(MAX196 only)
ON
S3
TRACK
TRACK S4
HOLD
RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE
HOLD
0 to +5
0 to +10
±5
0
—
V
x 1.2207
x 2.4414
x 1.2207
x 2.4414
REF
0
—
V
REF
S1 = BIPOLAR/UNIPOLAR SWITCH R1 = 12.5kΩ (MAX196) OR 5.12kΩ (MAX198)
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R2 = 8.67kΩ (MAX196) OR ∞ (MAX198)
—
—
-V
x 1.2207
x 2.4414
V
REF
REF
±10
-V
REF
V
REF
Figure 4. Equivalent Input Circuit
_______________________________________________________________________________________
8
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
Table 2. Control-Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
PD1
PD0
ACQMOD
RNG
BIP
A2
A1
A0
BIT
NAME
PD1, PD0
ACQMOD
RNG
DESCRIPTION
These two bits select the clock and power-down modes (Table 4).
7, 6
5
0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition
Selects the full-scale voltage magnitude at the input (Table 3).
4
3
BIP
Selects unipolar or bipolar conversion mode (Table 3).
2, 1, 0
A2, A1, A0
These are address bits for the input mux to select the “on” channel (Table 5).
Table 3. Range and Polarity Selection
Table 4. Clock and Power-Down Selection
PD1 PD0
DEVICE MODE
INPUT RANGE (V)
(MAX196)
INPUT RANGE (V)
(MAX198)
BIP
RNG
0
0
0
1
Normal Operation / External Clock Mode
Normal Operation / Internal Clock Mode
0
0
1
1
0
1
0
1
0 to 5
0 to 10
±5
0 to V /2
REF
Standby Power-Down (STBYPD); clock mode
is unaffected
0 to V
REF
1
1
0
1
±V /2
REF
Full Power-Down (FULLPD); clock mode is
unaffected
±10
±V
REF
Table 5. Channel Selection
A2
0
A1
0
A0
0
CH0
CH1
CH2
CH3
CH4
CH5
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
_______________________________________________________________________________________
9
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
Input Format
The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 2 shows the control-
byte format.
duration is internally timed. Conversion starts when this
six-clock-cycle acquisition interval (3µs with f
2MHz) ends (see Figure 5).
=
CLK
External Acquisition
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control
of acquisition and conversion times. The user controls
acquisition and start-of-conversion with two separate
write pulses. The first pulse, written with ACQMOD = 1,
starts an acquisition interval of indeterminate length. The
second write pulse, written with ACQMOD = 0, termi-
nates acquisition and starts conversion on WR’s rising
edge (Figure 6). However, if the second control byte
contains ACQMOD = 1, an indefinite acquisition interval
is restarted.
Output Data Format
The output data format is binary in unipolar mode and
twos-complement binary in bipolar mode. When reading
the output data, CS and RD must be low.
Ho w t o S t a rt a Co n ve rs io n
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX196/
MAX198 for either a unipolar or bipolar input range. A
write pulse (WR + CS) can either start an acquisition inter-
val or initiate a combined acquisition plus conversion. The
sampling interval occurs at the end of the acquisition
interval. The ACQMOD bit in the input control byte offers
two options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
6/MAX198
The address bits for the input mux must have the same
values on the first and second write pulses. Power-down
mode bits (PD0, PD1) can assume new values on the
second write pulse (see Power-Down Mode section).
Writing a new control byte during a conversion cycle will
abort the conversion and start a new acquisition interval.
Ho w t o Re a d a Co n ve rs io n
A standard interrupt signal, INT, is provided to allow the
device to flag the µP when the conversion has ended
and a valid result is available. INT goes low when con-
ve rs ion is c omp le te a nd the outp ut d a ta is re a d y
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.
Internal Acquisition
Select internal acquisition by writing the control byte with
the ACQMOD bit cleared (ACQMOD = 0). This causes
the write pulse to initiate an acquisition interval whose
tCSRH
tCS
tCSRS
CS
tACQI
tCONV
tCSWS
tCSWH
tDH
tWR
WR
tDS
CONTROL
BYTE
D7–D0
ACQMOD ="0"
tINT1
INT
RD
tTR
tD0
HIGH-Z
HIGH-Z
DATA VALID
DOUT
Figure 5. Conversion Timing Using Internal Acquisition Mode
10 ______________________________________________________________________________________
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
tCSRS
tCSRH
tCS
CS
tCSWS
tACQI
tCSHW
tCONV
tWR
WR
tDH
tDS
CONTROL
CONTROL
BYTE
ACQMOD = "0"
D7–D0
INT
BYTE
ACQMOD = "1"
tINT1
RD
tD0
tTR
DATA VALID
DOUT
Figure 6. Conversion Timing Using External Acquisition Mode
Clo c k Mo d e s
The MAX196/MAX198 operate with either an internal or
an external clock. Control bits (D6, D7) select either
internal or external clock mode. Once the desired clock
mod e is s e le c te d , c ha ng ing the s e b its to p rog ra m
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, external clock mode is selected.
2000
1500
1000
Internal Clock Mode
Se le c t inte rna l c loc k mod e to fre e the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 =
1. A 100pF capacitor between the CLK pin and ground
s e ts this fre q ue nc y to 1.56MHz nomina l. Fig ure 7
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
500
0
0
50 100 150 200 250 300 350
CLOCK PIN CAPACITANCE (pF)
External Clock Mode
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz
external clock with 45% to 55% duty cycle is required for
proper operation. Operating at clock frequencies lower
than 100kHz will cause a voltage droop across the hold
capacitor, and subsequently degrade performance.
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
______________________________________________________________________________________ 11
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
CLK
WR
tCWS
WR GOES HIGH WHEN CLK IS HIGH
ACQMOD = "0"
ACQUISITION ENDS
tCWH
ACQUISITION STARTS
CONVERSION STARTS
CLK
WR
6/MAX198
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS LOW
Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tCWS
tDH
WR
ACQMOD = "0"
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION ENDS
ACQUISITION STARTS
CONVERSION STARTS
CLK
WR
tCWH
tDH
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS LOW
ACQMOD = "0"
Figure 8b. External Clock and WR Timing (External Acquisition Mode)
12 ______________________________________________________________________________________
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
__________Ap p lic a t io n s In fo rm a t io n
4.096V
4.7µF
REF 26
P o w e r-On Re s e t
At power-up, the internal power-on reset circuitry sets
INT high and puts the device in normal operation/exter-
nal clock mode. This state is selected to keep the inter-
nal clock from loading the external clock driver when
the part is used in external clock mode.
MAX196
MAX198
C
REF
A = 1.638
V
REFADJ 25
In t e rn a l o r Ex t e rn a l Re fe re n c e
The MAX196/MAX198 can operate with either an inter-
nal or external reference. An external reference can be
connected to either the REF pin or the REFADJ pin
(Figure 9).
0.01µF
10k
2.5V
To use the REF input directly, disable the internal buffer
by tying REFADJ to V . Using the REFADJ input elimi-
DD
nates the need to buffer the reference externally. When
the reference is applied at REFADJ, bypass REFADJ with
a 0.01µF capacitor to AGND.
Figure 9a. Internal Reference
The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at the REF pin from a 2.5V reference.
REF 26
4.096V
4.7µF
MAX196
MAX198
Internal Reference
The inte rna lly trimme d 2.50V re fe re nc e is g a ine d
through the REFADJ buffer to provide 4.096V at REF.
Bypass the REF pin with a 4.7µF capacitor to AGND
and the REFADJ pin with a 0.01µF capacitor to AGND.
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
C
REF
A = 1.638
V
DD
V
REFADJ 25
10k
External Reference
At REF and REFADJ, the input impedance is a mini-
mum of 10kΩ for DC currents. During conversions, an
e xte rna l re fe re nc e a t REF mus t b e a b le to d e live r
400µA DC load currents, and must have an output
impedance of 10Ω or less. If the reference has higher
output impedance or is noisy, bypass it close to the
REF pin with a 4.7µF capacitor to AGND.
2.5V
Figure 9b. External Reference, Reference at REF
4.096V
4.7µF
REF 26
With an external reference voltage of less than 4.096V
at the REF pin or less than 2.5V at the REFADJ pin, the
increase in the ratio of the RMS noise to the LSB value
(FS / 4096) results in performance degradation (loss of
effective bits).
MAX196
MAX198
C
REF
A = 1.638
V
REFADJ 25
2.5V
0.01µF
P o w e r-Do w n Mo d e
To save power, you can put the converter into low-
current shutdown mode between conversions. Two
p rog ra mma b le p owe r-d own mod e s a re a va ila b le :
STBYPD and FULLPD. Select STBYPD or FULLPD by
programming PD0 and PD1 in the input control byte.
When power-down is asserted, it becomes effective
only after the end of conversion. In all power-down
modes, the interface remains active and conversion
10k
2.5V
Figure 9c. The external reference overdrives the internal refer-
ence.
______________________________________________________________________________________ 13
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
results may be read. Input overvoltage protection is
active in all power-down modes. The device returns to
normal operation on the first WR falling edge during
write operation.
than a fraction of an LSB), run a STBYPD power-down
cycle prior to starting conversions. Take into account
that the reference buffer recharges the bypass capaci-
tor at an 80mV/ms slew rate, and add 50µs for settling
time. Throughput rates of 10ksps offer typical supply
c urre nts of 470µA, us ing the re c omme nd e d 33µF
capacitor value.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at the REF pin. This is a “DC” state that
does not degrade after power-down of any duration.
Therefore, you can use any sampling rate with this
mode, without regard to start-up delays.
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts the MAX196/MAX198 down after each conversion
without requiring any start-up time on the next conversion.
However, in FULLPD mode, only the bandgap refer-
ence is active. Connect a 33µF capacitor between REF
and AGND to maintain the reference voltage between
conversions and to reduce transients when the buffer is
enabled and disabled. Throughput rates down to 1ksps
can be achieved without allotting extra acquisition time
for reference recovery prior to conversion. This allows
c onve rsion to be gin imme dia te ly a fte r powe r-down
ends. If the discharge of the REF capacitor during
FULLPD exceeds the desired limits for accuracy (less
Tra n s fe r Fu n c t io n
Output data coding for the MAX196/MAX198 is binary
in unipolar mode with 1LSB = (FS / 4096) and twos-
complement binary in bipolar mode with 1LSB = [(2 x
6/MAX198
FS ) / 4096]. Code transitions occur halfway between
| |
s uc c e s s ive -inte g e r LSB va lue s . Fig ure s 10 a nd 11
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively. For full-scale
(FS) values, refer to Table 1.
OUTPUT CODE
OUTPUT CODE
FS
4096
2 FS
4096
1 LSB =
1 LSB =
FULL-SCALE
TRANSITION
11... 111
011... 111
011... 110
11... 110
11... 101
000... 001
000... 000
111... 111
100... 010
100... 001
100... 000
00... 011
00... 010
00... 001
00... 000
-FS
0V
+FS - 1 LSB
FS
0
1
2
3
3
FS - / LSB
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
2
Figure 11. Bipolar Transfer Function
Figure 10. Unipolar Transfer Function
14 ______________________________________________________________________________________
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
6/MAX198
La yo u t , Gro u n d in g , a n d Byp a s s in g
Careful printed circuit board layout is essential for best
s ys te m p e rforma nc e . For b e s t p e rforma nc e , us e a
ground plane. To reduce crosstalk and noise injection,
ke e p a na log a nd d ig ita l s ig na ls s e p a ra te . Dig ita l
ground lines can run between digital signal lines to
minimize interference. Connect analog grounds and
DGND in a star configuration to AGND. For noise-free
operation, ensure the ground return from AGND to the
supply ground is low impedance and as short as possi-
ble. Connect the logic grounds directly to the supply
SUPPLY
GND
+5V
4.7µF
0.1µF
R* = 5Ω
**
V
DD
+5V
DGND
AGND
DGND
ground. Bypass V
with 0.1µF and 4.7µF capacitors
DD
to AGND to minimize high- and low-frequency fluctua-
tions. If the supply is excessively noisy, connect a 5Ω
DIGITAL
CIRCUITRY
MAX196
MAX198
resistor between the supply and V , as shown in
DD
Figure 12.
* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE
Figure 12. Power-Supply Grounding Connection
_________________________________________________________Fu n c t io n a l Dia g ra m
REF
REFADJ
10k
+2.5V
REFERENCE
A =
V
1.638
CH5
CH4
CH3
CH2
CH1
CH0
SIGNAL
CONDITIONING
BLOCK
&
T/H
OVERVOLTAGE
TOLERANT
MUX
CHARGE REDISTRIBUTION
12-BIT DAC
COMP
12
CLK
CLOCK
SUCCESSIVE-
APPROXIMATION
REGISTER
CS
WR
RD
CONTROL LOGIC
&
LATCHES
8
12
V
DD
MAX196
MAX198
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
INT
AGND
DGND
D0–D11
12-BIT DATA BUS
______________________________________________________________________________________ 15
Mu lt ira n g e , S in g le +5 V, 1 2 -Bit DAS
w it h 1 2 -Bit Bu s In t e rfa c e
_Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip To p o g ra p h y
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
Dice*
D11 CLK
CS
V
V
CC
DD
DGND
WR
MAX196BC/D
MAX196AENI
MAX196BENI
MAX196AEWI
MAX196BEWI
MAX196AEAI
MAX196BEAI
MAX196AMYI
MAX196BMYI
MAX198ACNI
MAX198BCNI
MAX198ACWI
MAX198BCWI
MAX198ACAI
MAX198BCAI
MAX198BC/D
MAX198AENI
MAX198BENI
MAX198AEWI
MAX198BEWI
MAX198AEAI
MAX198BEAI
MAX198AMYI
MAX198BMYI
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
D10
RD
D9
D8
INT
REF
28 Wide SO
D7
28 SSOP
28 SSOP
0. 231"
-55°C to +125°C 28 Narrow Ceramic SB**
-55°C to +125°C 28 Narrow Ceramic SB**
(5. 870mm)
REFADJ
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
6/MAX198
CH5
D6
28 Wide SO
CH4
CH3
CH2
D5
D4
28 SSOP
28 SSOP
D3
Dice*
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
D1
CH0
D2
D0 AGND
0. 144"
CH1
28 Wide SO
(3. 659mm)
28 SSOP
28 SSOP
TRANSISTOR COUNT: 2956
SUBSTRATE CONNECTED TO GND
-55°C to +125°C 28 Narrow Ceramic SB**
-55°C to +125°C 28 Narrow Ceramic SB**
* Dice are specified at T = +25°C, DC parameters only.
A
** Contact factory for availability and processing to MIL-STD-883.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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