MAX20751EKX+T [MAXIM]
Multiphase Master with PMBus Interface and Internal Buck Converter;
| 型号： | MAX20751EKX+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multiphase Master with PMBus Interface and Internal Buck Converter |
| 文件： | 总33页 (文件大小：3074K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
General Description
Benefits and Features
● Increased Power Density with Fewer External
The MAX20751 PMBus™-compliant multiphase
master IC, with extensive status and parameter monitor-
ing, is capable of driving up to four smart-slave integrated
power devices.
Components Needed
• Scalable, Multiphase Solution
• Compatibility with Coupled Inductors Enables Fast
Transient Response and Reduced C
• Integrated Internal Switching Regulator to Power
Smart Slaves
OUT
Utilizing Maxim’s smart-slave ICs, the device
provides a high-density and flexible solution that can be
tailored to a range of power loads used in commu-
nication equipment. Proprietary-coupled inductors,
recommended to reduce the effective inductor value with-
out excessive ripple current, results in improved transient
response and reduction in the number of output capaci-
tors required.
● Optimized Component Performance and Efficiency
with Reduced Design-In Time
• PMBus-Compliant Interface for Telemetry and
Power Management
• Field-Programmable Memory to Allow Storage of
Desired Configuration Parameters
• Fault Logging
The device incorporates current reporting, tempera-
ture monitoring, fault detection, and PMBus support.
Overcurrent and overtemperature faults are detected
by the individual smart slaves and faults communicated
through the master IC. The highest junction temperature
is reported, both before and after smart-slave regulation.
● Comprehensive System and IC Self-Protection
Features Promote Increased Power-Supply Reliability
• Overcurrent and Overtemperature
• Boost Voltage UVLO
• VX Short to Ground or V
Detection
DDH
• Phase-Current Steering for Thermal Balancing
The device features an integrated switching regulator
● 36-Pin (6mm x 6mm) QFN Package
that can optionally be used to supply the V
rail for the
DD
master controller and smart-slave devices to reduce the
power-rail requirements and simplify the regulator design.
Applications
● Communication, Networking, Servers, and Storage
PWM1
Smart
Slave
ISENSE1
ISENSE2
Equipment
• ASICs
• Microprocessor Chipsets
PWM2
Smart
Slave
V
OUT
TS_FAULTB
PWM3
• Memory V
DDQ
Power
Management
COntroller
PMBus
• Other High-Current Digital ICs
Ordering Information appears at end of data sheet.
PMBus is a trademark of SMIF, Inc.
MAX20751
Smart
Slave
ISENSE3
ISENSE4
PWM4
Smart
Slave
SENSE_N
SENSE_P
Figure 1. Basic Application Circuit
19-7080; Rev 2; 3/15
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Absolute Maximum Ratings
V
Supply Voltage...............................................-0.3V to +4V
SENSE_P.................................................................-0.3V to +4V
R_REF, MRAMP, R_SELx, PWMx, TS_FAULTB, ISENSEx,
DD33
VIN_UV, VR_ON and PWRGD Pins.........................-0.3V to +4V
Supply Voltage ...............................................-0.3V to +2.5V
V
A1_OUT, A2_x, A2B_OUT, A3_x...............-0.3 to V
+ 0.3V
DD
DD
PVX to PGND...........................................-0.6V to V
+ 0.6V
Junction Temperature (T )...............................................+150°C
DD33
J
PMBus Pins (PMD, PMC, ALERTB).........................-0.3V to +6V
SENSE_N.....................................................-0.3V to V +0.3V
Storage Temperature Range..............................-65°C to +150°C
Peak Reflow Temperature................................................+260°C
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Operating Ratings
V
V
Supply Voltage.....................................+2.97V to +3.63V
Supply Voltage ........................................+1.71V to +1.98V
SENSE_N.............................................................-0.1V to +0.2V
SENSE_P.............................................................-0.1V to +2.5V
DD33
DD
VIN_UV, VR_ON and PWRGD ............................-0.1V to +3.6V
Junction Temperature Range (T ).......................-40°C to +125°C
J
PMBus Pins (PMD, PMC, ALERTB) ....................-0.1V to +5.5V
Package Thermal Characteristics
TQFN
Junction-to-Case Thermal Resistance (θ )..............1.7°C/W
JC
This product is completely Halogen-free and Pb-free, employing SnAgCu solder balls. The product is RoHS compliant with an -e1 termina-
tion finish and is compatible with both SnPb and Pb-free soldering operations. The product is MSL classified at peak reflow temperatures
that meet JEDEC JSTD-020.
Electrical Characteristics
(V
= 1.71V to 1.98V, V
= 3.3V ±10%, T = +25°C, unless otherwise noted.)
DD
DD33 J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGES AND CURRENTS
Supply Voltage Range
V
If external V
supply is used
1.71
14
1.86
17
1.98
20
V
mA
V
DD
DD
Supply Current
I
PWM not switching (Note 2)
DD
3.3V Supply Voltage Range
V
2.97
3.30
3.63
DD33
No load, internal integrated
switcher disabled, PMBus idle
(Note 2)
3.3V Supply Current
I
24
130
µA
DD33
V
UVLO (UNDERVOLTAGE LOCKOUT)
DD
Supply Voltage Undervoltage-
Lockout Rising Threshold
V
(Note 2)
(Note 2)
1.62
1.60
1.66
V
V
DD_UVLO_RIS
DD_UVLO_FAL
Supply Voltage Undervoltage-
Lockout Falling Threshold
V
1.58
2.80
V
UVLO
DD33
3.3V Supply Voltage Undervoltage-
Lockout Rising Threshold
V
V
(Note 2)
(Note 2)
2.90
2.85
2.95
V
V
DD33_UV_RIS
3.3V Supply Voltage Undervoltage-
Lockout Falling Threshold
DD33_UV_FAL
Maxim Integrated
│ 2
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Electrical Characteristics (continued)
(V
= 1.71V to 1.98V, V
= 3.3V ±10%, T = +25°C, unless otherwise noted.)
DD
DD33
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIN UVLO (USING VIN_UV PIN)
VIN_UV Rising Threshold
VIN_UV
VIN_UV
(Note 2)
(Note 2)
0.380
0.328
0.390
V
V
RIS
VIN_UV Falling Threshold
0.318
125
FAL
Delay from VIN_UV UVLO to
System Shutdown
t
275
ns
dVIN_UV_UVLO
INTEGRATED INTERNAL SWITCHER
Output Valley Voltage
V
1.86
V
mA
A
OUT_IIS
Current Driving Capability
I
Tested at L = 2.2μH, t
= 1.30μs
300
OUT_IIS
ON
Switcher Peak Inductor Current
I
1.5
LPK_IIS
0.52
1.04
1.52
2.20
0.65
1.30
1.90
2.75
0.78
1.56
3.28
3.30
High-Side Switch On-Time
t
Default 1.30μs (Notes 1, 2)
µs
V
ON_IIS
V
(NOMINAL OUTPUT VOLTAGE AFTER STARTUP, WITHOUT DROOP)
NOM
Programmable through R_SEL
or PMBus, direct feedback of
Output Voltage Range
0.500
1.520
V
to SENSE_P (Notes 1, 2)
OUT
V
NOM
Resolution
(Note 2)
1V ≤ V
5
mV
%
≤ 1.52V (Note 2)
-0.5
-5
+0.5
+5
NOM
DC Accuracy
0.5V ≤ V
< 1V (Note 2)
mV
NOM
3.25
2.00
0.75
-0.50
-1.75
-3.00
-4.25
-5.50
3.75
2.50
1.25
0.00
-1.25
-2.50
-3.75
-5.00
4.25
3.00
1.75
+0.50
-0.75
-2.00
-3.25
-4.50
VID Set Point (V
Adjustment Voltage)
Fine-
Programmable with PMBus,
default is 0.00mV. (Notes 1, 2)
OUT
V
mV
OUT_FINE_ADJ
SWITCHING FREQUENCY
Nominal Switching Frequency
Range
Programmable through R_SEL or
PMBus (Note 1)
f
300
-10
800
+10
kHz
%
SW
Switching Frequency Tolerance
f
(Note 2)
SW_TOL
OUTPUT-VOLTAGE STARTUP SLEW RATES
0.5
1.25
2.5
5
Output-Voltage Slew Rate After
Initial Jump from 0V
Programmable through R_SEL or
PMBus (Note 1)
S
mV/μs
VOUT
Maxim Integrated
│ 3
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Electrical Characteristics (continued)
(V
= 1.71V to 1.98V, V
= 3.3V ±10%, T = +25°C, unless otherwise noted.).
DD
DD33
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
R_REF
Reference Voltage for R_REF
V
(Note 2)
(Note 2)
0.79
0.80
0.81
V
R_REF
AMPLIFIER A1
A1 Amplifier Closed-Loop
Differential Gain
A
2.17
7
2.19
2.23
V/V
1DM
Error-Amplifier Closed-Loop BW
Positive Sense Line Current
Negative Sense Line Current
AMPLIFIER A2
CLBW
15
90
MHz
µA
I
VSENSE_N grounded (Note 2)
VSENSE_P grounded (Note 2)
SENSE_P
I
-90
µA
SENSE_N
Amplifier Closed-Loop Gain of A2
with feedback capacitor C2 shorted
A
Set through external R (Note 1)
Gain = 2
1
4
V/V
V2
A2 Amplifier Open-Loop Gain
Closed-Loop Bandwidth
AMPLIFIER A2B
A
60
10
dB
OL2
CLBW_A2
MHz
A2B Amplifier Closed-Loop Gain
Closed-Loop Bandwidth
AMPLIFIER A3
A
1
V/V
DM
CLBW_A2B
11
MHz
A3 Amplifier Open-Loop Gain
Closed-Loop Bandwidth
MODULATOR RAMP RATE
A
60
10
dB
OL3
CLBW_A3
Gain = 2
MHz
Program through R at MRAMP pin
(Note 1)
Ramp-Rate Programming Range
M
0.4
2
V/µs
RAMP
OVERCURRENT PROTECTION (OCP)
Positive Current Limit (Sustaining),
Voltage across R
VCM, 4-phase system (Notes 1, 2)
referred to
DES
P
-0.658
0.157
-10
-0.598
0.183
-0.538
0.209
+10
V
V
OCP
OCP
Programmed Through R
DES
Voltage across R referred to
VCM, 4-phase system (Note 2)
DES
Negative Current Limit (Sustaining)
Positive Current-Limit Tolerance
N
Not including the external resistor
tolerance (1%) (Note 2)
I
%
LIM_TOL
OVERVOLTAGE PROTECTION (OVP)
Tracking OVP Threshold Voltage
(Note 2)
(Note 2)
205
199
90
217
Above V
(Rising)
NOM
V
mV
µs
_TRA_OVP
Tracking OVP Threshold Voltage
(Falling)
187
Tracking OVP Blanking Time from
the End of an IDAC Transition
t
_BL_OVP
Maxim Integrated
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Electrical Characteristics (continued)
(V
= 1.71V to 1.98V, V
= 3.3V ±10%, T = +25°C, unless otherwise noted.)
DD
DD33
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Umbrella OVP Threshold Voltage
(Rising)
(Note 2)
(Note 2)
2.52
2.59
V
V
_UMB_OVP
Umbrella OVP Threshold Voltage
(Falling)
2.38
2.45
1
V
Delay Time to Respond to OVP
t
µs
d_OVP
VR_ON (ENABLE) PIN
VR_ON
VR_ON
(Note 2)
(Note 2)
0.9
V
V
IH
IL
VR_ON
0.2
VR_ON Deglitch Filter Time
PWRGD (Note 3)
t
2
µs
FLT_VRON
PWRGD Assert Threshold (Rising)
Referenced to V
Referenced to V
(Note 2)
(Note 2)
-225
-227
-216
mV
mV
NOM
NOM
PWRGD Deassert Threshold
(Falling)
-234
V
THR_PG
PWRGD Deassert Threshold
Deglitch Filter Time
8
µs
PWRGD remains deasserted until
90μs after the end of the startup
PWRGD High-Deglitch
Filter Time
t
90
µs
V
d_PG
I
transition
DAC
Output Low Voltage
V
I
= -4mA (Note 2)
OL
0.3
PG_OL
ORTHOGONAL CURRENT REBALANCING (OCR)
0
1.8
3.5
4.4
Programmable through PMBus
(Note 1)
Gain
OCR
PMBus (PMC, PMD, ALERTB PINS)
Input High Voltage (PMC, PMD)
Input Low Voltage (PMC, PMD)
V
(Note 2)
(Note 2)
1.5
V
V
V
IH
PM
V
-0.1
+0.8
IL
Output Low Voltage (PMD,
ALERTB)
V
I
= -4mA (Note 2)
OL
0.4
V
OL
PMBus Resistor Pullup Voltage
(PMC, PMD, ALERTB)
V
1.71
-40
5.5
V
PM
PMBus Clock Frequency
f
100
400
kHz
PMC
NONVOLATILE MEMORY PROGRAMMING
Temperature Range for
Programming Data into Nonvolatile TEMP
Memory
Applies only to STORE_USER_
ALL PMBus command
+85
°C
NVM_PROG
Maxim Integrated
│ 5
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Electrical Characteristics (continued)
(V
= 1.71V to 1.98V, V
= 3.3V ±10%, T = +25°C, unless otherwise noted.).
DD
DD33
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PMBus MONITORING AND TELEMETRY
Range of Reported Output Current
as a Percentage of Positive Output
Current-Limit IPLIM
1, 2, or 3 slaves
-30
-30
+100
+88
4 slaves
%
4-phase system at 100A, 1.0V, not
Error of Reported Output Current
-6
+6
including R
tolerance (Note 2)
DES
IOUT
Resolution of Reported Output
Current
REPORT
0.5
512
1
A
µs
ms
°C
°C
°C
ms
ms
V
Update Rate of Reported Output
Current
Overcurrent Warning Response
Time Delay After Update
Range of Reported Highest Slave
Temperature
-40
-6
+127
+6
Error of Reported Highest Slave
Temperature
4-phase system at 70A, 1.0V
(Note 2)
Resolution of Reported Slave
Temperature
TEMP
1
3
1
REPORT
Update Rate of Reported Slave
Temperature
Temperature Warning or Fault-
Response Time Delay After Update
Scaled Voltage Range of Input
Voltage at VIN_UV Pin
VIN
0.317
4.625
-2
1.383
20.25
+2
SCALE
140/2048 for VIN_UV/VIN voltage
ratio, no offset added
Range of Reported Input Voltage
Error of Reported Input Voltage
V
Not including tolerance of resistor
voltage-divider (Note 2)
%
Resolution of Reported Input
Voltage
VIN
31.25
mV
ms
ms
REPORT
Update Rate of Reported Input
Voltage
3
1
Input-Voltage Warning or Fault-
Response Time Delay After Update
Maxim Integrated
│ 6
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Electrical Characteristics (continued)
(V
= 1.71V to 1.98V, V
= 3.3V ±10%, T = +25°C, unless otherwise noted.)
DD
DD33
J
PARAMETER
SYMBOL
CONDITIONS
MIN
0.500
-1
TYP
MAX
1.520
+1
UNITS
V
Range of Reported Output Voltage
1.000V ≤ V
≤ 1.520V (Note 2)
%
OUT
Error of Reported Output Voltage
0.500V ≤ V
< 1.000V (Note 2)
-10
+10
mV
OUT
Resolution of Reported Output
Voltage
5
3
1
mV
ms
ms
VOUT
REPORT
Update Rate of Reported Output
Voltage
Output Voltage Warning or Fault-
Response Time Delay After Update
Range of Reported Output
Power as a Percentage of
1, 2, or 3 slaves
4 slaves
0
0
100
88
%
(V
) x (IPLIM)
OUT
4-phase system at 100A, 1.0V, not
including R tolerance (Note 2)
Error of Reported Output Power
-7
+7
%
W
POUT
DES
REPORT
Resolution of Reported Output
Power
2
3
Update Rate of Reported Output
Power
ms
Note 1: Parameters are programmable.
Note 2: Specifications apply over the TJ = -40°C to +105°C temperature range.
Note 3: PWRGD output signal is different from the PMBus POWER_GOOD signal.
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Typical Operating Characteristics
(V = 12V, V
= 1.00V, f
= 300kHz, Four Phases, C
= 32 x 47μF Multilayer Ceramic Capacitors, L
= 100nH/Phase Two
OUT
IN
OUT
SW
OUT
Winding-Coupled Inductor for Each Pair of Phases.)
TURN-ON
WAVEFORMS - NO LOAD
OUTPUT-VOLTAGE
RIPPLE - NO LOAD
OUTPUT-VOLTAGE
RIPPLE - 120A LOAD
MAX20751 toc03
MAX20751 toc01
MAX20751 toc02
1
2
1
1
2
3
4
2
Time/div: 200μs
CONDITIONS: TRIGGER ON VR_ON, POSITIVE-GOING EDGE
1. V : 500mV/div, 20MHz BANDWIDTH
Time/div: 2µs
Time/div: 2µs
CONDITIONS: TRIGGER ON PWM2, POSITIVE-GOING EDGE
1. V : 5mV/div, 20MHz BANDWIDTH
CONDITIONS: TRIGGER ON PWM2, POSITIVE-GOING EDGE
1. V : 5mV/div, 20MHz BANDWIDTH
OUT
OUT
OUT
2. PWRGD: 2.00V/div, 20MHz BANDWIDTH
3. PWM2: 2.00V/div, 20MHz BANDWIDTH
4. VR_ON: 2.00V/div, 20MHz BANDWIDTH
2. PWM2: 1.00V/div, 20MHz BANDWIDTH
2. PWM2: 1.00V/div, 20MHz BANDWIDTH
TURN-OFF
OUTPUT-VOLTAGE LOAD
OUTPUT VOLTAGE IN HICCUP-MODE
WAVEFORMS - NO LOAD
TRANSIENT RESPONSE (60A-90A)
OVERCURRENT PROTECTION
MAX20751 toc04
MAX20751 toc05
MAX20751 toc06
1
2
1
2
3
3
1
4
Time/div: 20ms
Time/div: 20μs
Time/div: 10ms
CONDITIONS: TRIGGER ON VR_ON, NEGATIVE-GOING EDGE
1. V : 500mV/div, 20MHz BANDWIDTH
CONDITIONS: TRIGGER ON V
, POSITIVE-GOING EDGE
CONDITIONS: TRIGGER ON V , NEGATIVE-GOING EDGE
OUT
OUT
OUT
1. V
: 50mV/div, 20MHz BANDWIDTH
OUT
1. V : 500mV/div, 20MHz BANDWIDTH
OUT
2. PWRGD: 2.00V/div, 20MHz BANDWIDTH
3. PWM2: 1.00V/div, 20MHz BANDWIDTH
4. VR_ON: 2.00V/div, 20MHz BANDWIDTH
2. I
: 133.3A/div, 20MHz BANDWIDTH
OUT
3. PWM2: 2.00V/div, 20MHz BANDWIDTH
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Pin Configuration
(Top View)
36 35 34 33 32 31 30 29 28
V
R_REF
MRAMP
R_SEL0
R_SEL1
R_SEL2
27
26
25
24
23
1
2
3
4
5
DD33
PVX
PGND
PWRGD
ISENSE4
GND
(Underside Pin)
22 ISENSE3
R_SEL3 6
21
20
19
7
8
9
ISENSE2
GND
ISENSE1
V
DD
TS_FAULTB
VR_ON
10 11 12 13 14 15 16 17 18
Pin Description
PIN
NAME
FUNCTION
Connect the 20kΩ reference resistor R_REF from this pin to ground. The resistor should have
±0.5% tolerance or lower, with a temperature coefficient of ±25ppm/°C or lower.
1
R_REF
MRAMP
2
Connect this node to ground through a resistor to program the PWM regulator modulator ramp rate.
Programming Input. Connect these nodes to ground through a configuration resistor with ±1%
tolerance or lower and a temperature coefficient of ±100ppm/°C or lower.
3–6
R_SEL0–R_SEL3
GND
7
8
9
Ground
V
V
Supply Voltage Connection
DD
DD
VR_ON
Input for Regulator to Enable Regulation
No Connection. This node should not be connected to any other devices or components. It is
connected internally.
10
N.C.
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Pin Description (continued)
PIN
11
NAME
PMD
FUNCTION
PMBus Data I/O
PMBus Clock
12
PMC
13
ALERTB
Open-Drain, Active-Low PMBus Alert Output
Scaled Version of Slave V Voltage. A resistor-divider on this input is used to program the
DDH
14
VIN_UV
input undervoltage lockout (UVLO) threshold for the slave V
supply.
DDH
Pulse-Width-Modulation Phase-Control Outputs for the Regulator. Connect these nodes to
the input pins of the slave devices selected for the application. Connect pins for phases not
populated to ground. Do not leave any PWM pin unconnected.
15–18
PWM4–PWM1
Temperature Sensor and Slave Fault Flag. Connect this node to the TSENSE outputs of the
slave ICs. This node is an analog representation of the junction temperature for the hottest slave
of the regulator during normal operation and is also used by the slave devices to report faults (a
fault condition is asserted low).
19
TS_FAULTB
Phase Current-Sense Inputs. Connect these nodes to the ISENSE outputs of the slave devices.
20–23
24
ISENSE1–ISENSE4 Ground the pin if not in use (the corresponding RPH resistor should not be connected to ISENSE
when ISENSE is connected to ground) to minimize noise into the device.
Power-Good Output for the Regulator. This node indicates whether the output voltage is
PWRGD
within regulation. This open-drain output should be pulled high externally with a resistor of
approximately 10kΩ.
25
26
27
PGND
PVX
Power Ground. Connect this node to power ground.
Internal Switcher Switching Node. This node should be connected to an inductor for correct operation.
3.3V Supply for the IC and Internal Switcher
V
DD33
Phase-Shedding Feature (disabled in the MAX20751). This pin must be connected to A3_OUT_
NORM with a short trace or a 0Ω resistor.
28
A3_OUT_PS
Phase Current-Loop Amplifier Output for the Regulator. Must be connected to A3_OUT_PS with
a short trace or a 0Ω resistor.
29
30
31
A3_OUT_NORM
A3_IN
Phase Current-Loop Amplifier Negative Input
This node has the same value as A2_OUT during normal operation, but has programmable
positive and negative voltage clamps that limit the maximum positive and negative output current.
A2B_OUT
32
33
34
35
36
A2_OUT
A2_IN
Voltage-Loop Amplifier Output
Voltage-Loop Amplifier Negative Input
Differential Error-Amplifier Output
Negative Remote-Voltage Sense
Positive Remote-Voltage Sense
A1_OUT
SENSE_N
SENSE_P
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Block Diagram
3.3V
Driver
o - n
e a r l y t u r n
Umb_OVP
O T P I n t e r f a c e
S F R I n t e r f a c e
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
95%
90%
85%
80%
75%
70%
V
= 0.8V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Figure 2. System Efficiency: 4-Phase,100nH/Phase-Coupled Inductors, 350kHz Switching Frequency (V = 12V)
IN
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Control Architecture
Theory of Operation
Figure 3 shows the internal amplifier stages of the master
and how phase-current information is used to generate
the phase-control signals, as well as provide accurate
current reporting. The master IC contains multiple ampli-
fier stages and one duty-cycle modulator for each phase,
to allow independent control of the high-side MOSFET
on-time according to each individual phase current.
TheMAX20751masterICprovidesahigh-frequency,highly
integrated compact solution for high-performance, low-
voltage power conversion (with PMBus interface). The
basic system architecture consists of a single-rail master
controller and up to four smart-slave devices. These ICs,
along with a small number of external components, pro-
vide a complete solution for single-rail voltage regulation.
The first amplifier stage (A1) in Figure 3 is a differential
amplifier, the output being the error between the DAC
reference voltage and the differential voltage-sense lines
multiplied by a factor of 2.19. This stage enables true
remote voltage sensing, and its differential structure pro-
vides high common-mode rejection ratio to protect from
any noise present at the processor ground. The second
amplifier stage (A2) provides voltage-loop compensation,
with its DC gain used to set the load line of the voltage
regulator. The A2 amplifier is followed by a clamping
circuit and buffer amplifier (A2B) to provide overcur-
rent protection (OCP). The output of amplifier A2B is
The master IC contains a pulse-width-modulation (PWM)
control circuit, PMBus interface, and multiphase control
circuits for low-loss operation over a wide range of load
currents. The applicable smart-slave ICs utilize the full
benefits of a synchronous rectification topology. Both the
top and bottom power FETs are integrated on-chip, with
no external power components (MOSFETs or Schottky
diodes) required. Each smart-slave device contains
temperature and current monitoring. PWM signals are
generated in the master IC and sent to the slaves.
Current-sense and temperature feedback signals are
generated in the slaves and sent to the master.
converted to a current through the resistor (R
) and rep-
DES
The smart-slave ICs have integrated lossless current-
sense technology. This current-sense technology pro-
vides accurate current information that is not affect-
ed by temperature, process variation, or tolerances of
passive elements such as the output inductor, resistors
and capacitors, and NTCs used in other systems to
extract current information. With this approach, a current-
sense signal is fed back to the master as a current instead
of a voltage, as is the case with DCR and other forms of
current sensing. This allows very robust system
feedback of current, with better noise immunity than
other methods. The current information can be used
to control the load line precisely and in the calcula-
tion of real output-power measurements. Highly precise
current information removes the challenges of meeting
load-line specifications, especially at light load, an area
known to challenge DCR current sensing due to the low
signal levels and tolerances involved.
resents the desired total system current (I
the target for the current loop. The third amplifier (A3) acts
as a current-error amplifier, as it receives the current com-
), which sets
DES
mand (through R
) and each individual sensed current
DES
from the smart-slave ICs (through resistors R
, R
,
PH1 PH2
and R
, as shown in Figure 3. This stage has an inte-
PH3
grator connection. The very large DC gain of the A3 stage
guarantees that the total load current equals the current
command (I
) in steady state. As a result, the load line
DES
of the voltage regulator is set by the gain of the voltage-
loop amplifier (A2). Zero load line can be achieved by
configuring the amplifier as an integrator by placing
capacitor C2 in series with R2, as shown in Figure 3.
The system also offers programmable modulator ramp-
rate stability and noise immunity, set by connecting a
resistor between the MRAMP pin and ground. This ramp
determines the duty-cycle modulator gain and is used to
tune the current-loop compensation.
Loop compensation is implemented by adding series or par-
allel RC networks across the voltage-loop and current-loop
amplifiers (A2 and A3), respectively. For the voltage loop,
lead compensation can be added by using a series RC net-
work across the R1 resistor, as shown in Figure 3 (RLD_A2
and CLD_A2). Lag compensation can be added by adding
a series RC network across the R2-C2 network resistor.
The output voltage, output-voltage turn-on slew rate,
PMBus address, and PMBus output-current gain are
hardware programmable using configuration resistors,
as discussed in the Configuration section.
An internal integrated switching regulator allows
creation of the V
supply from the V
supply, with the
DD
DD33
addition of an LC filter.
Compensation for the current loop is achieved by
placing a series RC network across the current-loop
amplifier feedback (R -C , in Figure 3). This network
INT INT
provides extremely high gain at low frequency, which
guarantees tight current regulation (i.e., the output current
is very close to the current command).
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Equation 2:
Integrated 1.8V Switching Regulator
The MAX20751 master IC features an integrated switch-
ing regulator that provides the bias current to the master
controller and to the smart-slave ICs (both core analog/
digital circuits and gate drive).
V
− V
DD33
2L
DD
I
=
t
ON
MAX_AVE
PVX
If load current is higher than IMAX_AVE, the V
voltage
DD
This regulator enables efficient power conversion from
the 3.3V supply at both light load and heavy load using
a pulse-frequency-modulation (PFM) mode of operation.
The external LC filter for this regulator is extremely small
and inexpensive, as it only requires a chip inductor and
small case-size ceramic capacitors. The control scheme
adopted here is voltage mode constant on-time with the
inductor always operated in the discontinuous-conduction
mode (DCM) of operation, providing an inherent current-
limiting protection as well as soft-start capability. Details
of the integrated regulator can be seen in the Block
Diagram. The PGND pin should connect to the GND pins
through a single wide trace or via.
drops. If V
device resets.
drops below the falling UVLO threshold, the
DD
The on-time (t
PMBus. Table 1 shows the programmable on-times.
)
is programmable using the
ON
Before V has risen above the rising undervoltage-
DD
lockout (UVLO) threshold, the lowest on-time of 0.64μs
is used. When V has risen above both the rising
and falling UVLO thresholds, the switcher uses the
programmed on-time. The default value is 1.30μs.
DD
The switcher becomes active when V
risen above its rising UVLO threshold.
voltage has
DD33
The inductor (L
) must be able to support the
PVX
maximum peak current without saturating significantly,
since the inductor impedance is what provides the current
limit. The maximum peak current occurs at startup from
zero output voltage.
In order to achieve simple average-output current-limiting
protection, this converter is forced to stay in DCM mode
by only allowing high-side turn-on when the current
reaches zero. The peak current in the inductor is given in
Equation 1.
The output-voltage peak-to-peak ripple depends on the
capacitor (C
load and is given in Equation 3.
). The worst-case ripple occurs at light
VDD
Equation 1:
V
− V
DD
DD33
I
=
t
ON
Equation 3:
P
L
PVX
I
V
DD33
P
∆V
=
×
t
ON
P−P
where:
is the switcher inductor
2C
V
DD
VDD
L
PVX
where:
∆V
The maximum average current is given by Equation 2.
should be 30mV or less
P-P
Table 1. On-Time Selection Table
ON-TIME (µs)
0.64
1.30 (Default)
1.91
2.76
Slave1 Slave2 Slave3
SENSE SENSE SENSE
I
I
I
Phase Control
(One Phase Shown for Clarity)
ISNS3
RFILT3
VDD
IDAC
OCP CLAMP and Buffer Amplifier
OCP CLAMP
CINT
RINT
ISNS2
ISNS1
OCR
R2N
VCM
VCM
A2B_OUT
A2
R1N
R1P
A2B
RDES
A1_OUT
SENSE_N
SENSE_P
A2_IN
A3_IN
VCM
ph_clk
S
R
Q
A3
Vx
A1
R1
R2
C2
IDES
CRR
IRR
A3_OUT_NORM
A2_OUT
RLD_A2 CLD_A2
R2P
Figure 3. Control Architecture
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Startup and Shutdown Operation
When VDD and VDD33 are above their rising UVLO
thresholds, the device is enabled and goes through an
initialization and phase-detection procedure. Configuration
resistors are read and external resistors checked for valid
values. Any faults will prevent the output voltage from
turning on.
PVX
VDD
VDD33
LPVX
CDD
CDD33
The PMBus communication and telemetry are then
enabled. The VIN_UV voltage must be above its rising
UVLO threshold for the output voltage to turn on.
PGND
If the output voltage is programmed to below 0.25V
through the PMBus VOUT_COMMAND, the output is
disabled. Programming the output voltage to any other
allowable voltage using the PMBus VOUT_COMMAND
allows the output voltage to turn on.
Figure 4. Integrated Switcher Circuit
The control method regulates the valley voltage. The
peak voltage is the valley voltage plus the peak-to-peak
ripple voltage.
Depending on how the voltage-regulation enable is
configured, a VR_en signal from VR_ON and/or the
PMBus OPERATION command may also be required for
the output voltage to turn on. The default configuration for
the VR_en signal is the VR_ON signal at the high logic
level, with no PMBus command needed.
The current from the V
supply occurs in pulses of
DD33
charge given by Equation 4.
Equation 4:
I
P
Q
=
t
ON
VDD33
2
When the VIN_UV voltage is above its rising UVLO
threshold and the proper VR_en signal, if required,
has occurred, the output voltage turns on after the
PMBus programmable TON_DELAY time. The default
TON_DELAY time is 0ms.
where:
I is the peak current
P
Capacitor C
at the V
pin should be chosen to
DD33
DD33
supply the peak current and charge without too much
voltage change. A ceramic capacitor of at least 10μF is
recommended.
After the output voltage has reached its nominal value,
the PWRGD signal is asserted.
The startup sequence caused by VR_ON going high is
shown in Figure 5.
To estimate the V
current using the integrat-
DD33
ed switching regulator, assume a minimum efficien-
cy of 80% for the integrated switching regulator. For
example, if the maximum total master and slave IC
When shutdown occurs, the master IC causes the VX
nodes of the slaves to stop switching, which then causes
the output voltage to turn off. The PWRGD signal is deas-
serted and is actively pulled low.
current from V
is 175mA, V
= 1.9V, and
DD
DD
V
= 3.3V, then the V
current for the
DD33
DD33
Depending on how the voltage-regulation enable is
configured, the output voltage can be turned off using the
VR_ensignalfromVR_ONand/orthePMBusOPERATION
command. Depending on the PMBus configuration, the
output turns off immediately or with sequencing. When
the output turns off with sequencing, there is a delay time
determined by the PMBus programmable TOFF_DELAY
integrated switching regulator is (175mA x 1.9V)/(3.3V x
0.80) = 126mA.
To estimate the total V
current, also include
DD33
the PMBus resistor pulldown current if operated
from V . For example, if 2.15kΩ pulldown resis-
DD33
tors are used from the PMC, PMD, and ALERTB pins
to V , then the maximum PMBus current is 3 x
DD33
command and then V
ramps down with a turn-off slew
OUT
3.3V/2.15kΩ = 4.6mA. Therefore, the total V
cur-
DD33
rate that is the same as the turn-on slew rate for turn-on
slew rates of 1.25mV/μs, 2.5mV/μs, and 5mv/μs. For turn-
on slew rate 0.5mV/μs, if sequencing is used, the delay
time is followed by an immediate turn-off (no slew rate-
rent for the integrated switching regulator and PMBus is,
approximately, 131mA.
The integrated switching regulator can be disabled by
removing LPVX and connecting a 10Ω resistor from PVX
controlled V
ramp-down). The default TOFF_DELAY
OUT
to V
. An external supply is then applied to V
.
time is 0ms. Note that when V
ramps down, energy
DD33
DD
OUT
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
VDD
TA: Initialization time needed before startup
can begin. Maximum 6ms.
TA
VIN_UV
VDD33
VR_en
Delay from last ACK of PMBus
OPERATION command to enable
VOUT to VR_en: 75µs.
Delay from VR_ON to
VR_en: Typical 2µs.
VOUT
TC: Time from VR_en signal (from VR_ON or
PMBus) to VOUT startup with TON_DELAY.
TC
PWRGD
TF
VOUT TURN-ON SLEW RATE
TYPICAL TC
TF: Time from VOUT reaching VNOM to
PWRGD assertion. Typical 90µs.
1.25mV/µs, 2.5mV/µs, or 5mV/µs
200µs
4ms
0.5mV/µs
Note: For the 0.5mV/µs setting, TC:will increase if there is a nonzero prebias
voltage on VOUT. Also, the TON_MAX_FAULT_LIMIT and
TON_MAX_FAULT_RESPONSE commands do not work for the 0.5mV/µs setting.
Figure 5. Startup Sequence
may be delivered from V
should be sized to absorb this energy to prevent a large
to V . The V capacitors
The output voltage can be turned off by the VIN_UV
voltage going below the VIN_UV falling UVLO threshold.
This is logged as a hardware fault.
OUT
IN
IN
increase in the V voltage.
IN
The output voltage can be turned off by program-
ming the output voltage below 0.25V using the PMBus
VOUT_COMMAND. The turn-off in this case is also
determined by the PMBus configuration.
The VIN_UV UVLO thresholds should be higher than
the corresponding smart-slave IC’s V
UVLO thresh-
DDH
olds to prevent a slave fault from occurring, which could
potentially prevent the output voltage from turning back
on. If this occurs, the system may need to be reset by
If the V
or V
supplies go below their falling UVLO
DD
DD33
bringing the V
or V
supplies below their falling
DD
DD33
thresholds, the output voltage is turned off and the system
is reset.
UVLO thresholds.
The shutdown sequence caused by VR_ON going low is
shown in Figure 6.
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Orthogonal Current Rebalancing (OCR)
Phase-current imbalance can occur due to high-
frequency loading transients. The purpose of the OCR
circuit is to reduce phase-current imbalance.
VDD
This is accomplished by modifying the output of the A3
amplifier for each individual phase (k). Instead of the A3
amplifier output voltage being fed directly to the PWM
VDD33
comparator of a phase, a control voltage (V ) is used.
Ck
VIN_UV
VR_en
The equation for V is given in Equation 5.
Ck
Equation 5:
Delay from last ACK of
PMBus OPERATION
command to disable
Delay from VR_ON to
VR_EN: Typical 2µs.
N
1
V
OUT
to VR_EN:10µs.
V
= V
− G
V
−
V
∑
Ck
O3
OCR RPHk
RPHi
N
i=1
where:
V
= Voltage on resistor RPHk (a voltage proportional
RPHk
to the current in phase k)
VOUT
PWMi
V
= A3_OUT_NORM voltage
O3
N = Total number of phases
= Gain of the OCR circuit
G
OCR
V
= Voltage fed to the phase k PWM comparator
Ck
TY: Time from VR_en signal (from VR_ON or
PMBus) to V shutdown with
TOFF_DELAY=0ms. Typical 2µs for immediate
shutdown. For 1.25, 2.5, and 5mV/µs slew rate:
Typical 200us for sequenced shutdown.
T
Y
instead of the A3 amplifier output voltage
OUT
The difference between the current of a phase k from the
average current (with some gain G
PWRGD
) is subtracted
OCR
T
from V
to determine the control voltage (V ). If the
Z
O3
Ck
TZ: Time from VR_EN to PWRGD LO.W
Maximum 9µs.
current in any phase is greater than the average of all the
phases, then the corresponding V voltage will be less
Ck
Figure 6. Shutdown Sequence
than V
and the subsequent PWM pulse for that phase
O3
shorter, thus preventing further phase-current imbalance.
Droop and Load-Line Regulation
The default gain (G ) is 1.8.
OCR
If the A2 amplifier series R2-C2 network is replaced by
resistor R2 only, the MAX20751 provides accurate output
load line over the entire range of output currents. The load
Input Voltage Undervoltage Lockout (UVLO)
Using the VIN_UV Pin
The VIN_UV pin on the master IC is connected to
the middle point of a voltage-divider from the slave
line is set by the combination of the R1, R2, and R
resistors.
DES
V
(power input rail) to ground. This pin provides an
DDH
Switching Frequency and Output-Voltage
Turn-On Slew Rate
externally programmable input supply UVLO and sensing
for the PMBus V telemetry.
IN
The switching frequency and output voltage turn-on slew
rate are programmable using configuration resistors. See
the Configuration section. They are also programmable
using the PMBus.
The UVLO function is provided by comparing the VIN_UV
voltage to internal references with a comparator. When
the V
voltage exceeds the rising threshold, the
IN_UVLO
system is allowed to operate and the falling reference volt-
age is then used as a disable point for built-in hysteresis.
See the Electrical Characteristics table for more details.
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Figure 7 shows the VIN_UV circuit. Resistors R and
For example, for 2-phase operation, only phases 2 and 1
are used; therefore, pins PWM4 and PWM3 should each
be connected to GND with 0Ω resistors.
IN
R
form a voltage-divider that scales the V voltage
GND
IN
to the VIN_UV pin. The scale factor (VIN_RATIO) is given
by Equation 6. VIN_RATIO is programmable using the
PMBus. The default value is (140/2048) = 0.06836.
For 3-phase operation, PWM4 should be connected
to GND with a 0Ω resistor. For single-phase operation
PWM4, PWM3, and PWM1 should each be connected to
GND with 0Ω resistors.
Equation 6:
R
GND
+ R
IN
VIN_RATIO =
If the wrong PWMk pins are connected to GND with 0Ω
resistors, a configuration fault occurs in the fault-checking
R
GND
procedure (occurring prior to V
is halted.
startup) and operation
R
||R
should be approximately 2kΩ with
= 100pF. It is suggested to use 1% tol-
OUT
GND IN
capacitor C
IN_UV
erance resistors with the values R
= 29.4kΩ. The value for VIN_RATIO should be less than
or equal to 140/2048.
= 2.15kΩ and R
GND
IN
Protection And Monitoring
The master IC includes multiple protection circuits to
protect the regulator and load, and to monitor the output
voltage, as described in the following sections.
Phase Population Order
Depending on the total number of phases in the system,
specific phase positions must be populated, while the
others must be deactivated by connecting a 0Ω resistor
between the MAX20751’s phase-control pins (PWMk) of
the inactive phases and ground (Table 2).
Fault Detection when V
Initially Applied
and V
are
DD
DD33
When V
and V
are initially applied and at their
DD
DD33
proper levels, the master IC checks the following resistor
valuesandconnectionsandifdetectedasbeingoutsidethe
correct range or open, an error is flagged and the
regulator will not start regulation:
The phase number is defined by the PWMx pin name
(e.g., phase 2 is driven by PWM2).
● R
● R
MRAMP
REF
V
IN
● SENSE_P Open
R
IN
PWRGD (Power-Good) Pin
V
IN_UV
The PWRGD output (different from the PMBus POWER_
GOOD signal) is an active-high, open-drain output used
to show that the output is settled at its commanded
voltage. The output goes high after a fixed delay, after
the end of the output-voltage startup transition, assuming
the output voltage is above the PWRGD threshold. It is
deasserted when any of the following occurs:
R
GND
C
IN_UV
●
The output voltage drops below the threshold,
relative to the nominal voltage, for any reason.
Figure 7. VIN_UV Pin Voltage-Divider Circuit
●
●
An OVP fault is detected.
Table 2. Phase Population Positions
An OCP fault is detected when the mode is set to
hiccup mode and the regulator shuts down the output
voltage during the shutdown part of the hiccup cycle.
In constant current-limit mode, the PWRGD signal is
based on the PWRGD voltage threshold only.
NUMBER OF
POSITIONS TO BE POPULATED
POPULATED PHASES
(BY FIRING SEQUENCE)
1
2
3
4
2
2, 1
2, 1, 3
2, 4, 1, 3
●
The output is disabled.
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
The OCP is based on the instantaneous voltage over
RDES, and a small ripple voltage reflecting the out-
put-voltage ripple may be present. If the instantaneous
commanded current (output of amplifier A2) reaches
the inception voltage, the commanded current is imme-
diately clamped to the sustaining value. If the com-
manded current drops below the sustaining value, it must
once again reach the inception point before clamping
commences.
Overcurrent Protection (OCP)
System OCP is based on a fixed voltage threshold for the
voltage across the R
resistor. The overcurrent thresh-
DES
old is therefore set by selecting an appropriate value of
for the design. The voltage threshold is scaled
R
DES
internally, depending on the number of active phases (i.e.,
the voltage threshold is a fixed per-phase value).
The OCP trips when the peak voltage over RDES reaches
the inception value and remains tripped down to the
nominal/sustaining value (i.e., the values shown are the
sustaining currents and not the inception point, which is
5% higher). Negative (sinking) OCP is automatically set to
30% of the positive value.
An overcurrent fault is logged in the fault log if clamp-
ing continues for 5ms, to ensure that only periods of
continuous overloads are recorded as faults.
Table 3. Master Faults
MAX20751
MAX20751 OUTPUT
SYSTEM
SYSTEM
LOGGED IN
PROTECTION
SIGNAL(S) SHOWING FAULT
SHUTDOWN
LATCHED OFF?
FAULT LOG?
Resistor Out-of-Range
Detected at Startup
System
does not start
PWRGD low
Yes
No
Yes
PWRGD low (if output
drops below threshold)
Yes
(after 5ms)
OCP: Hiccup or CCM
No
Fixed (Umbrella) or
Tracking OVP
PWRGD low
Yes
Yes
Yes
PWRGD low (if output
drops below threshold)
VIN_UV UVLO
Yes
No
No
No
Yes
No
No
Output Undervoltage
PWRGD low
PWRGD low
No
V
UVLO
Yes
DD
(system in reset)
No
V
UVLO
PWRGD low
Yes
DD33
(system in reset)
No
Table 4. Effects of Slave Faults
MAX20751 OUTPUT SIGNAL
SYSTEM
SHUTDOWN
SYSTEM
LATCHED OFF*
LOGGED IN
FAULT LOG
SLAVE FAULT
SHOWING FAULT
Slave Cycle-by-Cycle OCP
(Sinking or Sourcing Current)
None
No
No
Yes
Yes
Slave Sourcing OCP
Current Shutdown
Yes
PWRGD low
PWRGD low
Yes
Yes
(through slave)
Slave OTP Shutdown (Sent to
Master through Slave TS_FAULTB
Low)
Yes
Yes
(through slave)
Slave Boost UVLO (Undervoltage
Lockout on Boost Supply)
PWRGD low
PWRGD low
Yes
Yes
No
Yes
Yes
Slave VX Short-to-Ground
Yes (through slave)
or V
DDH
*Note: “Yes (through slave)” refers to the fact that the slave latches in this condition and therefore the system latches. Once the
slave fault is cleared by cycling its power, the system can restart. This table shows the effect on the system.
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Three modes of operation are provided for positive
(sourcing) OCP: shutdown, constant current, and
hiccup (default); negative OCP is always constant current.
The mode can be changed using PMBus commands. If
hiccup OCP mode is selected, when the OCP is exceed-
ed, the system will deliver the maximum programmed
sustaining current for 5ms before shutting down
and waiting 45ms before restarting. This cycling
continues until the commanded current falls below
the programmed value. Should constant-current mode
be selected, the system tries to regulate at the OCP
sustaining current until the commanded current falls
below the sustaining value. The upper threshold of
current delivery is the OCP inception point and, once
this level is reached, the system folds back to the
sustaining level (the programmed value) to deliver
constant current indefinitely. The shutdown mode is similar
to the constant-current mode but shuts down VOUT after
5ms. The VOUT voltage can be enabled again by using the
VR_ON signal and/or the OPERATION PMBus command.
recorded, PWRGD is deasserted, and the system stops
regulating. OVP faults can only be cleared by toggling the
V
or V
supply rail.
DD
DD33
Undervoltage Lockout
The master IC includes three UVLO circuits, V
rail,
DD
V
rail and V (i.e., V ). V is monitored through
DDH IN IN
DD33
an external resistor-divider to bring the voltage down to
within the operating range of the VIN_UV pin. If a V
IN
UVLO is detected, the system stops regulating and indi-
cates an input-voltage fault. Once the input voltage rises
above the rising threshold, the IC reinitiates and follows
the same startup procedure as if enabled by VR_ON.
Configuration
Determining the Optimum Number of Phases,
I
, and Overcurrent Protection
OUTMAX
The typical starting point for a voltage-regulator design is
to choose a value of maximum output current (I ).
OUTMAX
is determined by the MAX20751
The value of I
OUTMAX
system overcurrent-protection (OCP) setting and is set to
85% of this setting. Therefore, a target minimum system
Overvoltage Protection (OVP)
Two separate OVP circuits are included, one based on
the programmed nominal output voltage, the other on an
“umbrella” fixed value. If either is tripped, an OVP fault is
OCP rating can easily be determined based on I
.
OUTMAX
Once this value is known, the area available, smart-slave
part numbers to be used, and the desired performance
Table 5. Selection of R
for Overcurrent Limit and Maximum
DES
Output Current I
= 0.85 I
OCP
OUTMAX
1-PHASE OCP (A)
2-PHASE OCP (A)
3-PHASE OCP (A)
4-PHASE OCP (A)
100
R
(Ω)
DES
25
27.3
29.7
32
50
75
604
54.7
59.3
64
82
109.3
118.6
549
511
464
432
412
383
365
340
324
309
294
280
274
261
249
89
96
128
34.3
36.7
39
68.6
73.3
78
103
137.3
146.6
155.9
165.2
174.6
183.9
193.2
202.5
211.8
110
116.9
123.9
130.9
137.9
144.9
151.9
158.9
165.9
172.9
179.9
41.3
43.6
46
82.6
87.3
91.9
96.6
101.3
105.9
110.6
115.2
119.9
48.3
50.6
53
55.3
57.6
60
221.2
230.5
239.8
Maxim Integrated
│ 20
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
versus cost should all be considered, with the number of
phases and smart-slave devices determined. Efficiency
curves and ratings shown on the respective smart-slave
data sheets can be used for this purpose. If any phases
aren’t used, their corresponding PWMx pins should be
connected to GND with 0Ω resistors, as discussed in the
Phase Population Order section.
Selecting R
DES
With the number of phases and part numbers
known, R should be selected to give the correct
DES
overcurrent-protection (OCP) value. The OCP value is
set by R , in that the master IC uses a fixed value
DES
of 150mV per phase. Since R
is also used by
DES
Table 6. Using R_SEL3 to Set the V
Slew Rate and Switching Frequency
OUT
V
SLEW RATE (V/ms)
f
(kHz)
R_SEL3 (Ω)
OUT
SW
300
0
350
400
450
500
600
700
800
300
350
400
450
500
600
700
800
300
350
400
450
500
600
700
800
300
350
400
450
500
600
700
800
17.8
33.2
48.7
64.9
80.6
95.3
115
133
154
178
200
226
249
274
301
332
365
402
432
464
499
536
576
619
665
715
768
825
887
953
1020
1.25
2.5
5
0.5
Maxim Integrated
│ 21
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
the PMBus telemetry circuitry to measure the output
For example, to choose an output-voltage slew rate of
0.5V/ms and a switching frequency of 350kHz, R_SEL3
= 665Ω.
current (I
), the value of R
must be selected from
OUT
DES
Table 5 of standard 1% resistors.
For example, if an I of 170A is required, I
must be a minimum of 170/0.85 = 200A. If a 4-phase
design has been selected, looking in the 4-Phase OCP
OUTMAX
OCP
Using Configuration Resistors to Program
the Output Voltage, PMBus Address Lowest
3 Bits, and I
Being Used
Telemetry for the R
Value
OUT
DES
column, we see the next highest value for I
is 202.5A
OCP
and requires the use of R
with a value of 294Ω, which
DES
Table 7 shows the parameter values and corresponding
configuration resistor values used to program the output
voltage, PMBus address lowest 3 bits (PMAD[3:1]), and
gives a nominal reported I
of 0.85 x 202.5 = 172A
OUTMAX
(I
is rounded to an integer value). Care should
OUTMAX
be taken with tolerance and rounding to ensure that the
required I is met.
PMBus I
telemetry circuitry with the R
value used
OUT
DES
OUTMAX
in the overcurrent-limit circuit.
Using Configuration Resistors to Program
the Output-Voltage Slew Rate and Switching
Frequency
R_SEL2 and R_SEL1 are the configuration resistors used
to set the output voltage. The output voltage is the sum of
the two voltages chosen by R_SEL2 and R_SEL1.
R_SEL3 is used to set the output-voltage slew rate and
switching frequency. Table 6 shows the output-voltage
slew rates, switching frequencies, and corresponding
values for R_SEL3.
R_SEL1 and R_SEL0 are the configuration resistors used
to set the lowest 3 bits (PMAD[3:1]) of the entire PMBus
address (PMAD[7:1]). The upper 4 bits (PMAD[7:4]) are
constant at the value 1110b.
R_SEL3 has 32 possible values, with each value
corresponding to a distinct pairing of slew rate and
switching frequency.
R_SEL0 is the configuration resistor used to program
the PMBus I
telemetry circuitry with the R
value
OUT
DES
being used in the overcurrent-limit circuit.
Table 7. Using R_SEL2, R_SEL1, and R_SEL0 to Set the Output Voltage, Set the Lowest
PMBus Address Bits, and Program the I Telemetry with the R Value Being Used
OUT
DES
V
(V)
R_SEL2 PMAD
V
(V)
R_SEL1
(Ω)
R
R_SEL0
(Ω)
V
(V)
R_SEL2 PMAD
V
OUT
(V)
R_SEL1
R R_SEL0
DES
OUT
OUT
DES
OUT
PMAD3
PMAD3
(Ω)
[2:1]
(Ω)
604
549
511
464
432
412
383
365
340
324
309
294
280
274
261
249
(Ω)
332
365
402
432
464
499
536
576
619
665
715
768
825
887
953
[2:1]
(Ω)
332
365
402
432
464
499
536
576
619
665
715
768
825
887
953
(Ω)
604
549
511
464
432
412
383
365
340
324
309
294
280
274
261
249
(Ω)
0
-0.005
0.000
0.005
0.010
0.015
0.020
0.025
0.030
-0.005
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0
0
0.890
0.930
0.970
1.010
1.050
1.090
1.130
1.170
1.210
1.250
1.290
1.330
1.370
1.410
1.450
-0.005
0.000
0.005
0.010
0.015
0.020
0.025
0.030
-0.005
0.000
0.005
0.010
0.015
0.020
0.025
332
365
402
432
464
499
536
576
619
665
715
768
825
887
953
1020
17.8
33.2
48.7
64.9
80.6
95.3
115
133
154
178
200
226
249
274
301
17.8
33.2
48.7
64.9
80.6
95.3
115
133
154
178
200
226
249
274
301
17.8
33.2
48.7
64.9
80.6
95.3
115
133
154
178
200
226
249
274
301
00
10
0.490
0.530
0.570
0.610
0.650
0.690
0.730
0.770
0.810
0.850
0
1
01
11
1.490 1020
0.030 1020
Note 1: Selecting V
below 0.25V disables the output voltage.
OUT
Note 2: R
defines I
, I
, and the I
PMBus telemetry.
DES
OCP OUTMAX OUT
Maxim Integrated
│ 22
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Each R_SELx resistor has 32 possible values, with
each value corresponding to one or more programmable
parameters.
Output Capacitance Calculation
One criterion for determining the value of the output
capacitance (C
) is the maximum allowable output-
OUT
voltage overshoot (∆V
) during unloading transients.
OST
For example, to program 1.000V output voltage,
For a maximum unloading current step (∆I) and maximum
allowed output-voltage overshoot change (∆V ), the
required output capacitance is given by Equation 9.
PMAD[3:1] = 011b, and R
= 294Ω, use:
DES
OST
R_SEL2 = 402Ω (0.970V),
R_SEL1 = 1020Ω (PMAD[2:1] = 11b, 0.030V),
R_SEL0 = 200Ω (PMAD3 = 0b, R = 294Ω)
Equation 9:
DES
L
2
This results in the output voltage = 0.970V + 0.030V =
1.000V, PMAD[3:1] = 011b, and R = 294Ω.
(∆I)
N
C
≥
DES
OUT
2(∆V
) V
OST OUT
The output voltage can also be programmed using the
PMBus. Note that the output voltage is disabled if it is set
below 0.25V through the PMBus.
where:
L = Inductance per phase
N = Number of phases
Inductor Phase-Current Ripple
For coupled inductors, the inductor peak-to-peak phase-
current ripple can be calculated from Equation 7 (which
assumes perfect coupling for coupled inductors, and duty
cycle ≤ 1/N).
V
= Nominal output voltage
OUT
For example, in a case where allowable overshoot is
the limiting factor for a 3-phase system with 250nH of
inductance per phase, 1.0V output, maximum current step
of 50A, and maximum allowable overshoot of 100mV,
Equation 7:
the minimum C
theoretically required is 1042μF.
OUT
V
f
1
V
OUT
OUT
Selecting a higher value gives good design margin
against component variation and effective capacitance
loss due to voltage bias.
I
=
−
PHPP
L n
V
SW CW
IN
where:
Bleed Resistor
I
f
= Peak-to-peak phase-current ripple in the inductor
= Switching frequency
PHPP
SW
A small bleed resistor of approximately 100Ω should
be connected between the output of the regulator
and ground to ensure that the output capacitors are
discharged shortly after the output is disabled. The
resistor should be sized so that when the maximum
expected output voltage is applied, the resistor’s power
dissipation is sufficiently below its rated power dissipation.
L = Inductance per phase
n
= Number of coupled windings
= Input voltage
CW
V
V
IN
= Output voltage
OUT
In practice, the coupling will not be perfect, but good
coupling can be achieved, with the actual ripple current
close to what is calculated by the equation.
Droop and No-Droop Operation
The device provides accurate output-droop resistance
The output current ripple is given by Equation 8,
assuming duty cycle ≤ 1/N.
over the entire range of output currents. The R
is
DROOP
set by the combination of the R1, R2, and R
according to Equation 10.
resistors,
DES
Equation 8:
Equation 10:
V
f
1
V
OUT
V
OUT
L
I
=
−
N
PP
N
SW
IN
R R
1
DES
R
=
DROOP
R 2.19A
where:
= Peak-to-peak output-current ripple
2
I
I
PP
where:
A = Slave current gain factor
L = Inductance per phase
N = Number of phases
I
R1 = Having a typical value of 600 to 800. The R2/R1
should be a minimum of 0.45
Maxim Integrated
│ 23
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
If R /R < 1, then R should be between 600Ω and 800Ω,
The ramp rate (S
switching frequency (f ), steady-state ramp voltage
) can be determined from the
2
1
1
RAMP
R
should be 353Ω, minimum, and the ratio of R2/R1
2
SW
should be 0.45, minimum.
(V
), and duty cycle (D = V
/V
according to
RAMPD
OUT IN),
Equation 14.
If R /R > 1, then R should be between 400Ω and 800Ω.
R should be 400Ω, minimum.
2
2
1
1
Equation 14:
No-droop operation can be achieved by adding capaci-
V
RAMPD
D
tor C2 in series with R in the A2 stage, according to
S
=
f
SW
2
RAMP
Equation 11.
The V
RAMPD
voltage typically ranges from 100mV to
Equation 11:
300mV. Note that V
remains constant.
changes with D, while S
RAMPD
RAMP
L
C
R
OUT
2
N
A smaller S
provides a larger-loop bandwidth for the
C2 ≥
RAMP
total inductor current (see the Loop Bandwidths section).
Once a ramp-rate value has been determined, the value
of the resistor can be calculated using Equation 15.
Above the frequency (Equation 12), the voltage-regulator
impedance approaches R
.
DROOP
Equation 15:
Equation 12:
23.81
1
R
=
f
=
MRAMP
2
S
2πR C
RAMP
2
2
where:
With either the droop or no-droop configuration, above the
frequency (Equation 13).
R
is in kΩ
MRAMP
S
is in V/μs
RAMP
Equation 13:
Example: If the required ramp rate = 1.0V/μs, then
= 23.81kΩ, and the closest 1% value is 23.7kΩ.
1
R
f
=
ZINT
R
MRAMP
PH
N
2π R
+
C
INT
INT
R
INT
Set R
Selection
according to Equation 16.
where:
N = Number of phases
The voltage-regulator impedance approaches:
INT
Equation 16:
For single phase:
V
-0.2V-V
CM
(
)
DD_MIN
R
PH
N
R
<
R
+
INT
INT
R
0.15V
I
PP
R
DROOP
N+
R
A
INT
DES
I
For 2 or more phases:
up to the voltage-loop bandwidth, unless the lead network
is used.
R
Selection
FILT
The R
V
-0.2V-V
CM
(
)
DD_MIN
resistor, together with the capacitance at the
FILT
R
< MIN
,3R
INT
DES
0.15V
I
PP
ISENSE pin, creates a lowpass filter for the sensed smart-
slave phase-current signal. A 3.01kΩ resistor should be
used for R
N+
R
A
DES
I
.
FILT
where:
Selecting the Modulator Ramp Rate
The modulator ramp rate is set using external resistor
V
= Minimum V
voltage used in the application
DD
DD_MIN
V
0.85V
= Compensation circuit common-mode voltage =
R
from the MRAMP pin to GND.
CM
MRAMP
Maxim Integrated
│ 24
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
R
= Resistor used to set the I
value
Loop Bandwidths
DES
OCP
The output-voltage loop bandwidth is given by Equation 20
(if the lead network is not used).
I
= Peak-to-peak ripple of the output current
PP
A = Save current-gain factor
I
Equation 20:
Note that a larger R
the total inductor current (see the Loop Bandwidths section).
provides a larger-loop bandwidth for
INT
1
BW
=
VL
R
PH
N
R
+
R
Selection
PH
INT
R
2πR
C
OUT
DROOP
Each of the Maxim slave’s current-sense pins is
connected to the A3_IN pin of the master IC through its
phase resistor (R
determines the amplitude of the phase current-sense
signal, which must be below 0.4V at all times, up to and
including the overcurrent limit.
INT
). The value of each phase resistor
PHk
If the lead network is used, the output-voltage loop band-
width and phase margin can be increased.
The loop bandwidth for the total inductor current is given
by Equation 21.
To help prevent phase-current imbalance due to load
transients, set according to Equation 17.
Equation 21:
Equation 17:
R
PH
N
R
INT
R
+
INT
R
≥
PH
V
f
N
G
(
+ 1
)
INT SW
OCR
BW <
IL
S
2πL
A
I
RAMP
where:
where:
L = Inductance per phase
A = Slave current gain factor
G
= Gain of the OCR circuit
OCR
Current Steering
The phase-current-balancing circuitry works to keep the
voltages across the R resistors approximately equal.
I
The loop bandwidths should meet the conditions given by
Equation 22.
PH
By increasing the R
resistor from the nominal value on
PH
Equation 22:
a particular phase, the steady-state current in that phase
can be reduced with respect to the other phases. This may
be useful in reducing the temperature on the smart-slave
device and inductor of that phase, if they tend to get hotter
than the corresponding components of the other phases
when the phase currents are all equal. Care should be
taken so the inductors of the other phases do not saturate
because of too much current; with coupled inductors, the
relative balance of phase currents is also important.
BW
BW
< BW
(by at least 50kHz difference)
VL
VL
IL
f
SW
<
4
Note: If BW < BW + 50kHz cannot be met, additional
VL
IL
phase margin can be added with the lead network.
C
Value
INT
should be selected to match the time constant of the
C
INT
double pole, which is intrinsic in the buck-converter duty
cycle-to-output transfer function given by Equation 19.
Equation 19:
L
C
OUT
R
N
C
≥
INT
PH
R
+
INT
N
Maxim Integrated
│ 25
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Increasing V
Using Resistor
OUT
Voltage-Divider Feedback
VOUT
To obtain a V
value above the maximum V
value,
OUT
NOM
a resistor voltage-divider feedback circuit can be used, as
shown in Figure 8. The equations for choosing R
,
VO_SP
RVO_SP
R
, and R
are as follows:
SP_GND
SN
SENSE_P
R
V
VO_SP
OUT
RSP_GND
=
−1
R
V
NOM
SP_GND
R
SENSE_N
RSN
R
VO_SP SP_GND
R
=
SN
R
+ R
SP_GND
VO_SP
Choose R
≤ 150Ω, then:
SN
Figure 8. Increasing V
Feedback
Using Resistor Voltage-Divider
OUT
V
OUT
R
=
R
SN
VO_SP
V
NOM
Basic PCB Layout Guidelines
R
VO_SP
OUT
R
=
SP_GND
For electrical and thermal reasons, the second layer from
the top and bottom should be reserved for contiguous
power ground planes. It is recommended to place the
MAX20751 master away from the load current path. An
analog ground (AGND) copper polygon or plane should
be used and the MAX20751 GND pins connected to it.
The AGND (or quiet ground) polygon or plane should
extend underneath the MAX20751 on one of the inner
layers and be connected to the MAX20751 PGND pin at
one point through a single wide trace or via. AGND should
V
V
− 1
NOM
where:
V
NOM
= Nominal output voltage programmed with the
R_SEL table or PMBus command.
The size of the resistors should be chosen so that their
power dissipation is within their rated value. R
omitted for a slight (usually less than 1%) reduction in
accuracy.
can be
SN
be used as a shield for the control signals (I
, PWM,
SENSE
SENSE_P/SENSE_N, and TS_FAULTB). The control
signals to and from the slaves are ideally the same length
for each phase.
The MAX20751 regulates and monitors the voltage from
SENSE_P to SENSE_N; therefore, the PWRGD and OVP
thresholds, droop resistance, V
slew rates, etc., are
OUT
SENSE_P/SENSE_N: These output sense lines are
important for regulation and should be routed as a
differential pair with sufficient AGND plane shielding.
all scaled by the voltage-divider feedback.
MAX20751 PMBus Interface Overview
Refer to Maxim AN5941: MAX20751 PMBus Application
Note.
I
Signals: The reconstructed current signals
SENSE
should be kept away from noise sources and shielded
with sufficient AGND plane.
Maxim Integrated
│ 26
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
PWM Signals: Keep away from noise-sensitive traces
and provide sufficient GND plane shielding. See Master/
Slave Placement.
●
Place a 100nF MLCC very close to the V
pin to
DD
filter high frequencies. A 22μF to 47μF MLCC is re-
quired, and should also be placed close to the induc-
tor and the IC.
TS_FAULTB: Provides AGND plane shielding.
●
●
3.3V power supply requires a small 100nF MLCC
close to the master’s pin, followed by a larger 10μF
MLCC.
V
/V
: Place decoupling capacitors as close as
DD DD33
possible to the part and on the same layer.
Compensation: The compensation components should
be placed as close as possible to the master and the
amplifier inputs/outputs they connect to and away from
noisy signals.
Use a PGND plane or polygon underneath the V
DD
switcher components. Connect the MAX20751
PGND pin to the PGND plane or polygon. The
PGND pin should connect to the MAX20751 GND
pins through a single wide trace or via. The PGND
plane or polygon should also connect to the power
R
/R_SEL/R
: These components should be
REF
MRAMP
placed close to the master and away from noisy
signals.
ground planes.
Master/Slave Placement: Position the master IC
so the side with all slave-related signals is facing the
slaves. This will avoid having noisy lines go under the
master and interact with the analog compensation nets
(Figure 9).
●
To make filtering capacitors effective, place vias to
shorten their path to the PGND pin. The number of
vias should be as many as allowed by area to reduce
path resistance to PGND.
Internal V
Switcher
DD
●
Place the inductor (A) as close as possible to the PVX
(phase output) pin.
Figure 9. Board and Layout for Slave Signals
Maxim Integrated
│ 27
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MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Figure 10. MAX20751 Schematic
Maxim Integrated
│ 28
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Figure 11. Smart Slave ICs Schematic
Maxim Integrated
│ 29
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Figure 12. V and V
Capacitors Schematic
IN
OUT
Ordering Information
PIN-
PACKAGE
PKG.
CODE
LAND
PATTERN NO.
PART
DESCRIPTION
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
OUTLINE NO.
ES AP-3565
ES AP-3565
36 QFN
(Type C)
MAX20751EKX+
MAX20751EKX+T
Master
Master
K3666+1
K3666+1
—
—
36 QFN
(Type C)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel (2.5kµ).
Maxim Integrated
│ 30
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Title:
Doc No.
Rev.
ES AP-3565
0
Package Outline - 36 Lead QFN [Type C]
Page 1 of 3
Maxim Integrated
│ 31
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Title:
Doc No.
Rev.
0
ES AP-3565
Package Outline - 36 Lead QFN [Type C]
Page 2 of 3
Maxim Integrated
│ 32
www.maximintegrated.com
MAX20751
Multiphase Master with PMBus Interface
and Internal Buck Converter
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
2
9/14
10/14
3/15
Initial Release
—
28, 29
26
Replaced Figures 10 and 11
Corrected application note number
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
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