MAX2112_V01 [MAXIM]
Complete, Direct-Conversion Tuner for DVB-S2 Applications;
| 型号： | MAX2112_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Complete, Direct-Conversion Tuner for DVB-S2 Applications |
| 文件： | 总19页 (文件大小：1074K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
General Description
Features
● 925MHz to 2175MHz Frequency Range
The MAX2112 low-cost, direct-conversion tuner IC is
designed for satellite set-top and VSAT applications.
The IC is intended for 8PSK and Digital Video Broadcast
(DVB-S2) applications.
● Monolithic VCO
• Low Phase Noise: -97dBc/Hz at 10kHz
• No Calibration Required
The MAX2112 directly converts the satellite signals
from the LNB to baseband using a broadband I/Q
downconverter. The operating frequency range extends
from 925MHz to 2175MHz.
● High Dynamic Range: -75dBm to 0dBm
● Integrated Variable BW LP Filters: 4MHz to 40MHz
● Single +3.3V ±5% Supply
The device includes an LNA and an RF variable-gain
amplifier, I and Q downconverting mixers, and baseband
lowpass filters with programmable cutoff frequency control
and digitally controlled baseband variable-gain amplifiers.
Together, the RF and baseband variable-gain amplifiers
provide more than 80dB of gain control range. The IC is
compatible with virtually all DVB-S2 demodulators.
● Low-Power Standby Mode
● Address Pin for Multituner Applications
● Differential I/Q Interface
2
● I C 2-Wire Serial Interface
● Very Small 28-Pin TQFN Package
The MAX2112 includes fully monolithic VCOs, as well
as a complete fractional-N frequency synthesizer.
Additionally, an on-chip crystal oscillator is provided
along with a buffered output for driving additional tuners
and demodulators. Synthesizer programming and device
configuration are accomplished with a 2-wire serial inter-
face. The IC features a VCO autoselect (VAS) function
that automatically selects the proper VCO. For multituner
applications, the device can be configured to have one
of two 2-wire interface addresses. A low-power standby
mode is available whereupon the signal path is shut
down while leaving the reference oscillator, digital inter-
face, and buffer circuits active, providing a method to
reduce power in single and multituner applications.
Ordering Information
PART
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
28 Thin QFN-EP*
28 Thin QFN-EP*
MAX2112CTI+
MAX2112ETI+
*EP = Exposed paddle.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration/
Functional Diagram
28
27
26
25
24
23
22
ꢀ
The MAX2112 is the most advanced DBS tuner available
today. The low noise figure eliminates the need for an
external LNA. A small number of passive components
are needed to form a complete DVB-S2 RF front-end
solution. The tuner is available in a very small 28-pin thin
QFN package.
21
IDC+
VCC_RF2
VCC_RF1
1
2
3
DC OFFSET
CORRECTION
MAX2112
INTERFACE LOGIC
AND CONTROL
LPF BW
CONTROL
IOUT-
IOUT+
20
19
18
17
GND
RFIN
GC1
QOUT-
QOUT+
4
5
Applications
● DirecTV and Dish Network DBS
● DVB-S2
● VSATs
FREQUENCY
SYNTHESIZER
DIV2/DIV4
EP
VCC_LO
6
7
16 VCC_DIG
VCC_VCO
15
REFOUT
8
9
10
11
12
13
14
19-0869; Rev 3; 4/20
MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
Absolute Maximum Ratings
V
to GND .........................................................-0.3V to +3.9V
Operating Temperature Range (MAX2112CTI+)....0°C to +70°C
Operating Temperature Range (MAX2112ETI+).. -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
CC
All Other Pins to GND.............................. -0.3V to (V
+ 0.3V)
CC
RF Input Power: RFIN....................................................+10dBm
VCOBYP, CPOUT, XTAL, REFOUT, IOUT_, QOUT_ , IDC_,
QDC_ to GND Short-Circuit Protection............................. 10s
Continuous Power Dissipation (T = +70°C)
A
28-Pin Thin QFN (derated 34.5mW/°C above +70°C) ..2.75W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC Electrical Characteristics
(MAX2112 Evaluation Kit: V
= +3.13V to +3.47V, T = 0°C to +70°C (MAX2112CTI+), T = -40°C to +85°C (MAX2112ETI+),
CC
A A
V
= +0.5V (max gain), default register settings except BBG[3:0] = 1011. No input signals at RF, baseband I/Os are open circuited.
GC1
Typical values measured at V
= +3.3V, T = +25°C.) (Note 1)
A
CC
PARAMETER
SUPPLY
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
3.13
3.3
100
3
3.47
160
V
Receive mode, bit STBY = 0
Standby mode, bit STBY = 1
Supply Current
mA
ADDRESS SELECT INPUT (ADDR)
Digital Input Voltage High, V
2.4
-50
V
V
IH
Digital Input Voltage Low, V
0.5
50
IL
Digital Input Current High, I
µA
µA
IH
Digital Input Current Low, I
IL
ANALOG GAIN-CONTROL INPUT (GC1)
Input Voltage Range
Maximum gain = 0.5V
0.5
-50
2.7
V
Input Bias Current
+50
µA
VCO TUNING VOLTAGE INPUT (VTUNE)
Input Voltage Range
0.4
2.3
V
2-WIRE SERIAL INPUTS (SCL, SDA)
Clock Frequency
400
kHz
V
0.7 x
Input Logic-Level High
Input Logic-Level Low
V
CC
0.3 x
V
V
CC
Input Leakage Current
Digital inputs = GND or V
±0.1
±1
µA
CC
2-WIRE SERIAL OUTPUT (SDA)
Output Logic-Level Low
I
= 1mA
0.4
V
SINK
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MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
AC Electrical Characteristics
(MAX2112 Evaluation Kit: V
+3.13V to +3.47V, T = 0°C to +70°C (MAX2112CTI+), T = -40°C to +85°C (MAX2112ETI+), default
CC =
A A
register settings except BBG[3:0] = 1011. Typical values measured at V
= +3.3V, T = +25°C.) (Note 1)
A
CC
PARAMETER
MAIN SIGNAL PATH PERFORMANCE
Input Frequency Range
RF Gain-Control Range (GC1)
Baseband Gain-Control Range
In-Band Input IP3
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 2)
0.5V < V
925
65
2175
MHz
dB
< 2.7V
73
15
GC1
Bits GC2 = 1111 to 0000
(Note 3)
13
dB
+2
dBm
dBm
dBm
dB
Out-of-Band Input IP3
(Note 4)
+15
+40
25
Input IP2
(Note 5)
Adjacent Channel Protection
(Note 6)
V
is set to 0.5V (maximum RF gain) and BBG[3:0]
GC1
is adjusted to give a 1V
baseband output level for a
8
P-P
-75dBm CW input tone at 1500MHz
Noise Figure
dB
dB
Starting with the same BBG[3:0] setting as above,
9
12
V
is adjusted to back off RF gain by 10dB (Note 7)
GC1
Minimum RF Input Return Loss
925MHz < f < 2175MHz, in 75Ω system
12
RF
BASEBAND OUTPUT CHARACTERISTICS
Nominal Output Voltage Swing
I/Q Amplitude Imbalance
R
= 2kΩ//10pF
0.5
1
V
P-P
LOAD
Measured at 500kHz; filter set to 22.27MHz
Measured at 500kHz; filter set to 22.27MHz
±1
dB
Degrees
Ω
I/Q Quadrature Phase Imbalance
3.5
Single-Ended I/Q Output Impedance Real Z , from 1MHz to 40MHz
30
3
O
Output 1dB Compression Voltage
Differential
V
P-P
Baseband Highpass -3dB Frequency
Corner
47nF capacitors at IDC_, QDC_
400
Hz
BASEBAND LOWPASS FILTERS
Filter Bandwidth Range
Rejection Ratio
4
40
MHz
dB
At 2 x f
39
37
-3dB
Group Delay
Up to 1dB bandwidth
ns
Ratio of In-Filter-Band to Out-of-
Filter-Band Noise
f
= 100Hz to 22.5MHz, f
= 87.5MHz
OUTBAND
INBAND
25
dB
to 112.5MHz
FREQUENCY SYNTHESIZER
RF-Divider Frequency Range
RF-Divider Range (N)
925
19
12
1
2175
251
30
MHz
MHz
Reference-Divider Frequency Range
Reference-Divider Range (R)
1
Phase-Detector Comparison
Frequency
12
30
MHz
VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION
Guaranteed LO Frequency Range
925
2175
MHz
f
f
f
= 10kHz
= 100kHz
= 1MHz
-97
OFFSET
OFFSET
OFFSET
LO Phase Noise
-100
-122
dBc/Hz
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MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
AC Electrical Characteristics (continued)
(MAX2112 Evaluation Kit: V
+3.13V to +3.47V, T = 0°C to +70°C (MAX2112CTI+), T = -40°C to +85°C (MAX2112ETI+), default
CC =
A A
register settings except BBG[3:0] = 1011. Typical values measured at V
= +3.3V, T = +25°C.) (Note 1)
A
CC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
XTAL Oscillator Frequency Range
Input Overdrive level
Parallel-resonance-mode crystal (Note 8)
AC-coupled sine-wave input
12
0.5
1
30
2.0
8
MHz
1
V
P-P
XTAL Output-Buffer Divider Range
XTAL Output Voltage Swing
XTAL Output Duty Cycle
4MHz to 30MHz, C
= 10pF
1
1.5
50
2
V
LOAD
P-P
%
Note 1: MAX2112CTI+: Min/max values are production tested at T = +70°C. Min/max limits at T = 0°C and T = +25°C are
A
A
A
guaranteed by design and characterization.
MAX2112ETI+: Min/max values are production tested at T = +85°C. Min/max limits at T = -40°C and T = +25°C are
A
A
A
guaranteed by design and characterization.
Note 2: Input gain range specifications met over this band.
Note 3: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the
RF input.
Note 4: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-20dBm each are applied at 2070MHz and 1975MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the
RF input.
Note 5: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz
to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm each
LO
are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input.
Note 6: Adjacent channel protection test conditions: GC1 is set to provide the nominal baseband output drive with a 2110MHz
27.5Mbaud signal at -55dBm. GC2 set for mid-scale. The test signal shall be set for PR = 7/8 and SNR of -8.5dB.
An adjacent channel at ±40MHz is added at -25dBm. DVB-S BER performance of 2E-4 shall be maintained for the desired
signal. GC2 may be adjusted for best performance.
Note 7: Guaranteed by design and characterization at T = +25°C.
A
Note 8: See Table 16 for crystal ESR requirements.
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MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
Typical Operating Characteristics
(MAX2112 Evaluation Kit: V = +3.3V, T = +25°C, baseband output frequency = 5MHz; V = +1.2V, default register settings except
CC
A
GC1
BBG[3:0] = 1011.)
STANDBY MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. BASEBAND FILTER CUTOFF FREQUENCY
SUPPLY CURRENT vs. SUPPLY VOLTAGE
98
97
96
95
94
93
92
91
90
89
88
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
104
T
A
= +85°C
102
100
98
96
94
92
90
88
86
84
T
= +85°C
A
T
= +25°C
= -40°C
A
T
A
= +25°C
T
A
T
A
= -40°C
3.3
3.0
1.0
0
3.1
3.2
3.3
3.4
3.5
3.6
3.5
20
3.0
3.1
3.2
3.4
3.5
3.6
4
8
12 16 20 24 28 32 36 40
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
BASEBAND FILTER CUTOFF FREQUENCY (MHz)
QUADRATURE MAGNITUDE MATCHING
vs. LO FREQUENCY
HD3 vs. V
OUT
QUADRATURE PHASE vs. LO FREQUENCY
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
93.5
92.5
91.5
90.5
89.5
88.5
87.5
86.5
1.0
f
= 10MHz
= +25°C
BASEBAND
f
= 10MHz
BASEBAND
0.8
0.6
0.4
0.2
0
T
T = +25°C
A
A
T
= +85°C
A
-0.2
-0.4
-0.6
-0.8
-1.0
T
A
= -40°C
T = -40°C
A
T
= +85°C
A
1.5
2.0
V
2.5
)
3.0
900
1200
1500
1800
2100
2400
900
1200
1500
1800
2100
2400
(V
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
OUT P-P
QUADRATURE PHASE
vs. BASEBAND FREQUENCY
QUADRATURE MAGNITUDE MATCHING
vs. BASEBAND FREQUENCY
BASEBAND FILTER
FREQUENCY RESPONSE
93.5
92.5
91.5
90.5
89.5
88.5
87.5
86.5
1.0
0.8
0.6
0.4
0.2
0
0
f
= 925MHz
f
LO
= 925MHz
LO
-10
-20
-30
-40
-50
-60
-70
-80
T
A
= +85°C
T
A
= +85°C
T
A
= +25°C
T
= -40°C
A
-0.2
-0.4
-0.6
-0.8
-1.0
T
= +25°C
T = -40°C
A
A
4
8
12
16
0
4
8
12
16
20
0
20
40
60
80
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
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MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
Typical Operating Characteristics (continued)
(MAX2112 Evaluation Kit: V = +3.3V, T = +25°C, baseband output frequency = 5MHz; V
= +1.2V, default register settings except
CC
A
GC1
BBG[3:0] = 1011.)
PROGRAMMED f
vs. MEASURED f
FREQUENCY
FREQUENCY
BASEBAND FILTER HIGHPASS
FREQUENCY RESPONSE
BASEBAND FILTER 3dB FREQUENCY
-3dB
-3dB
vs. TEMPERATURE
45
40
35
30
25
20
15
10
5
2
0
1.0
LPF[7:0] = 12 + (f
- 4MHz)/290kHz
-3dB
NORMALIZED TO T = +25°C
A
0.8
0.6
0.4
0.2
0
-2
-4
-6
-0.2
-0.4
-0.6
-0.8
-1.0
-8
-10
-12
-14
0
0
5
10 15 20 25 30 35 40 45
100
1000
10,000
-40
-20
0
20
40
60
80
PROGRAMMED f FREQUENCY (MHz)
BASEBAND FREQUENCY (Hz)
TEMPERATURE (°C)
-3dB
INPUT POWER vs. V
GC1
NOISE FIGURE vs. FREQUENCY
NOISE FIGURE vs. INPUT POWER
10
10.5
10.0
9.5
70
ADJUST BBG[3:0] FOR 1V
BASEBAND OUTPUT WITH
P-P
ADJUST BBG[3:0] FOR 1V BASEBAND
P-P
OUTPUT WITH
ADJUST BBG[3:0] FOR 1V BASEBAND
P-P
0
-10
-20
-30
-40
-50
-60
-70
-80
60
50
40
30
20
10
0
OUTPUT WITH P = -75dBm
IN
P
IN
= -75dBm AND V
= 0.5V.
GC1
P
IN
= -75dBm AND V
= 0.5V
GC1
AND V
= 0.5V
GC1
f
= 1500MHz
LO
T
= +25°C
A
T
A
= +85°C
9.0
T
A
= +70°C
T
A
= +85°C
T
A
= -40°C
8.5
T
A
= +25°C
8.0
7.5
0.5
1.0
1.5
2.0
(V)
2.5
3.0
900 1100 1300 1500 1700 1900 2100 2300
FREQUENCY (MHz)
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
V
GC1
OUT-OF-BAND IIP3 vs. INPUT POWER
IN-BAND IIP3 vs. INPUT POWER
IIP2 vs. INPUT POWER
30
20
30
20
10
60
50
40
SEE NOTE 4 ON PAGE 4 FOR CONDITIONS
SEE NOTE 3 ON PAGE 4 FOR CONDITIONS
SEE NOTE 5 ON PAGE 4 FOR CONDITIONS
10
0
0
-10
30
20
-20
-30
-40
-50
-60
-10
-20
-30
10
0
-10
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
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MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
Typical Operating Characteristics (continued)
(MAX2112 Evaluation Kit: V = +3.3V, T = +25°C, baseband output frequency = 5MHz; V = +1.2V, default register settings except
CC
A
GC1
BBG[3:0] = 1011.)
PHASE NOISE AT 10kHz OFFSET vs.
CHANNEL FREQUENCY
INPUT RETURN LOSS vs. FREQUENCY
0
-90
-95
-5
V
GC1
= 0.5V
-10
-15
-100
-105
-20
-25
V
GC1
= 2.7V
900 1125 1350 1575 1800 2025 2250
FREQUENCY (MHz)
925 1115 1305 1495 1685 1875 2065 2255
CHANNEL FREQUENCY (MHz)
PHASE NOISE vs. OFFSET FREQUENCY
LO LEAKAGE vs. LO FREQUENCY
-90
-100
-110
-120
-130
-70
-75
-80
-85
-90
MEASURED AT RF INPUT
f
LO
= 1800MHz
1.0E+03
1.0E+04
1.0E+05
1.0E+06
925
1175
1425
1675
1925
2175
OFFSET FREQUENCY (Hz)
LO FREQUENCY (MHz)
VCO: KV vs. VTUNE
450
400
350
300
250
200
150
100
50
SUB-BAND 23
SUB-BAND 12
SUB-BAND 0
0.5
0
0
1.0
1.5
2.0
2.5
3.0
VTUNE (V)
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MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
Pin Description
PIN
NAME
FUNCTION
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
1
VCC_RF2
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
2
VCC_RF1
3
4
GND
RFIN
Ground. Connect to board’s ground plane for proper operation.
Wideband 75Ω RF Input. Connect to an RF source through a DC-blocking capacitor.
RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range.
5
GC1
V
= 0.5V corresponds to the maximum gain setting.
GC1
DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a
1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
6
VCC_LO
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
7
VCC_VCO
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to
the pin. Do not share capacitor ground vias with other ground connections.
8
9
VCOBYP
VTUNE
High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short of a
connection as possible.
10
11
12
GNDTUNE
GNDSYN
CPOUT
Ground for VTUNE. Connect to the PCB ground plane.
Ground for Synthesizer. Connect to the PCB ground plane.
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest connection possible.
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a
1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
13
VCC_SYN
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series 1nF
capacitor. See the Typical Application Circuit.
14
15
XTAL
REFOUT
Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry.
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a
1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
16
VCC_DIG
17
18
19
20
21
22
23
24
QOUT+
QOUT-
IOUT+
IOUT-
IDC+
Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+.
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+.
IDC-
QDC+
QDC-
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
25
VCC_BB
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Complete, Direct-Conversion
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Pin Description (continued)
PIN
26
27
28
—
NAME
SDA
SCL
FUNCTION
2-Wire Serial-Data Interface. Requires ≥ 1kΩ pullup resistor to V
.
CC
2-Wire Serial-Clock Interface. Requires ≥ 1kΩ pullup resistor to V
.
CC
ADDR
EP
Address. Must be connected to either ground (logic 0) or supply (logic 1).
Exposed Paddle. Solder evenly to the board’s ground plane for proper operation.
configurations. The register configuration of Table 1
shows each bit name and the bit usage information for
all registers. Note that all registers must be written after
and no earlier than 100μs after the device is powered up.
Detailed Description
Register Description
The MAX2112 includes 12 user-programmable regis-
ters and 2 read-only registers. See Table 1 for register
Table 1. Register Configuration
MSB
LSB
REG
NUMBER
REGISTER READ/
REG
DATA BYTE
NAME
WRITE ADDRESS
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
N[9]
D[0]
N[8]
N-Divider
MSB
FRAC
1
1
2
3
4
5
Write
Write
Write
Write
Write
0x00
0x01
0x02
0x03
0x04
N[14]
N[13]
N[12]
N[11]
N[10]
N-Divider
LSB
N[7]
N[6]
N[5]
N[4]
N[3]
F[19]
F[11]
F[3]
N[2]
F[18]
F[10]
F[2]
N[1]
F[17]
F[9]
N[0]
F[16]
F[8]
Charge
Pump
CPMP[1]
0
CPMP[0]
0
CPLIN[1]
0
CPLIN[0]
1
F-Divider
MSB
F[15]
F[7]
F[14]
F[6]
F[13]
F[5]
F[12]
F[4]
F-Divider
LSB
F[1]
F[0]
XTAL
Divider
6
Write
0x05
XD[2]
XD[1]
XD[0]
R[4]
R[3]
R[2]
R[1]
R[0]
R-Divider
7
8
9
PLL
VCO
LPF
Write
Write
Write
0x06
0x07
0x08
D24
CPS
ICP
X
X
X
X
X
VCO[4]
LPF[7]
VCO[3]
LPF[6]
VCO[2]
LPF[5]
VCO[1]
LPF[4]
VCO[0]
LPF[3]
VAS
ADL
ADE
LPF[2] LPF[1] LPF[0]
PWDN
0
10
11
Control
Write
Write
0x09
0x0A
STBY
X
X
X
BBG[3]
BBG[2] BBG[1] BBG[0]
PLL
0
DIV
0
VCO
0
BB
0
RFMIX RFVGA
FE
0
Shutdown
0
0
LD
LD
LD
CPTST[2] CPTST[1] CPTST[0]
TURBO
1
12
Test
Write
0x0B
X
MUX[2] MUX[1] MUX[0]
0
0
0
0
0
0
Status
Byte-1
13
14
Read
Read
0x0C
0x0D
POR
VASA
VASE
LD
X
X
X
X
Status
Byte-2
VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
1 = Set to 1 for factory-tested operation.
X = Don’t care.
0 = Set to 0 for factory-tested operation.
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Complete, Direct-Conversion
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Table 2. N-Divider MSB Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
FRAC
7
1
Users must program to 1 upon powering up the device.
Sets the most significant bits of the PLL integer-divide number (N).
N can range from 19 to 251.
N[14:8]
6–0
0000000
Table 3. N-Divider LSB Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the least significant bits of the PLL integer-divide number.
N can range from 19 to 251.
N[7:0]
7–0
00100011
Table 4. Charge-Pump Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Charge-pump minimum pulse width. Users must program to 00 upon
powering up the device.
CPMP[1:0]
7–6
00
Controls charge-pump linearity. Users must program to 01 upon
powering up the device.
CPLIN[1:0]
F[19:16]
5–4
3–0
00
Sets the 4 most significant bits of the PLL fractional divide number.
Default value is F = 194,180 decimal.
0010
Table 5. F-Divider MSB Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the most significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
F[15:8]
7–0
11110110
Table 6. F-Divider LSB Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the least significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
F[7:0]
7–0
10000100
Table 7. XTAL Buffer and Reference Divider Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the crystal-divider setting.
000 = Divide by 1.
001 = Divide by 2.
XD[2:0]
7–5
000
011 = Divide by 3.
100 = Divide by 4.
101 through 110 = All divide values from 5 (101) to 7 (110).
111 = Divide by 8.
Sets the PLL reference-divider (R) number. Users must program to
00001 upon powering up the device.
R[4:0]
4–0
00001
00001 = Divide by 1; other values are not tested.
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Complete, Direct-Conversion
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Table 8. PLL Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
VCO divider setting.
D24
7
6
1
0 = Divide by 2. Use for LO frequencies ≥ 1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
Charge-pump current mode.
0 = Charge-pump current controlled by ICP bit.
1 = Charge-pump current controlled by VCO autoselect (VAS).
CPS
1
Charge-pump current.
0 = 600µA typical.
1 = 1200µA typical.
ICP
X
5
0
4–0
X
Don’t care.
Table 9. VCO Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Controls which VCO is activated when using manual VCO programming
mode. This also serves as the starting point for the VCO autoselection
(VAS) mode.
VCO[4:0]
7–3
2
11001
VCO autoselection (VAS) circuit.
0 = Disable VCO selection must be programmed through I C.
2
VAS
ADL
1
0
1 = Enable VCO selection controlled by autoselection circuit.
Enables or disables the VCO tuning voltage ADC latch when the VCO
autoselect mode (VAS) is disabled.
0 = Disables the ADC latch.
1
0
1 = Latches the ADC value.
Enables or disables VCO tuning voltage ADC read when the VCO
autoselect mode (VAS) is disabled.
0 = Disables ADC read.
ADE
0
1 = Enables ADC read.
Table 10. Lowpass Filter Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the baseband lowpass filter 3dB corner frequency.
LPF[7:0]
7–0
01001011
f
= 4MHz + (LPF[7:0]
- 12) x 290kHz.
-3dB
dec
Default value equates to f
= 22.27MHz typical.
-3dB
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Complete, Direct-Conversion
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Table 11. Control Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Software standby control.
0 = Normal operation.
STBY
7
0
1 = Disables the signal path and frequency synthesizer leaving only the
2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer
divider active.
X
PWDN
X
6
5
4
X
0
Don’t care.
Factory use only.
0 = Normal operation;
other value is not tested.
X
Don’t care.
Baseband gain setting (1dB typical per step).
0000 = Minimum gain (0dB, default).
…
BBG[3:0]
3-0
0000
1111 = Maximum gain (15dB typical).
Table 12. Shutdown Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
X
7
X
Don’t care.
PLL enable.
PLL
DIV
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 = Normal operation.
1 = Shuts down the PLL. Value not tested.
Divider enable.
0 = Normal operation.
1 = Shuts down the divider. Value not tested.
VCO enable.
0 = Normal operation.
1 = Shuts down the VCO. Value not tested.
VCO
BB
Baseband enable.
0 = Normal operation.
1 = Shuts down the baseband. Value not tested.
RF mixer enable.
0 = Normal operation.
1 = Shuts down the RF mixer. Value not tested.
RFMIX
RFVGA
FE
RF VGA enable.
0 = Normal operation.
1 = Shuts down the RF VGA. Value not tested.
Front-end enable.
0 = Normal operation.
1 = Shuts down the front-end. Value not tested.
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Complete, Direct-Conversion
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Table 13. Test Register
BIT NAME
CPTST[2:0]
X
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Charge-pump test modes.
7–5
4
000
X
000 = Normal operation (default).
Don’t care.
Charge-pump fast lock.
Users must program to 1 after powering up the device.
TURBO
3
0
REFOUT output.
000 = Normal operation. Other values are not tested.
LDMUX[2:0]
2–0
000
Table 14. Status Byte-1 Register
BIT NAME
BIT LOCATION (0 = LSB)
FUNCTION
Power-on reset status.
0 = Chip status register has been read with a stop condition since last power-on.
1 = Power-on reset (power cycle) has occurred. Default values have been loaded in
registers.
POR
7
Indicates whether VCO autoselection was successful.
VASA
VASE
6
5
0 = Indicates the autoselect function is disabled or unsuccessful VCO selection.
1 = Indicates successful VCO autoselection.
Status indicator for the autoselect function.
0 = Indicates the autoselect function is active.
1 = Indicates the autoselect process is inactive.
PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading.
LD
X
4
0 = Unlocked.
1 = Locked.
3:0
Don’t care.
Table 15. Status Byte-2 Register
BIT NAME
BIT LOCATION (0 = LSB)
FUNCTION
VCOSBR[4:0]
7-3
VCO band readback.
VAS ADC output readback.
000 = Out of lock.
001 = Locked.
ADC[2:0]
2-0
010 = VAS locked.
101 = VAS locked.
110 = Locked.
111 = Out of lock.
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MAX2112
Complete, Direct-Conversion
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Slave Address
2-Wire Serial Interface
2
The MAX2112 has a 7-bit slave address that must be sent
to the device following a START condition to initiate com-
munication. The slave address is internally programmed
to 1100000. The eighth bit (R/W) following the 7-bit
address determines whether a read or write operation
occurs.
The MAX2112 uses a 2-wire I C-compatible serial inter-
face consisting of a serial-data line (SDA) and a serial-
clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX2112 and the master
at clock frequencies up to 400kHz. The master initiates
a data transfer on the bus and generates the SCL signal
to permit data transfer. The MAX2112 behaves as a
slave device that transfers and receives data to and
from the master. SDA and SCL must be pulled high with
external pullup resistors (1kΩ or greater) for proper bus
operation. Pullup resistors should be referenced to the
The MAX2112 continuously awaits a START condition fol-
lowed by its slave address. When the device recognizes
its slave address, it acknowledges by pulling the SDA line
low for one clock period; it is ready to accept or send data
depending on the R/W bit (Figure 1).
MAX2112’s V
.
CC
The write/read address is C0/C1 if ADDR pin is connected
to ground. The write/read address is C2/C3 if ADDR pin is
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2112 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
is high and stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
connected to V
.
CC
SLAVE ADDRESS
1
1
0
0
0
0
6
0
7
S
ACK
9
R/W
8
SDA
SCL
1
2
3
4
5
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition on
SDA while SCL is high.
Figure 1. MAX2112 Slave Address Byte with ADDR Pin
Connected to Ground
Write Cycle
When addressed with a write command, the MAX2112
allows the master to write to a single register or to multiple
successive registers.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit (ACK)
or a not-acknowledge bit (NACK). Both the master and
the MAX2112 (slave) generate acknowledge bits. To
generate an acknowledge, the receiving device must
pull SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during the
high period of the clock pulse.
A write cycle begins with the bus master issuing a START
condition followed by the seven slave address bits and
a write bit (R/W = 0). The MAX2112 issues an ACK if
the slave address byte is successfully received. The bus
master must then send to the slave the address of the
first register it wishes to write to (see Table 1 for regis-
ter addresses). If the slave acknowledges the address,
the master can then write one byte to the register at the
specified address. Data is written beginning with the most
significant bit. The MAX2112 again issues an ACK if the
data is successfully written to the register. The master can
continue to write data to the successive internal registers
with the MAX2112 acknowledging each successful trans-
fer, or it can terminate transmission by issuing a STOP
condition. The write cycle does not terminate until the
master issues a STOP condition.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse. Monitoring
the acknowledge bits allows for detection of unsuccessful
data transfers. An unsuccessful data transfer happens if a
receiving device is busy or if a system fault has occurred.
In the event of an unsuccessful data transfer, the bus
master must reattempt communication at a later time.
WRITE DEVICE
ADDRESS
WRITE REGISTER
ADDRESS
WRITE DATA TO
REGISTER 0x00
WRITE DATA TO
REGISTER 0x01
WRITE DATA TO
REGISTER 0x02
R/W
0
ACK
—
ACK
—
ACK
—
ACK
—
ACK
—
START
STOP
1100000
0x00
0x0E
0xD8
0xE1
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
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Complete, Direct-Conversion
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S
T
A
R
T
S
T
A
R
T
DEVICE
ADDRESS
REGISTER
ADDRESS
DEVICE
ADDRESS
REG 00
DATA
REG 01
DATA
REG 02
DATA
N
A
C
K
S
T
O
P
R / W
0
R / W
1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
1100000
00000000
1100000
xxxxxxxx
xxxxxxxx
xxxxxxxx
Figure 3. Example: Receive Data from Read Registers
Read Cycle
Table 16. Maximum Crystal ESR
Requirement
When addressed with a read command, the MAX2112
allows the master to read back a single register, or mul-
tiple successive registers.
ESR
(Ω)
XTAL FREQUENCY (MHz)
MAX
80
12 < f
≤ 14
≤ 30
A read cycle begins with the bus master issuing a START
condition followed by the 7 slave address bits and a write
bit (R/W = 0). The MAX2112 issues an ACK if the slave
address byte is successfully received. The bus master
must then send the address of the first register it wishes
to read (see Table 1 for register addresses). The slave
acknowledges the address. Then, a START condition is
issued by the master, followed by the 7 slave address
bits and a read bit (R/W = 1). The MAX2112 issues an
ACK if the slave address byte is successfully received.
The MAX2112 starts sending data MSB first with each
SCL clock cycle. At the 9th clock cycle, the master can
issue an ACK and continue to read successive registers,
or the master can terminate the transmission by issuing a
NACK. The read cycle does not terminate until the master
issues a STOP condition.
XTAL
XTAL
60
14 < f
Baseband Lowpass Filter
The MAX2112 includes
7th-order Butterworth filter. The filter -3dB corner frequen-
cy can be adjusted from approximately 4MHz to 40MHz
by programming the LPF[7:0] register using the following
equation:
a programmable on-chip
LPF[7:0]
= (f
- 4MHz)/0.29MHz + 12,
is in units of MHz.
dec
-3dB
where f
-3dB
Total device supply current depends on the filter BW
setting. See Supply Current vs. Baseband Filter Cutoff
Frequency in the Typical Operating Characteristics for
more information.
Figure 3 illustrates an example in which registers 0
through 2 are read back.
DC Offset Cancellation
The DC offset cancellation is required to maintain the I/Q
output dynamic range. Connecting an external capacitor
between IDC+ and IDC- forms a highpass filter for the
I channel and an external capacitor between QDC+ and
QDC- forms a highpass filter for the Q channel. Keep the
value of the external capacitor less than 47nF to form a
typical highpass corner of 250Hz.
Application Information
The MAX2112 downconverts RF signals in the 925MHz to
2175MHz range directly to the baseband I/Q signals. The
devices are targeted for digital DBS tuner applications.
RF Input
The RF input of the MAX2112 is internally matched to
75Ω. Only a DC-blocking capacitor is needed. See the
Typical Application Circuit.
XTAL Oscillator
The MAX2112 contains an internal reference oscilla-
tor, reference output divider, and output buffer. All that
is required is to connect a crystal through a series 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL pin).
See Table 16 for crystal (XTAL) ESR (equivalent series
resistance) requirements.
RF Gain Control
The MAX2112 features a variable-gain low-noise ampli-
fier providing 73dB of RF gain range. The voltage con-
trol (VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
VCO Autoselect (VAS)
Baseband Variable-Gain Amplifier
The MAX2112 includes 24 VCOs. The local oscillator
frequency can be manually selected by programming the
VCO[4:0] bits in the VCO register. The selected VCO is
reported in the Status Byte-2 register (see Table 15).
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB steps.
The VGA gain can be serially programmed through the SPI
interface by setting bits BBG[3:0] in the Control register.
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Complete, Direct-Conversion
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Alternatively, the MAX2112 can be set to autonomously
choose a VCO by setting the VAS bit in the VCO reg-
ister to logic-high. The VAS routine is initiated once the
F-Divider LSB register word (REG 5) is loaded.
a VCO in the “VAS locked” range. This allows room for
a VCO to drift over temperature and remain in a valid
“locked” range.
The ADC must first be enabled by setting the ADE bit
in the VCO register. The ADC reading is latched by a
subsequent programming of the ADC latch bit (ADL = 1).
The ADC value is reported in the Status Byte-2 register
(see Table 15).
In the event that only the N-divider register or
F-divider MSB word is changed, the F-divider LSB
word must also be loaded last to initiate the VCO
autoselect function. The VCO value programmed in
the VCO[4:0] register serves as the starting point for the
automatic VCO selection process.
Standby Mode
The MAX2112 features normal operating mode and
During the selection process, the VASE bit in the Status
Byte-1 register is cleared to indicate the autoselection
function is active. Upon successful completion, bits VASE
and VASA are set and the VCO selected is reported in
the Status Byte-2 register (see Table 15). If the search
is unsuccessful, VASA is cleared and VASE is set. This
indicates that searching has ended but no good VCO has
been found, and occurs when trying to tune to a frequency
outside the VCO’s specified frequency range.
2
standby mode using the I C interface. Setting a logic-high
to the STBY bit in the Control register puts the device into
standby mode, during which only the 2-wire-compatible
bus, the crystal oscillator, the XTAL buffer, and the XTAL
buffer divider are active.
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active mode.
Default register values are provided for the user’s con-
venience only. It is the user’s responsibility to load all
the registers no sooner than 100μs after the device is
powered up.
Refer to the MAX2112/MAX2120 VCO Autoselect (VAS)
Application Note for more information.
3-Bit ADC
Layout Considerations
The MAX2112 has an internal 3-bit ADC connected to
the VCO tune pin (VTUNE). This ADC can be used for
checking the lock status of the VCOs.
The MAX2112 EV kit serves as a guide for PCB layout.
Keep RF signal lines as short as possible to minimize
losses and radiation. Use controlled impedance on all
high-frequency traces. For proper operation, the exposed
paddle must be soldered evenly to the board’s ground
plane. Use abundant vias beneath the exposed paddle
for maximum heat dissipation. Use abundant ground
vias between RF traces to minimize undesired coupling.
Table 17 summarizes the ADC output bits and the VCO
lock indication. The VCO autoselect routine only selects
Table 17. ADC Trip Points and Lock
Status
Bypass each V
placed as close as possible to the pin.
pin to ground with a 1nF capacitor
CC
ADC[2:0]
000
LOCK STATUS
Out of lock
Locked
001
010
VAS locked
VAS locked
Locked
101
110
111
Out of lock
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Complete, Direct-Conversion
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Typical Application Circuit
SERIAL-DATA
INPUT/OUTPUT
SERIAL-CLOCK
INPUT
V
CC
V
CC
28
27
26
25
24
23
22
ꢀ
IDC+
VCC_RF2
21
1
MAX2112
DC OFFSET
CORRECTION
V
CC
INTERFACE LOGIC
AND CONTROL
IOUT-
IOUT+
QOUT-
QOUT+
VCC_RF1
GND
LPF BW
CONTROL
20
19
18
17
16
15
2
3
BASEBAND
OUTPUTS
RF INPUT
RFIN
GC1
4
5
V
GC
V
V
CC
CC
FREQUENCY
SYNTHESIZER
DIV2
/DIV4
VCC_LO
VCC_DIG
REFOUT
6
7
V
CC
EP
VCC_VCO
8
9
10
11
12
13
14
V
CC
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Complete, Direct-Conversion
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Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE DOCUMENT
CODE
NO.
28 TQFN-EP
T2855+3
21-0140
90-0023
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Complete, Direct-Conversion
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Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
8/07
Initial release
—
12/07
Corrected errors in data sheet
1–7, 9–16
Corrected errors in FUNCTION cells of Tables 8 and 10, corrected formula in
Baseband Lowpass Filter section
2
3
5/10
4/20
11, 15
6
Updated the Baseband filter high pass frequency response X-axis unit from
MHz to Hz in the TOC08
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shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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