MAX2165 [MAXIM]
Single-Conversion DVB-H Tuner;
| 型号： | MAX2165 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-Conversion DVB-H Tuner |
| 文件： | 总24页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0646; Rev 1; 3/09
Single-Conversion DVB-H Tuner
MAX2165
General Description
Features
The MAX2165 direct-conversion tuner IC is designed for
handheld digital video broadcast (DVB-H) applications.
The tuner covers a 470MHz to 780MHz input frequency
range and features an I/Q baseband interface.
o 93mA (typ) Current Consumption from a Single
+2.85V Supply Voltage
o 21mW (typ) Average Power Consumption at 8%
Duty Cycle
The MAX2165’s direct-conversion architecture elimi-
nates the need for an IF-SAW filter, allowing for
reduced bill of materials cost. The design integrates a
variable-gain, low-noise amplifier (LNA); a notch filter;
an RF tracking filter; a quadrature mixer; a power
detector; programmable baseband lowpass channel-
selection filters; baseband variable-gain amplifiers
(VGA); DC offset correction circuitry; and a complete
fractional-N frequency synthesizer. The part is program-
mable through a 2-wire I2C-compatible serial interface.
o Direct-Conversion Architecture Eliminates IF-
SAW Filter
o Integrated RF Tuneable Notch Filter for Operation
in the Presence of Cellular Blockers
o Integrated DC Offset Correction Circuitry
o Integrated RF Notch Filter for Operation in the
Presence of Up to -7dBm Cellular Blockers
o Extended UHF Band Operation
o 5mm x 5mm x 0.8mm, 28-Pin Thin QFN Package
The MAX2165 integrates a tuneable notch filter. This fil-
ter is designed to notch out interfering signals in the
830MHz to 950MHz frequency range to allow for opera-
tion in the presence of large cellular signals.
Programmable baseband channel-selection filters allow
for operation with 7MHz and 8MHz channels. Digital DC
offset correction circuitry supports time-sliced operation
by minimizing power-up time delay. The fractional-N
synthesizer reduces VCO lock time and minimizes
close-in phase noise, eliminating the need for power-
hungry, phase-noise reduction algorithms.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX2165ETI+
-40°C to +85°C
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
Pin Configuration/
Functional Diagram
The MAX2165 is available in a tiny, 5mm x 5mm x
0.8mm, 28-pin thin QFN package with an exposed pad-
dle. It is specified for operation over the -40°C to +85°C
extended temperature range.
Applications
28
27
26
25
24
23
22
+
DVB-H Handheld Receivers
DVB-T Portable Devices
CHARGE
PUMP
1
21
20
19
18
17
16
15
SDA
SCL
LDO
SERIAL INTERFACE, CONTROL,
AND SYNTHESIZER
DMB-T/H Portable Devices
ISDB-T Receivers (13 Segment)
2
3
4
5
6
7
GND_TUNE
VTUNE
VCC_VCO
BB_AGC
BBI+
N.C.
MAX2165
RFIN
0°
90°
ADDR
VCC_RF
LEXT
TO
CONTROL
BLOCK
PWRDET
DAC
BBI-
EP
8
9
10
11
12
13
14
THIN QFN
5mm x 5mm
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Single-Conversion DVB-H Tuner
ABSOLUTE MAXIMUM RATINGS
All V
Pins to GND ..............................................-0.3V to +3.6V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
GND_TUNE to GND ..............................................-0.3V to +0.3V
All Other Pins to GND.................................-0.3V to (V + 0.3V)
BBI_, BBQ_ Short Circuit to Ground Duration ...............Indefinite
CC
Maximum RF Input Power ..............................................+13dBm
Continuous Power Dissipation (T = +70°C)
A
28-Pin Thin QFN (derate 34.5mW/°C above +70°C).....2758mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX2165
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2165 EV kit, V = +2.75V to +3.3V, V
= V
= 2.3V (maximum gain), no RF input signals at RFIN, default register set-
CC
RF_AGC
BB_AGC
tings, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +2.85V, T = +25°C, unless otherwise noted.) (Note 1)
A
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE AND CURRENT
Supply Voltage
2.75
3.30
134
116
20
V
LNASW = 1 (RF LNA on)
LNASW = 0 (RF LNA off)
109
93
Supply Current
mA
Shutdown Current
µA
V
Gain-Control Voltage
Required to obtain full range of RF and baseband gain
0.4
-50
2.3
RF_AGC and BB_AGC Input
Bias Current
V
AGC
at +0.4V and +2.3V
+50
µA
SERIAL INTERFACE
0.3 x
Input Logic-Level Low
V
V
V
V
CC
0.7 x
Input Logic-Level High
Input Hysteresis
V
CC
0.05 x
V
CC
SDA, SCL Input Current
Output Logic-Level Low
-10
+10
0.4
µA
V
I
I
= 0.3mA
SINK
V
CC
-
Output Logic-Level High
= 0.3mA
V
SOURCE
0.4
AC ELECTRICAL CHARACTERISTICS
isters set according to the specified default register conditions, T = -40°C to +85°C, unless otherwise noted. Typical values are at
(MAX2165 EV kit, V
= +2.75V to +3.3V, V
= V
= 2.3V (maximum gain), V
A
= 1V , 75Ω system impedance, reg-
CC
RF_AGC
BB_AGC
OUT P-P
V
CC
= +2.85V, T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OVERALL PERFORMANCE (RF INPUT TO BASEBAND OUTPUTS)
Meets specified performance
Operating Frequency Range
470
470
783
832
MHz
dB
Operates with derated performance (Note 2)
50Ω system, worst case across band, any gain-control
Input Return Loss
setting (Note 3)
7
2
_______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2165 EV kit, V
= +2.75V to +3.3V, V
= V
= 2.3V (maximum gain), V
= 1V , 75Ω system impedance, reg-
CC
RF_AGC
BB_AGC
OUT P-P
isters set according to the specified default register conditions, T = -40°C to +85°C, unless otherwise noted. Typical values are at
A
V
CC
= +2.85V, T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum gain
74
82
Z
1kΩ
= 75Ω, Z
>
SOURCE
LOAD
Voltage Gain
dB
Minimum gain on
(LNASW = 1)
23
29
34
25
RF Gain-Control Range
0.4V ≤ V
0.4V ≤ V
≤ 2.3V
≤ 2.3V
29
21
dB
dB
RF_AGC
BB_AGC
Baseband Gain-Control Range
Gain change caused by switching RF LNA on (LNASW =
1) and off (LNASW = 0)
LNA Gain Step
13.5
17
10
dB
degrees
dB
Phase change caused by switching RF LNA on (LNASW
= 1) and off (LNASW = 0)
LNA Gain Step Phase Change
Noise Figure (Note 3)
Input IP2 (Note 4)
At 470MHz
3.8
4.0
9
6.5
6.5
At 783MHz
Maximum gain
0
dBm
23dB gain reduction
Maximum gain
26
-4
-20
-22
Input IP3 (Note 5)
dBm
dBm
dB
23dB gain reduction
Maximum gain (Note 6)
17
In-Band Input P
1dB
Cellular Tx blocker gain compression
Cellular Tx blocker noise figure rise
1.2
3
3
Cellular Blocker Desensitization
(Note 7)
Two tones (782.8MHz and 782.3MHz) within passband of
baseband filter, 780MHz LO frequency
In-Band IM3
-55
-40
dBc
dBc
dBc
170MHz to 960MHz RF input frequency
960MHz to 1400MHz RF input frequency
< -60
< -60
RF Beats Converted to Output
RF Isolation
DC to 50MHz, RF input to baseband outputs relative to
desired channel
-60
I/Q Output Swing
I/Q DC Voltage
Z
= 10kΩ || 10pF
0.5
1
V
LOAD
P-P
V
I+, I-, Q+, Q- outputs to ground
Phase error
V
/ 2
CC
2
degrees
dB
I/Q Quadrature Accuracy
Amplitude error
-1.5
+1.5
-33
-35
-35
50MHz to 470MHz
470MHz to 878MHz
878MHz to 1732MHz
-38
-52
-49
dBmV
dBm
Spurious Emissions at RF Input
(Note 3)
Spur at four times Rx frequency, tested at f = 474MHz,
LO
-58
-51
f
= 1896MHz
SPUR
1kHz offset to 10kHz (Note 3)
1MHz offset (Note 3)
> 10MHz offset
-86
-96
Closed-Loop Phase Noise
dBc/Hz
-108
-126
-140
_______________________________________________________________________________________
3
Single-Conversion DVB-H Tuner
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2165 EV kit, V
= +2.75V to +3.3V, V
= V
= 2.3V (maximum gain), V
= 1V , 75Ω system impedance, reg-
CC
RF_AGC
BB_AGC
OUT P-P
isters set according to the specified default register conditions, T = -40°C to +85°C, unless otherwise noted. Typical values are at
A
V
CC
= +2.85V, T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Shutdown to full operation, VCO settled to the Rx
frequency, DC offset calibrated (Note 8)
Power-Up Time
< 1
20
ms
BASEBAND FILTERS
MAX2165
0 or
200
Lower corner (Note 9)
Hz
dB
Passband Cutoff Attenuation
Upper corner at 3.85MHz (UHF mode), T = +25°C
0.9
2.7
0.5
150
5
5
5
A
Upper corner at 3.35MHz (VHF mode), T = +25°C
A
Amplitude Ripple
T
= +25°C
1.5
dB
A
P-P
Group Delay Ripple
Group Delay Matching
µs
P-P
ns
4.75MHz (VHF mode) (Note 11)
5.25MHz (UHF mode) (Note 11)
14.5MHz (VHF and UHF mode) (Note 12)
> 16.2MHz
23
23
59
Rejection Ratio (Note 10)
dB
75
84
FRACTIONAL SYNTHESIZER
RF N-Divider Ratio
RF R-Divider Ratio
Fractional Ratio
7
1
251
2
Length of fractional accumulator (Note 13)
20
bits
Integer Spurs
Worst-case spur inside baseband filter bandwidth
-60
dBc
35MHz step, settled to within 100Hz frequency error / 20°
phase error
Settling Time
200
µs
ICP = 0
ICP = 1
0.6
1.2
Charge-Pump Current
mA
µA
Charge-Pump Leakage
REFERENCE OSCILLATOR
Reference Frequency
-10
+10
26
4
MHz
Reference Buffer Output Voltage
Swing
10kΩ || 10pF load
0.5
1
V
P-P
When used as a passive input for an external reference
oscillator
Input Impedance
Input Voltage
12
kΩ
mV
When used as a passive input for an external reference
oscillator
100
0.1
600
RMS
OVERLOAD DETECTOR
Attack-Point Accuracy
Attack-Point Increment
2.5
2.5
dB
dB
mA
µA
3-bit DAC, change per LSB step
Detector on
Detector Output Sink
Detector off
5
4
_______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2165 EV kit, V
= +2.75V to +3.3V, V
= V
= 2.3V (maximum gain), V
= 1V , 75Ω system impedance, reg-
CC
RF_AGC
BB_AGC
OUT P-P
isters set according to the specified default register conditions, T = -40°C to +85°C, unless otherwise noted. Typical values are at
A
V
CC
= +2.85V, T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
CONDITIONS
MIN
TYP
150
5
MAX
UNITS
V/V
Detector Gain
Detector Response Time
2-WIRE SERIAL INTERFACE
Clock Rate
µs
2
I C fast mode, slave category
400
kHz
Note 1:
Min and max limits are guaranteed by test at T = +25°C and are guaranteed by design and characterization at T
-40°C and +85°C. The default register settings are not production tested. Load registers no sooner than 100µs after
power-up.
=
A
A
Note 2:
Notch filter must be disabled by programming the TF_NTCH[3:0] bits to 1111 to enable operation up to 832MHz. Under
extreme conditions, the part can experience up to 3dB degradation in sensitivity and intermodulation distortion.
Guaranteed by design and characterization over the specified operating conditions. Not production tested.
UHF tones resulting in f - f beat frequency within the baseband output. Two tones at 350MHz and 1133MHz
Note 3:
Note 4:
1
2
with IM2 measured at 783MHz.
Note 5:
Note 6:
Two tones converted to 5.25MHz and 10.75MHz, IM3 measured at 250kHz.
A desired signal at P
= -78dBm is injected and downconverted to 3.75MHz. A blocker tone is injected at 10MHz
DESIRED
higher in frequency. Specified level is blocker power at which desired output signal compresses by 1dB. T = +25°C.
A
Note 7:
Note 8:
Note 9:
A single blocker at -7dBm with a bandwidth of less than 4MHz is injected at 880MHz with the receiver tuned to 783MHz
and set to maximum gain.
VCO locked to within 100Hz of the Rx frequency. Wake-up initiated by toggling the SHDN pin from low to high and con-
necting the STBY pin to ground.
Applies to continuous DC correction operation (DVB-T mode). In DVB-H mode, optional correction hold feature allows
quasi-DC-coupling.
Note 10: Depends on 7MHz/8MHz bandwidth mode.
Note 11: Equivalent to video carrier in upper adjacent channel. T = +25°C.
A
Note 12: Equivalent to f
- 3.8MHz for 18.3MHz sampling rate baseband DAC.
20
NYQUIST
Note 13: Total frequency resolution is f
/ 2 , or approximately 20Hz with a 20MHz reference frequency.
REF
Typical Operating Characteristics
(MAX2165 EV kit, V
= +2.85V, default register settings, V
= V
= 2.3V, V
= V
= 500mV , T = +25°C,
QOUT P-P A
CC
RF_AGC
BB_AGC
IOUT
unless otherwise noted.)
VOLTAGE GAIN vs. RFAGC
SUPPLY CURRENT vs. SUPPLY VOLTAGE
VOLTAGE GAIN vs. FREQUENCY
90
80
70
60
50
40
30
120
115
110
105
100
100
95
90
85
80
75
70
65
BB_AGC = 2.3V
T
= -40°C
A
T = +85°C
A
T
= -40°C
A
T = +25°C
T = +25°C
A
A
T
A
= +85°C
T
= +25°C
A
T
= +85°C
A
T = -40°C
A
0
0.5
1.0
1.5
2.0
2.5
2.6
2.8
3.0
(V)
3.2
3.4
470
535
600
665
730
795
860
RF_AGC CONTROL VOLTAGE (V)
V
FREQUENCY (MHz)
CC
_______________________________________________________________________________________
5
Single-Conversion DVB-H Tuner
Typical Operating Characteristics (continued)
(MAX2165 EV kit, V
= +2.85V, default register settings, V
= V
= 2.3V, V
= V
= 500mV , T = +25°C,
QOUT P-P A
CC
RF_AGC
BB_AGC
IOUT
unless otherwise noted.)
VOLTAGE GAIN vs. BBAGC
NOISE FIGURE vs. RF Tx INPUT POWER
NOISE FIGURE vs. FREQUENCY
90
80
70
20
15
10
5
12
9
T
= -40°C
A
RF_AGC = 2.3V
BLOCKER AT 880MHz
MAX2165
T
= +25°C
A
T
= +25°C
A
T = +85°C
A
60
50
6
T
= +85°C
A
3
40
30
T = -40°C
A
0
0
-17.5
-10.0
-7.5 -5.0
0
0.5
1.0
1.5
2.0
2.5
-25.0 -22.5 -20.0
-15.0 -12.5
470
535
600
665
730
795
860
BB_AGC CONTROL VOLTAGE (V)
RF Tx INPUT POWER (dBm)
FREQUENCY (MHz)
NORMALIZED BASEBAND
FREQUENCY RESPONSE
RF INPUT RETURN LOSS
vs. FREQUENCY
NORMALIZED BASEBAND
FREQUENCY RESPONSE
5
0
0
10.0
0
Z
= 75Ω
E
O
5
+0 ADJUSTMENT FACTOR
-10.0
-20.0
D
C
10
TRACKING FILTER SETTING "1"
+2 ADJUSTMENT FACTOR
-5
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
B
F
15
20
25
30
-10
-15
A
G
H
-20
-25
-30
I
TRACKING FILTER SETTING "15"
35
40
-6 ADJUSTMENT FACTOR
-100.0
-110.0
TRACKING FILTER SETTING "7"
3.0
3.5
4.0
FREQUENCY (MHz)
F: -3 ADJUSTMENT FACTOR
4.5
5.0
5.5
470
535
600
665
730
795
860
6
8
16 18
20
14
0
2
4
10 12
FREQUENCY (MHz)
FREQUENCY (MHz)
A: +2 ADJUSTMENT FACTOR
B: +1 ADJUSTMENT FACTOR G: -4 ADJUSTMENT FACTOR
PHASE NOISE vs. RF FREQUENCY
PHASE NOISE vs. OFFSET FREQUENCY
H: -5 ADJUSTMENT FACTOR
I: -6 ADJUSTMENT FACTOR
C: 0 ADJUSTMENT FACTOR
D: -1 ADJUSTMENT FACTOR
E: -2 ADJUSTMENT FACTOR
-60
-70
-50
-60
10kHz OFFSET
-70
-80
-90
-100
-110
-120
-130
-140
-150
-80
-90
-100
-110
-160
470
535
600
665
730
795
860
1
10
100
1000
10,000
RF FREQUENCY (MHz)
OFFSET FREQUENCY (kHz)
6
_______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
Typical Operating Characteristics (continued)
(MAX2165 EV kit, V
= +2.85V, default register settings, V
= V
= 2.3V, V
= V
= 500mV , T = +25°C,
QOUT P-P A
CC
RF_AGC
BB_AGC
IOUT
unless otherwise noted.)
POWER-DETECTOR OUTPUT VOLTAGE
vs. RF INPUT POWER
REFERENCE BUFFER OUTPUT SIGNAL
MAX2165 toc13
4
3
2
1
0
40kΩ PULLUP TO 2.85V
10kΩ || 10pF LOAD
PD_TH[2:0] = 111
200mV/div
PD_TH[2:0] = 000
-70
-50
-40
-60
-30
20ns/div
RF INPUT POWER (dBm)
Pin Description
PIN
1
NAME
SDA
FUNCTION
Serial-Data Input/Output. Requires a pullup resistor to V
.
CC
2
SCL
Serial-Clock Input. Requires a pullup resistor to V
.
CC
3
N.C.
No Connection. Connect this pin to ground.
4
RFIN
ADDR
RF Input. Internally matched to 75Ω. Requires a DC-blocking capacitor.
2
5
Address-Select Input. Selects the I C slave address. See Table 20.
RF Power-Supply Input. Connect to a low-noise, power-supply voltage. Bypass to the PCB ground
plane with a 2200pF and 100nF capacitor placed as close as possible to the pin.
6
7
8
VCC_RF
LEXT
External Inductor Connection. Connect to V with a 39nH inductor.
CC
RF Gain-Control Voltage Input. Accepts voltages from 0.4V to 2.3V with 2.3V providing maximum RF
gain. This pin can also be controlled by the OVLD_DET output. See the Typical Application Circuit.
RF_AGC
Shutdown Input. Drive this pin low to disable all internal circuits and to put the device into low-power
shutdown mode. Drive this pin high for normal operation.
9
SHDN
STBY
Standby Input. Controls the power-up sequence of the chip. See the Power-Up Sequence section for
more information on this pin’s operation.
10
Overload-Detection Output. This output provides an error signal between the internal power-detector
output voltage and an internal programmable reference voltage. This output can be connected to the
RF_AGC input to implement a closed RF automatic gain-control loop.
11
OVLD_DET
Baseband Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB
ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.
12
13
VCC_BB
BBQ-
Inverting Quadrature Baseband Output
_______________________________________________________________________________________
7
Single-Conversion DVB-H Tuner
Pin Description (continued)
PIN
14
NAME
BBQ+
BBI-
FUNCTION
Noninverting Quadrature Baseband Output
Inverting In-Phase Baseband Output
Noninverting In-Phase Baseband Output
15
16
BBI+
Baseband Gain-Control Voltage Input. Accepts voltages from 0.4V to 2.3V with 2.3V providing the
maximum baseband gain.
17
18
BB_AGC
MAX2165
VCO Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB ground
plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.
VCC_VCO
19
20
VTUNE
VCO Tuning Voltage Input. Connect to the PLL loop filter output.
VCO Tuning Voltage Ground. Connect to the PCB ground plane.
GND_TUNE
VCO Linear-Regulator Noise Bypass. Bypass to the PCB ground plane with a 470nF capacitor placed
as close as possible to the pin.
21
22
23
LDO
CP
Charge-Pump Output. Connect to the PLL loop filter input.
Synthesizer Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB
ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.
VCC_SYN
Multiplexed Output Line. Output for various test functions, can also be used as a PLL lock-detect
indicator. See Table 9 for more information. When used as a PLL lock detector, logic-high indicates
PLL is not locked and logic-low indicates PLL is locked.
24
MUX
Reference Buffer Output. Provides a buffered crystal-oscillator signal that can be used as a clock
reference for the demodulator. Requires a DC-blocking capacitor.
25
26
27
REFOUT
VCC_XTAL
XB
Crystal-Oscillator Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the
PCB ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.
Reference Input. Connect to a parallel resonant mode crystal through a load-matching capacitor or to
a reference oscillator.
Reference-Oscillator Feedback Input. Connect to a capacitive feedback network when the on-chip
reference oscillator is used. Leave unconnected when an external reference is used.
28
EP
XE
EP
Exposed Paddle. Solder evenly to the board’s ground plane to achieve the lowest impedance path.
requirements. A 0 or 1 indicates that the bit must be set
Detailed Description
to the defined 0 or 1 value for proper operation.
Operation is not tested or guaranteed if these bits are
programmed to other values and is only for
factory/bench evaluation. In typical application, always
program to the operation defined state.
Register Descriptions
The MAX2165 includes 15 programmable registers and
three read-only registers. See Table 1 for register con-
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all reg-
isters. U labeled under each bit name indicates that the
bit value is user defined to meet specific application
See Tables 2–19 for detailed descriptions of each reg-
ister. All registers must be written 100µs after power-up
and no earlier than 100µs after power-up.
8
_______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
Table 1. Register Configuration*
REGISTER SETTINGS
MSB
LSB
REGISTER
NAME
REGISTER
ADDRESS
DATA BYTE
D3
OPERATION DEFAULT
DEFINED
(POR)
D7
D6
D5
D4
D2
D1
D0
N7
U
N6
U
N5
U
N4
U
N3
U
N2
U
N1
U
N0
U
N-Divider Integer
N-Divider Frac2
N-Divider Frac1
N-Divider Frac0
Tracking Filter
LNA
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x10
0x11
0x12
—
H17
X
0
X
0
X
0
FRAC
U
F19
U
F18
U
F17
U
F16
U
—
—
H18
H00
H00
H72
H01
H0A
H08
H00
H50
HF3
H71
H00
H00
H00
N/A
N/A
N/A
F15
U
F14
U
F13
U
F12
U
F11
U
F10
U
F9
U
F8
U
F7
U
F6
U
F5
U
F4
U
F3
U
F2
U
F1
U
F0
U
—
TF_NTCH3
U
TF_NTCH2
U
TF_NTCH1
U
TF_NTCH0
U
TF_BAL3
U
TF_BAL2
U
TF_BAL1
U
TF_BAL0
U
—
X
0
X
0
X
0
X
0
X
0
X
0
X
0
LNASW
U
—
PLL
Configuration
RDIV
U
ICP
U
CPS
U
ADLY0
U
ADLY0
U
LFDIV2
U
LFDIV1
U
LFDIV0
U
—
CP_TST2
0
CP_TST1
0
CP_TST0
0
X
0
X
1
LD_MUX2
U
LD_MUX1
U
LD_MUX0
U
Test
—
X
0
SHDN_REF
U
X
0
SHDN_SYN
U
SHDN_RF
U
SHDN_BB
U
SHDN_PD
U
SHDN_BG
U
Shutdown
VCO Control
—
VCO1
U
VCO0
U
BS2
U
BS1
U
BS0
U
VAS
1
ADL
0
ADE
0
—
Baseband
Control
BB_BW3
U
BB_BW2
U
BB_BW1
U
BB_BW0
U
BB_BIA0
0
PD_TH2
U
PD_TH1
U
PD_TH0
U
—
X
0
DC_MO1
1
DC_MO0
1
DC_SP1
1
DC_SP0
0
DC_TH1
0
DC_TH0
0
DC Offset Control
DC Offset DAC
H79
H00
—
DC_DAC8
DC_DAC7
0
DC_DAC6
0
DC_DAC5
0
DC_DAC4
0
DC_DAC3
0
DC_DAC2
0
DC_DAC1
0
DC_DAC0
0
ROM Table
Address
X
0
FUSE_TH
0
X
0
WR
0
TFA3
U
TFA2
U
TFA1
U
TFA0
U
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Reserved
H00
N/A
N/A
N/A
ROM Table Data
Readback
TRF7
POR
TRF6
VASA
VCO0
TRF5
VASE
BS2
TRF4
LD
TRF3
DC_LO
BS0
TRF2
DC_HI
ADC2
TRF1
X
TRF0
PD_OVLD
ADC0
Chip Status
Readback
Autotuner
Readback
VCO1
BS1
ADC1
*See the Register Descriptions section for more information on recommended settings.
Table 2. N-Divider Integer Register (Address: 0x00)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
N[7:0]
7–0
Programs the integer value of the PLL N-divider ratio. Default integer divide value is 23.
_______________________________________________________________________________________
9
Single-Conversion DVB-H Tuner
Table 3. N-Divider Frac2 Register* (Address: 0x01)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
X
7, 6, 5
Reserved. Set to 000 for normal operation.
PLL mode select:
1 = Fractional mode selected.
0 = Integer mode selected.
FRAC
4
MAX2165
F[19:16]
3–0
Sets the 4 most significant bits of the fractional PLL divider ratio.
*When programming the fractional divider ratio, all three fractional divider registers must be written before the ratio is updated.
Table 4. N-Divider Frac1 Register* (Address: 0x02)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
F[15:8]
7–0
Sets bits 15 through 8 of the fractional PLL divider ratio.
*When programming the fractional divider ratio, all three fractional divider registers must be written before the ratio is updated.
Table 5. N-Divider Frac0 Register* (Address: 0x03)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
F[7:0]
7–0
Sets the 8 least significant bits of the fractional PLL divider ratio.
*When programming the fractional divider ratio, all three fractional divider registers must be written before the ratio is updated.
Table 6. Tracking Filter Register (Address: 0x04)
BIT LOCATION
BIT NAME
TF_NTCH[3:0]
TF_BAL[3:0]
FUNCTION
(0 = LSB)
Programs the notch frequency of the internal tracking filter. Optimal values for notch
frequencies of 783MHz and 725MHz can be read from the ROM table entries. See the
Reading the ROM Table section.
7–4
Programs the tracking filter balun. Optimum values over frequency can be interpolated
from the ROM table entries. See the Reading the ROM Table section.
3–0
Table 7. LNA Register (Address: 0x05)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
X
7–1
Reserved. Set to all zeros for normal operation.
LNA enable:
1 = LNA is enabled.
0 = LNA is disabled.
LNASW
0
10 ______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
Table 8. PLL Configuration Register (Address: 0x06)
BIT LOCATION
(0 = LSB)
BIT NAME
FUNCTION
Selects the PLL reference divider:
1 = Divide reference by 2.
0 = Divide reference by 1.
RDIV
7
6
Selects the charge-pump current:
1 = 1.2mA
ICP
0 = 0.6mA
Selects how the charge-pump current is programmed:
1 = Charge-pump current is automatically programmed to the optimal setting by the VCO
autotuner.
CPS
5
0 = Charge-pump current is set manually by programming the ICP bit.
Sets the VCO autoselect wait time:
00 = ~200µs
ADLY[1:0]
4, 3
01 = ~400µs
10 = ~800µs
11 = ~1600µs
Sets the prescaler for internal low-frequency clocks; program these bits so the
crystal frequency divided by the prescaler value is equal to 2MHz:
000 = Divide by 8 (for 16MHz crystals).
001 = Divide by 9 (for 18MHz crystals).
010 = Divide by 10 (for 20MHz crystals).
011 = Divide by 11 (for 22MHz crystals).
LF_DIV[2:0]
2, 1, 0
100 = Divide by 12 (for 24MHz crystals).
101 = Divide by 13 (for 26MHz crystals).
110 = Divide by 14 (for 28MHz crystals).
111 = Divide by 2 (for 4MHz crystals).
Table 9. Test Register (Address: 0x07)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
Charge-pump test modes:
000 = Normal operation.
100 = Force charge pump into low-impedance state.
101 = Force charge-pump source current.
110 = Force charge-pump sink current.
CP_TST[2:0]
X
7, 6, 5
4, 3
111 = Force charge pump into high-impedance state.
Reserved. Set to 01 for normal operation.
Selects which signal is output to the MUX pin:
000 = PLL lock indicator (normal operation).
001 = N-divider output (after divide by 2).
010 = R-divider output (after divide by 2).
011 = Factory use only.
LD_MUX[2:0]
2, 1, 0
1XX = Factory use only.
______________________________________________________________________________________ 11
Single-Conversion DVB-H Tuner
Table 10. Shutdown Register (Address: 0x08)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
X
7
Reserved. Set to 0 for normal operation.
Crystal-oscillator buffer shutdown control:
1 = Buffered crystal-oscillator output is disabled.
SHDN_REF
X
6
5
4
0 = Buffered crystal-oscillator output is enabled.
Note: The crystal oscillator is activated by either the SHDN_SYN bit or the SHDN_REF bit. If
either bit is 0, the crystal oscillator is enabled. If both are 1, the crystal oscillator is disabled.
MAX2165
Reserved. Set to 0 for normal operation.
PLL shutdown control:
1 = PLL is disabled.
0 = PLL is enabled.
SHDN_SYN
Note: The crystal oscillator is activated by either the SHDN_SYN bit or the SHDN_REF bit. If
either bit is 0, the crystal oscillator is enabled. If both are 1, the crystal oscillator is disabled.
RF front-end shutdown control:
1 = RF circuits are disabled.
0 = RF circuits are enabled.
SHDN_RF
SHDN_BB
SHDN_PD
3
2
1
Mixer, baseband filters, and baseband variable-gain amplifiers (VGA) shutdown control:
1 = Mixer, baseband filters, and baseband VGA are disabled.
0 = Mixer, baseband filters, and baseband VGA are enabled.
Baseband power-detector shutdown control:
1 = Baseband power detector is disabled.
0 = Baseband power detector is enabled.
Main bias shutdown control:
1 = Main bias circuits are disabled.
0 = Main bias circuits are enabled.
SHDN_BG
0
Note: The main bias circuits can and will be shut down once all other blocks are shut
down (all bits in the Shutdown register are set to 1, and the VCO[1:0] bits in the VCO
Control register and the DC_MO[1:0] in the DC Offset Control register are set to 00).
12 ______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
Table 11. VCO Control Register (Address: 0x09)
BIT LOCATION
(0 = LSB)
BIT NAME
FUNCTION
Controls which VCO is activated when using manual VCO programming mode:
00 = VCO disabled.
VCO[1:0]
7, 6
01 = Select VCO 0 (lowest frequency VCO).
10 = Select VCO 1.
11 = Select VCO 2 (highest frequency VCO).
Selects which VCO sub-band is activated when using manual VCO programming mode:
000 = Select sub-band 0 (lowest frequency sub-band).
001 = Select sub-band 1.
010 = Select sub-band 2.
SB[2:0]
5, 4, 3
011 = Select sub-band 3.
100 = Select sub-band 4.
101 = Select sub-band 5.
110 = Select sub-band 6.
111 = Select sub-band 7 (highest frequency sub-band).
Enables or disables the VCO autotuner function:
1 = VCO and VCO sub-band are programmed automatically by the autotuner.
0 = VCO and VCO sub-band selection is controlled manually by programming the
VCO[1:0] and SB[2:0] bits.
VAS
ADL
ADE
2
1
0
Enables or disables the VCO tuning voltage ADC latch when the VCO autotuner is
disabled (VAS = 0):
1 = Latches the ADC output.
0 = Disables the ADC latch.
Enables or disables the VCO tuning voltage ADC read when the VCO autotuner is
disabled (VAS = 0):
1 = Enables ADC read.
0 = Disables ADC read.
Table 12. Baseband Control Register (Address: 0x0A)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
Programs the bandwidth of the baseband filter. Optimum values for 6MHz to 8MHz wide
channels can be calculated after reading a ROM table entry. See the Reading the ROM
Table section.
BB_BW[3:0]
7–4
Baseband filter bias current control:
1 = High-bias current.
BB_BIA
3
0 = Low-bias current.
Programs the power-detector attack point for closed-loop RF gain control; see the
Typical Operating Characteristics for power-detector behavior:
000 = Most aggressive RF gain reduction.
PD_TH[2:0]
2, 1, 0
001
…
110
______________________________________________________________________________________ 13
Single-Conversion DVB-H Tuner
Table 13. DC Offset Control Register (Address: 0x0B)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
X
7
6
Reserved. Set to 0 for normal operation.
DC_DAC8
Most significant bit of the DC offset correction DAC.
Controls the DC offset correction mode of operation:
00 = Offset correction disabled.
MAX2165
DC_MO[1:0]
DC_SP[1:0]
DC_TH[1:0]
5, 4
3, 2
1, 0
01, 10 = I/Q channel DC correction DACs are programmed direct from the DC_DAC[8:0]
bits for manual offset correction.
11 = Normal operation.
Controls the DC offset correction speed (highpass corner frequency):
00 = Offset correction off, hold DAC values.
01 = Select correction speed 1 (slowest correction speed, ~20Hz highpass corner).
10 = Select correction speed 2.
11 = Select correction speed 3 (fastest correction speed, ~500Hz highpass corner).
Control the DC offset correction accuracy thresholds:
00 = Not recommended.
01 = Keep typical DC offset to within 100mV.
10 = Keep typical DC offset to within 200mV.
11 = Keep typical DC offset to within 400mV.
Table 14. DC Offset DAC Register (Address: 0x0C)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
Programs the I/Q DC offset DAC for manual DC offset correction. Note the MSB,
DC_DAC8, is located in the DC Offset Control register.
DC_DAC[7:0]
7–0
Table 15. ROM Table Address Register (Address: 0x0D)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
X
7–4
Reserved. Set to 0000 for normal operation.
Programs which ROM table address that data is to be read from (see Table 21):
0001 = Tracking filter notch coefficients for 783MHz and 725MHz.
0010 = Balun coefficients for 470MHz and 780MHz.
TFA[3:0]
3–0
0011 = Baseband filter bandwidth settings for 7MHz and 8MHz channels.
All other codes = Reserved.
Table 16. Reserved Register (Address: 0x0E)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
X
7–0
Reserved. Set to 0x00 for normal operation.
14 ______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
Table 17. ROM Table Data Readback Register (Address: 0x10)
BIT LOCATION
(0 = LSB)
BIT NAME
FUNCTION
ROM table data read register. Data from the register at the address programmed into the
TFA[3:0] bits are written to this register for reading by the host processor.
TFR[7:0]
7–0
Table 18. Chip-Status Readback Register (Address: 0x11)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
Power-on-reset indicator:
POR
7
1 = Power has been reset since last read.
0 = Power has not been reset since last read.
Indicates whether VCO autotuner selection was successful:
1 = Indicates successful automatic VCO selection.
0 = Indicates the autoselect function is disabled or automatic VCO selection was unsuccessful.
VASA*
VASE*
LD
6
5
4
3
Status indicator for the VCO autotuner function:
1 = Indicates the automatic VCO selection process is active.
0 = Indicates the automatic VCO selection process is inactive.
PLL lock detect:
1 = PLL is locked.
0 = PLL is unlocked.
Indicates DC offset correction accuracy:
1 = DC offset correction detected negative signal excursions in either the I or Q channel.
0 = No signal excursions detected.
DC_LO*
Indicates DC offset correction accuracy:
DC_HI*
X
2
1
1 = DC offset correction detected positive signal excursions in either the I or Q channel.
0 = No signal excursions detected.
Reserved.
Indicates whether the signal level is above or below the programmed attack-point
threshold:
1 = Signal is above the programmed attack-point threshold.
0 = Signal is below the programmed attack-point threshold.
PD_OVLD
0
*The functionality of these bits is not production tested or guaranteed.
Table 19. Autotuner Readback Register (Address: 0x12)
BIT LOCATION
BIT NAME
FUNCTION
(0 = LSB)
VCO[1:0]*
BS[2:0]*
7, 6
Indicates which VCO was selected by the VCO autotuner.
Indicates which VCO sub-band was selected by the VCO autotuner.
Provides a 3-bit digital reading of the VCO tuning voltage.
5, 4, 3
2, 1, 0
ADC[2:0]*
*The functionality of these bits is not production tested or guaranteed.
______________________________________________________________________________________ 15
Single-Conversion DVB-H Tuner
Acknowledge and Not-Acknowledge Conditions
2-Wire Serial Interface
The MAX2165 uses a 2-wire I2C-compatible serial inter-
face consisting of a serial-data line (SDA) and a serial-
clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX2165 and the master
at clock frequencies up to 400kHz. The master initiates
a data transfer on the bus and generates the SCL sig-
nal to permit data transfer. The MAX2165 behaves as a
slave device that transfers and receives data to and
from the master. SDA and SCL must be pulled high
with external pullup resistors (1kΩ or larger) for proper
bus operation.
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2165 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
MAX2165
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2165 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high peri-
od of the SCL clock pulse. Changes in SDA while SCL is
high and stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
Slave Address
The MAX2165 has a 7-bit slave address that must be
sent to the device following a START condition to initi-
ate communication. The slave address can be pro-
grammed to one of two possible addresses through the
ADDR pin (Table 20). The eighth bit (R/W) following the
7-bit address determines whether a read or write oper-
ation occurs.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
The MAX2165 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
Table 20. Programmable Device Address
ADDR
READ ADDRESS
0xC3
WRITE ADDRESS
1
0
0xC2
0xC0
Write Cycle
When addressed with a write command, the MAX2165
allows the master to write to a single register or to multi-
ple successive registers.
0xC1
2
I C bus is a registered trademark of Philips Corp.
SLAVE ADDRESS
0
S
1
1
1
0
3
0
5
0
6
0
7
R/W
ACK
P
SDA
SCL
2
4
8
9
2
®
NOTE: TIMING PARAMETERS CONFORM WITH I C BUS SPECIFICATIONS.
Figure 1. MAX2165 Slave Address Byte
16 ______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
WRITE DEVICE
ADDRESS
WRITE REGISTER
ADDRESS
WRITE DATA TO
REGISTER 0x00
WRITE DATA TO
REGISTER 0x01
WRITE DATA TO
REGISTER 0x02
R/W
0
ACK
ACK
ACK
ACK
ACK
START
STOP
110000[ADDR]
0x00
0x0E
0xD8
0xE1
Figure 2. Example of Writing Registers 0 Through 2 with 0x0E, 0xDS, and 0xE1, Respectively
WRITE DEVICE
ADDRESS
WRITE 1st REGISTER
ADDRESS
WRITE DEVICE
ADDRESS
WRITE DATA
REG 0
WRITE DATA
REG 1
R/W
0
ACK
ACK
R/W
1
ACK
ACK
NACK
START
START
STOP
110000[ADDR]
00000000
110000[ADDR]
D7–D0
D7–D0
Figure 3. Example of Reading Data from Registers 0 Through 2
A write cycle begins with the bus master issuing a START
condition followed by the 7 slave address bits and a write
bit (R/W = 0). The MAX2165 issues an ACK if the slave
address byte is successfully received. The bus master
must then send to the slave the address of the first regis-
ter it wishes to write to (see Table 1 for register address-
es). If the slave acknowledges the address, the master
can then write one byte to the register at the specified
address. Data is written beginning with the most signifi-
cant bit and is clocked in on the rising edge of SCLK. The
MAX2165 again issues an ACK if the data is successfully
written to the register. The master can continue to write
data to the successive internal registers with the
MAX2165 acknowledging each successful transfer, or it
can terminate transmission by issuing a STOP condition.
The write cycle does not terminate until the master issues
a STOP condition.
The read cycle does not terminate until the master
issues a STOP condition. Figure 3 illustrates an exam-
ple in which registers 0 and 1 are read back.
Applications Information
RF Input
The RF input is internally matched and provides good
return loss over the entire band of operation for either 50Ω
or 75Ω systems, and requires a DC-blocking capacitor.
RF and Baseband Gain Control
The MAX2165 features separate RF and baseband gain-
control inputs that can be used to achieve optimum SNR
over a wide input dynamic range. Baseband gain control
is achieved through the BB_AGC pin. This pin is typically
controlled by the baseband processor and can accept
voltages from 0.4V to 2.3V with 2.3V providing maximum
baseband gain.
Figure 2 illustrates an example in which registers 0 through
2 are written with 0x0E, 0xD8, and 0xE1, respectively.
RF gain control is achieved through the RF_AGC pin. This
pin also accepts control voltages from 0.4V to 2.3V with
2.3V providing maximum RF gain. Closed-loop automatic
RF gain control can be achieved by connecting the
OVLD_DET pin through a lowpass filter to the RF_AGC
pin. See the IF Power Detector section.
Read Cycle
All registers on the MAX2165 are available to be read by
the master with 3 of the registers being read-only.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX2165 issues an ACK
if the slave address byte is successfully received. The
master then sends the address of the first register that it
wishes to read. The MAX2165 then issues another ACK.
Next, the master must issue a START condition followed
by the 7 slave address bits and a read bit (R/W = 1).
The MAX2165 issues an ACK if it successfully recog-
nizes its address and begins sending data from the
specified register address starting with the most signifi-
cant bit (MSB). Data is clocked out of the MAX2165 on
the rising edge of SCLK. On the 9th rising edge of
SCLK, the master can issue an ACK and continue read-
ing successive registers, or it can issue a NACK fol-
lowed by a STOP condition to terminate transmission.
The RF signal path features a low-noise amplifer (LNA)
that can be switched in an out-of-signal path. Program
the LNASW bit in the LNA register (Table 7) to 1 to enable
the LNA. Enabling the LNA adds about 17mA of current,
16dB of gain, and causes less than 10° of phase change
in the received signal.
IF Power Detector
The MAX2165 baseband power detector compares the
total weighted received input signal within approximately
2 channels of the wanted channel to a programmable
threshold. This threshold can be programmed to differ-
ent values with the PD_TH[2:0] bits in the baseband
control register.
______________________________________________________________________________________ 17
Single-Conversion DVB-H Tuner
To close the RF gain-control loop, connect the 300µA
control current sink of the power detector (pin
pump-current selection, or program CPS to 0 to enable
manual charge-pump-current selection. The autotuner
function must be enabled (VAS = 1) to enable automat-
ic charge-pump-current selection. When in manual
mode, the charge-pump current is programmed by the
ICP bit in the PLL Configuration register.
OVLD_DET) to V
with a 40kΩ pullup resistor. The
CC
resulting voltage is fed with an RC lowpass to the
RF_AGC input.
VCO Autotuner
The MAX2165 includes 3 VCOs with each VCO contain-
ing 8 VCO sub-bands. The appropriate VCO and VCO
sub-band for the desired local oscillator frequency can
be manually selected by programming the VCO[1:0]
and SB[2:0] bits in the VCO control register (Table 11).
VCO Autotuner Delay Selection
During the autotuner selection process, the autotuner
must allow time for the PLL to settle before determining
if VCO selection was successful. This wait time is pro-
grammable through the ADLY[1:0] bits in the PLL
Configuration register (Table 8). Program the wait time
to be longer than the expected PLL settling time.
MAX2165
Alternatively, the MAX2165 can be set to autonomously
choose a VCO and VCO sub-band. Automatic VCO
selection is enabled by setting the VAS bit in the VCO
Control register (Table 11). The autotuner begins
selecting the appropriate VCO once the fractional por-
tion of the N-divider has been programmed. Therefore,
when changing LO frequencies, all the N-divider regis-
ters (integer and fractional) must be programmed to
activate the autotuner function.
RF Notch Filter
The MAX2165 integrates an RF notch filter that can be
used to notch out large interfering signals in the
830MHz to 950MHz frequency range to prevent perfor-
mance degradation when operating in the presence of
large cellular phone signals. The notch frequency of the
filter is programmable through the TF_NTCH[3:0] bits in
the Tracking Filter register (Table 6). Optimal notch fil-
ter codes for two different notch frequencies are stored
in an on-chip ROM table. See the Baseband Filter and
Tracking Filter section for additional details. When no
interfering cellular signals are present or when receiving
signals in the 783MHz to 860MHz frequency range, the
TF_NTCH[3:0] bits must be programmed to 111 to move
the notch out to the highest possible frequency to mini-
mize the filter’s in-band attenuation.
PLL lock detection can be achieved by monitoring the
MUX pin or by reading the LD bit in the Chip-Status
Readback register (Table 18).
Charge-Pump Current Selection
The PLL charge-pump current can also be either manu-
ally programmed or automatically selected by the VCO
autotuner. Program the CPS bit in the PLL configuration
register (Table 8) to 1 to enable automatic charge-
Table 21. ROM Table
MSB
LSB
DESCRIPTION
ADDRESS
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
0x0
X
X
X
X
X
X
X
X
Optimal tracking
filter notch settings
for operation
below 725MHz
and above
TF_NTCH[3:0]
TF_NTCH[3:0]
Tracking filter notch low
Tracking filter notch high
0x1
Recommended notch frequency settings for Rx Recommended notch frequency settings for Rx
725MHz
frequencies below 725MHz
frequencies above 725MHz
Optimal tracking
settings at
780MHz and
470MHz
TF_BAL[3:0]
TF_BAL[3:0]
0x2
0x3
Optimal tracking filter settings at 780MHz
Optimal tracking filter settings at 470MHz
Optimal baseband
filter BW for 8MHz
channel
BB_BW[3:0]
8MHz wide
X
X
X
X
18 ______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
Unlike the tracking filter, it is not necessary to interpolate
where:
notch filter settings for various operating frequencies.
When receiving channels below 725MHz in the presence
of cellular blockers, the TF_NTCH[3:0] bits should be pro-
grammed to the lower notch frequency that is stored in
the ROM table. When receiving channels above 725MHz
in the presence of cellular blockers the TF_NTCH[3:0]
bits can be programmed to the upper notch frequency
that is stored in the ROM table.
Value = decimal value of the optimal TF_BAL[3:0] set-
ting for desired channel frequency, f
BAL_L = decimal value of the optimal TF_BAL[3:0] set-
ting for 470MHz as read from the ROM table
BAL_H = decimal value of the optimal TF_BAL[3:0] set-
ting for 780MHz as read from the ROM table
f = desired channel frequency in MHz
Example: Assume the TF_BAL[3:0] values read from
the ROM table for 780MHz and 470MHz are 14 and 2,
respectively, and we wish to program the balun for
operation at an RF frequency of 620MHz.
Baseband Filter and Tracking Filter
The MAX2165 includes programmable baseband and
tracking filters. The baseband filter bandwidth is con-
trolled through the BB_BW[3:0] bits in the Baseband
Control register (Table 12). The tracking filter’s balun fre-
quency can be programmed through the TF_BAL[3:0] in
the Tracking Filter register (Table 6).
Using the previous equation, we can calculate:
620MHz − 470MHz
780MHz − 470MHz
Value at 620MHz= 2 + (14 - 2)x
= 7.8
Reading the ROM Table
To accommodate process variations, each part is factory
calibrated. During calibration, the best notch filter settings
for two different notch frequencies, the best balun set-
tings for 470MHz and 780MHz, and the best baseband
filter settings for 6MHz to 8MHz channels are determined.
These settings are stored in an on-chip ROM table that
must be read upon power-up and stored in the micro-
processor local memory (3 bytes total). Table 21 shows
the address and bits for each ROM table entry.
Rounding to the nearest integer value gives us 8; there-
fore, when operating at 620MHz, the TF_BAL[3:0] bits in
the Tracking Filter register must be programmed to 1000.
Setting the Baseband Filter
The MAX2165 baseband filter is freely programmable
over a wide range of 3dB cutoff frequencies from
approximately 3.0MHz to 4.3MHz, but the exact cutoff
frequency varies from part-to-part due to manufactur-
ing process variations. To avoid requiring the user to
find the correct setting, the best setting for a 3.9MHz
cutoff frequency (i.e., 8MHz wide DVB-T/-H channels)
is determined by Maxim and stored on a ROM table on
every chip. The user needs to read this value from the
ROM table entry 0x3 (see Table 21) and write it back
into register 0xA bits BB_BW[3:0] (see Table 12) upon
powering up the MAX2165.
Each ROM table entry must be read using a two-step
process. First, the address of the bits to be read must be
programmed into the TFA[3:0] bits in the ROM Table
Address register (Table 15).
Once the address has been programmed, the data
stored in that address is transferred to the TRF[7:0] bits in
the ROM Table Data Readback register (Table 17). The
ROM data at the specified address can then be read
from the TRF[7:0] bits and stored in the microprocessor’s
local memory.
Baseband Filter Setting for RF Channels Other than
8MHz or Modulation Types Other than DVB-T
Interpolating Balun Coefficients
The TF_BAL[3:0] bits must be reprogrammed for each
channel frequency to optimize performance over the
band. The values given for 780MHz and 470MHz in the
ROM table can be used to interpolate the optimal coeffi-
cients for any other frequency using the equation:
If a different cutoff frequency than 3.9MHz is desired, a
fixed value per Table 22 can be added or subtracted
from the number read-out of the ROM table, before
writing it back into the corresponding MAX2165 register.
This way the factory calibration is still utilized and the
resulting cutoff frequency is still reasonably accurate.
f − 470MHz
Value = BAL_L + (BAL_H− BAL_L)x
780MHz − 470MHz
______________________________________________________________________________________ 19
Single-Conversion DVB-H Tuner
Table 22. Offsets for Various Cutoff Frequencies
OFFSET TO BE ADDED TO ROM TABLE ENTRY 0x3 BEFORE
DESIRED 3dB CUTOFF FREQUENCY (TYPICAL) (MHz)
WRITING BACK INTO REGISTER 0xA
3.10
3.20
3.30
3.44
3.56
3.70
3.90
4.10
4.23
-6
-5
-4
-3
-2
-1
0
MAX2165
+1
+2
DC Offset Correction
Direct-conversion receivers are susceptible to DC offsets
that can limit linearity performance, as well as down-
stream data converter/demodulator dynamic range. The
MAX2165 includes on-chip fast-settling DC offset cancel-
lation circuitry that requires no off-chip components to
remove any undesirable DC offsets that are present in the
output signal.
Power-Up Sequence and Shutdown Modes
Driving the SHDN pin low places the MAX2165 in hard-
ware shutdown mode, where all internal circuits are dis-
abled and the supply current decreases to less than
20µA. Driving SHDN low shuts the entire IC down
regardless of the state of the internal registers except for
the shutdown reference bit (SHDN_REF). Register set-
tings are maintained when the part comes out of shut-
down mode.
The correction threshold can be programmed to four dif-
ferent values through the DC_TH[1:0] bits in the DC
Offset Control register (Table 13).
The MAX2165 also features a software-shutdown mode.
In software-shutdown mode, the individual bits of the
Shutdown register can be programmed to power down
the MAX2165 functional blocks. Program the Shutdown
register (Table 10) to 0xFF, the VCO[1:0] bits in the VCO
Control register (Table 11) to 00, and the DC_MO[1:0]
bits in the DC Offset Control register (Table 13) to 00 to
shut down the entire chip through the software.
When offset correction is active, the correction circuitry
creates a highpass characteristic in the signal path with
the highpass cutoff frequency determining the offset
correction speed. This correction speed is program-
mable through the DC_SP[1:0] bits in the DC Offset
Control register.
The MAX2165 features a power-up sequencer that very
quickly removes the DC offset upon exiting hardware
shutdown mode. To enable the power-up sequence fea-
ture, connect STBY to ground while SHDN transitions
from low to high.
For DVB-H applications, it is recommended that the DC
correction be performed once after the part is taken out of
shutdown, then disabled by programming the
DC_SP[1:0] bits to 00 (hold state). Disabling the DC offset
correction during signal reception prevents the highpass
characteristic introduced by the correction circuitry from
distorting the lower frequency components of the
received signal and allows for DC-coupling to the demod-
ulator. The only requirements for operation with DC-cou-
pling are that the receive frequency and baseband filter
setting remain constant after the one-time cancellation.
The typical time-sliced operating nature of DVB-H easily
allows for operation under these conditions.
Power-Up Sequence
Holding STBY low while SHDN transitions high causes the
part to power up in a two-step process. In the first step,
the VCO and PLL power up and settle. The typical current
consumption during this first step is approximately 20mA.
In the second step, the entire signal path is powered up
and the RF_AGC voltage, the BB_AGC voltage, and the
DC correction are automatically overridden with DC offset
correction performed in less than 0.5ms. Once DC cor-
rection has been achieved the part is returned to its origi-
nally programmed state. The entire power-up process
completes in approximately 2ms.
The part can be configured to automatically perform DC
correction upon power-up through the use of the SHDN
and STBY pins. See the Power-Up Sequence section for
further information.
20 ______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
The benefit of the automatic DC correction is that it allows
the DC offset to be removed in less than 0.5ms, much
faster than the effective highpass corner frequency of the
correction circuit would otherwise allow. If the DC_SP[1:0]
bits are programmed to 00 prior to exiting hardware shut-
down, the part performs a one-time DC offset cancellation
upon power up then disables the DC correction circuitry
after the power-up sequence completes. This allows for
DC-coupling between the baseband outputs and the
demodulator as long as the receive frequency, baseband
filter setting, and chip temperature stay constant after the
one-time cancellation. A change in these parameters
while the chip is receiving requires recalibration of the DC
offset. However, the typical time-sliced nature of DVB-H
does meet the above requirements for operation with
DC-coupling.
of approximately 1V
phase noise of the external reference must exceed
-140dBc/Hz at offsets of 1kHz to 100kHz.
and leave XE unconnected. The
P-P
When connecting directly to a crystal, see the Typical
Application Circuit for the required topology.
Crystal-Oscillator Buffer Output
A buffered crystal-oscillator signal is provided at the
REFOUT pin and can be used to drive the demodulator.
This output requires a DC-blocking capacitor. This buffer
can be enabled or disabled through the SHDN_REF bit in
the Shutdown register (Table 10).
Layout Considerations
The EV kit can serve as a guide for PCB layout. Keep RF
signal lines as short as possible to minimize losses and
radiation. Use controlled impedance on all high-frequen-
cy traces. The exposed paddle must be soldered evenly
to the board’s ground plane for proper operation. Use
abundant vias beneath the exposed paddle for maximum
heat dissipation. Use abundant ground vias between RF
traces to minimize undesired coupling. To minimize cou-
pling between different sections of the IC, the ideal
power-supply layout is a star configuration, which has a
When STBY is connected to V , the chip does not follow
CC
the power-up procedure described above, and all circuit
blocks are powered up at the same time. If the
DC_SP[1:0] bits are set to 00 (i.e., quasi-DC-coupled), a
DC calibration is never executed and the MAX2165 is not
functional.
The state of the STBY pin only determines whether or not
DC correction is automatically performed upon exiting
hardware shutdown.
large decoupling capacitor at the central V
node. The
CC
V
traces branch out from this node with each trace
CC
going to separate V
pins of the MAX2165. Each V
CC
CC
Crystal-Oscillator Interface
The MAX2165 reference-oscillator input can be config-
ured as a crystal oscillator or it can be used as a high-
impedance reference input driven by an external source.
pin must have a bypass capacitor with a low imped-
ance to ground at the frequency of interest. Do not
share ground vias among multiple connections to the
PCB ground plane.
When using an external reference oscillator, drive XB
through an AC-coupling capacitor with a signal amplitude
______________________________________________________________________________________ 21
Single-Conversion DVB-H Tuner
Typical Application Circuit
V
CC
V
CC
BUFFERED
CRYSTAL
OUTPUT
LOCK
DETECT
V
CC
MAX2165
XE
28
XB
27
VCC_XTAL
26
REFOUT
25
MUX
24
VCC_SYN
23
CP
22
+
SDA
SCL
LDO
SERIAL-DATA
INPUT/OUTPUT
1
2
3
4
5
6
7
21
20
19
18
17
16
15
CHARGE PUMP
GND_TUNE
VTUNE
VCC_VCO
BB_AGC
BBI+
SERIAL-CLOCK
INPUT
MAX2165
SERIAL INTERFACE, CONTROL,
AND SYNTHESIZER
N.C.
V
CC
RFIN
0°
90°
ADDR
VCC_RF
LEXT
ADDRESS
SELECT
BASEBAND GAIN-
CONTROL VOLTAGE
TO
CONTROL
BLOCK
V
CC
PWRDET
I+
I-
DAC
EP
+
-
BBI-
8
9
10
STBY
11
OLVD_DET
12
VCC_BB
13
14
BBQ+
RF_AGC
SHDN
BBQ-
V
CC
SHUTDOWN
STANDBY
Q-
Q+
22 ______________________________________________________________________________________
Single-Conversion DVB-H Tuner
MAX2165
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
28 TQFN-EP
PACKAGE CODE
DOCUMENT NO.
21-0140
T2855-8
______________________________________________________________________________________ 23
Single-Conversion DVB-H Tuner
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
6/07
Initial release
—
Added Note 3 to Spurious Emissions at RF Input specification, added condition to
Passband Cutoff Attenuation and Amplitude Ripple specifications, corrected Notes
1, 6, and 11
1
3/09
3, 4, 5
MAX2165
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products. Inc.
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