MAX22005ALM+ [MAXIM]
12-Channel Factory-Calibrated Configurable Industrial-Analog Input;
| 型号： | MAX22005ALM+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Channel Factory-Calibrated Configurable Industrial-Analog Input |
| 文件： | 总47页 (文件大小：1216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
General Description
Benefits and Features
The MAX22005 is a twelve-channel industrial-grade ana-
log input voltage-mode device that can also be configured
as analog-input current-mode device using an external
precision resistor per channel. It can also operate as con-
figurable analog-input using an external precision resistor
and low-cost switch per channel. Input channels can be
used as twelve single-ended inputs, or six differential in-
puts, or up to eight multichannel configurable differential
inputs. In total, the device supports up to 26 different con-
figurations.
● Enables More Robust and Reliable Systems
• ±36V High-Voltage Protection for All Input Ports
• 2kV HBM ESD Protection of All Pins
• ±2kV Surge Protection (with External 5kΩ Resistor)
• CRC Detection for Robust Serial Communication
• Watchdog Timer
● Software Configurability
• ±12.5V Analog Input-Voltage Mode
• ±25mA Analog Input-Current Mode Using External
Sense Resistor
The MAX22005 features an integrated 24-bit delta-sigma
ADC that is shared between all channels. The ADC can
be used with either an integrated 5ppm/°C precision refer-
ence or an external reference. Standard industrial analog
input voltage ranges are converted to the ADC input volt-
age range using high-voltage, zero-drift input amplifiers.
All input ports are robustly protected up to ±36V reverse
polarity and ±2kV surge pulses without the need of TVS
diodes.
• Configurable Inputs Using External Sense Resistor
and Low-Cost Switches
● Best-in-Class System Accuracy
• 0.02% FSR at 25°C Factory Calibrated
• 0.05% FSR over ±50°C from 25°C Factory
Calibration
• Maximum of 30nA Input Leakage
• 5ppm/°C Internal Reference
● Additional Features
Eight general-purpose digital I/O (GPIO) ports are avail-
able for common use, or they can be used to control ex-
ternal switches for configurable inputs.
• Internal or External ADC Reference
• Eight GPIO Ports
• 48.5mW Low Power Dissipation with ±5V Supply
• 30MHz SPI/QSPI/DSP-Compatible Serial Interface
The MAX22005 is factory calibrated with best-in-class sys-
tem performance of less than 0.05% FSR Total-Unadjust-
ed-Error (TUE) over temperature.
● Operating Temperature -40°C to +125°C
● 7.5mm × 7mm 48-pin LGA package
The host communicates with the MAX22005 through a
high-speed 30MHz SPI bus for all configurations and infor-
mation management, as well as for acquiring conversion
results. An optional 8-bit CRC enhances the reliability of
the SPI interface, protecting against all 8-bit bursts, as well
as all double-bit errors.
Ordering Information appear at end of datasheet.
The MAX22005 operates from 2.7V to 3.6V analog and
digital supplies, and up to ±24V high-voltage supplies.
The MAX22005 is available in 48-pin LGA package and
operates over the -40°C to +125°C industrial temperature
range.
Applications
● Programmable Logic Controllers (PLC)
● Programmable Automation Controllers (PAC)
● Distributed Control Systems (DCS)
19-101026; Rev 0; 4/21
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Simplified Block Diagram
DVDD
AVDD
GPIO[7:0]
HVDD
AI1
AI2
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
8
AI3
AI4
CS
AI5
SCLK
SDI
SDO
INT
RST
RDY
SYNC
CLK
AI6
SPI INTERFACE
CONTROL-LOGIC
SIGNAL
24-BIT Δ-Σ ADC
AI7
PROCESSING
AI8
AI9
AI10
AI11
AI12
REF_ADC
REF_OUT
NR
MUX
2.5V REFERENCE
1.8V LDO
BYP_ADC
AGND
REF_ADC_EXT
HVSS
DGND
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Maxim Integrated | 2
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
TABLE OF CONTENTS
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
48-PIN LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAX22005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Range Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Differential-Input Common-Mode Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input-Voltage Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supply Voltages and Power-Supply Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Product Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog Input ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog Input Offset and Gain Error Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADC Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADC RDY (Data Ready) Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADC Conversion Synchronization Using the SYNC Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MAX22005 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Supply Headroom Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Surge Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MAX22005 12-Channel Configurable Industrial Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Maxim Integrated | 3
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
TABLE OF CONTENTS (CONTINUED)
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Maxim Integrated | 4
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
LIST OF FIGURES
Figure 1. SPI Write Timing (N = 24 when CRC is Disabled and N = 32 when CRC is Enabled) . . . . . . . . . . . . . . . . . . 11
Figure 2. SPI Read Timing (N = 24 when CRC is Disabled and N = 32 when CRC is Enabled) . . . . . . . . . . . . . . . . . . 11
Figure 3. Input Port Triplet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. Input Ports Pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Two Point System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. RDY Output Timing, a) Single-Cycle Mode, b) Continuous Single-Cycle Mode, c) Continuous Conversion
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. SYNC Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Maxim Integrated | 5
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
LIST OF TABLES
Table 1. Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. SPI Transaction with CRC Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. SPI Transaction with CRC Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. Product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Input-Channel Configuration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Input-Channel Limit Values and Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Selection of Data Rates for Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Selection of Data Rates for Single-Cycle Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Selection of Data Rates for Single-Cycle Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Full-Scale Range of Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Maxim Integrated | 6
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Absolute Maximum Ratings
AVDD to AGND ..................................................... -0.3V to +3.9V
DVDD to DGND..................................................... -0.3V to +3.9V
AGND to DGND..................................................... -0.3V to +0.3V
BYP_ADC to DGND .............................................. -0.3V to +2.1V
HVDD to HVSS ...................................................... -0.3V to +52V
HVDD to AGND...................................................... -0.3V to +40V
AGND to HVSS ...................................................... -0.3V to +40V
CS, SCLK, SDI, SDO, RDY, RST, SYNC, CLK, GPIO[7:0] to
AI_ to HVSS...-0.3V to the lower of (+52V or (V
- V
) +
HVSS
HVDD
0.3V)
INT to DGND ............................................................-0.3V to +6V
Maximum Current into Any Pin ..........................................±50mA
Continuous Power Dissipation 48-pin LGA (JEDEC 2S2P PCB)
(T = +70°C, derate 19.51mW/°C above +70°C.) .....1560.98mW
A
Operating Temperature Range...........................-40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range ..............................-65°C to +150°C
Soldering Temperature (reflow) ........................................+260°C
DGND.................. -0.3V to the lower of (+3.9V or V
REF_ADC, REF_ADC_EXT, NR, REF_OUT to AGND....-0.3V to
+ 0.3V)
DVDD
the lower of (+3.9V or VAVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
48-PIN LGA
Package Code
L487A7M+1
21-100448
90-100160
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θ
)
51.25°C/W
23.46°C/W
JA
Junction-to-Case Thermal Resistance (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
Electrical Characteristics
(V
= V
= 3.3V, V
= +15V, V
= -15V, Reference Source = Internal Reference, T = T
to T
, unless otherwise
AVDD
DVDD
HVDD
HVSS
A
MIN
MAX
noted. Typical values are at T = +25ºC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT-VOLTAGE MODE—SINGLE-ENDED
From V
From V
2.5
2.5
HVSS
HVDD
Headroom
V
ADC full-scale range
±12.5
V
IN
Linear range V
(Note 2)
= -5V, V
= +5V
HVDD
HVSS
Input-Voltage Range
-2.5
+2.5
V
Linear range (Note 2)
-10.5
+10.5
±1.3
Offset Error
Offset Drift
Gain Error
V
T
T
= +25°C
±0.1
mV
µV/°C
ppm
OFFSET
A
= +25°C ± 50°C, with internal
A
±13.6
±450
reference (Note 3)
T
A
= +25°C
±200
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Maxim Integrated | 7
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Electrical Characteristics (continued)
(V
= V
= 3.3V, V
= +15V, V
= -15V, Reference Source = Internal Reference, T = T
to T
, unless otherwise
AVDD
DVDD
HVDD
HVSS
A
MIN
MAX
noted. Typical values are at T = +25ºC.) (Note 1)
A
PARAMETER
Gain Drift
SYMBOL
CONDITIONS
MIN
TYP
MAX
±3.4
UNITS
T
A
= +25°C ± 50°C, with internal
reference (Note 3)
ppm/°C
INL Error
INL Drift
INL
T
A
T
A
T
A
T
A
= +25°C
±600
±4.0
µV
= +25°C ± 50°C (Note 3)
= +25°C (Note 4)
µV/°C
±0.02
±0.05
Total Unadjusted Error
TUE
% FSR
= +25°C ± 50°C (Note 3 and Note 4)
ADC sample rate is 11.52ksps, ADC
mode is Continuous Single-Cycle.
Input-Voltage Noise
Input Current
V
138
µV
RMS
NOISE
±30
nA
dB
DC, V
DC, V
= +5V to +24V
= -24V to -5V
100
100
2
HVDD
HVSS
Supply-Rejection Ratio
PSRR
From AI_ to V
Open Detector
Resistance
HVDD
MΩ
dB
From AI_ to AGND
2
DCHNL_RATE[3:0] = 0b0010, 0b0011,
0b0100, 0b0101
87
75
50Hz/60Hz Normal-
Mode Rejection
DCHNL_RATE[3:0] = 0b0000, 0b0001
V
IN
changes from 0V to -10.5V or 0V to
+10.5V, digital output reaches 1% of final
value. ADC sample rate is 57.6ksps, ADC
mode is Continuous.
Settling Time
0.2
ms
ANALOG INPUT VOLTAGE MODE—DIFFERENTIAL
ADC full-scale range
±25
Input-Voltage Range
V
IN
V
linear range (Note 2)
-21
+21
Offset Error
Offset Drift
Gain Error
Gain Drift
V
T
T
= +25°C
±0.2
±2.6
mV
µV/°C
ppm
OFFSET
A
= +25°C ± 50°C, with internal
A
±23.1
±450
±4.8
reference (Note 3)
T
T
= +25°C
±200
A
= +25°C ± 50°C, with internal
A
ppm/°C
reference (Note 3)
INL Error
INL Drift
INL
T
T
T
T
= +25°C
±1.2
±5.0
mV
A
A
A
A
= +25°C ± 50°C (Note 3)
= +25°C (Note 4)
μV/°C
±0.02
±0.05
Total Unadjusted Error
Input-Voltage Noise
TUE
% FSR
= +25°C ± 50°C (Note 3 and Note 4)
ADC sample rate is 11.52ksps, ADC
mode is Continuous Single-Cycle.
V
275
µV
RMS
NOISE
Common-Mode
Rejection Ratio
V
0V
= -10V to +10V. Differential input is
CM
CMRR
PSRR
72
dB
DC, V
DC, V
= +5V to +24V
= -24V to -5V
100
100
HVDD
HVSS
Supply-Rejection Ratio
Input Current
dB
nA
I
±30
IN
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Maxim Integrated | 8
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Electrical Characteristics (continued)
(V
= V
= 3.3V, V
= +15V, V
= -15V, Reference Source = Internal Reference, T = T
to T
, unless otherwise
AVDD
DVDD
HVDD
HVSS
A
MIN
MAX
noted. Typical values are at T = +25ºC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
87
TYP
MAX
UNITS
DCHNL_RATE[3:0] = 0b0010, 0b0011,
0b0100, 0b0101
50Hz/60Hz Normal-
Mode Rejection
dB
DCHNL_RATE[3:0] = 0b0000, 0b0001
75
From AI_ to V
2
2
Open-Detector
Resistance
HVDD
MΩ
ms
From AI_ to AGND
V
IN
changes from 0V to -10.5V or 0V to
+10.5V, digital output reaches 1% of final
value. ADC sample rate is 57.6ksps; ADC
mode is Continuous.
Settling Time
0.2
ADC REFERENCE (REF_ADC)
REF_ADC Output
Voltage
V
Internal reference
2.5
1
V
REF_ADC
Output-Voltage
Accuracy
Referred to V
, T = +25°C
A
-0.2
+0.2
%
REF_ADC
Output-Voltage
Temperature Coefficient
T
A
= -40°C to +125°C (Note 3)
5
ppm/°C
µV/V
µF
Line Regulation
2.7V ≤ V
≤ 3.6V
130
AVDD
REF_ADC Bypass
Capacitor
4.7
2.5
V
Input
REF_ADC_EXT
External Reference
V
Range
DIGITAL INPUTS
0.3 ×
Input Logic-Low Voltage
V
V
V
IL
V
DVDD
0.7 ×
Input Logic-High Voltage
V
IH
V
DVDD
Input Hysteresis
V
200
10
mV
µA
pF
HYS
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS
I
-1
+1
IN
C
IN
Output Logic-Low
Voltage
V
I
I
= 4mA
= 4mA
0.4
V
V
OL
OL
Output Logic-High
Voltage (SDO, RDYB,
GPIO[7:0])
0.9 ×
V
OH
OH
V
DVDD
Three-State Leakage
Current
-10
+10
µA
pF
Three-State Output
Capacitance
10
SUPPLIES
Analog Supply Voltage
Digital Supply Voltage
V
V
2.7
2.7
3.3
3.3
3.6
3.6
V
V
AVDD
DVDD
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Maxim Integrated | 9
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Electrical Characteristics (continued)
(V
= V
= 3.3V, V
= +15V, V
= -15V, Reference Source = Internal Reference, T = T
to T
, unless otherwise
AVDD
DVDD
HVDD
HVSS
A
MIN
MAX
noted. Typical values are at T = +25ºC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
24
UNITS
Positive High-Voltage
Supply
V
5
V
HVDD
Negative High-Voltage
Supply
V
-24
10
-5
V
HVSS
High-Voltage Supply
DVDD POR Threshold
V
V
- V
HVSS
48
V
V
HV
HVDD
V
Voltage rising
1.5
1.5
DVDD_POR
HVDD-HVSS
Undervoltage Threshold
Voltage rising
V
ADC sample rate is 11.52ksps, ADC
mode is Continuous Single-Cycle. Single-
ended AI1–AI12 at AGND
Analog Supply Current
Digital Supply Current
I
4.5
1.8
2.5
mA
AVDD
ADC sample rate is 11.52ksps, ADC
mode is Continuous Single-Cycle. Single-
ended AI1–AI12 at AGND
I
mA
mA
DVDD
ADC sample rate is 11.52ksps, ADC
mode is Continuous Single-Cycle. Single-
ended AI1–AI12 at AGND
High-Voltage Supply
Current
I
HV
ADC sample rate is 11.52ksps, ADC
mode is Continuous Single-Cycle. Single-
ended AI1–AI12 at AGND
95.8
45.8
Total Power
mW
AI1–AI12 at AGND, V
= 5V and
HVDD
V
HVSS
= -5V, all inputs are on
TIMING CHARACTERISTICS
SCLK Frequency
f
All SPI transactions
All SPI transactions
All SPI transactions
All SPI transactions
30
MHz
ns
SCLK
SCLK Clock Period
t
33
13
13
CP
CH
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
ns
t
ns
CL
CS falling edge to 1st SCLK rising edge
setup time
CS Fall Setup Time
CS Fall Hold Time
CS Rise Hold Time
t
7
0
3
ns
ns
ns
CSS0
CSH0
CSH1
SCLK rising edge to CS falling edge hold
time
t
t
SCLK falling edge to CS rising edge hold
time
CS Pulse-Width High
SDI Setup Time
SDI Hold Time
t
Minimum CS pulse-width high
150
5
ns
ns
ns
CSW
t
SDI setup time to SCLK rising edge
SDI hold time after SCLK rising edge
DS
DH
t
5
SDO transition valid after SCLK falling
edge
SDO Transition Time
SDO Hold Time
t
20
25
ns
ns
ns
DOT
DOH
DOD
Output remains valid after falling edge of
SCLK
t
t
2
CS rising edge to SDO disable, C
20pF
=
LOAD
SDO Disable Time
Note 1: Limits are 100% tested at T = +25°C, unless otherwise noted. Limits over the operating temperature range and relevant
A
supply-voltage range are guaranteed by design and characterization.
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Maxim Integrated | 10
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Note 2: Offset error, gain error, INL error, TUE, and settling times are only guaranteed in the linear range. The minimum and maximum
specification of the linear range are guaranteed through offset, gain, INL error, and TUE.
Note 3: Guaranteed by design and characterization. Not tested in production.
Note 4: FSR stands for full-scale range. It is 25V in single-ended mode and 50V in differential mode.
t
t
t
t
t
t
t
t
t
CSW
CSH0 CSS0
CH CL
CP
DS
DH
CSH1
CS
SCLK
SDI
1
2
3
4
5
6
7
8
9
10
11
N+6
N+7
N+8
W
A
A
A
A
A
A
A
D
D
N-2
D
D
2
D
1
D
0
6
5
4
3
2
1
0
N-1
N-3
HIGH-Z
SDO
Figure 1. SPI Write Timing (N = 24 when CRC is Disabled and N = 32 when CRC is Enabled)
t
t
t
t
t
t
t
t
t
CSW
CSH0 CSS0
CH CL
CP
DS
DH
CSH1
CS
SCLK
SDI
1
2
3
4
5
6
7
8
9
10
11
N+6
N+7
N+8
R
A
A
A
A
A
A
A
0
6
5
4
3
2
1
tDOT
t
t
DOD
DOH
HIGH-Z
HIGH-Z
SDO
D
N-1
D
N-2
D
N-3
D
D
D
0
2
1
Figure 2. SPI Read Timing (N = 24 when CRC is Disabled and N = 32 when CRC is Enabled)
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Maxim Integrated | 11
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Typical Operating Characteristics
(V
= V
= +3.3V, V
= +15V, V
= -15V, T = +25°C, unless otherwise noted.)
AVDD
DVDD
HVDD
HVSS A
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Maxim Integrated | 12
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Typical Operating Characteristics (continued)
(V
= V
= +3.3V, V
= +15V, V
= -15V, T = +25°C, unless otherwise noted.)
HVSS A
AVDD
DVDD
HVDD
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Maxim Integrated | 13
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Pin Configuration
MAX22005
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
+
AI8
AI7
1
INT
36
35
34
33
32
31
30
29
28
27
26
25
2
SDI
AI6
3
4
5
6
7
8
9
SDO
SCLK
CS
AI5
AI4
AI3
DVDD
AVDD
AGND
I.C.
MAX22005
AI2
AI1
HVDD
HVSS 10
AGND 11
AVDD 12
I.C.
RDY
CLK
13
14
15
16
17
18
19
20
21
22
23
24
LGA
7.5mm x 7.0mm
Pin Description
PIN
NAME
FUNCTION
ANALOG INPUTS
1
2
3
AI8
AI7
AI6
Analog Input 8
Analog Input 7
Analog Input 6
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Maxim Integrated | 14
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Pin Description (continued)
PIN
NAME
AI5
FUNCTION
4
Analog Input 5
Analog Input 4
Analog Input 3
Analog Input 2
Analog Input 1
Analog Input 12
Analog Input 11
Analog Input 10
Analog Input 9
5
AI4
6
AI3
7
AI2
8
45
AI1
AI12
AI11
AI10
AI9
46
47
48
POWER
Positive High-Voltage Power Supply for the Input Path, +5V to +24V. Bypass HVDD to AGND
through a 1µF capacitor.
9
HVDD
Negative High-Voltage Power Supply for the Input Path, -5V to -24V. Bypass HVSS to AGND
through a 1µF capacitor.
10
HVSS
AGND
AVDD
11, 13, 29
12, 30
Analog Ground. Connect all AGND pins together.
Analog Power Supply, 2.7V to 3.6V. Connect all AVDD together. Bypass each AVDD through a
1μF ceramic capacitor to AGND.
Digital Power Supply, 2.7V to 3.6V. Connect all DVDD together. Bypass each DVDD pin through a
1μF ceramic capacitor to DGND.
21, 31
24
DVDD
DGND
Digital Ground
REFERENCE AND INTERFACE
Voltage Reference Noise Reduction. Bypass NR through a 1µF ceramic capacitor to AGND to
improve wideband noise.
14
15, 16, 27, 28
17
NR
I.C.
Internally Connected. Connect to AGND for proper use.
REF_ADC_E
XT
ADC External Voltage-Reference Input. Connect to AGND if not used.
Voltage Reference Output. Bypass REF_OUT through a (0.1μF || 1μF) ceramic capacitor to
AGND.
18
19
REF_OUT
REF_ADC
ADC Voltage Reference-Buffered Output. Bypass REF_ADC through a 4.7μF ceramic capacitor to
AGND.
ADC Synchronization Input. SYNC resets the ADC modulator and digital filters. Connect SYNC of
multiple MAX22005s in parallel to synchronize their ADCs to an external trigger and external clock.
Connect SYNC to DGND if not used.
20
SYNC
22
23
25
BYP_ADC
RST
1.8V Sub-Regulator Output. Bypass BYP_ADC through a 220nF or larger capacitor to DGND.
Active-Low Reset Input. Keep RST high for normal operation.
CLK
External Clock Input. Connect to DGND if not used.
Active-Low Data Ready Output. RDY goes low when a new ADC conversion result is available in
the data register. When a read operation of a full output word completes, RDY returns high. RDY is
always driven.
26
RDY
32
33
34
35
36
CS
SCLK
SDO
SDI
Active-Low SPI Chip-Select Input
SPI Serial Clock Input
SPI Serial Data Output
SPI Serial Data Input
INT
Interrupt Output. INT is an open-drain active-low output.
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Maxim Integrated | 15
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Pin Description (continued)
PIN
NAME
FUNCTION
GPIO PORTS
37
38
39
40
41
42
43
44
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
General Purpose I/O 0
General Purpose I/O 1
General Purpose I/O 2
General Purpose I/O 3
General Purpose I/O 4
General Purpose I/O 5
General Purpose I/O 6
General Purpose I/O 7
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Maxim Integrated | 16
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Detailed Description
The MAX22005 is an industrial-grade configurable analog-input solution. The MAX22005 offers twelve single-ended
inputs, six pairs of adjacent differential inputs, or eight multifunctional differential pairs defined around four triplets of
inputs. A triplet of inputs is shown in Figure 3. The port INA would be the “common” input, while INC and the middle port,
INB, would be the other two ports defining the triplet of inputs.
The pairing of ports are illustrated in Figure 4. The inputs highlighted in yellow are the common inputs (COM).
The MAX22005 provides a high-performance 24-bit delta-sigma ADC in the receive path. A high-performance decimation
filter following the ADC provides a minimum of 87dB rejection for 50Hz/60Hz at select ADC data rates. The device
includes a high-performance 5ppm/°C (max) voltage reference on-chip. However, external references can optionally be
used.
5kΩ
5kΩ
5kΩ
LONG CABLE
LONG CABLE
INA
INB
INC
INA
INB
INC
ONE TRIPLET
CHANNEL
HIGH-VOLTAGE
SIGNAL
250Ω
OUT TO
ADC
PROCESSING
Figure 3. Input Port Triplet
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Maxim Integrated | 17
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
DIFFERENTIAL PAIRS
MULTIFUNCTIONAL DIFFERENTIAL PAIRS
AI1
AI2
AI3
AI4
AI5
AI6
AI7
AI8
AI9
AI10
AI11
AI12
Figure 4. Input Ports Pairs
Modes of Operation
The MAX22005 offers the following modes of operation:
● 12 single-ended analog inputs
● 6 differential analog inputs
● 8 multifunctional differential analog inputs
Switching among those modes does not require changing the printed circuit board (PCB). The inputs can be configured
for analog input-voltage mode (AIVM) or analog input-current mode (AICM). Current measurements by the MAX22005
rely on an external precision resistor to convert the current to voltage. For current measurements, one can use any odd
channel input and its sense port. The integrated GPIO port can control an external analog switch to connect or disconnect
the current-sense resistor electronically (refer to Figure 3). The external switches do not need to be accurate since the
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Maxim Integrated | 18
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
current measurement is performed differentially. We recommend 2.5Ω low voltage CMOS switches.
The MAX22005 supports two-wire configuration for all single-ended and differential inputs, and three-wire configuration
for multifunctional differential inputs, which could be used, for example, for a resistance temperature detector (RTD)
connection. Refer to AN7413 for other possible configuration options.
Input Range Settings
To maintain best accuracy, the MAX22005 provides multiple voltage ranges for its inputs.
Table 1 summarizes available ranges. The nominal range specifies the range for the intended application. The linear
range encompasses the nominal range, where performance specifications such as gain error, offset error, INL, PSRR,
and CMRR are still guaranteed. Even wider, the full-scale range sets the conversion limits of the data converter. This
extended range defines the input-voltage limits that can be converted without clipping the ADC.
The MAX22005 sets the linear range at 105% of the nominal range, and the full-scale range at 125% of the nominal
range. For example, for a ±10V nominal range, the MAX22005 provides a linear range of ±10.5V and a full-scale range
of ±12.5V.
Table 1. Input Ranges
MODE
AIVM
AICM
SETTING
NOMINAL
±10V
LINEAR
±10.5V
±21mA
FULL SCALE
±12.5V
±12.5V
±25mA
±20mA
±25mA
Differential-Input Common-Mode Range
If the signal amplitude is less than the full-scale range of an input, the MAX22005 permits a greater input common-mode
range.
The maximum allowed input common-mode range is calculated as follows:
V
CM
= 25 - V
DIFF
where,
V
V
= Maximum input common-mode range
CM
= Peak-to-peak input voltage
DIFF
Input-Voltage Rating
All high-voltage analog inputs are ±36V tolerant with respect to AGND. In general, the following scenario at an analog
input is depicted in Figure 5. Every analog input must have a series 5kΩ protection resistor. As long as the supply
voltages at HVSS and HVDD are actively driven, the voltage at the MAX22005 input pin does not swing more than one
diode voltage drop above HVDD or below HVSS. Since the series resistor limits the current, the diode voltage drop is
small.
If one of the DC-DC converter malfunctions and is no longer capable of sinking or sourcing current, then the resistive
feedback network around the DC-DC converter can be used to effectively protect the input pin of the MAX22005. It is
the engineer’s responsibility to design the total resistance R
of the current path such that the voltages at the analog
PATH
input pins of MAX22005 do not exceed their voltage ratings.
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Maxim Integrated | 19
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
MAX22005
HVDD
DC-DC
CONVERTER
ESD DIODE
R
PATH
5kΩ
EXTERNAL
INPUT
ESD DIODE
DC-DC
CONVERTER
HVSS
Figure 5. Input Protection
Supply Voltages and Power-Supply Sequencing
The MAX22005 has three independent supplies: a low-voltage analog supply (AVDD, AGND), a low-voltage digital supply
(DVDD, DGND), both specified at 2.7V to 3.6V, and an analog bipolar high-voltage supply (HVDD, HVSS for the input
AFE). For the high-voltage AFE to operate properly, the V
supply needs to be less than or below -5V and the V
HVSS
HVDD
supply needs to be greater than or equal to 5V. For ±12V inputs, at least V
= -15V and V
= 15V are required.
HVDD
HVSS
The three supplies pairs (AVDD/AGND, DVDD/DGND, HVDD/HVSS) can be powered up in any order.
Power-On Reset
The AVDD and DVDD supplies are monitored by power-on reset circuitry. The MAX22005 is held in a reset state until
the AVDD and DVDD supplies have reached a certain threshold that allows safe operations without loss of data. Once
this threshold is exceeded, the SPI interface and low-voltage circuitry are fully functional. The high-voltage supply is also
constantly monitored. The MAX22005 needs only the AVDD and DVDD supplies to communicate over the SPI interface.
With AVDD and DVDD powered, loss of the high-voltage supply is reported through the HVDD_INT bit in the GEN_INT
register.
SPI Interface
An SPI interface allows communication of all important information between a microprocessor and the MAX22005. An
optional CRC enhances confidence in the data communicated to and from the MAX22005. This feature, disabled by
default after a hardware reset or power-up (but not a software reset), can be enabled or disabled at any time through the
SPI interface.
The SPI transactions are 40-bits long if CRC is enabled as shown in Table 2. If CRC is disabled, the SPI transactions are
32-bits long, as shown in Table 3.
Table 2. SPI Transaction with CRC Enabled
BITS 39:33
BIT 32
BITS 31:8
BITS 7:0
Register Address
R/W
24-bit Payload
CRC
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Maxim Integrated | 20
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Table 3. SPI Transaction with CRC Disabled
BITS 31:25
BIT 24
BITS 23:0
Register Address
R/W
24-bit Payload
8
5
4
0
The MAX22005 implements the CRC-8/MAXIM algorithm with an 0x31 polynomial (x + x + x + x ), the same
polynomial that is used in Maxim’s 1-wire® products. This CRC algorithm uses reflected input and output bytes (i.e., LSB
first instead of MSB first on a byte basis; the byte order of the input sequence is not changed). The initial value is 0x00,
and the output is reported as is without any XOR operation.
This CRC can detect the following types of errors:
● Any odd number of errors anywhere within the 32-bit number
● All double-bit errors anywhere within the 32-bit number
● Any cluster of errors that can be contained within an 8-bit window (1–8 bits incorrect)
● Most large clusters of errors
For write transactions, the CRC is calculated on the 32 bits that precede it, namely the 7-bit register address, 1-bit read
or write control, and the 24-bit payload.
Here are two examples of write operations:
Write 0x00_0F00 to register GEN_CHNL_CTRL: 0x06_000F_0011
Write 0x34_0000 to register CHNL_CMD: 0x40_3400_00A0
For read transactions, the CRC sent by the MAX22005 back to the host is calculated on 32 bits made of the 8-bit header
received from the host (register address and read control) and the 24 bits of payload.
Here are two examples of read operations:
Read the default value from register GEN_CNFG: 0x05_1000_00CB
Read the default value from register DCHNL_STA: 0x43_0000_08AA
CRC is disabled by default. Refer to AN27 for more details.
Watchdog Timer
The MAX22005 features a watchdog timer for additional security of losing communication with the host controller.
The watchdog can be enabled in the GEN_CNFG register (0x02) by setting the TMOUT_EN bit and setting up the
TMOUT_CNFG, and TMOUT_SEL[3:0] bits for a desired interrupt behavior and timeout duration. The interrupt is
asserted on the INT pin and in TMOUT_INT bit in the GEN_INT register (0x07) if the duration between two properly
formatted SPI transactions exceeds the timeout period. A properly formatted transaction is a transaction that has a
minimum of 32 bits (if CRC is disabled) or 40 bits (if CRC is enabled). A properly formatted transaction is always
accounted for at the end of the transaction. Refer to the Register Map descriptions for more information.
Product Tracking
The MAX22005 includes a 32-bit wide unique serial number used for device tracking (SERIAL[32:0] in registers
GEN_PROD and GEN_REV).
In addition, an eight-bit product ID that helps to distinguish different parts of the industrial I/O family (PROD_ID[7:0] in
register GEN_PROD). The product ID can be decoded as follows:
Table 4. Product ID
BIT 7
6
5
4
3
2
1
0
Number of output Channels
Number of Input Channels
RTD/TC Support
The MAX22005 can accept up to 12 input channels; the product ID is 0x18.
The revision of the silicon is reflected in the eight-bit revision ID (REV_ID[7:0] in register GEN_REV).
Analog Input ADC
The analog input channels share one high-performance 24-bit delta-sigma analog-to-digital converter (ADC). The data
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Maxim Integrated | 21
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
rate is programmable from 1sps (samples per second) to 115.2ksps. The ADC can utilize either the internal 2.5V
reference or an external reference. The ADC services a total of 26 input configurations, which are selectable through bits
AI_DCHNL_SEL[4:0] in register GEN_CHNL_CTRL. Table 5 summarizes the channel selection options.
Table 5. Input-Channel Configuration Selection
AI_DCHNL_SEL[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
INPUT CONFIGURATION
Input AI1 in single-ended mode (-12.5V to +12.5V range)
Input AI2 in single-ended mode (-12.5V to +12.5V range)
Input AI3 in single-ended mode (-12.5V to +12.5V range)
Input AI4 in single-ended mode (-12.5V to +12.5V range)
Input AI5 in single-ended mode (-12.5V to +12.5V range)
Input AI6 in single-ended mode (-12.5V to +12.5V range)
Input AI7 in single-ended mode (-12.5V to +12.5V range)
Input AI8 in single-ended mode (-12.5V to +12.5V range)
Input AI9 in single-ended mode (-12.5V to +12.5V range)
Input AI10 in single-ended mode (-12.5V to +12.5V range)
Input AI11 in single-ended mode (-12.5V to +12.5V range)
Input AI12 in single-ended mode (-12.5V to +12.5V range)
Inputs AI1–AI2 in differential mode (-25.0V to +25.0V range)
Inputs AI3–AI4 in differential mode (-25.0V to +25.0V range)
Inputs AI5–AI6 in differential mode (-25.0V to +25.0V range)
Inputs AI7–AI8 in differential mode (-25.0V to +25.0V range)
Inputs AI9–AI10 in differential mode (-25.0V to +25.0V range)
Inputs AI11–AI12 in differential mode (-25.0V to +25.0V range)
Inputs AI1(COM)–AI2 in multifunctional differential mode (-25.0V to +25.0V range)
Inputs AI1(COM)–AI3 in multifunctional differential mode (-25.0V to +25.0V range)
Inputs AI4(COM)–AI5 in multifunctional differential mode (-25.0V to +25.0V range)
Inputs AI4(COM)–AI6 in multifunctional differential mode (-25.0V to +25.0V range)
Inputs AI7(COM)–AI8 in multifunctional differential mode (-25.0V to +25.0V range)
Inputs AI7(COM)–AI9 in multifunctional differential mode (-25.0V to +25.0V range)
Inputs AI10(COM)–AI11 in multifunctional differential mode (-25.0V to +25.0V range)
Inputs AI10(COM)–AI12 in multifunctional differential mode (-25.0V to +25.0V range)
The ADC results are stored in register DCHNL_DATA in two’s complement format. Table 6 summarizes the ADC output
codes and corresponding input voltages.
Table 6. Input-Channel Limit Values and Codes
AI_DCHNL_SEL[4:0]
INPUT CHANNEL
ADC CODE
0x800000
(-8388608) (V)
ADC CODE
0x000000
(0) (V)
ADC CODE
0x7FFFFF
(+8388607) (V)
00000
00001
00010
00011
00100
00101
00110
AI1 single-ended
AI2 single-ended
AI3 single-ended
AI4 single-ended
AI5 single-ended
AI6 single-ended
AI7 single-ended
-12.5
-12.5
-12.5
-12.5
-12.5
-12.5
-12.5
0
0
0
0
0
0
0
+12.5
+12.5
+12.5
+12.5
+12.5
+12.5
+12.5
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Maxim Integrated | 22
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Table 6. Input-Channel Limit Values and Codes (continued)
AI_DCHNL_SEL[4:0]
INPUT CHANNEL
ADC CODE
0x800000
(-8388608) (V)
ADC CODE
0x000000
(0) (V)
ADC CODE
0x7FFFFF
(+8388607) (V)
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
AI8 single-ended
AI9 single-ended
-12.5
-12.5
-12.5
-12.5
-12.5
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
-25.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
+12.5
+12.5
+12.5
+12.5
+12.5
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
+25.0
AI10 single-ended
AI11 single-ended
AI12 single-ended
AI1–AI2 differential
AI3–AI4 differential
AI5–AI6 differential
AI7–AI8 differential
AI9–AI10 differential
AI11–AI12 differential
AI1(COM)–AI2 multifunctional differential
AI1(COM)–AI3 multifunctional differential
AI4(COM)–AI5 multifunctional differential
AI4(COM)–AI6 multifunctional differential
AI7(COM)–AI8 multifunctional differential
AI7(COM)–AI9 multifunctional differential
AI10(COM)–AI11 multifunctional differential
AI10(COM)–AI12 multifunctional differential
The mode of operation is selected using the DCHNL_MODE[1:0] bits in register DCHNL_CMD. By default, the ADC is in
standby mode to reduce the overall power consumption.
The delta-sigma modulator is followed by a chain of high-performance digital filters, consisting of a fifth-order SINC filter,
an averaging filter, and a fourth-order SINC filter, depending on the data rate chosen. Several data rates offer at least
75dB of 50Hz or 60Hz suppression.
The ADC offers three conversion modes of operation: continuous mode, single-cycle mode, and continuous single-cycle
mode.
In continuous mode, the ADC operates continuously at the selected sample rate. Based on the data rate, the digital
filter requires up to five output samples to settle. This mode is used when data from a single channel is collected, and a
high sample rate is desired.
Single-cycle mode offers a single-cycle no-latency conversion, after which the ADC goes back into standby mode. This
mode is used when single measurements on several channels are made, and a moderate sample rate is required.
In continuous single-cycle mode the ADC performs continuous no-latency conversions at the selected rate. This mode
is used if continuous monitoring of one channel is required, but settling of the digital filters should be masked. This is
useful in the case if a quick settling after a change in the input is desired, but the increased data rate in continuous mode
is not required.
The modes of operation are selected using bits SCYCLE and CONTSC in register DCHNL_CTRL1. Continuous mode
and continuous single-cycle mode can be exited by changing the DCHNL_MODE[1:0] bits in register DCHNL_CMD
to standby mode. In addition, any change to the input channel selection (bits AI_DCHNL_SEL[4:0] in register
GEN_CHNL_CTRL), the ADC control registers (DCHNL_CTRL1, DCHNL_CTRL2) also abort any ongoing continuous
conversion and return the ADC to standby mode.
The available data rates are selected by setting bits DCHNL_RATE[3:0] in register DCHNL_CMD. Table 7 summarizes
the data rates that are available in continuous mode. The data rates in bold offer 50Hz and/or 60Hz suppression in excess
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Maxim Integrated | 23
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
of 75dB. Note that system calibration correction cannot be selected for the highest data rate.
Table 7. Selection of Data Rates for Continuous Conversion
DCHNL_RATE[3:0]
DATA RATE (SPS)
EFFECTIVE NUMBER OF BITS
0000
5
10
21
21
21
20
20
20
19
19
19
18
18
18
17
17
17
16
0001
0010
15
0011
30
0100
50
0101
60
0110
225
0111
450
1000
900
1001
1800
3600
7200
14400
28800
57600
115200 (Note)
1010
1011
1100
1101
1110
1111
Note: System calibration is not supported with the highest data rate.
Table 8 shows the data rates available in single-cycle mode. Operation in single-cycle mode requires an overhead at
the beginning of a conversion to allow the analog front-end of the ADC to settle. In addition, time is required to process
the raw modulator output. The nominal data rate is shown in Table 8, as it is an indication of the sampling period of the
input signal. The actual data rate depends on whether system calibration is used or not, as the computational overhead
is different in the two cases. The data rates in bold offer 50Hz and/or 60Hz suppression in excess of 75dB.
Table 8. Selection of Data Rates for Single-Cycle Conversion
DCHNL_RATE[3:0]
NOMINAL DATA
RATE (sps)
ACTUAL DATA
RATE (sps)
ACTUAL DATA RATE PLUS SYSTEM
CALIBRATION (sps)
EFFECTIVE
NUMBER OF BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1 (0.9955)
2.5
1 (0.9955)
2.5
1 (0.9955)
2.5
21
21
21
20
20
20
19
19
19
18
18
18
17
17
17
16
5
5
5
10
10
10
12.5
15
12.5
15
12.5
15
50
50
50
60
60
60
150
150
150
300
299
298
900
891
886
1800
2880
5760
11520
23040
1772
2810
5486
10473
19200
1752
2759
5297
9804
17067
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Maxim Integrated | 24
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Table 9 shows the data rates available in single-cycle continuous mode. The single-cycle continuous mode operation is
similar to single-cycle mode, but the overhead is slightly different, and therefore the actual data rates differ slightly as
well. Again, the data rates in bold offer 50Hz and/or 60Hz suppression in excess of 75dB.
Table 9. Selection of Data Rates for Single-Cycle Continuous Conversion
DCHNL_RATE[3:0]
NOMINAL DATA
RATE (sps)
ACTUAL DATA
RATE (sps)
ACTUAL DATA RATE PLUS SYSTEM
CALIBRATION (sps)
EFFECTIVE
NUMBER OF BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1 (0.9955)
2.5
1 (0.9955)
2.5
1 (0.9955)
2.5
21
21
21
20
20
20
19
19
19
18
18
18
17
17
17
16
5
5
5
10
10
10
12.5
15
12.5
15
12.5
15
50
50
50
60
60
60
150
150
150
300
299
299
900
892
887
1800
2880
5760
11520
23040
1776
2818
5519
10593
19609
1755
2768
5327
9910
17389
The ADC offers a status bit to signal an overrange condition. If the output of the digital filter overflows, bit DOR in register
DCHNL_STA is set to logic high. In this case, the digital output is set to 0x7FFFFF if a positive overflow occurs, or to
0x800000 if a negative overflow occurs.
Analog Input Offset and Gain Error Calibration
System Calibration
The MAX22005 is factory calibrated to satisfy its TUE specification. However, the user is able to perform their own
system-level calibration to eliminate gain and offset errors of the entire analog input signal chain, including board level
components. A two-point measurement algorithm can be used to calculate and correct the system level offset and gain
error. Separate pairs of offset and gain correction registers are provided in the MAX22005 for each of the 26 input
configurations. The two-point calibration to calculate both gain and offset coefficients is depicted in Figure 6. Refer to
AN7449 "MAX22005 User Calibration Guide" for more information.
Before attempting a user/system calibration, the offset and gain calibration registers (DCHNL_N_SOC and
DCHNL_N_SGC) of the respective channel should be set to 0x00_0000 and 0xC0_0000, respectively.
Two input voltages V and V that are close to the application full-scale range must be applied, and the corresponding
1
2
digital output codes C and C , respectively, are recorded.
1
2
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Maxim Integrated | 25
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
OUTPUT CODE
IDEAL TRANSFER
CHARACTERISTIC
C
1
V
2
INPUT VOLTAGE
V
1
C
2
Figure 6. Two Point System Calibration
The gain A of the input channel can then be calculated as follows:
C − C
1
2
(
) × V
FSR
24
2
A =
(V − V )
1
2
where V
10.
is the full-scale range of the input channel selected. The full-scale range for each channel is shown in Table
FSR
Table 10. Full-Scale Range of Input Channels
AI_DCHNL_SEL[4:0]
INPUT CHANNEL
FULL_SCALE
DIGITAL GAIN
DIGITAL SIGN
RANGE V
A
S
FSR
DIG
DIG
(V)
00000
00001
00010
00011
00100
00101
AI1 single-ended
AI2 single-ended
AI3 single-ended
AI4 single-ended
AI5 single-ended
AI6 single-ended
25
2
2
2
2
2
2
+1
-1
25
25
25
25
25
-1
+1
+1
-1
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Maxim Integrated | 26
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Table 10. Full-Scale Range of Input Channels (continued)
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
AI7 single-ended
25
25
25
25
25
25
50
50
50
50
50
50
50
50
50
50
50
50
50
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
+1
-1
AI8 single-ended
AI9 single-ended
-1
AI10 single-ended
+1
+1
-1
AI11 single-ended
AI12 single-ended
AI1–AI2 differential
+1
-1
AI3–AI4 differential
AI5–AI6 differential
+1
+1
-1
AI7–AI8 differential
AI9–AI10 differential
AI11–AI12 differential
+1
+1
+1
+1
+1
+1
+1
+1
AI1(COM)–AI2 multifunctional differential
AI1(COM)–AI3 multifunctional differential
AI4(COM)–AI5 multifunctional differential
AI4(COM)–AI6 multifunctional differential
AI7(COM)–AI8 multifunctional differential
AI7(COM)–AI9 multifunctional differential
AI10(COM)–AI11 multifunctional
differential
11000
11001
AI10(COM)–AI12 multifunctional
differential
50
2
+1
The gain calibration coefficient can now be calculated by dividing the default gain calibration coefficient by the calculated
gain:
gain calibration coefficient = 1.5/A.
The result is expressed in unsigned binary format with a fraction length of 23 bits and loaded into the appropriate
DCHNL_N_SGC register.
The input-referred offset can be calculated as
C × V
1
FSR
V
=
− A × V
1
OFFSET
24
2
In order to calculate the offset calibration coefficient, the digital gain A
and the sign S
of the signal chain needs
DIG
DIG
to be taken into account. Both gain and sign are summarized in Table 9. With this information the offset calibration
coefficient DCHNL_N_SOC can be calculated as follows:
V
S
1
DIG
×
1.5 × A
24
DCHNL_N_SOC = C − A ×
× 2
1
(
V
)
FSR
DIG
The resulting value of DCHNL_N_SOC must be expressed in two's complement format.
The calculated calibration coefficients are stored in registers DCHNL_N_SOC for the offset calibration coefficient, and
DCHNL_N_SGC for the gain calibration coefficient, respectively. These registers are selectable using indirect addressing
(see the DCHNL_N_SEL register).
By default, the raw ADC output data is corrected using the system gain and offset calibration coefficients. However, the
correction can be disabled using bits NOSYSG and NOSYSO bits in register DCHNL_CTRL2.
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Maxim Integrated | 27
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
ADC Software Reset
The host can issue a software reset to restore the default state of the ADC. A software reset sets the DCHNL_ registers
back into their default states and resets the internal state machines. However, a software reset does not execute the
complete power-on reset or hardware reset sequence. A software reset is, thus, not effective if e.g., the SPI interface
does not respond.
Two SPI transactions are required to issue a software reset: first, bit DCHNL_PD in register DCHNL_CTRL1 must be set
to logic high (reset). Then a write transaction to register DCHNL_CMD must be issued with DCHNL_MODE[1:0] set to
‘01’.
To confirm the completion of the reset operation, bits PDSTAT[1:0] in register DCHNL_STA must be monitored. While
the ADC is in its reset phase, PDSTAT[1:0] is set to ‘11’ (reset). After the reset operation is complete, PDSTAT[1:0] is set
to ‘10’ (standby). It is usually not required to monitor the reset (‘11’) state. Polling for standby mode (‘10’) is sufficient.
ADC RDY (Data Ready) Output
RDY indicates the ADC conversion status and the availability of the conversion result. When RDY is low, a conversion
result is available. When RDY is high, a conversion is in progress, and the data for the current conversion is not available.
RDY is driven high after a complete read of the DCHNL_DATA register. If the data is read after each sample becomes
available, RDY transitions from high-to-low at the output data rate. If the previous data was not read, then RDY transitions
from low-to-high approximately 0.5µs before new data becomes available. A falling edge on RDY then indicates the
availability of new data. In continuous mode, RDY remains high for the first four conversion results and on the 5th result,
RDY goes low to indicate valid data.
CONVERT COMMANDS
CS/SCLK/SDI
t
CNV
tCNV
a)
RDY
DATA NOT RETRIEVED
t
CNV
DATA
RETRIEVED
b)
c)
RDY
RDY
t
CNV
5 tCNV
Figure 7. RDY Output Timing, a) Single-Cycle Mode, b) Continuous Single-Cycle Mode, c) Continuous Conversion Mode
ADC Conversion Synchronization Using the SYNC Pin
The MAX22005 incorporates a highly stable internal oscillator, providing a nominal system clock of 7.3728MHz
(8.192MHz x 0.9) for both analog and digital timing. Optionally, a highly stable external clock can be used. The SYNC
pin, ideally in conjunction with an external clock, can be used to synchronize the data conversions to external events.
Although the synchronization method also works with an internal clock, resynchronization is inevitable due to local
oscillators with limited frequency accuracy. A highly stable external clock that can be shared by multiple MAX22005s
allows for much longer time intervals without the requirement of resynchronization.
Set bit SYNC_MODE in register DCHNL_CTRL2 to logic high to enable external synchronization mode. Also, SCYCLE
in register DCHNL_CTRL1 must be set to logic zero, as SYNC_MODE is operational only for the continuous conversion
mode. Optionally, set bit EXTCLK in register DCHNL_CTRL2 to logic high to use a highly accurate external clock signal.
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Maxim Integrated | 28
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
The synchronization mode is used to detect if the current conversions are synchronized to a continuous-pulse signal
with a period greater than the data rate. The pulse-width of the synchronization signal is not critical, as only the rising
edge of the synchronization pulse is used as a timing reference. The pulse-width, however, must be longer than 300ns if
the internal clock source is used, and longer than twice the clock period if an external clock source is used. In addition,
the low time of the SYNC signal between consecutive SYNC pulses must be longer than 300ns if the internal clock
source is used, and longer than twice the clock period if an external clock source is used. Ideally, the frequency of the
synchronization signal is an integer multiple of the conversion rate. The synchronization mode records the number of
ADC clock cycles between a falling edge of RDY and the rising edge of the next SYNC pulse. At the following SYNC
pulse, the number of ADC clock cycles between a falling edge of RDY and the rising edge of the SYNC pulse is evaluated
again and compared to the recorded value. If the new number of ADC clock cycles differs by more than one from the
recorded value, the conversion in progress is stopped, the digital filter contents are reset, and a new conversion starts.
As the digital filter is reset, the full digital filter latency is required before valid results are available. If the new ADC clock
count is within the ±1 count limit, the conversions continue uninterrupted.
Figure 8 shows the timing relationship between the MAX22005 ADC clock and the SYNC signal. Due to startup delays,
any SYNC pulses before the first falling edge of RDY are ignored. The first rising edge on the SYNC pin after a falling
edge of RDY establishes the relationship between the SYNC signal and the conversion timing.
FIRST VALID
SYNC
> 2xt
> 2xt
CLK
IGNORED
CLK
SYNC SIGNAL
RDY
FIRST
CONVERSION
READY
N
N’
CLK
...
t
CLK
PART INITIATES A RESET AND RESTARTS CONVERSIONS WHEN N AND N’ DIFFER BY
MORE THAN ±1 CLK COUNT. OTHERWISE, CONVERSIONS CONTINUE UNINTERRUPTED.
Figure 8. SYNC Input Timing
Hardware Reset
The MAX22005 features an active-low RST pin to perform a hardware reset. Pulling the RST pin low reconfigures all
registers to the power-on reset state. All analog inputs are disconnected. Any ADC conversion in progress is stopped,
and the digital filters are reset. When RST goes back to logic “1,” the part behaves the same way as when power is first
applied.
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Maxim Integrated | 29
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Register Map
MAX22005 Register Map
ADDRESS
NAME
MSB
LSB
GEN Registers
GEN_PROD[23:16]
GEN_PROD[15:8]
GEN_PROD[7:0]
GEN_REV[23:16]
GEN_REV[15:8]
GEN_REV[7:0]
PROD_ID[7:0]
SERIAL_MSB[15:8]
SERIAL_MSB[7:0]
REV_ID[7:0]
0x00
0x01
SERIAL_LSB[15:8]
SERIAL_LSB[7:0]
ADCREF
_SEL
GEN_CNFG[23:16]
GEN_CNFG[15:8]
GEN_CNFG[7:0]
CRC_EN
–
–
–
–
–
–
–
–
–
–
–
–
0x02
0x03
0x04
–
–
–
–
TMOUT_ TMOUT_
EN CNFG
TMOUT_SEL[3:0]
GEN_CHNL_CTRL[23:1
6]
AIP_TEST[1:0]
AIN_TEST[1:0]
–
–
–
–
–
–
–
GEN_CHNL_CTRL[15:8
]
–
–
–
–
AI_DCHNL_SEL[4:0]
–
GEN_CHNL_CTRL[7:0]
–
–
–
GEN_GPIO_CTRL[23:1
6]
GPIO_EN[7:0]
GPIO_DIR[7:0]
GEN_GPIO_CTRL[15:8
]
GEN_GPIO_CTRL[7:0]
GEN_GPI_INT[23:16]
GEN_GPI_INT[15:8]
GEN_GPI_INT[7:0]
GPO_DATA[7:0]
GPI_POS_EDGE_INT[7:0]
GPI_NEG_EDGE_INT[7:0]
0x05
0x06
–
–
–
–
–
–
–
–
–
GEN_GPI_DATA[23:16]
GEN_GPI_DATA[15:8]
GEN_GPI_DATA[7:0]
GEN_INT[23:16]
GPI_POS_EDGE_INT_STA[7:0]
GPI_NEG_EDGE_INT_STA[7:0]
GPI_DATA[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
TMOUT_
INT
GEN_INT[15:8]
–
–
0x07
HVDD_I
NT
CNFG_I CRC_IN
GEN_INT[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
GPI_INT
NT
T
GEN_INTEN[23:16]
GEN_INTEN[15:8]
–
–
–
–
–
TMOUT_
INTEN
–
–
0x08
0x09
HVDD_I
NTEN
CNFG_I CRC_IN GPI_INT
GEN_INTEN[7:0]
–
–
–
–
–
–
–
NTEN
TEN
EN
GEN_PWR_CTRL[23:1
6]
GEN_RS
T
–
GEN_PD
–
–
GEN_PWR_CTRL[15:8]
GEN_PWR_CTRL[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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Maxim Integrated | 30
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
ADDRESS
NAME
MSB
LSB
DCHNL Registers
DCHNL_CMD[23:16]
DCHNL_CMD[15:8]
DCHNL_CMD[7:0]
DCHNL_STA[23:16]
DCHNL_STA[15:8]
DCHNL_STA[7:0]
–
–
–
–
–
–
DCHNL_MODE[1:0]
DCHNL_RATE[3:0]
0x20
0x21
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
REFDET
DOR
MSTAT
–
RATE[3:0]
PDSTAT[1:0]
RDY
DCHNL_
PD
CONTS
C
DCHNL_CTRL1[23:16]
–
–
–
–
–
SCYCLE
0x22
DCHNL_CTRL1[15:8]
DCHNL_CTRL1[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SYNC_M
ODE
NOSYS
G
NOSYS
O
DCHNL_CTRL2[23:16]
EXTCLK
–
–
–
–
0x23
0x24
DCHNL_CTRL2[15:8]
DCHNL_CTRL2[7:0]
DCHNL_DATA[23:16]
DCHNL_DATA[15:8]
DCHNL_DATA[7:0]
DCHNL_N_SEL[23:16]
DCHNL_N_SEL[15:8]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DCHNL_DATA[23:16]
DCHNL_DATA[15:8]
DCHNL_DATA[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x25
DCHNL_
OTP_SE
L
DCHNL_N_SEL[7:0]
–
–
DCHNL_N_SEL[4:0]
DCHNL_N_SOC[23:16]
DCHNL_N_SOC[15:8]
DCHNL_N_SOC[7:0]
DCHNL_N_SGC[23:16]
DCHNL_N_SGC[15:8]
DCHNL_N_SGC[7:0]
DCHNL_N_SOC[23:16]
DCHNL_N_SOC[15:8]
DCHNL_N_SOC[7:0]
DCHNL_N_SGC[23:16]
DCHNL_N_SGC[15:8]
DCHNL_N_SGC[7:0]
0x26
0x27
Register Details
GEN_PROD (0x0)
BIT
Field
23
15
22
14
21
13
20
19
18
10
17
16
PROD_ID[7:0]
Reset
0x18
Access
Type
Read Only
BIT
Field
12
11
9
8
SERIAL_MSB[15:8]
0xXX
Reset
Access
Type
Read Only
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Maxim Integrated | 31
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BIT
Field
7
6
5
4
3
2
1
0
SERIAL_MSB[7:0]
0xXX
Reset
Access
Type
Read Only
BITFIELD
PROD_ID
BITS
23:16
15:0
DESCRIPTION
8-bit product ID code
The most significant 16-bits of a 32-bit code unique to each MAX22005.
SERIAL_MSB
GEN_REV (0x1)
BIT
Field
23
15
7
22
14
6
21
13
5
20
19
18
17
16
REV_ID[7:0]
Reset
0x00
Access
Type
Read Only
BIT
Field
12
11
10
9
8
SERIAL_LSB[15:8]
0xXX
Reset
Access
Type
Read Only
BIT
Field
4
3
2
1
0
SERIAL_LSB[7:0]
0xXX
Reset
Access
Type
Read Only
BITFIELD
REV_ID
BITS
23:16
15:0
DESCRIPTION
8-bit revision ID code
The least significant 16-bits of a 32-bit code unique to each MAX22005.
SERIAL_LSB
GEN_CNFG (0x2)
If an ADC conversion is in progress, every write to bit ADCREF_SEL aborts the ADC conversion unless the write
transaction does not result in a change of the content of ADCREF_SEL.
BIT
23
22
21
20
19
18
17
16
ADCREF_S
EL
Field
CRC_EN
0b0
–
–
–
–
–
–
Reset
–
0b0
–
–
–
–
–
Access
Type
Write, Read
–
Write, Read
–
–
–
–
–
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
–
–
8
–
–
Reset
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
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Maxim Integrated | 32
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BIT
Field
7
–
–
–
6
–
–
–
5
4
3
2
1
0
TMOUT_C
NFG
TMOUT_EN
0b0
TMOUT_SEL[3:0]
0x0
Reset
0b0
Access
Type
Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0b0: CRC checker disabled
0b1: CRC checker enabled
CRC_EN
23
CRC checker enable
ADC voltage reference
Timeout enable
ADCREF_SE
L
0b0: Internal voltage reference
0b1: External voltage reference
21
5
0b0: Timeout disabled
0b1: Timeout enabled
TMOUT_EN
0b0: When the timeout period expires,
TMOUT_INT is asserted.
TMOUT_CN
FG
0b1: When the timeout period expires,
4
Timeout configuration
TMOUT_INT is asserted, and the register field
GPIO_EN[7:0] is reset, which disables all GPIO
ports.
0x0: 100ms
0x1: 200ms
0x2: 300ms
0x3: 400ms
0x4: 500ms
0x5: 600ms
0x6: 700ms
0x7: 800ms
0x8: 900ms
0x9: 1.0s
TMOUT_SEL
3:0
Timeout duration selection
0xA: 1.1s
0xB: 1.2s
0xC: 1.3s
0xD: 1.4s
0xE: 1.5s
0xF: 1.6s
GEN_CHNL_CTRL (0x3)
If an ADC conversion is in progress, every write to bits AI_DCHNL_SEL[4:0] aborts the ADC conversion unless the
write transaction does not result in a change of the content of AI_DCHNL_SEL[4:0].
BIT
23
22
21
20
19
18
17
16
Field
AIP_TEST[1:0]
AIN_TEST[1:0]
–
–
–
–
Reset
0x0
0x0
–
–
–
–
Access
Type
Write, Read
Write, Read
–
–
–
–
BIT
Field
15
–
14
–
13
–
12
11
10
AI_DCHNL_SEL[4:0]
0x00
9
8
Reset
–
–
–
Access
Type
–
–
–
Write, Read
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Maxim Integrated | 33
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
–
–
0
–
–
Reset
Access
Type
–
–
–
–
–
–
–
–
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Diagnostic disabled
0x1: 2MΩ resistor to AGND
0x2: 2MΩ resistor to HVDD
Diagnostic switches for AI1, AI4, AI5, AI7,
AI10, and AI11
AIP_TEST
23:22
21:20
0x3: 2MΩ resistor to both HVDD and AGND
0x0: Diagnostic disabled
0x1: 2MΩ resistor to AGND
0x2: 2MΩ resistor to HVDD
Diagnostic switches for AI2, AI3, AI6, AI8,
AI9, and AI12
AIN_TEST
0x3: 2MΩ resistor to both HVDD and AGND
0x0: AI1 single-ended
0x1: AI2 single-ended
0x2: AI3 single-ended
0x3: AI4 single-ended
0x4: AI5 single-ended
0x5: AI6 single-ended
0x6: AI7 single-ended
0x7: AI8 single-ended
0x8: AI9 single-ended
0x9: AI10 single-ended
0xA: AI11 single-ended
0xB: AI12 single-ended
0xC: AI1–AI2 differential
0xD: AI3–AI4 differential
0xE: AI5–AI6 differential
0xF: AI7–AI8 differential
0x10: AI9–AI10 differential
0x11: AI11–AI12 differential
0x12: AI1(COM)–AI2 multifunctional differential
0x13: AI1(COM)–AI3 multifunctional differential
0x14: AI4(COM)–AI5 multifunctional differential
0x15: AI4(COM)–AI6 multifunctional differential
0x16: AI7(COM)–AI8 multifunctionall differential
0x17: AI7(COM)–AI9 multifunctional differential
0x18: AI10(COM)–AI11 multifunctional differential
0x19: AI10(COM)–AI12 multifunctional differential
0x1A: reserved
Analog-input configuration selection
If the host attempts to write a reserve state to
this field, a configuration interrupt is issued
(CNFG_INT) and the register field remains
unchanged; thus, reflecting the last valid
configuration selection.
AI_DCHNL_
SEL
12:8
0x1B: reserved
0x1C: reserved
0x1D: reserved
0x1E: reserved
0x1F: reserved
GEN_GPIO_CTRL (0x4)
BIT
Field
23
22
21
20
19
18
17
16
GPIO_EN[7:0]
Reset
0x00
Access
Type
Write, Read
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Maxim Integrated | 34
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BIT
Field
15
14
13
12
11
10
9
8
GPIO_DIR[7:0]
Reset
0x00
Access
Type
Write, Read
BIT
Field
7
6
5
4
3
2
1
0
GPO_DATA[7:0]
0x00
Reset
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
GPIO ports enable control. The MSB
corresponds to GPIO7 and the LSB to
GPIO0.
0: The corresponding GPIO is disabled (default)
1: The corresponding GPIO is enabled
GPIO_EN
23:16
0: The corresponding GPIO is configured as an
input port (default)
1: The corresponding GPIO is configured as output
port
GPIO ports direction control. The MSB
corresponds to GPIO7 and the LSB to
GPIO0.
GPIO_DIR
15:8
7:0
Data bits sent to the GPO-configured ports.
0: The corresponding GPO set as logic low
GPO_DATA
The MSB corresponds to GPIO7 and the LSB (default)
to GPIO0.
1: The corresponding GPO set as logic high
GEN_GPI_INT (0x5)
BIT
Field
23
22
21
13
20
19
18
10
17
16
GPI_POS_EDGE_INT[7:0]
0x00
Reset
Access
Type
Write, Read
BIT
Field
15
14
12
11
9
8
GPI_NEG_EDGE_INT[7:0]
0x00
Reset
Access
Type
Write, Read
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
–
–
0
–
–
Reset
Access
Type
–
–
–
–
–
–
–
–
BITFIELD
BITS
DESCRIPTION
DECODE
Positive-edge detection control for signals
received on GPI-configured ports. The MSB
corresponds to GPIO7 and the LSB to
GPIO0.
0: Positive-edge detection disabled on the
corresponding GPI port (default)
1: Positive-edge detection enabled on the
corresponding GPI port
GPI_POS_E
DGE_INT
23:16
15:8
Negative-edge detection control for signals
received on GPI-configured ports. The MSB
corresponds to GPIO7 and the LSB to
GPIO0.
0: Negative-edge detection disabled on
corresponding GPI port (default)
1: Negative-edge detection enabled on
corresponding GPI port
GPI_NEG_E
DGE_INT
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Maxim Integrated | 35
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
GEN_GPI_DATA (0x6)
BIT
Field
23
15
7
22
14
6
21
20
19
18
10
2
17
16
GPI_POS_EDGE_INT_STA[7:0]
0x00
Reset
Access
Type
Read Clears All
BIT
Field
13
12
11
9
8
GPI_NEG_EDGE_INT_STA[7:0]
0x00
Reset
Access
Type
Read Clears All
BIT
Field
5
4
3
1
0
GPI_DATA[7:0]
0x00
Reset
Access
Type
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
0: No positive edge was detected on the
configured port has detected a positive edge. corresponding GPI port (default)
The MSB corresponds to GPIO7 and the LSB 1: At least one positive edge was detected on the
Each bit indicates if its corresponding GPI-
GPI_POS_E
DGE_INT_S
TA
23:16
to GPIO0.
corresponding GPI port
Each bit indicates if its corresponding GPI-
configured port has detected a negative
edge. The MSB corresponds to GPIO7 and
the LSB to GPIO0.
0: No negative edge was detected on the
corresponding GPI port (default)
1: At least one negative edge was detected on the
corresponding GPI port
GPI_NEG_E
DGE_INT_S
TA
15:8
7:0
Each bit contains the logic level applied to its 0: Logic-level low detected at the GPI-configured
corresponding GPI-configured port. The MSB port
corresponds to GPIO7 and the LSB to
GPIO0.
GPI_DATA
1: Logic-level high detected at the GPI-configured
port
GEN_INT (0x7)
BIT
Field
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
Reset
–
–
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
8
–
–
–
TMOUT_IN
T
Reset
–
–
–
–
–
–
0b0
Access
Type
Read
Clears All
–
–
–
–
–
–
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Maxim Integrated | 36
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BIT
Field
7
6
–
–
5
–
–
4
–
–
3
–
–
2
1
0
HVDD_INT
0b0
CNFG_INT
0b0
CRC_INT
0b0
GPI_INT
0b0
Reset
Access
Type
Read
Clears All
Read
Clears All
Read
Clears All
Read Only
–
–
–
–
BITFIELD
BITS
DESCRIPTION
DECODE
Asserted when the timeout duration expires if
the timeout function is enabled.
Cleared when read.
0b0: Timeout duration not expired
0b1: Timeout duration expired
TMOUT_INT
9
Asserted when the high-voltage supply
HVDD/HVSS falls below a preset threshold,
indicating that the functionality of the
amplifiers is not guaranteed.
0b0: HVDD supply is above the preset threshold
0b1: HVDD supply is below the preset threshold
HVDD_INT
7
Cleared when the high-voltage supply
exceeds the threshold again.
Asserted when the host selects states 0x1A
to 0x1F for AI_DCHNL_SEL or
DCHNL_N_SEL.
0b0: No configuration error detected
0b1: Configuration error detected
CNFG_INT
CRC_INT
GPI_INT
2
1
0
Cleared when read.
Asserted when a CRC error is detected when
the CRC mode is enabled.
Cleared when read.
0b0: No CRC error detected
0b1: CRC error detected
Asserted when at least one positive or
negative edge was detected at the input of at
least one GPI-configured port.
0b0: No edge detected on any GPI-configured port
0b1: At least one edge detected on at least one
GPI-configured port
Cleared when read.
GEN_INTEN (0x8)
BIT
Field
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
Reset
–
–
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
8
–
–
–
TMOUT_IN
TEN
Reset
–
–
–
–
–
–
0b0
Access
Type
–
–
–
–
–
–
Write, Read
BIT
7
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
1
0
HVDD_INT
EN
CNFG_INT
EN
CRC_INTE
N
Field
GPI_INTEN
0b0
Reset
0b0
0b0
0b0
Access
Type
Write, Read
Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
TMOUT_INT
EN
0b0: The corresponding interrupt cannot assert INT
0b1: The corresponding interrupt can assert INT
9
TMOUT interrupt enable
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Maxim Integrated | 37
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BITFIELD
BITS
DESCRIPTION
HVDD interrupt enable
DECODE
HVDD_INTE
N
0b0: The corresponding interrupt cannot assert INT
0b1: The corresponding interrupt can assert INT
7
CNFG_INTE
N
0b0: The corresponding interrupt cannot assert INT
0b1: The corresponding interrupt can assert INT
2
1
0
CNFG interrupt enable
CRC interrupt enable
GPI interrupt enable
0b0: The corresponding interrupt cannot assert INT
0b1: The corresponding interrupt can assert INT
CRC_INTEN
GPI_INTEN
0b0: The corresponding interrupt cannot assert INT
0b1: The corresponding interrupt can assert INT
GEN_PWR_CTRL (0x9)
BIT
Field
23
–
22
–
21
–
20
–
19
GEN_PD
0b0
18
–
17
GEN_RST
0b0
16
–
Reset
–
–
–
–
–
–
Access
Type
–
–
–
–
Write, Read
–
Write, Read
–
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
–
–
8
–
–
Reset
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
–
–
0
–
–
Reset
Access
Type
–
–
–
–
–
–
–
–
BITFIELD
BITS
DESCRIPTION
DECODE
0b0: Normal operation
0b1:
Power-down: Setting GEN_PD to logic high has an
effect equivalent to powering down all input paths.
When GEN_PD is set to logic low, the channels
recover the configuration they had before GEN_PD
was set to logic high. Therefore, no register needs
to be reprogrammed after exiting power-down
mode. Additionally, register contents can be
modified while in power-down mode if desired.
Power-down control for the register
GEN_CHNL_CTRL that controls the analog
path settings
GEN_PD
19
0b0: Normal operation
0b1: Reset mode: Setting GEN_RST is equivalent
to clearing GEN_CHNL_CTRL register. Also, any
on-going conversion is aborted. If a conversion
was aborted, it needs to be restarted using
DCHNL_CMD register.
Soft-reset control for the register
GEN_CHNL_CTRL that controls the analog
path settings.
GEN_RST
17
DCHNL_CMD (0x20)
If an ADC conversion is in progress, every write transaction to the DCHNL_CMD register is ignored unless the write
transaction puts the ADC in a power-down mode.
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Maxim Integrated | 38
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BIT
Field
23
–
22
–
21
20
19
18
17
16
DCHNL_MODE[1:0]
0x0
DCHNL_RATE[3:0]
0x0
Reset
–
–
Access
Type
–
–
Write, Read
Write, Read
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
–
–
8
–
–
Reset
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
–
–
0
–
–
Reset
Access
Type
–
–
–
–
–
–
–
–
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Reserved
0x1: Power down performed based on the
DCHNL_PD setting
0x2: Reserved
DCHNL_MO
DE
21:20
19:16
Analog Input ADC mode
ADC data rates.
0x3: Conversion mode
DCHNL_RAT
E
DCHNL_STA (0x21)
BIT
Field
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
Reset
–
–
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
15
–
14
REFDET
0b0
13
–
12
–
11
–
10
–
9
8
–
–
DOR
0b0
Reset
–
–
–
–
–
Access
Type
–
Read Only
–
–
–
–
Read Only
–
BIT
Field
7
6
5
4
3
2
1
0
RATE[3:0]
PDSTAT[1:0]
MSTAT
0b0
RDY
0b0
Reset
0x0
0x2
Access
Type
Read Only
Read Only
Read Only
Read Only
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Maxim Integrated | 39
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BITFIELD
BITS
DESCRIPTION
DECODE
Reference voltage detection (internal or
external reference).
0b0: No reference voltage detected (reference
voltage < 0.35V)
0b1: Reference voltage detected (reference
voltage > 0.35V)
This bit does not inhibit normal operation and
is intended for status only. The value of the
REFDET bit is valid within 30μs after a
conversion start command and is invalid
when not in conversion.
REFDET
14
0b0: The conversion result is within the digital
operating range of the ADC
0b1: The conversion result has exceeded the
maximum or minimum value of the converter and
the result has been set to the maximum or
minimum value.
DOR
9
Digital overrange
RATE[3:0] indicates the conversion rate that
corresponds to the results in the
DCHNL_DATA register or the rate that was
used for the calibration coefficient calculation.
The corresponding RATE[3:0] is only valid
until the DCHNL_DATA register is read.
RATE
7:4
3:2
Refer to Table 7, Table 8 and Table 9.
0x0: Conversion mode
0x1: Reserved
0x2: Standby
PDSTAT
Power states of the analog input ADC
0x3: Reset
ADC Status. Due to internal timing, the status
update of MSTAT might be delayed up to 2µs
after start or completion of a conversion. This
delay should be taken into account if MSTAT
is polled immediately after a status change.
0b0: The delta-sigma modulator is not converting
0b1: Conversion is in progress
MSTAT
RDY
1
0
A new conversion is result ready.
A complete read of the DCHNL_DATA
register deasserts this bit.
0b0: No new conversion result available
0b1: A new conversion result available
DCHNL_CTRL1 (0x22)
If an ADC conversion is in progress, every write transaction to the DCHNL_CTRL1 register aborts the ADC conversion
unless the write transaction does not result in a change of the content of the register.
BIT
23
22
21
20
DCHNL_PD
0b0
19
18
17
SCYCLE
0b1
16
CONTSC
0b0
Field
–
–
–
–
–
Reset
–
–
–
–
–
Access
Type
–
–
–
Write, Read
–
–
Write, Read Write, Read
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
–
–
8
–
–
Reset
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
–
–
0
–
–
Reset
Access
Type
–
–
–
–
–
–
–
–
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Maxim Integrated | 40
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BITFIELD
BITS
DESCRIPTION
DECODE
0b0: Standby
0b1: Reset
DCHNL_PD
20
Analog input ADC power-down state
0b0: Continuous conversion mode (latency due to
digital filtering)
SCYCLE
CONTSC
17
16
Single-cycle conversion mode
Continuous single-cycle mode
0b1: Single-Cycle mode where a no-latency
conversion is followed by a power-down to standby
mode
0b0: Single conversion
0b1: Continuous single-cycle conversions
DCHNL_CTRL2 (0x23)
If an ADC conversion is in progress, every write transaction to the DCHNL_CTRL2 register aborts the ADC conversion
unless the write transaction does not result in a change of the content of the register.
BIT
23
EXTCLK
0b0
22
21
20
19
NOSYSG
0b0
18
NOSYSO
0b0
17
16
SYNC_MO
DE
Field
–
–
–
–
Reset
–
0b0
–
–
–
Access
Type
Write, Read
–
Write, Read
–
Write, Read Write, Read
–
–
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
–
–
8
–
–
Reset
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
–
–
0
–
–
Reset
Access
Type
–
–
–
–
–
–
–
–
BITFIELD
BITS
DESCRIPTION
DECODE
0b0: Internal oscillator
0b1: External clock
EXTCLK
23
External clock selection
SYNC_MOD
E
0b0: Disabled
0b1: Enabled
21
19
External synchronization mode
0b0: System calibration gain coefficient SGC is
used to compute the final output data
0b1: System calibration gain coefficient SGC is not
used to compute the final output data
NOSYSG
NOSYSO
No system calibration gain correction
No system calibration offset correction
0b0: System calibration offset coefficient SOC is
used to compute the final output data
0b1: System calibration offset coefficient SOC is
not used to compute the final output data
18
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Maxim Integrated | 41
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
DCHNL_DATA (0x24)
BIT
Field
23
15
7
22
14
6
21
13
5
20
19
18
17
16
DCHNL_DATA[23:16]
0x000000
Reset
Access
Type
Read Only
BIT
Field
12
11
10
9
8
DCHNL_DATA[15:8]
0x000000
Reset
Access
Type
Read Only
BIT
Field
4
3
2
1
0
DCHNL_DATA[7:0]
0x000000
Reset
Access
Type
Read Only
BITFIELD
DCHNL_DATA
BITS
23:0
DESCRIPTION
Analog input configuration conversion result in two’s complement
DCHNL_N_SEL (0x25)
BIT
Field
23
–
22
21
–
20
–
19
–
18
–
17
–
16
–
–
–
Reset
–
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
15
–
14
–
13
–
12
–
11
–
10
–
9
–
–
8
–
–
Reset
–
–
–
–
–
–
Access
Type
–
–
–
–
–
–
–
–
BIT
Field
7
–
–
–
6
–
–
–
5
4
3
2
1
0
DCHNL_OT
P_SEL
DCHNL_N_SEL[4:0]
0x00
Reset
0b0
Access
Type
Write, Read
Write, Read
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Maxim Integrated | 42
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
BITFIELD
BITS
DESCRIPTION
DECODE
0b0: The DCHNL_N_SOC and DCHNL_N_SGC
registers for the channel selected by
DCHNL_N_SEL[4:0] can be modified through SPI
transactions.
DCHNL_OTP
_SEL
5
Calibration coefficient selection
0b1: The SOC and SGC registers for the channel
selected by DCHNL_N_SEL[4:0] are loaded with
the corresponding factory calibrated coefficients,
overwriting the current content of the selected SOC
and SGC registers.
The value written in this register corresponds
to the input configuration as defined for
AI_DCHNL_SEL[4:0]. Once this register is
written with the desired input configuration,
the DCHNL_N_SOC and DCHNL_N_SGC
registers for the selected input configuration
can be modified through SPI transactions.
If the host attempts to write a reserve state to
this field (0x1A to 0x1F), a configuration
interrupt is issued (CNFG_INT) and
DCHNL_N_S
EL
4:0
DCHNL_N_SEL remains unchanged; thus,
reflecting the last valid entry.
DCHNL_N_SOC (0x26)
If an ADC conversion is in progress, every write transaction to the DCHNL_N_SOC register is ignored if
DCHNL_N_SEL[4:0] corresponds to the channel currently selected for conversion, and the register retains its current
value. Write transactions to the DCHNL_N_SOC register if DCHNL_N_SEL[4:0] does not correspond to the channel
currently selected for conversion are allowed, and the register is updated with the new value.
BIT
23
15
7
22
14
6
21
13
5
20
19
18
17
16
Field
DCHNL_N_SOC[23:16]
0x000000
Reset
Access
Type
Write, Read
BIT
Field
12
11
10
9
8
DCHNL_N_SOC[15:8]
0x000000
Reset
Access
Type
Write, Read
BIT
Field
4
3
2
1
0
DCHNL_N_SOC[7:0]
0x000000
Reset
Access
Type
Write, Read
BITFIELD
DCHNL_N_SOC
BITS
23:0
DESCRIPTION
System offset calibration value for the input configuration selected by
DCHNL_N_SEL[4:0] in two’s complement format.
DCHNL_N_SGC (0x27)
If an ADC conversion is in progress, every write transaction to the DCHNL_N_SGC register is ignored if
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Maxim Integrated | 43
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
DCHNL_N_SEL[4:0] corresponds to the channel currently selected for conversion, and the register retains its current
value. Write transactions to the DCHNL_N_SGC register if DCHNL_N_SEL[4:0] does not correspond to the channel
currently selected for conversion are allowed, and the register is updated with the new value.
BIT
23
15
7
22
14
6
21
13
5
20
19
18
17
16
Field
DCHNL_N_SGC[23:16]
0xC00000
Reset
Access
Type
Write, Read
BIT
Field
12
11
10
9
8
DCHNL_N_SGC[15:8]
0xC00000
Reset
Access
Type
Write, Read
BIT
Field
4
3
2
1
0
DCHNL_N_SGC[7:0]
0xC00000
Reset
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
System gain calibration value for the input configuration selected by
DCHNL_N_SEL[4:0] in unsigned binary format with a fraction length of 23
bits, i.e., only the MSB is an integer bit.
Examples:
0x80_0000 Gain of 1.0
0xC0_0000 Gain of 1.5
0xA0_0000 Gain of 1.25
DCHNL_N_SGC
23:0
0x60_0000 Gain of 0.75
Once the OTP outputs are stable after the deassertion of the power-on reset
or the external reset, the corresponding OTP bank content is loaded into each
DCHNL_N_SGC register. The register content value is approximately 1.5
(0xC0_0000) to counter the inherent signal-chain gain of 0.67, which is
required by the delta-sigma modulator.
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Maxim Integrated | 44
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Applications Information
Power Supply Headroom Requirements
Analog inputs power from HVDD and HVSS, and generally need 2.5V of headroom to meet all linearity specifications. To
accept ±10V inputs, whose full-scale range is ±12.5V, supply the MAX22005 with at least ±15V on HVDD/HVSS.
Any external reference voltage on the REF_ADC_EXT pin must never exceed V
between REF_ADC_EXT and AVDD can help satisfy this requirement.
. A schottky diode connected
AVDD
Power Supply Sequencing
The four supplies, AVDD, DVDD, HVDD and HVSS can power up in any order. Add a 1μF bypass capacitor between
each supply pin and respected return (AGND or DGND) pin. It is recommended to supply HVDD and HVSS
simultaneously.
Board Layout
Use proper grounding techniques such as a multilayer board with a low-inductance ground plane.
● Keep DGND separate from AGND, connecting the two at one point.
● Use a ground plane shielding to improve noise immunity.
● Keep analog signal traces away from digital signal traces, especially clock traces.
For a detailed recommended layout, refer to the MAX22005 EV kit data sheet.
Surge Protection
With external circuitry, the input ports are protected against ±2kV/42Ω surge pulses as per IEC61000-4-5. Place a
minimum 4.7kΩ surge tolerant resistor in series with each analog input port.
The other MAX22005 pins are rated for a Human Body Model (HBM). If surge voltages can couple from the high voltage
supplies (HVDD, HVSS) to the low-voltage supplies (DVDD or AVDD), place additional TVS suppressors on these power
rails, or place TVS suppressors on the digital signal traces.
Each external sense resistor for current input mode (AICM) should be protected separately by an external TVS
suppressor.
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Maxim Integrated | 45
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Typical Application Circuits
MAX22005 12-Channel Configurable Industrial Analog Input
3.3V
3.3V
15V
1µF
1µF
1µF
SINGLE-
ENDED
VOLTAGE
SENSOR
HVDD
DVDD
AVDD
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
AI1
AI2
SINGLE-
ENDED
VOLTAGE
SENSOR
3.3V
AI3
AI4
AI5
AI6
AI7
AI8
INT
DIFFERENTIAL
VOLTAGE
SENSOR
RDY
CLK
RST
SDO
SYNC
SDI
CURRENT
SENSOR
SPI INTERFACE
CONTROL-LOGIC
SIGNAL
5kΩ
5kΩ
5kΩ
24-BIT Δ-Σ ADC
PROCESSING
CURRENT
OR
VOLTAGE
SENSOR
SCLK
CS
5kΩ
5kΩ
5kΩ
AI9
REF_ADC
REF_OUT
AI10
CURRENT
OR
VOLTAGE
SENSOR
MUX
AI11
AI12
NR
2.5V REFERENCE
5kΩ
4.7µF
1µF
0.1µF
0.1µF
1.8V LDO
GPIO[2:0]
BYP_ADC
220nF
REF_ADC_EXT
AGND
HVSS
DGND
¼ MAX14757
1µF
-15V
Ordering Information
PART NUMBER
MAX22005ALM+
MAX22005ALM+T
TEMP. RANGE
-40°C to +125°C
-40°C to +125°C
PACKAGE
LEAD PITCH
0.5mm
ADC RESOLUTION
48-Pin LGA (7.5mm x 7.0mm)
48-Pin LGA (7.5mm x 7.0mm)
24 bit
24 bit
0.5mm
+Denotes lead(Pb)-free/RoHS compliance.
T = Tape and reel.
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Maxim Integrated | 46
MAX22005
12-Channel Factory-Calibrated
Configurable Industrial-Analog Input
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
4/21
Release for Market Intro
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2021 Maxim Integrated Products, Inc.
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