MAX22192 [MAXIM]
Octal Industrial Digital Input with Diagnostics and Digital Isolation;
| 型号： | MAX22192 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Octal Industrial Digital Input with Diagnostics and Digital Isolation |
| 文件： | 总50页 (文件大小：1135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here to ask about production status of specific part numbers.
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
General Description
Benefits and Features
The MAX22192 is an IEC 61131-2 compliant industrial
digital input device with integrated digital isolation. The
MAX22192 translates eight, 24V current-sinking, indus-
trial inputs to an isolated serialized SPI-compatible output
that interfaces with 1.71V to 5.5V logic voltage. A current-
setting resistor allows the MAX22192 to be configured for
Type 1, Type 2, or Type 3 inputs. For proximity switches,
the field-wiring is verified using the wire break feature.
When wire break is enabled, the LFAULT output is assert-
ed and a register flag set if the input current drops below
the wire break threshold for more than 20ms. Additional
diagnostics that assert LFAULT include: overtemperature
protection, low 24V field supply, 24V field supply missing,
and CRC communication error.
● High Integration Reduces BOM Count and Board Space
• Eight Input Channels with Serializer
• Integrated Isolation of 600V
for 60s (V
)
RMS
ISO
• Operates Directly from Field Supply (7V to 65V)
• Compatible with 1.8V, 3.3V or 5V Logic
• 6mm x 10mm GQFN Package
● Reduced Power and Heat Dissipation
• Accurate Input-Current Limiters
• Energyless Field-Side LED Drivers
● Fault Tolerant with Built-In Diagnostics
• Input Protection to ±40V with Low-Input Leakage
Current
• Wire-Break Detection
• Integrated Field-Supply Voltage Monitors
• Integrated Overtemperature Monitors
• 5-Bit CRC Code Generation for Error Detection
For robust operation in industrial environments, each input
includes a programmable glitch filter. The filter delay on
each channel can be independently programmed to one
of eight values between 50µs and 20ms, or filter bypass.
● Configurability Enables a Wide Range of Applications
• Configurable IEC 61131-2 Type 1, 2, 3 Inputs
• Configurable Input Current-Limiting from 0.5mA to
3.4mA
The MAX22192 has an isolated 4-pin SPI interface, and
in addition uses isolated LLATCH input for synchronizing
input data across multiple devices in parallel, and iso-
lated LFAULT output for instantly alerting the host of any
diagnostic issues. The digital signals with a name starting
with L are logic-side signals, and the digital signals with a
name starting with F are field-side signals.
• Selectable Input Glitch Filter
• Capable of Daisy-Chaining Other Field-Side De-
vices Sharing Isolated SPI
● Robust Design
The MAX22192 field-side accepts a single 7V to 65V sup-
• ±8kV Contact ESD and ±15kV Air-Gap ESD Using
Minimum 1kΩ Resistor
• ±1kV Surge Tolerant Using Minimum 1kΩ Resistor
• -40°C to +125°C Ambient Operating Temperature
ply to the V
pin. When powered by the field supply,
DD24F
the MAX22192 generates a 3.3V output on the V
pin
DD3F
from an integrated LDO regulator, which can provide up to
25mA of current for external loads in addition to powering
the MAX22192. Alternatively, the MAX22192 can be pow-
Applications
● Programmable Logic Controllers
ered from a 3.0V to 5.5V supply connected to the V
DD3F
pin. The logic-side of the MAX22192 is powered from a
● Industrial Automation
single 1.71V to 5.5V supply to the V
with 1.8V, 3.3V, or 5V logic levels.
pin to interface
● Process Automation
DDL
Safety Regulatory Approvals
● UL According to UL1577
● cUL According to CSA Bulletin 5A
The MAX22192 has an isolation rating of 600V
for 60
RMS
seconds and is available in a 70-pin GQFN package with
2.3mm clearance and creepage. The package material
has a minimum comparative tracking index (CTI) of 600V,
which gives it a group I rating in creepage tables.
Ordering Information and Typical Operating Circuits appear
at end of data sheet.
19-100406; Rev 3; 9/20
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Isolated Octal Type 1/3 Digital Input
24V
3.3V
1.8V
1µF
0.1µF
0.1µF
1µF
0.1µF
1µF
M1
M0
V
DDL
V
V
V
LF
DD24F
DD3F
7.5kΩ
REFDI
REFWB
EXTVM
24kΩ
V
DD
AFS
GPI
1.5kΩ
1.5kΩ
IN1
FIELD INPUT
FIELD INPUT
LCS
CS
LED1
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
MAX22192
MICRO
CONTROLLER
IN2
LSDO
LED2
LLATCH
1.8V
INPUT AT PIN
1.5kΩ
4.7kΩ
IN8
FIELD INPUT
SDOEN
LFAULT
LED8
GPI or INT
470Ω
470Ω
470Ω
LEDC2
LEDC1
LEDC0
GND
24VM
LEDR2
LEDR1
LEDR0
FCS FSCLK FSDO FSDI OSDI FFAULT IFAULT OREADY IREADY FLATCH GNDF GNDL
4.7kΩ
4.7kΩ
3.3V
Maxim Integrated
│ 2
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Absolute Maximum Ratings
DD3F LF
V
V
, V to GNDF.............................................-0.3V to +6V
LSCLK, LCS, LSDI, LLATCH, SDOEN to GNDL ....-0.3V to +6V
LFAULT to GNDL.....................................................-0.3V to +6V
to GNDF .................................................-0.3V to +70V
FSCLK, FCS, OSDI, FSDO to GNDF .......-0.3V to (V + 0.3V)
FLATCH to GNDF .....................................-0.3V to (V + 0.3V)
DD24F
LSDO, AFS to GNDL..............................-0.3V to (V + 0.3V)
LF
LF
DDL
Maximum Current for All Digital Output Pins......................20mA
Continuous Power Dissipation (70-GQFN)
FSDI, IFAULT, IREADY to GNDF ...........................-0.3V to +6V
OREADY, FFAULT to GNDF ...................................-0.3V to +6V
Multilayer Board T = +70°C.....................................2286mW
A
LEDC_, LEDR_ to GNDF.................... -0.3V to (V
REFWB, REFDI to GNDF ................... -0.3V to (V
M1, M0, EXTVM to GNDF.......................................-0.3V to +6V
IN1 – IN8 to GNDF.................................................-40V to +40V
LED1 – LED8 to GNDF...........................................-0.3V to +6V
+ 0.3V)
+ 0.3V)
Derate above +70°C..............................................28.6mW/°C
Operating Temperature Range......................... -40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering (reflow) ............................................................+260°C
DD3F
DD3F
V
to GNDL........................................................-0.3V to +6V
DDL
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 70 GQFN
Package Code
R70610M+1
21-100252
90-100111
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
35°C/W
2.9°C/W
JA
Junction to Case (θ
)
JC
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Maxim Integrated
│ 3
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
DC Electrical Characteristics
V
- V
= +3.0V to +5.5V, V
- V
= +3.0V to +5.5V, V
- V
= +7V to +65V, V
- V
= +1.71V to +5.5V,
LF
GNDF
DD3F
GNDF
DD24F
GNDF
DDL
GNDL
T
= -40°C to +125°C, unless otherwise noted. Typical values are at V - V
= +3.3V, V
- V
= +3.3V, V
- V
A
LF
GNDF
DD3F
GNDF
DD24F GNDF
= +24V, V
- V
= +3.3V, V
= +24V, C = 15pF and T = +25°C. (Note 1)
DDL
GNDL
IN_ L A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
V
Normal operation
7
65
DD24F
Supply Voltage
V
Powered from an external supply,
V
3.0
5.5
DD3F
V
unconnected
DD24F
Field Logic Supply Voltage
Logic Supply Voltage
V
Referenced to GNDF
Referenced to GNDL
3.0
5.5
5.5
V
V
LF
V
1.71
DDL
IN1 to IN8 = 0V, LED1
to LED8 = GNDF, SPI
static, REFDI = 7.5kΩ,
REFWB = 24kΩ
Field Supply Current of V
I
V
= 24V
0.6
0.6
1.2
1.2
mA
mA
DD24F
DD24F
DD24F
IN1 to IN8 = 0V, LED1
to LED8 = GNDF, SPI
static, REFDI = 7.5kΩ,
REFWB = 24kΩ
V
V
= 3.3V,
DD3F
Field Supply Current Powered
From V
I
DD3F
DD24F
DD3F
unconnected
V
- V
LCS = V
All logic pins static
,
LF
GNDF
DDL
Field Logic Supply Current
Logic Supply Current
I
2
2
mA
mA
V
LF
= 5.5V
V
V
-
LCS = V ,
DDL
DDL
I
1.5
0.07
0.5
DDL
= 5.5V All logic pins static
GNDL
V
Undervoltage-Lockout
DD3F
V
V
V
V
V
Rising
2.4
6
2.9
UVLO
DD3F
Threshold
V
Undervoltage-Lockout
DD3F
V
V
UVHYST
Threshold Hysteresis
V
Undervoltage-Lockout
DD24F
V
Rising
6.8
V
UVLO24F
DD24F
Threshold
V
Undervoltage-Lockout
DD24F
V
V
UVHYST24F
Threshold Hysteresis
V
Undervoltage-Lockout
LF
V
Rising
0.9
1.66
V
UVLOVLF
LF
Threshold
V
Undervoltage-Lockout
LF
V
0.07
1.6
45
V
UVHYSTVLF
Threshold Hysteresis
V
Undervoltage-Lockout
DDL
V
Rising
1.5
3.0
1.66
3.6
V
UVLOVL
DDL
Threshold
V
Undervoltage-Lockout
DDL
V
mV
UVHYSTVL
Threshold Hysteresis
Regulator Output Voltage
Line Regulation
=
V
I
I
I
1mA
3.3
0
V
DD3F
LOAD
LOAD
LOAD
dV
= 1mA, V
= 12V to 24V
DD24F
mV
mV
DD3FLINE
Load Regulation
dV
= 1mA to 10mA, V
= 24V
4
DD3FLOAD
DD24F
Maxim Integrated
│ 4
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
DC Electrical Characteristics (continued)
V
- V
= +3.0V to +5.5V, V
- V
= +3.0V to +5.5V, V
- V
= +7V to +65V, V
- V
= +1.71V to +5.5V,
LF
GNDF
DD3F
GNDF
DD24F
GNDF
DDL
GNDL
T
= -40°C to +125°C, unless otherwise noted. Typical values are at V - V
= +3.3V, V
- V
= +3.3V, V
- V
A
LF
GNDF
DD3F
GNDF
DD24F GNDF
= +24V, V
- V
= +3.3V, V
= +24V, C = 15pF and T = +25°C. (Note 1)
DDL
GNDL
IN_ L A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Regulator Current Capability
Short-Circuit Current Limit
Field-Side OREADY Threshold
I
25
mA
DD3F_CC
V
current when V
shorted to
DD3F
DD24F
I
28
50
mA
V
DD24F_SC
GNDF, V
= 12V
DD24F
V
V
Rising, V Floating
DD24F
2.4
2.9
OREADY
DD3F
Field-Side OREADY Threshold
Hysteresis
V
OREADY_
0.07
V
HYST
Field-Side OREADY Delay
Logic-Side AFS Delay
SUPPLY ALARMS
t
V
valid to OREADY low
1
ms
D_OREADY
DD3F
IREADY low to AFS high
IREADY high to AFS low
100
100
t
µs
D_AFS
V
V
UV Alarm On/Off
UV Alarm Off/On
V
V
V
Rising, Undervoltage
Falling, Undervoltage
17
V
V
DD24F
ALRMOFFUV
DD24F
V
15
DD24F
ALRMONUV
DD24F
Glitch Filter for V
UV
3
µs
V
DD24F
V
V
VM Alarm On/Off
VM Alarm Off/On
V
V
V
Rising, Missing Voltage
Falling, Missing Voltage
13.9
DD24F
ALRMOFFVM
DD24F
V
12.1
V
DD24F
ALRMONVM
DD24F
Glitch Filter for V
VM
3
µs
V
DD24F
EXTVM Threshold UV On/Off
EXTVM Threshold UV Off/On
EXTVM Threshold VM On/Off
EXTVM Threshold VM Off/On
EXTVM Selection Threshold
V
EXTVM Voltage Rising, Undervoltage
EXTVM Voltage Falling, Undervoltage
EXTVM Voltage Rising, Missing Voltage
EXTVM Voltage Falling, Missing Voltage
0.96
0.93
0.77
0.74
1
1.04
1.01
0.84
0.82
EXTOFFUV
V
0.97
0.81
0.79
0.3
V
EXTONUV
V
V
EXTOFFVM
V
V
EXTONVM
EXTVM
V
SEL
EXTVM Selectable V
Threshold
DD24F
EXTVM
10
-1
30
+1
V
VDD24F
L_EXTVM
EXTVM Leakage Current
TEMPERATURE ALARMS
Overtemperature Alarm 1
Overtemperature Alarm 2
I
µA
T
T
ALRMT1 bit set in FAULT1 register
ALRMT2 bit set in FAULT1 register
115
140
°C
°C
ALRM1
ALRM2
Overtemperature Alarm
Hysteresis
T
T
10
°C
ALRM_HYS
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
T
OTSHDN bit set in FAULT2 register
165
10
°C
°C
SHDN
SHDN_HYS
Maxim Integrated
│ 5
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
DC Electrical Characteristics (continued)
V
- V
= +3.0V to +5.5V, V
- V
= +3.0V to +5.5V, V
- V
= +7V to +65V, V
- V
= +1.71V to +5.5V,
LF
GNDF
DD3F
GNDF
DD24F
GNDF
DDL
GNDL
T
= -40°C to +125°C, unless otherwise noted. Typical values are at V - V
= +3.3V, V
- V
= +3.3V, V
- V
A
LF
GNDF
DD3F
GNDF
DD24F GNDF
= +24V, V
- V
= +3.3V, V
= +24V, C = 15pF and T = +25°C. (Note 1)
DDL
GNDL
IN_ L A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
WIRE-BREAK ALARMS
REFWB Wire-Break Voltage
REFWB Wire-Break Resistor
V
R
R
= 5.2kΩ to 50kΩ
0.61
V
REFWB
REFWB
Nominal value
5.2
400
40
50
510
60
kΩ
REFWB
R
R
= 5.2kΩ
= 50kΩ
470
47
REFWB
Wire-Break Current Range
I
µA
REFWB
REFWB
PCB FAULT ALARMS
REFWB Pin Short Threshold
REFWB Pin Open Threshold
REFDI Pin Short Threshold
REFDI Pin Open Threshold
IC INPUTS (TYPES 1, 2, 3)
Input Threshold Low-to-High
Input Threshold High-to-Low
Input Threshold Hysteresis
LED On-State Current
I
RFWBS bit set in FAULT2 register
RFWBO bit set in FAULT2 register
RFDIS bit set in FAULT2 register
RFDIO bit set in FAULT2 register
550
6.6
550
6.6
µA
µA
µA
µA
REFWBS
I
REFWBO
I
REFDIS
I
REFDIO
V
IN1 to IN8
IN1 to IN8
IN1 to IN8
6
3
V
V
THP+
V
4.4
1.5
THP-
V
0.8
V
INPHYST
I
R
= 7.5kΩ, V = 3V
LED
mA
V
LEDON
REFDI
LED On-State Voltage
V
LEDON
IN1 to IN8 = 36V
IN1 to IN8 = 24V
73
42
DI Leakage, Current Sources
Disabled
I
µA
DI_LEAK
FIELD INPUTS
REFDI Pin Voltage
V
R
R
from 5.2kΩ to 36kΩ
0.61
V
REFDI
REFDI
REFDI Current-Limit Resistor
Nominal value
5.2
36
kΩ
REFDI
R
R
R
= 5.2kΩ
= 7.5kΩ
= 36kΩ
3.39
2.35
0.48
REFDI
REFDI
REFDI
Current-Limit Setting
I
mA
INLIM
TYPE 1 and 3: External Series Resistor R = 1.5kΩ, R
= 7.5kΩ, Wire-Break Detection Off, unless otherwise noted
IN
REFDI
28V > V
LED on, R
at the pin > 5V,
IN_
Input Current Limit
I
2.10
7.4
2.35
2.60
9.9
mA
V
INLIM
= 7.5kΩ (Note 2)
REFDI
Field Input Threshold
Low-to-High
Field Input Threshold
High-to-Low
Field Input Threshold
Hysteresis
R
= 7.5kΩ, R = 1.5kΩ external
REFDI IN
V
INF+
series resistor
R = 7.5kΩ, R = 1.5kΩ external
REFDI
series resistor
R = 7.5kΩ, R = 1.5kΩ external
REFDI
IN
V
V
INF-
INFHYST
IN
V
0.9
V
series resistor
Maxim Integrated
│ 6
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
DC Electrical Characteristics (continued)
V
- V
= +3.0V to +5.5V, V
- V
= +3.0V to +5.5V, V
- V
= +7V to +65V, V
- V
= +1.71V to +5.5V,
LF
GNDF
DD3F
GNDF
DD24F
GNDF
DDL
GNDL
T
= -40°C to +125°C, unless otherwise noted. Typical values are at V - V
= +3.3V, V
- V
= +3.3V, V
- V
A
LF
GNDF
DD3F
GNDF
DD24F GNDF
= +24V, V
- V
= +3.3V, V
= +24V, C = 15pF and T = +25°C. (Note 1)
DDL
GNDL
IN_ L A
PARAMETER
SYMBOL
CONDITIONS
= 5.2kΩ, Wire-Break Detection Off, unless otherwise noted
REFDI
MIN
TYP
MAX
UNITS
TYPE 2: External Series Resistor R = 1kΩ, R
IN
28V > V
LED on, R
at the pin > 5V,
IN_
Input Current Limit
I
3.05
3.39
0.9
3.71
9.9
mA
V
INLIM
= 5.2kΩ (Note 2)
REFDI
Field Input Threshold
Low-to-High
R
= 5.2kΩ, R = 1kΩ external
REFDI IN
V
INF+
series resistor
R = 5.2kΩ, R = 1kΩ external
REFDI
series resistor
R = 5.2kΩ, R = 1kΩ external
REFDI
Field Input Threshold
High-to-Low
IN
V
7.4
V
INF-
INFHYST
Field Input Threshold
Hysteresis
IN
V
V
series resistor
FILTER DELAY
FBP = 1: bypass filtering
FBP = 0, DELAY = 0
FBP = 0, DELAY = 1
FBP = 0, DELAY = 2
FBP = 0, DELAY = 3
FBP = 0, DELAY = 4
FBP = 0, DELAY = 5
FBP = 0, DELAY = 6
FBP = 0, DELAY = 7
2
µs
0.05
0.1
0.4
0.8
1.6
3.2
12.8
20
Input Filter Delay
(See DELAY[2:0] bits in FLT_
Registers)
t
BOUNCE
ms
Wire-Break Filter Delay
t
20
ms
WBD
LOGIC INTERFACE (FIELD-SIDE AND LOGIC-SIDE)
0.7 x
LCS, LSCLK,
2.25V ≤ V
1.71V ≤ V
≤ 5.5V
DDL
V
DDL
LSDI, LLATCH,
SDOEN, relative
to GNDL
0.75 x
Input High Voltage
V
< 2.25V
V
IH
DDL
V
DDL
M1, M0, FSDI, IFAULT, IREADY, FCS,
FSCLK, FSDO, FLATCH relative to GNDF
0.7 x
V
LF
LCS, LSCLK,
2.25V ≤ V
≤ 5.5V
0.8
DDL
DDL
LSDI, LLATCH,
SDOEN, relative
to GNDL
Input Low Voltage
V
1.71V ≤ V
< 2.25V
0.7
V
V
IL
M1, M0, FSDI, IFAULT, IREADY, FCS,
FSCLK, FSDO, FLATCH relative to GNDF
0.3 x
V
LF
FCS, FSCLK, FSDO, OSDI, FLATCH,
relative to GNDF, 4mA source
V
0.4
-
LF
Output High Voltage (Note 3)
V
OH
AFS, LSDO, relative to GNDL,
4mA source
V
DDL
0.4
-
Maxim Integrated
│ 7
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
DC Electrical Characteristics (continued)
V
- V
= +3.0V to +5.5V, V
- V
= +3.0V to +5.5V, V
- V
= +7V to +65V, V
- V
= +1.71V to +5.5V,
LF
GNDF
DD3F
GNDF
DD24F
GNDF
DDL
GNDL
T
= -40°C to +125°C, unless otherwise noted. Typical values are at V - V
= +3.3V, V
- V
= +3.3V, V
- V
A
LF
GNDF
DD3F
GNDF
DD24F GNDF
= +24V, V
- V
= +3.3V, V
= +24V, C = 15pF and T = +25°C. (Note 1)
DDL
GNDL
IN_ L A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FCS, FSCLK, FSDO, OSDI, FLATCH, FFAULT,
OREADY, relative to GNDF, 4mAsource
0.4
0.4
Output Low Voltage (Note 3)
V
V
OL
AFS, LSDO, LFAULT, relative to GNDL,
4mA source
Input Pullup Resistance
R
R
FCS, FLATCH, relative to GNDF
195
195
PU
PD
kΩ
Input Pulldown Resistance
FSCLK, FSDI, M1, M0, relative to GNDF
IREADY pullup to V
LCS, LLATCH, SDOEN pullup to V
,
LF
Input Pullup Current (Note 3)
I
-10
1.5
-1
-5
5
-1.5
10
µA
µA
µA
PU
PD
DDL
Input Pulldown Current
(Note 3)
FSDO, IFAULT pulldown to GNDF,
LSCLK, LSDI pulldown to GNDL
I
Output High-Impedance
Leakage Current (Note 3)
FFAULT, OREADY, relative to GNDF,
LSDO, LFAULT, relative to GNDL
I
+1
OL
LED/GPO DRIVER (LEDR_, LEDC_)
V
0.3
-
LF
Output High Voltage
V
LED on, I
LED on, I
= 5mA
= 5mA
V
OH_LED
LED
LED
Output Low Voltage
V
0.3
V
OL_LED
LED Driver Scan Rate
f
1
kHz
LED
Dynamic Electrical Characteristics
V
- V
= +3.0V to +5.5V, V
- V
= +3.0V to +5.5V, V
- V
= +7V to +65V, V
- V
= +1.71V to +5.5V,
LF
GNDF
DD3F
GNDF
DD24F
GNDF
DDL
GNDL
T
= -40°C to +125°C, unless otherwise noted. Typical values are at V - V
= +3.3V, V
- V
= +3.3V, V
- V
A
LF
GNDF
DD3F
GNDF
DD24F GNDF
= +24V, V
- V
= +3.3V, V
= +24V, C = 15pF and T = +25°C. (Note 1)
DDL
GNDL
IN_
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FIELD INPUT SAMPLING
Input Filter Bypass Mode
Input Filter Delay Mode
1000
200
Input (IN_) Sampling Rate
f
kHz
µs
IN
Minimum Detectable IN_ Pulse
Width
No External Capacitors on Pins
IN1 to IN8 (Note 2)
t
3
PW
Assertion of LLATCH or LCS until
input data is frozen
LLATCH Delay
t
75
ns
µs
LLATCH
LFAULT Minimum Pulse Width
t
LFAULT low, pullup 4mA
0.8
PW_LFAULT
DIGITAL ISOLATION
Common-Mode Transient
Immunity
CMTI
I_ = GND_ (Note 4)
50
kV/µs
Maxim Integrated
│ 8
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Dynamic Electrical Characteristics (continued)
V
- V
= +3.0V to +5.5V, V
- V
= +3.0V to +5.5V, V
- V
= +7V to +65V, V
- V
= +1.71V to +5.5V,
LF
GNDF
DD3F
GNDF
DD24F
GNDF
DDL
GNDL
T
= -40°C to +125°C, unless otherwise noted. Typical values are at V - V
= +3.3V, V
- V
= +3.3V, V
- V
A
LF
GNDF
DD3F
GNDF
DD24F GNDF
= +24V, V
- V
= +3.3V, V
= +24V, C = 15pF and T = +25°C. (Note 1)
DDL
GNDL
IN_
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI CHARACTERISTICS
LSCLK Data Rate
DR
5
MHz
ns
MAX
LSCLK Pulse Width-High
LSCLK Pulse Width-Low
LSCLK Clock Period
t
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
20
20
120
20
5
LSCLKH
t
ns
LSCLKL
t
ns
LSCLK
LCS Pulse Width
t
ns
LCSPW
LSDI-to-LSCLK Setup Time
LSDI-to-LSCLK Hold Time
LCS-Fall-to-LSCLK Rise Time
t
ns
LSDISU
t
15
80
ns
LSDIH
LSCLK_SU
t
ns
Rising edge of LSCLK to rising
edge of LCS (Figure 1)
LSCLK-Rise-to-LCS Rise Time
t
40
ns
LCSH
t
LCS_LSDO_
VALID
LSDO Enable Time
LCS falling to LSDO valid (Figure 1)
LCS rising to LSDO High-Z (Figure 1)
70
70
60
ns
ns
ns
LSDO Disable Time
t
LCS_LSDO_TRI
LSCLK falling to LSDO valid
(Figure 1)
Output Data Propagation Delay
t
43
DO
LSDO Rise Time
LSDO Fall Time
t
LSDO 10% to 90% rising
LSDO 90% to 10% falling
4
4
ns
ns
R
t
F
Note 1: All units are production tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: External resistor REFDI is selected to set any desired current limit between 0.48mA and 3.39mA (typical values). The cur-
rent limit accuracy of ±11% is guaranteed for values greater or equal to 2mA.
Note 3: All currents into the device are positive. All currents out of the device are negative. All voltages are referenced to their
respective ground (GNDF and GNDL), unless otherwise noted.
Note 4: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to
both rising and falling common-mode voltage edges. Tested with the transient generator connected between GNDF and
GNDL.
t
LCSBPW
t
LSCLK_SU
t
LCSBH
LCS
t
t
t
LSCLKH
...
LSCLKL
t
LSCLK
14
1
2
10
11
12
13
15
16
LSCLK
LSDI
t
LSDISU
LSDIH
MSB
...
...
LSB
t
t
t
LCSB_LSDO_TRI
HIGH-Z
LCSB_LSDO_VALID
DO
HIGH-Z
LSDO
MSB
LSB
Figure 1. SPI Timing Diagram
Maxim Integrated
│ 9
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Insulation Characteristics
PARAMETER
SYMBOL
CONDITIONS
VALUE
UNITS
Maximum Withstand Isolation
Voltage
V
f
= 60Hz, duration = 60s (Note 5, 6)
600
V
RMS
ISO
SW
12
V
V
V
= 500V, T = 25°C
> 10
IO
IO
IO
A
11
Insulation Resistance
R
= 500V, 100°C ≤ T ≤ 125°C
> 10
Ω
IO
A
9
= 500V at T = 150°C
S
> 10
Barrier Capacitance Field-Side
to Logic-Side
CIO
f
= 1MHz (Note 7)
2
pF
SW
Minimum Creepage Distance
Minimum Clearance Distance
Internal Clearance
CPG
CLR
2.3
2.3
mm
mm
mm
Distance through insulation
Material Group I (IEC 60112)
0.015
Comparative Tracking Index
Climate Category
CTI
> 600
40/125/21
Pollution Degree
(Table 1 of DIN VDE 0110)
2
Note 5: V
is defined by the IEC 60747-5-5 standard.
ISO
Note 6: Product is qualified at V
for 60s and 100% production tested at 120% of V
for 1s.
ISO
ISO
Note 7: Capacitance is measured with all logic pins on field-side and logic-side tied together.
ESD Protection
PARAMETER
SYMBOL
CONDITIONS
VALUE
UNITS
Human Body Model, All Field-Side Pins Referenced
to GNDF, All Logic-Side Pins Referenced to GNDL
ESD
±2
kV
ESD and EMC Characteristics
PARAMETER
SYMBOL
CONDITIONS
VALUE
UNITS
IEC 61000-4-5, 1.2/50µs pulse, minimum 1kΩ resistor
in series with IN1 - IN8, with respect to GNDF
Line-to-Line
±2
Surge
ESD
kV
IEC 61000-4-5, 1.2/50µs pulse, minimum 1kΩ resistor
in series with IN1 - IN8, with respect to GNDF
Line-to-GNDF
Contact
±1
±8
IEC 61000-4-2, minimum 1kΩ resistor in series with
IN1- IN8, with respect to GNDF
kV
IEC 61000-4-2, minimum 1kΩ resistor in series with
IN1- IN8, with respect to GNDF
Air-Gap
±15
Safety Regulatory Approvals
UL
The MAX22192 are certified under UL1577. For more details, refer to File E351759.
Rated up to 600V isolation voltage for single protection.
RMS
cUL (EQUIVALENT TO CSA NOTICE 5A)
The MAX22192 are certified up to 600V
for single protection. For more details, refer to File E351759.
RMS
Maxim Integrated
│ 10
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
the junction temperature. Thermal impedance values (θ
JA
Safety Limits
and θ ) are available in the Package Information sec-
JC
Damage to the IC can result in a low-resistance path
to ground or to the supply and, without current limiting,
the MAX22192 could dissipate an excessive amount of
power. Excessive power dissipation can damage the die
and result in damage to the isolation barrier, potentially
causing downstream issues. Table 1 shows the safety
limits for the MAX22192.
tion of the data sheet. The power dissipation (P ) can be
D
calculated as:
P
D
= ∑(V
× I ) + V
IN_
× I
+
IN_
LF
DD24F
× I
DDL
DD24F
V
× I + V
LF
DDL
Calculate the junction temperature (T ) as:
J
T = T + (P × θ )
JA
J
A
D
The maximum safety temperature (T ) for the device is
S
the 150°C maximum junction temperature specified in the
absolute maximum ratings (see the Absolute Maximum
Ratings section). The power dissipation (P ) and junc-
Figure 2 and Figure 3 show the thermal derating curve
for safety limiting the power and the current of the device.
Ensure that the junction temperature does not exceed
150°C.
D
JA
tion-to-ambient thermal impedance (θ ) determine
THERMAL DERATING CURVE
FOR SAFETY POWER LIMITING
THERMAL DERATING CURVE
FOR SAFETY CURRENT LIMITING
2500
25
MULTILAYER
MULTILAYER
BOARD
BOARD
2000
20
15
10
5
1500
1000
500
0
0
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 2. Thermal Derating Curve for Safety Power Limiting
Figure 3. Thermal Derating Curve for Safety Current Limiting
Table 1. Safety Limiting Values for the MAX22192
PARAMETER
Safety Current on Any Pin
Total Safety Power Dissipation
Maximum Safety Temperature
SYMBOL
TEST CONDITIONS
MAX
20
UNIT
mA
I
T = 150°C, T = 25°C, Multilayer Board
S
J
A
P
T = 150°C, T = 25°C, Multilayer Board
2286
150
mW
°C
S
S
J
A
T
Maxim Integrated
│ 11
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Typical Operating Characteristics
(V
= +24V, V
= V = +3.3V, V
= +3.3V, T = +25°C, R
= 7.5kΩ, R
= 24kΩ, R = 1.5kΩ, unless otherwise
DD24F
DD3F
LF
DDL
A
REFDI
REFWB
IN
noted.)
VDD24F SUPPLY CURRENT
VDD3F SUPPLY CURRENT
VDD24F SUPPLY CURRENT
vs. TEMPERATURE
vs. VDD24F SUPPLY VOLTAGE
vs. VDD3F SUPPLY VOLTAGE
toc03
toc01
toc02
0.77
0.725
0.720
0.715
0.710
0.705
0.700
0.695
0.690
0.70
0.68
0.66
0.64
0.62
0.60
LCS = VDDL, NO LSCLK SWITCHING,
VDD24F UNCONNECTED,
ALL VIN_ = 24V, EXTVM = VDD3F
LCS = VDDL, NO LSCLK SWITCHING,
VDD24F = 24V, VDD3F UNCONNECTED,
ALL VIN_ = 24V, EXTVM = GNDF
LCS = VDDL, NO LSCLK SWITCHING,
VDD3F UNCONNECTED,
ALL VIN_ = 24V, EXTVM = GNDF
0.75
0.73
0.71
0.69
0.67
-50
-25
0
25
50
75
100 125
5
15
25
35
45
55
65
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (⁰C)
VDD24F SUPPLY VOLTAGE (V)
VDD3F SUPPLY VOLTAGE (V)
VDD3F SUPPLY CURRENT
vs. VIN_ INPUT VOLTAGE
VDD3F SUPPLY CURRENT
vs. TEMPERATURE
VDD24F SUPPLY CURRENT
vs. VIN_ INPUT VOLTAGE
toc04
toc05
toc06
0.65
0.64
0.63
0.62
0.61
0.60
0.72
0.70
0.68
0.66
0.64
0.62
0.60
0.64
0.62
0.60
0.58
0.56
0.54
0.52
LCS = VDDL, NO LSCLK SWITCHING,
VDD24F UNCONNECTED,
ALL VIN_ = 24V, EXTVM = VDD3F
ALL VIN_ SHORTED TOGETHER
ALL VIN_ MEASURED AT THE PIN
LCS = VDDL, NO LSCLK SWITCHING,
VDD24F = 24V
ALL VIN_ SHORTED TOGETHER
ALL VIN_ MEASURED AT THE PIN
LCS = VDDL, NO LSCLK SWITCHING,
VDD3F = 3.3V, VDD24F FLOATING
-50
-25
0
25
50
75
100 125
0
8
16
24
32
40
0
8
16
24
32
40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (⁰C)
INPUT CURRENT LIMIT IINLIM
vs. RREFDI
INPUT CURRENT LIMIT IINLIM
vs. TEMPERATURE
toc07
toc08
4.0
2.8
VIN_ = 40V
VDD24F = 24V, VIN_ = 24V,
RREFDI = 7.5kΩ
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
5
10
15
20
25
30
35
-50
-25
0
25
50
75
100 125
RREFDI (kΩ)
TEMPERATURE (⁰C)
Maxim Integrated
│ 12
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Typical Operating Characteristics (continued)
(V
= +24V, V
= V = +3.3V, V
= +3.3V, T = +25°C, R
= 7.5kΩ, R
= 24kΩ, R = 1.5kΩ, unless otherwise
DD24F
DD3F
LF
DDL
A
REFDI
REFWB
IN
noted.)
INPUT CURRENT LIMIT IINLIM
vs. VDD3F SUPPLY VOLTAGE
INPUT CURRENT LIMIT IINLIM
vs. VDD3F SUPPLY VOLTAGE
INPUT CURRENT LIMIT IINLIM
vs. VDD3F SUPPLY VOLTAGE
toc09
toc10
toc11
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.8
VDD24F UNCONNECTED, VIN_ = 24V,
RREFDI = 7.5kΩ, WIRE-BREAK OFF
VDD24F UNCONNECTED, VIN_ = 24V,
RREFDI = 7.5kΩ,
RREFWB = 24kΩ, WIRE-BREAK ON
VDD24F UNCONNECTED, VIN_ = 24V,
RREFDI = 5.2kΩ, WIRE-BREAK OFF
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD3F SUPPLY VOLTAGE (V)
VDD3F SUPPLY VOLTAGE (V)
VDD SUPPLY VOLTAGE (V)
INPUT CURRENT LIMIT IINLIM
vs. VDD3F SUPPLY VOLTAGE
INPUT CURRENT LIMIT IINLIM
vs. VIN_ INPUT VOLTAGE
INPUT CURRENT LIMIT IINLIM
vs. VIN_ INPUT VOLTAGE
toc12
toc13
toc14
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD24F UNCONNECTED, VIN_ = 24V,
RREFDI = 5.2kΩ,
RREFWB = 24kΩ, WIRE-BREAK ON
VDD24F = 24V, RREFDI = 7.5kΩ
VIN_ AT THE PIN,
RREFWB = 24kΩ, WIRE-BREAK OFF
VDD24F = 24V, RREFDI = 7.5kΩ
VIN_ AT THE PIN,
RREFWB = 24kΩ, WIRE-BREAK ON
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
VDD3F SUPPLY VOLTAGE (V)
INPUT VOLTAGE THRESHOLD
vs. TEMPERATURE
INPUT VOLTAGE THRESHOLD
vs. TEMPERATURE
toc15
toc16
11
10
9
12
VDD24F = 24V, RREFDI = 7.5kΩ, RIN = 1.5kΩ
LOW-TO-HIGH
VDD24F = 24V, RREFDI = 5.2kΩ, RIN = 1kΩ
LOW-TO-HIGH
11
10
9
8
8
7
HIGH-TO-LOW
HIGH-TO-LOW
7
6
6
5
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TEMPERATURE (⁰C)
TEMPERATURE (⁰C)
Maxim Integrated
│ 13
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Typical Operating Characteristics (continued)
(V
= +24V, V
= V = +3.3V, V
= +3.3V, T = +25°C, R
= 7.5kΩ, R
= 24kΩ, R = 1.5kΩ, unless otherwise
REFWB IN
DD24F
DD3F
LF
DDL
A
REFDI
noted.)
INPUT VOLTAGE THRESHOLD
vs. TEMPERATURE
INPUT VOLTAGE HYSTERESIS
vs. TEMPERATURE
toc17
toc18
7
6
5
4
1.3
1.2
1.1
VDD24F = 24V, RIN = 0Ω
LOW-TO-HIGH
RIN = 1.5kΩ
RIN = 1kΩ
1.0
0.9
0.8
0.7
0.6
RIN = 0Ω
HIGH-TO-LOW
3
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TEMPERATURE (⁰C)
TEMPERATURE (⁰C)
WIRE-BREAK CURRENT THRESHOLD
vs. RREFWB
LDO LOAD REGULATION
toc19
toc20
0.6
0.5
0.4
0.3
0.2
0.1
3.33
3.30
3.27
3.24
3.21
3.18
3.15
0.0
0
10
20
30
40
50
0
5
10
15
20
25
30
RREFWB (kΩ)
VDD3F OUTPUT CURRENT (mA)
LDO OUTPUT VOLTAGE
vs. TEMPERATURE
LDO LINE REGULATION
toc21
toc22
3.35
3.31
3.27
3.23
3.19
3.38
3.34
3.30
3.26
3.22
3.18
3.14
3.10
IDD3F = 5mA
IDD3F = 5mA
IDD3F = 20mA
3.15
5
15
25
35
45
55
65
-50
-25
0
25
50
75
100 125
TEMPERATURE (⁰C)
VDD24F SUPPLY VOLTAGE (V)
Maxim Integrated
│ 14
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Typical Operating Characteristics (continued)
(V
= +24V, V
= V = +3.3V, V
= +3.3V, T = +25°C, R
= 7.5kΩ, R
= 24kΩ, R = 1.5kΩ, unless otherwise
REFWB IN
DD24F
DD3F
LF
DDL
A
REFDI
noted.)
LDO SHORT-CIRCUIT CURRENT
vs. VDD24F SUPPLY VOLTAGE
LDO SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
toc23
toc24
50
45
40
35
30
25
20
15
50
45
40
35
30
25
20
15
10
VDD24F = 24V,
ALL VIN_ = 0V,
THERMAL SHUTDOWN TRIGGERED AT
THERMAL SHUTDOWN IS TRIGGERED WHEN
VDD24F > 39V, VDD3F SHORTED TO GNDF,
ALL VIN_ = 0V
TA > 125⁰C
10
5
10
15
20
25
30
35
-50
-25
0
25
50
75
100 125
SUPPLY VOLTAGE (V)
TEMPERATURE (⁰C)
LOGIC SUPPLY VLF CURRENT
vs. DATA RATE
VDD3F SUPPLY CURRENT
vs. DATA RATE
toc25
toc26
3.9
3.4
2.9
2.4
1.9
1.4
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
VDD24F UNCONNECTED,
VDD3F = VLF = VDDL = 3.3V,
ALL VIN_ = 0V,
VDD24F =24V, VLF = VDDL = 3.3V,
ALL VIN_ = 0V,
LCS = GNDL, DAISY CHAIN MODE,
LSDI = 01010101 PATTERN
LCS = GNDL, DAISY CHAIN MODE,
LSDI = 01010101 PATTERN
0.9
0
0
2
4
6
8
10
2
4
6
8
10
SPI DATA RATE (MHz)
SPI DATA RATE (MHz)
LOGIC SUPPLY VDDL CURRENT
vs. DATA RATE
EXTVM THRESHOLD VOLTAGE
vs. TEMPERATURE
toc28
toc27
12.0
11.5
11.0
10.5
10.0
9.5
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
VDD24F =24V, VLF = VDDL = 3.3V,
ALL VIN_ = 0V,
VDD24F = 24V,
EXTERNAL RESISTORS 11kΩ/1kΩ
LCS = GNDL, DAISY CHAIN MODE,
LSDI = 01010101 PATTERN
LOW-TO-HIGH
9.0
HIGH-TO-LOW
8.5
8.0
1.2
0
-50
-25
0
25
50
75
100 125
2
4
6
8
10
TEMPERATURE (⁰C)
SPI DATA RATE (MHz)
Maxim Integrated
│ 15
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Pin Configurations
TOP VIEW
A
B
C
D
E
F
G
H
J
K
+
1
REFWB GNDF IN8
IN7
IN6
IN5
IREADY
GNDL NC
V
LF
MAX22192
2
3
4
5
6
7
LEDR0 REFDI LED8 LED7 LED6 LED5 FFAULT OREADY
LEDR2 LEDR1 GNDF GNDF GNDF FSDO IFAULT GNDF
LEDC0 LEDC1 GNDF GNDF GNDF FLATCH FSDI GNDF
LEDC2 M1 GNDF GNDF GNDF FSCLK OSDI GNDF
AFS
V
DDL
LFAULT LSDO
LLATCH LSDI
LSCLK LCS
GNDL SDOEN
M0
LED1 LED2 LED3 LED4 FCS
GNDF
V
DD24F
IN1
IN2
IN3
IN4 EXTVM GNDF
NC
NC
V
V
DD3F
DD24F
GQFN
(6mm x 10mm)
Pin Description
PIN
NAME
FUNCTION
REFERENCE
POWER SUPPLY
Logic-Side Power Supply. Bypass with 0.1µF ceramic capacitor as close as
possible to the pin. Set logic level for all logic-side signals.
J2
V
GNDL
-
DDL
J1, J6
A7, B6
GNDL
Power and Signal Ground for Logic-Side
24V Field Supply. Bypass with 0.1µF capacitor in parallel with 1µF capacitor to
V
GNDF
DD24F
GNDF. If powering the MAX22192 from V
, leave V
unconnected.
DD24F
DD3F
3.3V Field-Side Output. Internal LDO output when powered from V
, or
DD24F
B7
G1
V
3.0V–5.5V supply input when V
0.1µF capacitor in parallel with 1µF capacitor.
is unconnected. Bypass to GNDF with
GNDF
DD3F
DD24F
Field-Side Logic Interface Supply. Bypass with 0.1µF ceramic capacitor as
close as possible to the pin. Set logic level for all field-side digital signals.
V
GNDF
-
LF
B1, C3-C5, D3-
D5, E3-E5, H3-H7
GNDF
Power and Signal Ground for Field-Side
Maxim Integrated
│ 16
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Pin Description (continued)
PIN
NAME
FUNCTION
REFERENCE
LOGIC-SIDE DIGITAL PINS
Logic-Side Chip-Select Input. Input to CS Isolation Channel. Has a weak
internal pullup to V . Drive LCS low to enable LSDO and assert FCS low,
which latches input states and enable the field-side SPI interface.
K5
J5
LCS
LSCLK
LSDI
GNDL
GNDL
GNDL
DDL
Logic-Side Serial Clock Input to SCLK Isolation Channel. Has a weak internal
pulldown.
Logic-Side Serial Data Input to SDI Isolation Channel. Has a weak internal
pulldown. Data is clocked into LSDI on the rising edge of LSCLK. OSDI is the
output of SDI channel on the field-side.
K4
Logic-Side Serial Data Output. Becomes High-Z when LCS and SDOEN are
both high. LSDO is enabled when either LCS or SDOEN is low. Data is updated
on the falling edge of LSCLK.
K3
LSDO
GNDL
Logic-Side Input to LATCH Isolation Channel. Has a weak internal pullup to V
Drive LLATCH low to assert FLATCH low, which latches all eight input states.
.
DDL
J4
J3
LLATCH
LFAULT
GNDL
GNDL
Logic-Side Open-Drain Output of FAULT Isolation Channel. LFAULT goes low
to indicate fault conditions on the field-side. Connect a pullup resistor to V
.
DDL
LSDO Enable. Has a weak internal pullup to V
. Drive SDOEN low to enable
DDL
LSDO when sharing the isolation with other field-side SPI devices in the inde-
pendent slave configuration; drive SDOEN high and allow LCS to enable LSDO
in the standalone or daisy-chain configuration.
K6
SDOEN
GNDL
Field-Side Active. AFS is high to indicate field-side is operating normally and
IREADY is low. When field-side is not powered, AFS is set low and all logic-side
outputs are in a default state (LFAULT is low and LSDO is low when enabled). A
nominal 100µs delay is added between the detection of field-side power and the
assertion of AFS to ensure power supply is settled and a minimum pulse width
for AFS.
K2
AFS
NC
GNDL
-
K1, J7, K7
Not Connected. Leave it unconnected, or connect to GNDL
FIELD-SIDE DIGITAL PINS
Output of CS Isolation Channel and Field-Side Chip-Select Input. All digital
input states are latched and field-side SPI interface is active when FCS is
low. Connect the CS of other field-side SPI devices to FCS when sharing the
MAX22192 isolation in the daisy-chain configuration.
G6
F5
FCS
GNDF
GNDF
Output of SCLK Isolation Channel and Field-Side Serial Clock Input. Connect
the SCLK of other field-side SPI devices to FSCLK when sharing the
MAX22192 isolation.
FSCLK
Output of SDI Isolation Channel. In the standalone SPI or independent slave
configuration, connect OSDI to FSDI. In the daisy-chain configuration, connect
OSDI to the SDI of the first field-side SPI device. The MAX22192 is the last
device in the chain. Refer to Figure 12 for details.
G5
OSDI
GNDF
Maxim Integrated
│ 17
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Pin Description (continued)
PIN
NAME
FUNCTION
REFERENCE
Field-Side Serial Data Input. Has a weak internal pulldown. Data is clocked into
FSDI on the rising edge of FSCLK. In the standalone SPI or independent slave
configuration, connect OSDI to FSDI. In the daisy-chain configuration, connect
FSDI to the SDO of the next to last field-side SPI device. The MAX22192 is the
last device in the chain. Refer to Figure 12 for details.
G4
FSDI
GNDF
Field-Side Serial Data Output and Input to SDO Isolation Channel. Data is
updated on the falling edge of FSCLK. When FCS is high, FSDO is high-
impedance. In the SPI independent slave configuration, connect the SDO of
other field-side SPI devices to FSDO. In the daisy-chain configuration, the
MAX22192 is the last device in the chain since FSDO is internally connected to
the isolation. Refer to Figure 12 for details.
F3
FSDO
GNDF
Output of LATCH Isolation Channel and Field-Side LATCH Input. FLATCH and
FCS control the data latch at the input of the field-side serializer. The latch is
transparent when both FCS and FLATCH are high. The input data is frozen on
the falling edge of either FLATCH or FCS. Connect FLATCH to the LATCH input
of other field-side SPI devices when sharing the MAX22192 isolation.
F4
FLATCH
FFAULT
GNDF
GNDF
Field-Side Open-Drain Active-Low Fault Indicator. Connect a pullup resistor to
V
. Connect FFAULT to IFAULT to isolate FAULT signal. FFAULT goes low to
LF
G2
indicate that one or more of the flags in the FAULT registers have been set. The
faults include: supply monitors, temperature monitors, CRC error, wire-break
detection, and short or open at REFDI or REFWB pins.
Field-Side Input to FAULT Isolation Channel. Has a weak internal pulldown.
Connect FFAULT and FAULT of other field-side SPI devices to IFAULT when
sharing the MAX22192 isolation.
G3
H2
IFAULT
GNDF
GNDF
Field-Side Open-Drain Active-Low Ready Indicator. OREADY goes low indicating
the field-side is powered up and ready for operation. Connect OREADY to
OREADY
IREADY to isolate READY signal. Connect a pullup resistor to V
.
LF
Field-Side Ready Input to READY Isolation Channel. Has a weak internal
pullup. Assert IREADY low when field-side is ready for operation. When
IREADY is high, AFS is low and logic-side outputs are in their default state
(LFAULT is low and LSDO is low when enabled). When IREADY is low, AFS
is high and all isolation channels operate normally. Connect OREADY and
READY of other field-side SPI devices to IREADY when sharing the MAX22192
isolation.
H1
IREADY
GNDF
GNDF
B5
A6
M1
M0
SPI Control Mode. See Table 3 for details.
Maxim Integrated
│ 18
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Pin Description (continued)
PIN
NAME
FUNCTION
REFERENCE
INPUT PINS
Field Digital Inputs. For Type 1 and Type 3 inputs, place a 1.5kΩ resistor between
the field input and IN_ pin. For Type 2 inputs, place a 1kΩ resistor between field
input and IN_ pin. Capacitors for filtering should not be connected to the IN_ pins.
See the Surge Protection of Field Inputs section for further information.
C7, D7, E7, F7,
F1, E1, D1, C1
IN1 - IN8
GNDF
GNDF
GNDF
C6, D6, E6, F6,
F2, E2, D2, C2
LED1 -
LED8
Energyless LED Driver Outputs. Connect to GNDF if LEDs are not used.
Open-Drain Auxiliary LED Matrix Row 0–2 Output, or Push-Pull GPO Output.
Connect to LED cathode when configured as LED output. Connect a resistor in
series with the LED between LEDR_ and LEDC_. Refer to the GPO Register
and LED Register for details.
LEDR0 -
LEDR2
A2, B3, A3
A4, B4, A5
Open-Drain Auxiliary LED Matrix Column 0–2 Output, or Push-Pull GPO Out-
put. Connect to LED anode when configured as LED output. Connect a resistor
in series with the LED between LEDR_ and LEDC_. Refer to the GPO Register
and LED Register for details.
LEDC0 -
LEDC2
GNDF
Digital Input Current-Limit Reference Resistor. For Type 1 and Type 3 inputs,
place a 7.5kΩ resistor from REFDI to GNDF. For Type 2 inputs, place a 5.2kΩ
resistor from REFDI to GNDF.
B2
A1
REFDI
GNDF
GNDF
Wire-Break Current-Limit Reference Resistor. Connect a 5.2kΩ–50kΩ resis-
tor from REFWB to GNDF to set the wire-break threshold. See the Wire-Break
Detection section for details.
REFWB
External V
Supply Monitoring Input. Connect EXTVM to GNDF to use
DD24F
internal thresholds for both V
undervoltage and voltage missing monitor-
DD24F
ing. Connect EXTVM to external resistive divider to set the external thresholds
G7
EXTVM
GNDF
for both V undervoltage and voltage missing monitoring. Connect EXTVM
DD24F
to V
to disable V
voltage monitoring, while 24VM and 24VL faults
DD24F
DD3F
are always off. This is useful when the device is powered by V
DD3F.
Maxim Integrated
│ 19
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Functional Block Diagram
V
DDL
3.3V
REGULATOR
CONTROL REGISTERS
SUPPLY
MONITOR
REFDI
REF_DI
REFWB
REF_WB
LFAULT
TEMPERATURE
MONITOR
AFS
DELAY
REF_WB
REF_DI
V
LF
REFWB
FILTER
UVLO
IN1
LSDO
REFDI
FILTER
S
E
R
I
A
L
I
SDOEN
LCS
LATCH
LED1
Z
E
R
LSCLK
LSDI
INPUT CHANNEL 1,
TYPICAL OF 8
IN8
LED8
INPUT CHANNEL 8
LLATCH
LED MATRIX DRIVER
GPO DRIVER
GNDF
GNDL
Maxim Integrated
│ 20
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Input Filters
Detailed Description
Each input (IN1–IN8) has a programmable filter and input
data can be filtered to reduce noise, or it can be read
directly for more rapid response. The input is sampled
and data is updated at 1MHz (typ) when the input filter
is disabled. When the digital filter is enabled, the input
is sampled at 200kHz (typ). Bit FBP in the correspond-
ing FLT_ register is used to bypass the filter or to enable
the filter. One of eight filter delays (50µs, 100µs, 400µs,
800µs, 1.6ms, 3.2ms, 12.8ms, 20ms) can be indepen-
dently selected for each channel. Noise rejection is
accomplished through a nonrollover up-down counter
where the state of the field input controls the counting
direction (up or down). The filter uses an up-down coun-
ter fed by a 200kHz clock. If the input is high, it counts
up; if the input is low, it counts down. The filter output is
updated when the counter hits the upper or lower limit,
with the upper limit depending on the selected filter delay
and the lower limit being zero regardless of the filter delay.
The low-to-high transition of the filter occurs when the
counter reaches the upper limit. The high-to-low transi-
tion occurs when the counter reaches the lower limit.
There is no rollover; counting simply stops when the
upper or lower limit is hit. The filter delay is the time it
takes to reach the upper/lower limit in response to a step
input when the counter starts from the lower/upper limit.
The MAX22192 senses the state (on, high or off, low) of
eight digital inputs. The voltages at the IN1 to IN8 input
pins are compared against internal references to deter-
mine whether the sensor is ON (logic 1) or OFF (logic 0).
All eight inputs are simultaneously latched by the asser-
tion of either LLATCH or LCS, and the data made avail-
able in a serialized format using the isolated SPI interface.
Placing a 7.5kΩ current-setting resistor between REFDI
and GNDF, and a 1.5kΩ resistor between each field input
and the corresponding IN_ input pin ensures that the cur-
rent at the ON and OFF trip points, as well as the voltage
at the trip points, satisfy the requirements of IEC 61131-2
for Type 1 and Type 3 inputs. The current sunk by each
input pin rises linearly with input voltage until the level
set by the current limiter is reached; any voltage increase
beyond this point does not increase the input current.
Limiting the input current ensures compliance with IEC
61131-2 while significantly reducing power dissipation
compared to traditional resistive inputs.
The current-setting resistor R
using this equation:
can be calculated
REFDI
R
= 17.63V / I
REFDI
INLIM
STANDARD OPERATING RANGE FOR 24V DC DIGITAL INPUTS (CURRENT SINKING)
V
(V)
IN
V
HMAX
ON REGION
I
I
HMAX
HMIN
V
V
or V
TMAX
HMIN
V
LMAX
I
TRANSITION REGION
OFF REGION
TMAX
I
TMIN
or V
LMAX
TMIN
I
LMIN
I
LMAX
0
I
(mA)
IN
V
LMIN
TYPE 1 LIMITS
TYPE 2 LIMITS
OFF REGION TRANSITION
TYPE 3 LIMITS
TYPE
OF
OFF REGION TRANSITION
ON REGION
ON REGION
OFF REGION TRANSITION
ON REGION
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
H
LIMIT
L
L
T
T
H
H
L
L
T
T
H
H
L
L
T
T
H
(V)
(mA)
(V)
(mA)
(V)
(mA)
(V)
(mA)
(V)
(mA)
(V)
(mA)
(V)
(mA)
(V)
(mA)
(V)
(mA)
MAX
MIN
15/5
15
15
15
30
15
11/5
30
11
30
30
30
11/5
15
11
15
30
15
-3
ND
5
0.5
15
2
-3
ND
5
2
11
6
-3
ND
5
1.5
11
2
ND = NOT DEFINED
Figure 4. Switching Characteristics for IEC 61131-2 Type 1, 2, and 3 24V
Digital Inputs
DC
Maxim Integrated
│ 21
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
If the input is not a step function, but is bouncing, as
shown in Figure 5, the output changes state after a total
delay of:
open switch with a diagnostic resistor placed across it.
The wire break current threshold is set by placing a resis-
tor between REFWB and GNDF, and is adjustable from
50µA to 470µA. If this current is missing, due to an open-
wire or a wire shorted to GNDF, the comparator trips, and
after filtering, sets a corresponding sticky bit in the WB
register. Bits in this register remain set until the register is
read, which automatically clears all bits in the register. All
wire-break detectors include a fixed 20ms filter, and like
the input data, the input to the WB register is frozen when
either LCS or LLATCH is held low. The eight wire-break
flags are ORed together to produce the WBG flag in the
FAULT1 register. This flag remains set until all flags in the
WB register have been cleared.
Total Delay = Filter Delay + 2 x (Total Time at the Old State)
In the example in Figure 5, the filter has a nominal delay
of 1.6ms, and the input returns high for two 0.2ms periods
after the first transition from high to low. These transitions
back to the high state extend the time before the output
of the filter switches. Total Delay = 1.6ms + 2 × (0.2ms +
0.2ms) = 2.4ms.
Wire-Break Detection
Each input (IN1–IN8) includes a second threshold com-
parator that can be individually enabled to verify the
integrity of field wiring. The comparator senses the pres-
ence of the small input current produced by a two-wire
proximity sensor in its open state, or the current from an
The wire-break threshold resistor R
lated using this equation:
can be calcu-
REFWB
R
= 2.44V ÷ I
WB
REFWB
CLEAR-ON-READ
TO SERIALIZER
RESET
LCS
SET
WB STICKY
LATCH
LLATCH
REFWB
20ms
FILTER
BYPASS CONTROL
FILTER BYPASS
1MHz SAMPLING
FULL
M
U
X
REFIN
IN_
S
SCALE
Q
TRANSPARENT
LATCH
UP/DOWN
TO SERIALIZER
UP/DOWN
COUNTER
(NO ROLLOVER)
CLK
0
LCS
LLATCH
Q
200kHz
R
COUNTER FS CONTROL
50μs TO 20ms
TOTAL TIME AFTER FIRST EDGE
IN_
SATURATED HIGH (1.6ms)
OUTPUT IS HIGH
COUNTER VALUE
SWITCH THRESHOLD = 0.0ms
1.6ms
1.1ms
1.3ms
0.8ms
1.0ms
0.0ms
AT 0.0ms,
OUTPUT SWITCHES FROM HIGH TO LOW
SWITCHING THRESHOLD SET TO FULL SCALE (1.6ms)
OUTPUT
Figure 5. MAX22192 Digital Filter
Maxim Integrated
│ 22
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
MAX22192 channel. For proper surge protection, it is
important that each MAX22192 input has its own resistor.
Any two MAX22192 channels can be used; they need not
be contiguous (Figure 6). Either channel can be read to
determine the input state. The additional power dissipa-
tion from this Type 2 configuration can reduce the maxi-
mum ambient operating temperature, especially when all
Type 2 Sensor Inputs
The additional input current (6mA min) and associated
power dissipation of the Type 2 input requires the use
of two MAX22192 inputs in parallel. The current of each
channel is set to a nominal 3.39mA (6.78mA total) by
placing a 5.2kΩ resistor from REFDI to GNDF. The proper
voltage drop across the input resistor is maintained by
reducing the resistance from 1.5kΩ to 1kΩ for each
the inputs are high, the MAX22192 is powered by V
DD24F
more than 30V, or V
has additional load.
DD3F
24V
3.3V
1.8V
1µF
0.1µF
0.1µF
1µF
0.1µF
1µF
M1
M0
V
V
V
V
LF
DDL
DD24F
DD3F
5.2kΩ
REFDI
REFWB
EXTVM
24kΩ
V
DD
AFS
GPI
1kΩ
1kΩ
FIELD INPUT
CH1
IN1
LCS
CS
LED1
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
MAX22192
MICRO
CONTROLLER
IN2
LSDO
LED2
LLATCH
1.8V
INPUT AT PIN
1kΩ
1kΩ
4.7kΩ
FIELD INPUT
CH4
IN7
SDOEN
LFAULT
LED7
GPI or INT
IN8
GND
LED8
470Ω
470Ω
470Ω
LEDC2
LEDC1
LEDC0
24VM
LEDR2
LEDR1
LEDR0
FCS FSCLK FSDO FSDI OSDI FFAULT IFAULT OREADY IREADY FLATCH GNDF GNDL
4.7kΩ
4.7kΩ
3.3V
Figure 6. Implementing a 4-Channel Type 2 Digital Input with MAX22192
Maxim Integrated
│ 23
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
each LEDC_ output (Figure 7). Current from each resistor
flows through only one LED at a time.
Energyless LED Drivers
When IN_ is determined to be ON, its input current is
diverted to the LED_ pin and flows from that pin to GNDF.
Placing an LED between LED_ and GNDF provides an
indication of the input state without increasing overall
power dissipation. If the indicator LEDs are not used, con-
nect LED_ to GNDF.
When powering the MAX22192 directly from the V
DD24F
using
field supply, the V
is powered from V
DD3F
DD24F
an internal LDO. Care should be taken not to exceed the
maximum power dissipation ratings (see the Absolute
Maximum Ratings section). Since the LEDs draw current
ultimately from V
supply, each LED in the On state
DD24F
Programmable Auxiliary LEDs
generates approximately the same amount of power dis-
sipation as an input channel in the On state. This is not
a concern when the LEDs are used as wire-break indica-
tors, because for each LED that is on, at least one input
is in wire-break and guaranteed to be off.
LEDR_ and LEDC_ pins can be configured as LED driv-
ers for a 3 × 3 LED crossbar matrix by setting the DIR
bit low in the GPO register. LEDR_ pins are open-drain
pulldown drivers to be connected to LED’s cathode, and
LEDC_ pins are open-drain pullup drivers to be connected
to LED’s anode (see Figure 7). This offers a pin-optimized
configuration for driving nine LEDs. One LED, located at
row 2 column 2 (R2C2), is dedicated to the status of the
LEDR_ and LEDC_ as GPOs
The LEDR_ and LEDC_ pins used for the LED driver
matrix can also be configured as push-pull GPO pins.
It provides further flexibility and allows general purpose
steady-state signals to be created without multiplexing.
Set the DIR bit in the GPO register to high to configure the
pins as direct drive outputs and disable the LED matrix
drivers. The output state of each pin is configured by the
corresponding bits (bits [5:0]) in the GPO register, 0 as
output low and 1 as output high (see the Register Detailed
Description section).
V
supply. It is on when V
supply voltage is
DD24F
DD24F
above the 24VM voltage missing threshold. The remain-
ing eight LEDs are typically configured to indicate the wire
break status of eight channels, but can also be used for
other purposes. Each LED’s On or Off status is controlled
by setting the corresponding bit in the LED register. LEDs
in the On state are driven with a 33% duty cycle, 1kHz
square wave powered by V
supply. Each LED’s on-
DD3F
current is set by a current-limiting resistor in series with
Fault Detection and Monitoring
FFAULT is an open-drain output that can be wire ORed
with other open-drain field-side outputs and used to notify
the host processor of a fault. When enabled, FFAULT goes
low to indicate that one or more of the flags in the FAULT1
24V
3.3V
0.1µF 1µF
1µF
0.1µF
register have been set. These faults include: V
low
DD24F
voltage alarm (24VL), V
voltage missing alarm
DD24F
V
V
V
DD24F DD3F LF
(24VM), overtemperature alarm 1 (ALRMT1), overtem-
perature alarm 2 (ALRMT2), CRC error detected on the
previous SPI frame (CRC), power-on-reset event (POR),
wire-break group error detected (WBG), and sources
from the FAULT2 register. The FFAULT pin can be con-
figured to be asserted by one or more fault flags if the
corresponding fault bits are enabled in the FAULT1EN or
FAULT2EN registers. The enabled bits do not affect the
flags in the FAULT1 register, they only affect the FFAULT
pin. Flags ALRMT1, ALRMT2, 24VL, and 24VM in the
FAULT1 register are latched; they remain set until read
even if the fault goes away. WBG is equivalent to the
ORed output of the individual wire-break flags (WB[7:0]),
which are latched until cleared by reading the WB regis-
ter. CRC is not latched, but remains set until an uncor-
rupted SPI frame is received.
470Ω
LEDC2
LEDC1
LEDC0
470Ω
470Ω
24VM
MAX22192
LEDR2
LEDR1
LEDR0
GNDF
Figure 7. MAX22192 LED Matrix (LEDR_, LEDC_)
Maxim Integrated
│ 24
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
The STK bit in the GPO register configures the FFAULT
necting the FFAULT pin to the IFAULT pin on the field-
side, which is the input of the FAULT isolation channel.
The FAULT isolation channel can be shared by multiple
field-side devices by wiring OR with other open-drain
FAULT outputs, and connecting all field-side FAULT sig-
nals to IFAULT pin.
pin to be sticky or to clear when the fault is removed. For
example: if a low voltage condition on V
is detect-
DD24F
ed, the 24VL bit in the FAULT1 register is set and FFAULT
asserts low provided bit 24VLE in the FAULT1EN register
is set. If V
then returns to normal levels, the 24VL
DD24F
bit in the FAULT1 register remains set until read; however
the state of FFAULT pin depends on configuration bit STK
in the GPO register. If STK is low, the FFAULT pin is not
sticky and clears when the fault goes away even though
the 24VL bit remains set. If STK is high, then the FFAULT
pin reflects the state of the bit in the FAULT1 register and
remains set until the bit is cleared by reading the FAULT1
register. The minimum pulse width for the FFAULT pin
asserting low is 1µs typical. This ensures adequate time
for the assertion of FFAULT to be recognized by the host
even if the fault was present for a shorter time.
Clearing Bits in the FAULT1 Register
24VL and 24VM sticky (or latched) bits in the FAULT1
register can be read and cleared either through a direct
read of the FAULT1 register, or through a SPI Mode 0 or
Mode 2 read or write command if bit 24VF in the CFG
register is equal to 0. SPI Modes 0 and 2 transactions
read and clear bits 24VL and 24VM (Table 5). This valid
SPI transaction also clears the CRC bit. Note that the
CRC bit is only active in Modes 0 and 2 since the CRC
code is only generated in these two modes. The WBG bit
in the FAULT1 register is the real-time ORed value of bits
WB[7:0] in the WB register and the WBG bit is not cleared
by reading the FAULT1 register. Reading the bits in the
WB register clears the WB register and for convenience
also clears the WBG bit in the FAULT1 register.
The power-on default for the FAULT1EN register is to enable
CRC and POR. The FFAULT pin is in the nonsticky mode.
The MAX22192 provides an isolated LFAULT pin on the
logic-side. The FFAULT signal can be isolated by con-
V
LF
FAULT2 REGISTER
FAULT1 REGISTER
0
0
CRC*
POR*
FAULT2*
ALRMT2**
ALRMT1**
24VL**
10kΩ
FAULT8CK
OTSHDN
RFDIO
RFDIS
RFWBO
RFWBS
CLEAR-ON-READ
(COR)
* DYNAMIC
** CLEAR-ON-READ
(COR)
FFAULT
24VM**
REGISTER GPO, BIT 7 STK:
WBG*
STK = 0: FFAULT PIN IS NOT STICKY
STK = 1: FFAULT PIN IS STICKY
SET BITS IN FAULT2EN TO ENABLE EACH ERROR FLAG
SET BITS IN FAULT1EN TO ENABLE EACH ERROR FLAG
WB REGISTER
WB7
WB6
WB5
WB4
WB3
WB2
CLEAR-ON-READ
(COR)
WB1
WB0
Figure 8. FFAULT/LFAULT Output Sources
Maxim Integrated
│ 25
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
the detection. When less than a 6.6µA current is detected,
meaning an open at REFDI, the 2mA minimum input cur-
rent is not guaranteed. When open or short at the REFDI
pin is detected, the RFDIO or RFDIS bit in the FAULT2
register is set (Table 2).
External V
Voltage Monitor
DD24F
The EXTVM input controls the V
field supply volt-
DD24F
age monitoring thresholds for both the V
age alarm (24VL) and the V
(24VM). When the EXTVM is connected to V
low volt-
DD24F
voltage missing alarm
DD24F
, the
DD3F
V
voltage monitoring on both 24VL and 24VM are
When more than 550µA current is detected at the REFWB
pin, meaning a short at the REFWB pin, the wire-break
faults are always on even though the input wires are
correctly connected. When less than 6.6µA current is
detected, meaning an open at REFWB, the wire-break
faults are always off even though the input wires are not
connected. When open or a short at the REFWB pin is
detected, the RFWBO or RFWBS bit in the FAULT2 reg-
ister is set (Table 2). Note the RFWBO bit is set when the
wire-break function of all channels are off, or after power-
on-reset (see the Register Detailed Description section).
DD24F
turned off, and the 24VL and 24VM bits in the FAULT1 reg-
ister are always low. This is useful when the MAX22192 is
being powered directly from a 3.3V supply on V
and
DD3F
V
is unconnected. When EXTVM is connected to
DD24F
GNDF, the voltage on V
low voltage and voltage missing thresholds to clear the
24VL and 24VM alarms. To use the user-defined V
voltage monitoring thresholds, use an external resistive
divider to apply an analog voltage directly to EXTVM. The
voltage at EXTVM must be greater than the 24VL thresh-
must be above the internal
DD24F
DD24F
old of 1V (V
) nominal, and the 24VM threshold of
) nominal to clear the faults. Figure 9 shows
24VL
Thermal Consideration
0.81V (V
24VM
The MAX22192 operates at an ambient temperature of
125°C on a properly designed PCB. Operating at higher
voltages, with heavy output loads or driving LEDs while
input channels are on increases power dissipation and
reduces the maximum allowable operating temperature.
See the Package Information and Absolute Maximum
Ratings sections for safety operation temperature and
maximum power dissipation.
an example of the V
being monitored with the use
DD24F
of external resistive divider to set user-defined 24VL and
24VM thresholds, V and V
.
DD24_VM
DD24_VL
V
= V
= V
× (1 + R2 / R1)
× (1 + R2 / R1)
DD24_VL
24VL
V
DD24_VM
24VM
Short/Open Detection at REFDI and REFWB
Short or open detection at the REFDI and REFWB pins
is implemented by monitoring the current at REFDI and
REFWB pin. When more than 550µA of current is detected
at the REFDI pin, meaning a short at REFDI, all input chan-
nels are disabled, but the REFDI buffer is still on to keep
The MAX22192 is in thermal shutdown when the ther-
mal shutdown temperature threshold (165°C typical) is
exceeded. During thermal shutdown, the internal volt-
age regulator, input channels, REFDI and REFWB cir-
cuitry, and field-side SPI communication are all turned
off, except that register values are retained. A thermal
shutdown event can be read back from the FAULT2 reg-
ister once the device is out of thermal shutdown (Table 2).
24V
3.3V
0.1µF 1µF
1µF
0.1µF
Powering the MAX22192 with the V
Pin
DD3F
The MAX22192 can alternatively be powered using a
3.0V–5.5V supply connected to the V pin. In this
V
V
V
DD24F DD3F LF
DD3F
R2
R1
case, a 24V supply is no longer needed and the V
DD24F
EXTVM
pin must be left unconnected. This configuration has
lower power consumption and heat dissipation since the
MAX22192
on-chip LDO voltage regulator is disabled (the V
DD24F
7.5kΩ
undervoltage lockout is below the threshold and automati-
cally disables the LDO). See Figure 10 for details.
REFDI
24kΩ
REFWB
In this configuration, connect the EXTVM pin to V
DD3F
to disable the V
voltage monitoring function.
DD24F
GNDF
Otherwise, the device always indicates a “24V FAULT”
due to bits 24VL and 24VM in the FAULT1 register, and
the FFAULT pin is always active (low) if the bits are
enabled in the FAULT1EN register. To overcome this, set
bits 24VLE and 24VME in the FAULT1EN register to 0.
Figure 9. External V
External Resistor Divider
Thresholds Set by EXTVM and
DD24F
Maxim Integrated
│ 26
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Table 2. Thermal Shutdown and Open/Short at REFDI and REFWB
BIT IN FAULT2
BEHAVIOR
INTERNAL BLOCKS
REGISTER
SHORT at REFDI
OPEN at REFDI
RFDIS
RFDIO
Input channels are disabled
2mA minimum current limit is not guaranteed
Wire-break faults are always on
All input channels disabled, REFDI buffer on
-
-
-
SHORT at REFWB
OPEN at REFWB*
RFWBS
RFWBO
Wire-break faults are always off
Internal LDO disabled, all input channels
disabled, REFDI buffer off, field-side SPI off,
SPI configuration maintained
THERMAL
SHUTDOWN
OTSHDN
Device shutdown
*RFWBO is set after power-on-reset or when wire-break detection on all channels are turned off.
3.3V
1.8V
0.1µF
1µF
0.1µF
1µF
M1
M0
V
DDL
V
V
V
LF
DD24F
DD3F
7.5kΩ
24kΩ
3.3V
REFDI
V
DD
REFWB
AFS
GPI
EXTVM
IN1
1.5kΩ
1.5kΩ
FIELD INPUT
FIELD INPUT
LCS
CS
LED1
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
MAX22192
MICRO
CONTROLLER
IN2
LSDO
LED2
LLATCH
1.8V
INPUT AT PIN
1.5kΩ
4.7kΩ
IN8
FIELD INPUT
SDOEN
LFAULT
LED8
GPI or INT
470Ω
470Ω
470Ω
LEDC2
LEDC1
LEDC0
GND
24VM
LEDR2
LEDR1
LEDR0
FCS FSCLK FSDO FSDI OSDI FFAULT IFAULT OREADY IREADY FLATCH GNDF GNDL
4.7kΩ
4.7kΩ
3.3V
Figure 10. MAX22192 Field-Side Powered by V
, V
Unconnected, EXTVM Disabled
DD3F DD24F
Maxim Integrated
│ 27
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
other field-side devices can be connected to FSDO when
sharing the isolation in the independent slave mode.
Refer to the Typical Operating Circuits for details.
Digital Isolation
The MAX22192 provides galvanic isolation for digital sig-
nals that are transmitted between two ground domains,
GNDF and GNDL. The device withstands up to 600V
The FFAULT is the field-side active-low open-drain FAULT
indicator. Connect the FFAULT output to the IFAULT input
to isolate the FAULT signal, and LFAULT is the logic-side
open-drain output. When sharing the isolation with other
field-side devices, connect the open-drain FAULT signals
from other devices to IFAULT. Both FFAULT and LFAULT
pins require a pullup resistor.
RMS
for up to 60 seconds in the 70-pin GQFN package, which
has 2.3mm of creepage and clearance. The package
material has a minimum comparative tracking index (CTI)
of 600V, giving it a Group I rating in creepage tables.
The MAX22192 offers low-power operation, high elec-
tromagnetic interference (EMI) immunity, and stable
temperature performance through Maxim’s proprietary
process technology. The device isolates different ground
domains and blocks high-voltage/high-current transients
from sensitive or human interface circuitry.
The OREADY is the field-side active-low READY indica-
tor. OREADY goes low indicating the field-side is powered
up and ready for operation. Connect the OREADY output
to the IREADY input to isolate the READY signal, and
AFS is the logic-side output. When IREADY is high, AFS
is low and logic-side outputs are in their default state,
indicating the field-side is not ready for operation. When
IREADY is low, AFS is high and the MAX22192 operates
normally. The READY isolation channel can be shared
by other field-side devices by connecting other open-
drain READY signals to IREADY. Refer to the Typical
Operating Circuits for details.
The logic supply voltages V and V
determine the
DDL
LF
logic levels on the field-side and logic-side, respectively.
The V can be set independetly to any voltage from 3.0V
LF
to 5.5V, and the V
can be set from 1.71V to 5.5V.
DDL
Isolation Channels
The MAX22192 provides six isolation channels including
CS, SCLK, SDI, SDO, FAULT, and LATCH. The LCS,
LSCLK, LSDI, LSDO, LFAULT and LLATCH are logic-side
signals, referenced to GNDL. These signals are isolated
from field-side and usually interface with microcontrollers
or FPGAs. The FCS, FSCLK, FSDI, OSDI, FSDO,
FFAULT, IFAULT, OREADY, and IREADY are field-side
signals, referenced to GNDF. They can be connected with
other field-side SPI and control signals when sharing the
MAX22192 isolation channels.
When sharing the READY isolation channel with other open-
drain active-low READY signals such as that of MAX22190,
the OREADY signal and the READY signal from the
MAX22190s are connected together to the IREADY pin. The
IREADY is pulled low when one of the OREADY or READY
signal from the MAX22190s is low and ready for operation.
Care must be taken on the software to determine if all of the
devices are ready. Alternatively, an OR gate can be used
between OREADY and other READY signals to guarantee
the IREADY signal is only pulled low when all the READY
signals are low.
The LCS and LSCLK are the logic-side isolation inputs,
and the FCS and FSCLK are their corresponding field-
side isolation outputs. The CS and SCLK signals from
other field-side devices can be connected to FCS and
FSCLK when sharing the isolation in the daisy-chain
or independent slave mode. The CS signals from other
field-side devices should have their own external isolation
channels in the independent slave mode. The OSDI is
the field-side output of the SDI isolation channel, and the
LSDI is the corresponding logic-side input. Connect the
OSDI to FSDI in the standalone or independent slave
mode. The SDI signals from other field-side devices
can be connected to OSDI when sharing the isolation in
the independent slave mode. In the daisy-chain mode,
connect the OSDI to the SDI of the first field-side device
in the chain, and connect FSDI to the SDO of the next
to last field-side device in the chain. The MAX22192 is
the last device in the chain. The FSDO is the field-side
input of the SDO isolation channel, and the LSDO is the
corresponding logic-side output. The SDO signals from
The logic-side SDOEN signal is an output enable control
for LSDO. It is useful when the MAX22192 isolation chan-
nels are shared by other field-side devices in the inde-
pendent slave mode by enabling the LSDO when LCS is
not asserted. When the MAX22192 is operating in stand-
alone or daisy-chain mode, LCS low enables all field-side
devices’ SPI interface as well as the LSDO output. When
the MAX22192 is operating in the independent slave
mode, the MAX22192 uses LCS to enable its own SPI,
while other field-side devices have their own dedicated
CS isolation channel, external to the MAX22192. The
independent slave mode requires LSDO to be enabled
any time one of the CS signals is asserted, which can be
accomplished by asserting SDOEN low. In the case that
there is no need for LSDO to be high-impedance, SDOEN
can be permanently connected to GNDL. Refer to the
Typical Operating Circuits for details.
Maxim Integrated
│ 28
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
rising edge of LSCLK and data at LSDO is updated on the
falling edge of LSCLK. The MSB (R/W bit) is always the
first bit of the SPI frame. Transitions of LSCLK while LCS
is deasserted (high) are ignored. LSCLK must idle low
when LCS is asserted.
SPI Interface
The MAX22192 has an SPI compatible interface used
to read input data, read diagnostic data, and configure
all the registers. Each configuration register can be read
back to ensure proper configuration. The interface can be
operated in one of four modes as controlled by the strap-
ping inputs M0 and M1 (Table 3). Asserting LCS low latch-
es the state of all inputs and enables the SPI interface.
For all modes, data at the LSDI input is sampled on the
SPI Protocol
The serial output of the device adheres to the SPI proto-
col, running with CPHA = 0 and CPOL = 0. In all modes,
the first 8-bits clocked out of LSDO after LCS is asserted
are data bits showing the status of inputs IN8–IN1; this
allows for rapid and convenient retrieval of the primary
data. For write operations in SPI Modes 0 and 1, the
next 8-bits clocked out of LSDO are the status bits of the
WB (wire-break) register. This is true even if wire-break
detection is not enabled, in which case all bits are 0. For
reads in SPI Modes 0 and 1, the second 8-bits are the
data from the specified register. See Figure 11 for an SPI
communication example.
Table 3. SPI Interface Modes
MODE M1: M0 FRAME LENGTH CRC DAISY CHAIN
0
1
2
3
0 0
0 1
1 0
1 1
24-bit
16-bit
24-bit
16-bit
Yes
No
No
No
Yes
No
Yes
Yes
MODE 0 WRITE CYCLE
LCS
IN[8:1]
INPUTS
4
5
6
7
18
19
20
1
2
3
8
9
10
11
12
13
14
15
16
17
21
22
23
24
LSCLK
LSDI
1* A6
A5
A4
A3
A2
A1
A0
D7
D4 D3
D2 D1
D0
0
0
0
C4
C3
C2
C1
C0
D5
D6
HIGH-Z
HIGH-Z
DI7 DI6 DI5 DI4 DI3 DI2
WB5 WB4 WB3 WB2 WB1
24VM WBG C4
WB0 24VL
C3 C2
C1
C0
DI1 DI0 WB7 WB6
LSDO
MODE 0 READ CYCLE
LCS
IN[8:1]
INPUTS
4
5
6
7
18
19
20
1
2
3
8
9
10
11
12
13
14
15
16
17
21
22
23
24
LSCLK
LSDI
0* A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
C4
C3
C2
C1
C1
C0
C0
0
0
HIGH-Z
HIGH-Z
DI7 DI6 DI5 DI4 DI3 DI2
D5
D4
D3 D2 D1
24VM WBG C4
D0 24VL
C3 C2
DI1 DI0 D7
D6
LSDO
* READ = 0 OR WRITE = 1
CRC[4:0] FOR LSDI IS GENERATED BY HOST SUCH AS MCU
CRC[4:0] FOR LSDO IS GENERATED BY MAX22192
NOTE: INPUT PINS ARE LABELLED IN8–IN1, AND MAP TO DI REGISTER BITS DI7–DI0, AND WB REGISTER BITS WB7–WB0
Figure 11. SPI Communication Example (Mode 0)
Maxim Integrated
│ 29
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
SPI Modes 2 and 3 are more complex, since the
content of the second byte is determined by the previous
instruction. For non-daisy-chain compatible modes (SPI
Modes 0 and 1), the read instruction is decoded on-the-
fly as the SPI frame is clocked in. The instruction is
immediately executed and data from the specified register
is clocked out in the same SPI frame. This is convenient
and quick, but not compatible with daisy-chaining. When
daisy-chaining, each unit does not know which portion of
the bit stream it should decode until LCS is deasserted
(the frame is finished). To accommodate this, all daisy-
chainable read instructions require two SPI frames. The
first frame contains the read instruction and register
address, and the second frame returns the register data
as the second byte of the frame. This is true regardless of
the instruction being clocked in during the second frame.
the CRC bits can be disabled by operating in SPI modes
1 and 3. The CRC uses the following polynomial:
5
4
2
0
P(x) = x + x + x + x
The 5-bit CRC value is calculated using the first 19 data
bits, padded with the 5-bit initial word 00111. The 5-bit
CRC result is then appended to the original data bits to
create the 24-bit SPI data frame. When the MAX22192
receives a data frame with a CRC error, the CRC error
flag (CRC) in the FAULT1 register is set and, if CRCE is
set, FFAULT pin is asserted. The CRC bit is not sticky, but
does remain set until an error-free frame is received. SPI
commands within a corrupted frame are ignored.
SPI Power Status
On the field-side, only the SPI port buffers are powered
from the V supply; internal SPI circuits are powered from
LF
LLATCH is used to simultaneously capture the input
states of the MAX22192s and companion Octal Digital
Input device MAX22190s, which are not controlled by the
same LCS. This could be MAX22192 and MAX22190s in
the same module, or MAX22192s in different modules.
the V
supply. Both V
and V must be valid for
DD3F
DD3F LF
SPI communication to take place. In addition to powering
the SPI circuits, V also sustains the SPI memory (con-
figuration and status registers). If power is being supplied
through V , then an auxiliary supply for the memory is
DD3F
DD24F
also available. The auxiliary supply only sustains the mem-
ory, and it does not allow SPI communication. The auxiliary
Clock Count for Multiples of 8
For each SPI cycle (between LCS going low and going
high), the device counts the number of LSCLK pulses. If it
is not a multiple of 8, the SPI input data is discarded and
bit FAULT8CK is set in the FAULT2 register.
supply takes over if V
is lost due to external loading
DD3F
or a thermal shutdown event. When the event is over, the
device configuration is maintained and fault information is
available in the FAULT registers (Table 4).
CRC generation
The logic-side SPI communication is powered from the
V
DDL
supply regardless of the V
or V
status.
In SPI Interface Modes 0 and 2, five CRC bits can be
used to check data integrity during transfer between the
device and an external microcontroller. In applications
where the integrity of data transferred is not of concern,
DD24F
DD3F
The internal digital isolation operates normally as long as
and V voltages are in the normal operating range.
V
LF
DDL
Table 4. SPI Port Power Status
SPI REGISTER
FIELD-SIDE SPI
LOGIC-SIDE SPI
COMMUNICATION
V
V
V
V
DDL
DD24F
DD3F
LF
VALUE
COMMUNICATION
Normal Operation
Normal Operation
Valid
Valid
Valid
Valid
Valid
Valid
Valid
X*
Valid
Data Maintained
Normal Operation
Not Valid Data Maintained
LCS ignored, LSDO is High-Z
Not Valid
Valid
X*
Data Maintained FCS ignored, FSDO is High-Z* LCS ignored, LSDO is High-Z*
Not Valid
Not Valid
Valid
Valid
X*
Valid
Data Maintained
Normal Operation
Normal Operation
Normal Operation
Valid
Not Valid Data Maintained
LCS ignored, LSDO is High-Z
Not Valid Not Valid
Valid
*When V and V
between field-side and logic-side, no matter if V
by multiple field-side devices.
X*
X
Data Lost
FCS ignored, FSDO is High-Z* LCS ignored, LSDO is High-Z*
FCS ignored, FSDO is High-Z LCS ignored, LSDO is High-Z
X
Not Valid
Data Maintained
are both valid, the internal isolation is powered up and operates normally, and SPI signals are transmitted
DDL
LF
or V
is valid or not. This is useful when the isolation channels are shared
DD24F
DD3F
Maxim Integrated
│ 30
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
(FLT_) are set to BYPASS, all input channels are enabled,
and all fault sources are disabled on the LFAULT pin
except the CRC and POR flags. Upon power-up, the POR
flag is set to 1. If the LFAULT pin is being used, then a
write operation must be performed to the FAULT1 register
to reset POR to 0 for normal operating conditions. Now
the MAX22192 is ready to be polled to read data from DI
register to show the logic state of the eight input channels.
Daisy-Chaining
For systems with more than eight sensor inputs, multiple
field-side devices can be daisy-chained to allow access
to all data inputs through a single isolated serial port.
When using a daisy-chain configuration on the field-side,
connect OSDI to the SDI of the first device in the chain.
Connect FSDI to the SDO of the next to last device in
the chain. The MAX22192 is the last device in the chain.
For all middle links, connect SDI to SDO of the previous
device and SDO to SDI of the next device. FCS and
FSCLK of all devices in the chain should be connected
together in parallel, see Figure 12, which illustrates a
24-input application for daisy-chaining and Figure 13,
which shows SPI daisy-chian timing for Mode 3.
Configurable Mode: The MAX22192 can be configured
for different parameters based upon the application
requirements. The MCU can write to the various registers
to set the options for wire break, input channel filters,
enabling different fault sources, or disabling specific input
channels. In addition, the user can enable features such
as driving the LED matrix or making the LFAULT pin sticky
or not. Once the configuration is complete, the MAX22192
is ready to be polled to read from DI register to show the
logic state of the eight input channels.
Configuration Flowchart
The MAX22192 powers on with default register settings
and can be used in default mode to read the data inputs,
or it can be configured to match the individual application
requirements. Before any register access for configuration
or reading data, the MCU needs to wait until AFS goes
high indicating that the MAX22192 is powered up and
ready for use. Next, the MCU needs to clear the LFAULT
pin that asserts low after every power-up event due to the
default state (high) of the POR bit in the FAULT1 register.
See Figure 14 for details.
FAULT Asserted: The MAX22192 uses the open-drain
LFAULT pin to indicate to the MCU that a fault has
occurred, often by using this pin to trigger an interrupt
function within the MCU. The MCU can determine the
source of the fault by reading regsiter FAULT1. If bit 5 of
the FAULT1 register is set, then register FAULT2 is indi-
cating a fault, and the FAULT2 register must also be read.
Reading the FAULT_ register clears the fault flag, unless
the fault condition persists, which would immediately reset
the flag.
Default Mode (Power-up mode): In this mode, the Wire-
Break (WB) function is disabled, all input channel filters
3.3V
1.8V
FCS
FSCLK
R
R
V
V
V
DDL
FAULT
READY
LF
DDL
OSDI
AFS
LCS
GPI
CS
SCLK
SDO
CS
SCLK
SDO
V
V
L
L
CS
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
INT
MAX22190
DEVICE A
MAX22190
DEVICE B
MAX22192
DEVICE C
MICRO
CONTROLLER
SDI
SDI
FSDI
LSDO
LLATCH
LFAULT
READY FAULT LATCH
READY FAULT LATCH
FSDO
FLATCH
OREADY IREADY FFAULT IFAULT GNDF
GNDL
GNDL
Figure 12. SPI Daisy-Chain Diagram
Maxim Integrated
│ 31
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
MODE 3, DAISY-CHAIN READ
FRAME 1
FRAME 2
LCS
2
B
...
8
18
1
9
10
0
...
16
0
17
0
... 24
25
26
...
32
2
18
... 24
1
...
8
9
10
...
16
17
25
“X”
“X”
26
...
32
LSCLK
LSDI
OSDI
B
0
0
...
0
0
...
0
“X”
A6
A0
B
A6
A
A0
A0
A
B
SDO
FSDI
A
HIGH-Z
HIGH-Z
HIGH-Z
...
IN8 IN7 IN1 D7
D0
A
“X”
“X”
0
0
0
...
0
A
A
A
A
A6
B
B
B
HIGH-Z
...
...
IN8 IN7 IN1 D7
D0
B
IN8 IN7
A
IN1 D7
A
D0
A
LSDO
B
B
B
A
A
B
B
“X”
MODE 3, DAISY-CHAIN WRITE
FRAME 1
16
FRAME 2
LCS
2
B
...
8
18
1
9
10
...
17
1
... 24
25
26
...
32
2
18
... 24
1
...
8
9
10
...
16
17
25
“X”
“X”
26
...
32
LSCLK
LSDI
OSDI
B
1
...
...
...
“X”
A6
A0 D7
B
D6
D0
B
A6
A
A0 D7
A
D6
D6
D0
A
B
B
A
A
B
SDO
FSDI
A
HIGH-Z
HIGH-Z
HIGH-Z
...
...
IN8 IN7 IN1 WB7
WB0
A
“X”
“X”
1
A
A
A
A
B
A6
B
A0
D7
B
D0
B
B
B
B
HIGH-Z
...
IN8 IN7 IN1 WB7
WB0 IN8 IN7
IN1 WB7
A
WB0
A
LSDO
B
B
B
A
A
B
A
B
“X”
3.3V
1.8V
FCS
FSCLK
R
R
V
LF
V
DDL
V
DDL
FAULT
READY
OSDI
AFS
LCS
GPI
CS
SCLK
SDO
V
L
CS
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
INT
MAX22190
DEVICE A
MAX22192
DEVICE B
MICRO
CONTROLLER
SDI
FSDI
LSDO
LLATCH
LFAULT
READY FAULT LATCH
FSDO
FLATCH
OREADY IREADY FFAULT IFAULT GNDF
GNDL
GNDL
Figure 13. SPI Daisy-Chain Communication Example (Mode 3)
Maxim Integrated
│ 32
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
POWER UP
N
Y
WAIT UNTIL MAX22192 IS POWERED UP
AFS HIGH?
Y
OREADY, AFS ASSERTED
FAULT1: POR BIT = 1
FFAULT, LFAULT ASSERTED
MAX22192 CONFIGURED FOR USER
DEFINED MODES
MAX22192 OPERATES IN DEFAULT MODES
N
DEFAULT MODE?
WIRE-BREAK FEATURE CAN BE
ENABLED ON A PER CHANNEL BASIS
WB DISABLED
VALUE = 0x00
WIRE-BREAK FEATURE IS DISABLED
WRITE WB
ALL INPUT CHANNEL FILTERS
ARE SET TO BYPASS
INPUT CHANNEL FILTERS CAN BE
SET ON A PER CHANNEL BASIS
FLT1 to FLT8
VALUE = 0x08
WRITE FLT1 to FLT8
FIX FILTERS AT MID-SCALE, ENABLE
DETECTION OF SHORT ON REFDI
LED, GPO
VALUE = 0x00
WRITE CFG, SET CLRF
OR REFDI_SH_ENA BITS
LED MATRIX IS OFF
MAKE FFAULT, LFAULT PIN STICKY OR NOT
CONFIGURE LED MATRIX OR GPO
ALL INPUT CHANNELS ARE
ENABLED FOR READING DATA
INEN
VALUE = 0xFF
WRITE GPO, LED
SET STK BIT
ALL FAULT SOURCES DISABLED
EXCEPT CRC AND POR
FAULT1EN
VALUE = 0xC0
ENABLE INDIVIDUAL FAULT SOURCES
ENABLE INDIVIDUAL FAULT SOURCES
WRITE FAULT2EN
WRITE FAULT1EN
CLEAR POR
FFAULT, LFAULT DEASSERTED
WRITE FAULT1,
SET POR BIT = 0
CLEAR CRC AND POR
FFAULT, LFAULT DEASSERTED
WRITE FAULT1,
SET POR BIT = 1
READ INPUT DATA (POLLING)
READ DI
READ DI
READ INPUT DATA (POLLING)
FAULT INTERRUPT
N
LFAULT LOW?
Y
DETERMINE FAULT SOURCE, CLEAR BITS ON READ
READ FAULT1
0
1
IS FAULT IN REGISTER FAULT1 OR FAULT2?
ERRORS ARE IN FAULT2
Bit 5: FAULT2 ?
ERRORS ARE IN FAULT1
SOME FAULT1 FLAGS
ARE LATCHED
READ FAULT1
READ FAULT2
FAULT2 IS CLEAR-ON-READ
SERVICE FAULT
SOURCE
SERVICE FAULT
SOURCE
ENSURE FAULT
CONDITION IS CLEARED
ENSURE FAULT
CONDITION IS CLEARED
Y
Y
LFAULT LOW?
N
LFAULT LOW?
N
NORMAL OPERATION
NORMAL OPERATION
Figure 14. MAX22192 Configuration Flowchart
Maxim Integrated
│ 33
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Table 5. SPI Frames for SPI Modes
Mode 0: M1 = 0, M0 = 0
Write
MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
000 Fill Data
3-bits
CRC from Host
5-bits
LSB
LSDI
Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
CRC from MAX22192
5-bits
LSDO
24VL 24VM WBG
Read
MSB = 0
1-bit
Register Address
7-bits
0000,0000 Fill Data
8-bits
000 Fill Data
3-bits
CRC from Host
5-bits
LSB
LSDI
Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
CRC from MAX22192
5-bits
LSDO
24VL 24VM WBG
Mode 1: M1 = 0, M0 = 1
Write
MSB = 1
1-bit
Register Address
7-bits
Input data: IN8 – IN1
8-bits
Write Data
8-bits
LSDI
WB data: WB7 – WB0
8-bits
LSDO
Read
MSB = 0
1-bit
Register Address
7-bits
0000,0000 Fill Data
8-bits
LSDI
Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
LSDO
Mode 2: M1 = 1, M0 = 0
Write – Preceding frame was a write or no-op
MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
000 Fill Data
3-bits
CRC from Host
5-bits
LSB
LSDI
Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
CRC from MAX22192
5-bits
LSDO
24VL 24VM WBG
Write – Preceding frame was a read
MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
000 Fill Data
3-bits
CRC from Host
5-bits
LSB
LSDI
Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
CRC from MAX22192
5-bits
LSDO
24VL 24VM WBG
Read – Preceding frame was a write or no-op
MSB = 0
1-bit
Register Address
7-bits
0000,0000 Fill Data
8-bits
000 Fill Data
3-bits
CRC from Host
5-bits
LSB
LSDI
Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
CRC from MAX22192
5-bits
LSDO
24VL 24VM WBG
Maxim Integrated
│ 34
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Table 5. SPI Frames for SPI Modes (continued)
Read – Preceding frame was a read
MSB = 0
1-bit
Register Address
7-bits
0000,0000 Fill Data
8-bits
000 Fill Data
3-bits
CRC from Host
5-bits
LSB
LSDI
Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
CRC from MAX22192
5-bits
LSDO
24VL 24VM WBG
Mode 3: M1 = 1, M0 = 1
Write – Preceding frame was a write or no-op
MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
LSDI
Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
LSDO
Write – Preceding frame was a read
MSB = 1
1-bit
Register Address
7-bits
Write Data
8-bits
LSDI
Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
LSDO
Read – Preceding frame was a write or no-op
MSB = 0
1-bit
Register Address
7-bits
0000,0000 Fill Data
8-bits
LSDI
Input data: IN8 – IN1
8-bits
WB data: WB7 – WB0
8-bits
LSDO
Read – Preceding frame was a read
MSB = 0
1-bit
Register Address
7-bits
0000,0000 Fill Data
8-bits
LSDI
Input data: IN8 – IN1
8-bits
Register Data: D7 – D0
8-bits
LSDO
Notes:
LSDI: CRC generated by external device such as MCU, Data D7–D0 clocked out from MCU
LSDO: CRC generated by MAX22192, Data D7–D0 clocked out from MAX22192 Register
NO-OP: No Operation, i.e., write cycle with no valid data to specified address
Write Cycle: DI[7:0] and WB[7:0] are from internal latches, whose outputs are frozen when LCS or LLATCH goes low. Bits 24VL,
24VM and WBG are frozen by LCS going low but not by LLATCH.
Read Cycle: D7–D0 are the register data addressed through LSDI. Bits 24VL, 24VM, and WBG reflect the corresponding bits in the
FAULT1 register.
Input Channel: Pins are numbered IN1–IN8, so input IN1 maps to bit DI0, input IN2 to bit DI1 ... and input IN8 to bit DI7
Maxim Integrated
│ 35
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Maxim Integrated
│ 36
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Register Detailed Description
WB (Clear-On-Read)
Address = 0x00
Default = 0x00
BIT
NAME
DESCRIPTION
0: WBx = 0, No wire-break condition detected for channel x
1: WBx = 1, Wire-break condition detected for channel x
7:0
WB[7:0]
Wire-break status for each channel. The bit remains high even if the wire-break condition disappears and is
only cleared upon reading the register. Not cleared if the wire-break condition is still present upon reading the
register
Note: Input Channels are numbered IN1–IN8, so IN1 maps to WB0, IN2 to WB1 ... and IN8 to WB7.
DI (Read)
Address = 0x02
Default = 0x00
BIT
NAME
DESCRIPTION
0: DIx = 0, Channel x is driven low
1: DIx = 1, Channel x is driven high
7:0
DI[7:0]
Digital input state, DI_ is the state of the corresponding input pin.
Note: Input Channels are numbered IN1–IN8, so IN1 maps to DI0, IN2 to DI1 ... and IN8 to DI7.
FAULT1 (Mixed)
Address = 0x04
Default = 0x46
BIT
NAME
DESCRIPTION
0: The last received SPI frame was not corrupted
1: The last received SPI frame was corrupted
It is not cleared upon read, but when an uncorrupted SPI frame is received.
CRC is only active in SPI Interface Modes 0 and 2
7
CRC
0: Normal operating conditions
1: POR event has reset the register map to its power-on-reset state
This bit is cleared only if the user writes “0” to it. The other bits in this register are unaffected by the write
6
POR
access.
0: An enabled bit in the FAULT2 register is not set
5
4
3
FAULT2
1: An enabled bit in the FAULT2 register is set
This bit is cleared on read only if the FAULT2 register is cleared or the bit is disabled.
0: Temperature Alarm 2 threshold has not been exceeded
ALRMT2* 1: Temperature Alarm 2 threshold has been exceeded
Cleared upon reading this register.
0: Temperature Alarm 1 threshold has not been exceeded
ALRMT1* 1: Temperature Alarm 1 threshold has been exceeded
Cleared upon reading this register.
0: 24V supply is normal (above the 24VL threshold)
1: 24V supply is low (below the 24VL threshold)
Cleared upon reading this register. If bit 4 in the CFG Register (24VF) is 0, 24VL can also be cleared after
2
24VL*
any SPI transaction while operating in mode 0 or 2.
Maxim Integrated
│ 37
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
BIT
NAME
DESCRIPTION
0: 24V supply is normal (above the 24VM threshold)
1: 24V supply is missing (below the 24VM threshold)
Cleared upon reading this register. If bit 4 in the CFG Register (24VF) is 0, 24VM can also be cleared after
any SPI transaction while operating in mode 0 or 2.
1
24VM*
WBG
0: No bit in the WB register is set
1: One or more bits in the WB register are set
Cleared upon reading the WB register.
0
*These flags are “latched” and they remain set until read even if the fault goes away, and are not cleared if the fault condition is still
present when the register is read.
FLT1 to FLT8 (Read/Write)
Address = 0x06 – 0x14 (increments of 2)
Default = 0x08
BIT
NAME
DESCRIPTION
7:5
0
Reserved
0: Wire-Break detection is disabled for channel x
1: Wire-Break detection is enabled for channel x
4
3
WBE
FBP
If WBE = 0, the corresponding WBx bit is always low and the WB detection circuits for channel x are off.
The REFWB resistor on pin REFWB can be removed if the WBE bits of all the channels are low.
The RFWBO bit in the FAULT2 register is set if WBE bits of all channels are low.
0: Programmable filter on INx is used
1: Programmable filter on INx is bypassed
Programmable filter values for INx (the wire-break filter value is 20ms and is not programmable).
DELAY[2:0] = 000 = 50µs
DELAY[2:0] = 001 = 100µs
DELAY[2:0] = 010 = 400µs
2:0
DELAY[2:0] DELAY[2:0] = 011 = 800µs
DELAY[2:0] = 100 = 1.6ms
DELAY[2:0] = 101 = 3.2ms
DELAY[2:0] = 110 = 12.8ms
DELAY[2:0] = 111 = 20ms
CFG (Read/Write)
Address = 0x18
Default = 0x00
BIT
NAME
DESCRIPTION
7:5
0
Reserved
0: Flags 24VL and 24VM are cleared after any full frame SPI transaction or by reading the FAULT1 register
1: 24VL and 24VM are cleared only by reading the FAULT1 register
Only affects SPI Interface Modes 0 and 2
4
3
24VF
0: Filters (input filters and wire-break filters) operate normally
1: All the filters (input filters and wire-break filters) are fixed at the mid-scale value for the chosen delay
The filters resume normal operation when CLRF is cleared.
CLRF
0
2:1
0
Reserved
REFDI_
SH_ENA
0: Disables the detection of a short-circuit condition on the REFDI pin
1: Enables the detection of a short-circuit condition on the REFDI pin
Maxim Integrated
│ 38
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
INEN (Read/Write)
Address = 0x1A
Default = 0xFF
BIT
NAME
DESCRIPTION
0: CHx = 0, INx is disabled, the current source is set to 0mA, and the DIx bit in the DI register is set to 0
1: CHx = 1, INx is enabled
7:0
CH[7:0]
Note: Input Channels are numbered IN1–IN8, so IN1 maps to CH0, IN2 to CH1 ... and IN8 to CH7.
FAULT2 (Clear-On-Read)
Address = 0x1C
Default = 0x02
BIT
NAME
DESCRIPTION
7:6
0
Reserved
0: SPI receives a number of clock pulses equal to a multiple of eight, valid transaction
1: SPI receives a number of clock pulses not equal to a multiple of eight, the SPI command is rejected
5
4
FAULT8CK
OTSHDN
0: Normal operating conditions
1: Overtemperature Shutdown (the safe operating temperature has been exceeded)
Overtemperature Shutdown: all inputs and LED drivers are turned off to reduce power dissipation and
protect the device. The SPI interface and internal regulator remain active and if the temperature continues
to rise, the regulator is turned off.
0: Normal operating conditions
1: Open condition is detected on the REFDI pin
3
2
RFDIO
RFDIS
This bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
This bit is 1 when thermal shutdown happens because REFDI function turns off in thermal shutdown.
No action on the intput channels when this condition occurs.
0: Normal operating conditions
1: Short condition is detected on the REFDI pin
The bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
All the input channels are disabled as long as the short condition on REFDI is present.
0: Normal operating conditions
1: Open condition is detected on the REFWB pin
This bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
This bit is 1 when thermal shutdown happens because REFWB function turns off in thermal shutdown.
This bit is 1 after power-on-reset when all input channel’s wire-break detection functions are off.
No action on the input channels when this condition occurs and one or more channels’ wire-break function
is enabled.
1
0
RFWBO
RFWBS
0: Normal operating conditions
1: Short condition is detected on the REFWB pin
This bit remains 1 even if the fault condition disappears and is cleared upon reading this register.
No action on the input channels when this condition occurs and one or more channels’ wire-break function
is enabled.
Maxim Integrated
│ 39
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
FAULT2EN (Read/Write)
Address = 0x1E
Default = 0x00
BIT
NAME
DESCRIPTION
7:6
0
Reserved
0: Disable bit FAULT2 in the FAULT1 register
1: Enable bit FAULT2 in the FAULT1 register to be set when FAULT8CK is high
5
4
3
2
1
0
FAULT8CKE
OTSHDNE
RFDIOE
0: Disable bit FAULT2 in the FAULT1 register
1: Enable bit FAULT2 in the FAULT1 register to be set when OTSHDN is high
0: Disable bit FAULT2 in the FAULT1 register
1: Enable bit FAULT2 in the FAULT1 register to be set when RFDIO is high
0: Disable bit FAULT2 in the FAULT1 register
1: Enable bit FAULT2 in the FAULT1 register to be set when RFDIS is high
RFDISE
0: Disable bit FAULT2 in the FAULT1 register
1: Enable bit FAULT2 in the FAULT1 register to be set when RFWBO is high
RFWBOE
RFWBSE
0: Disable bit FAULT2 in the FAULT1 register
1: Enable bit FAULT2 in the FAULT1 register to be set when RFWBS is high
LED (Read/Write)
Address = 0x20
Default = 0x00
BIT
NAME
DESCRIPTION
0: The LED located at row 2, column 1 of the LED matrix is off
1: The LED lcoated at row 2, column 1 of the LED matrix is on
7
R2C1
Note: the LEDs of the matrix are scanned with a duty cycle of 33%. The LED located at row 2, column 2 is
reserved to show the status of the V
voltage missing threshold (24VM).
voltage monitoring. It is on when V
voltage is above the
DD24F
DD24F
0: The LED located at row 2, column 0 of the LED matrix is off
1: The LED lcoated at row 2, column 0 of the LED matrix is on
6
5
4
3
2
1
0
R2C0
R1C2
R1C1
R1C0
R0C2
R0C1
R0C0
0: The LED located at row 1, column 2 of the LED matrix is off
1: The LED lcoated at row 1, column 2 of the LED matrix is on
0: The LED located at row 1, column 1 of the LED matrix is off
1: The LED lcoated at row 1, column 1 of the LED matrix is on
0: The LED located at row 1, column 0 of the LED matrix is off
1: The LED lcoated at row 1, column 0 of the LED matrix is on
0: The LED located at row 0, column 2 of the LED matrix is off
1: The LED lcoated at row 0, column 2 of the LED matrix is on
0: The LED located at row 0, column 1 of the LED matrix is off
1: The LED lcoated at row 0, column 1 of the LED matrix is on
0: The LED located at row 0, column 0 of the LED matrix is off
1: The LED lcoated at row 0, column 0 of the LED matrix is on
Maxim Integrated
│ 40
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
GPO (Read/Write)
Address = 0x22
Default = 0x00
BIT
NAME
DESCRIPTION
0: FFAULT pin is not sticky. FFAULT condition is determined by the logical OR of the unmasked real-time
FAULT1 register sources, and not the FAULT1 register bits.
1: FFAULT pin is sticky. If at least one bit in the FAULT1 register is set and unmasked, FFAULT remains low
until FAULT1 register is read (Figure 8).
7
STK
0: LEDR_ and LEDC_ pins are configured as LED drivers, and are controlled by the LED register
1: LEDR_ and LEDC_ pins are configures as GPO drivers, and are controlled by GPO register bits [5:0]
6
5
4
3
2
1
0
DIR
R2
R1
R0
C2
C1
C0
0: Set LEDR2 pin low
1: Set LEDR2 pin high
0: Set LEDR1 pin low
1: Set LEDR1 pin high
0: Set LEDR0 pin low
1: Set LEDR0 pin high
0: Set LEDC2 pin low
1: Set LEDC2 pin high
0: Set LEDC1 pin low
1: Set LEDC1 pin high
0: Set LEDC0 pin low
1: Set LEDC0 pin high
FAULT1EN (Read/Write)
Address = 0x24
Default = 0xC0
BIT
NAME
DESCRIPTION
0: FFAULT pin is not asserted when CRC is 1
1: FFAULT pin is asserted when CRC is 1
7
CRCE
0: FFAULT pin is not asserted when POR is 1
1: FFAULT pin is asserted when POR is 1
6
5
4
3
2
1
0
PORE
FAULT2E
ALRMT2E
ALRMT1E
24VLE
0: FFAULT pin is not asserted when FAULT2 is 1
1: FFAULT pin is asserted when FAULT2 is 1
0: FFAULT pin is not asserted when ALRMT2 is 1
1: FFAULT pin is asserted when ALRMT2 is 1
0: FFAULT pin is not asserted when ALRMT1 is 1
1: FFAULT pin is asserted when ALRMT1 is 1
0: FFAULT pin is not asserted when 24VL is 1
1: FFAULT pin is asserted when 24VL is 1
0: FFAULT pin is not asserted when 24VM is 1
1: FFAULT pin is asserted when 24VM is 1
24VME
0: FFAULT pin is not asserted when WBG is 1
1: FFAULT pin is asserted when WBG is 1
WBGE
Maxim Integrated
│ 41
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
NOP (N/A)
Address = 0x26
Default = N/A
BIT
NAME
NOP[7:0]
DESCRIPTION
Dummy register. DI[7:0] and WB[7:0] are clocked out normally during attempted SPI writes to this register.
Useful for daisy-chain modes.
7:0
● Maximize the metal coverage for all layers, especially for
Applications Information
top and bottom layer to optimize the heat dissipation.
Power Supply Sequencing
The MAX22192 does not require special power supply
sequencing. The field-side SPI interface logic level (V
is set independently from the field supply (V
● Use 2oz. copper for top and bottom layer if possible
so that more heat can be drawn to the PCB.
)
LF
● Maximize the number of vias under the package for
thermal purposes. If possible, fill the via with cop-
per, which further enhances the vertical heat transfer
through the PCB.
) or
DD24F
LDO output (V
) levels. The logic levels of field-side
DD3F
and logic-side SPI are also set independently by V and
LF
V
. Each supply can be present over the entire speci-
DDL
fied range regardless of the level or presence of the other
supply.
IEC 61131-2 EMC Requirement
The MAX22192 is required to operate reliably in harsh
industrial environments. The device can meet the tran-
sient immunity requirements as specified in IEC 61131-2,
including Electrostatic Discharge (ESD) per IEC 61000-
4-2, Electrical Fast Transient/Burst (EFT) per IEC 61000-
4-4, and Surge Immunity per IEC 61000-4-5. Maxim’s
proprietary process technology provides robust input
channels and field supply with internal ESD structures
and high absolute maximum ratings (see the Absolute
Maximum Ratings section), but external components are
also required to absorb excessive energy from ESD and
surge transients. The circuit with external components
shown in Figure 15 allows the device to meet and exceed
the transient immunity requirements as specified in IEC
61131-2 and related IEC 61000-4-x standards. The sys-
tem shown in Figure 15, using the components shown in
Table 7, is designed to be robust against ESD, EFT, and
Surge specifications as listed in Table 8. In all these tests,
the part or DUT is soldered onto a properly designed
application board (e.g., MAX22192EVKIT#) with neces-
sary external components. Refer to Application Note 7132
for details.
Power Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass V
, V
, and V with a low-ESR
DD24F DD3F LF
and low-ESL 0.1µF ceramic capacitor in parallel with a
1µF ceramic capacitor to GNDF, respectively. Bypass
V
with a low-ESR and low-ESL 0.1µF ceramic capaci-
DDL
tor in parallel with a 1µF ceramic capacitor to GNDL.
Place the bypass capacitors as close as possible to each
power supply input pins.
PCB Layout Recommendations
The PCB designer should follow some critical recom-
mendations in order to get the best performance from the
design.
● Keep the input/output traces as short as possible. To
keep signal paths low-inductance, avoid using vias.
● Keep the area underneath the MAX22192 isolation
barrier free from ground and signal planes. Any gal-
vanic or metallic connection between the field-side
and logic-side defeats the isolation.
Maxim Integrated
│ 42
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
24V
3.3V
1.8V
D1
C1
C2
C4
C3
C4
C3
M1
M0
V
DDL
V
V
V
LF
DD24F
DD3F
7.5kΩ
24kΩ
REFDI
REFWB
EXTVM
V
DD
AFS
GPI
R1
R1
IN1
FIELD INPUT
FIELD INPUT
LCS
CS
LED1
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
MAX22192
MICRO
CONTROLLER
IN2
LSDO
LED2
LLATCH
1.8V
INPUT AT PIN
R1
4.7kΩ
IN8
FIELD INPUT
SDOEN
LFAULT
LED8
GPI or INT
470Ω
470Ω
470Ω
LEDC2
LEDC1
LEDC0
GND
24VM
LEDR2
LEDR1
LEDR0
FCS FSCLK FSDO FSDI OSDI FFAULT IFAULT OREADY IREADY FLATCH GNDF GNDL
C6
C5
4.7kΩ
4.7kΩ
3.3V
PE
Figure 15. Typical EMC Protection Circuitry for the MAX22192
Table 7. Recommended Components
COMPONENT
DESCRIPTION
REQUIRED/RECOMMENDED
Required
C1
1μF, 100V ceramic capacitor
C2
0.1μF, 100V ceramic capacitor
1μF, 10V ceramic capacitor
0.1μF, 10V ceramic capacitor
Required
C3
Required
C4
Required
C5
1000pF safety rated Y capacitor (2220 or similar)
3300pF safety rated Y capacitor (2220 or similar)
Recommended
Required
C6
D1
R1
Unidirectional TVS diode (SMBJ33A (42Ω) or SM30T39AY (2Ω))
Required
1.5kΩ or 1kΩ, 1W pulse withstanding resistor (CMB0207 or similar)
0603, 0.1W resistors
Required
All other Resistors
All LEDs
Required
LEDs for visual input status indication
Recommended
Maxim Integrated
│ 43
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
The input resistor value shifts the field voltage switching
threshold scaled by the input current; thus, determines
the input characteristics of the application. The package
of the resistor should be large enough to prevent the arc-
ing across the two resistor pads. Arcing depends on the
ESD level applied to the field input and the application’s
pollution degree.
ESD Protection of Field Inputs
The input resistor limits the energy into the MAX22192
IN_ pin and protects the internal ESD structure from
excessive transient energy. An input series resistor is
required and should be rated to withstand such ESD
levels. The MAX22192 input channels can withstand up
to ±8kV ESD contact discharge and ±15kV ESD air-gap
discharge with an input series resistor of 1kΩ or larger.
Table 8. Transient Immunity Test Results
TEST
RESULT
±8kV
Contact ESD
IEC 61000-4-2 Electrostatic Discharge (ESD)
Air-Gap ESD
Input Line
±15kV
±4kV
IEC 61000-4-4 Electrical Fast Transient/Burst (EFT)
Line-to-Ground
Line-to-Line
±1kV
±2kV
IEC 61000-4-5 Surge Immunity (1.2/50µs, 42Ω)
Power Supply
±500V
R
C
R
I
D
50MΩ TO 100MΩ
330Ω
100%
90%
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
SOURCE
10%
t = 0.7ns TO 1ns
r
t
30ns
60ns
Figure 16a. ESD Generator Equivalent Circuit
Figure 16b. ESD Contact Discharge Test Waveform
Maxim Integrated
│ 44
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
EFT Protection of Field Inputs
The input channels can withstand up to ±4kV, 5kHz or 100kHz fast transients (Figure 17) with performance criterion A,
normal operation within specification limits. A capacitive coupling clamp is used to couple the fast transients (burst) from
the EFT generator to the field inputs of the MAX22192 without any galvanic connection to the MAX22192 input pins.
V
EFT PULSE
EFT VOLTAGE
t
200µs AT 5kHz
10µs AT 100kHz
REPETITION FREQUENCY
V
EFT/BURST
EFT VOLTAGE
...
...
t
15ms AT 5kHz
0.75ms AT 100kHz
BURST
DURATION
BURST PERIOD 300ms
Figure 17. Electrical Fast Transient/Burst Waveform
Maxim Integrated
│ 45
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
The second option, which can result in a smaller overall
footprint, is to use a bidirectional TVS to GND at the field
input with a low-power series resistor, greater or equal to
1kΩ. The TVS must be able to absorb the surge energy
and has the function of limiting the peak voltage so that
the resistor only sees a low differential voltage. Suitable
TVS with a small footprint are SPT02-236 or PDFN3-32,
offering protection against 1kV/42Ω surge.
Surge Protection of Field Inputs
In order to protect the IN_ pins against 1kV/42Ω, 1.2/50µs
surges (Figure 18 and Figure 19), two options exist. The
first option is to use a series pulse withstanding resistor
as shown in the various application diagrams in the data
sheet. A pulse resistor greater or equal to 1kΩ should be
used for safe operation. The pulse resistor should sup-
port dissipation of the surge energy. Examples of suitable
resistors are CMB0207 MELF or CRCW-IF thick film as
well as others. The resistor value is defined by the Type 1,
2, 3, or other input characteristics. Capacitors for filtering
should not be connected to the IN_ pins.
Surge Protection of 24V Supply
In order to protect the V
pin against 500V/42Ω,
DD24F
1.2/50µs surges (Figure 18), a SMBJ33A TVS can be
applied to the V pin.
DD24F
V
100%
90%
50%
t
2
0
t
30% MAX
t
1
FRONT TIME: t = 1.2µs ±30%
1
TIME TO HALF VALUE: t = 50µs ±20%
2
Figure 18. 1.2/50µs Surge Voltage Waveform
COUPLING/DECOUPLING NETWORK
0.5μF
40Ω
1kΩ
1kΩ
2Ω
IN1
MAX22192
IN2
GENERATOR
A
B
GND
A = LINE-TO-LINE
B = LINE-TO-GND
Figure 19. Surge Testing Methods
Maxim Integrated
│ 46
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Typical Operating Circuits
24V
3.3V
3.3V
1.8V
1µF
0.1µF
0.1µF
1µF
0.1µF
1µF
M1
M0
V
DDL
V
V
V
LF
DD24F
DD3F
7.5kΩ
24kΩ
REFDI
REFWB
EXTVM
V
DD
AFS
GPI
1.5kΩ
1.5kΩ
IN1
FIELD INPUT
FIELD INPUT
LCS
CS
LED1
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
MAX22192
MICRO
CONTROLLER
IN2
LSDO
LED2
LLATCH
1.8V
1.5kΩ
4.7kΩ
IN8
FIELD INPUT
SDOEN
LFAULT
LED8
GPI or INT
470Ω
470Ω
470Ω
LEDC2
LEDC1
LEDC0
GND
24VM
LEDR2
LEDR1
LEDR0
3.3V
FCS FSCLK FSDO FSDI OSDI FFAULT IFAULT OREADY IREADY FLATCH GNDF GNDL
4.7kΩ
4.7kΩ
CS SCLK
SDO SDI FAULT
READY
LATCH
3.3V
V
DD
POWERED BY MAX22192 V
DD3F
1µF
0.1µF
V
L
V
DD24
1.5kΩ
IN1
FIELD INPUT
MAX22190
LED1
1.5kΩ
FIELD INPUT
IN2
LED2
1.5kΩ
IN8
FIELD INPUT
LED8
REFDI
REFWB
M1
M0
GNDF
7.5kΩ
24kΩ
3.3V
16-CHANNEL, TYPE 1/3, ISOLATED, DIGITAL INPUTS WITH DAISY CHAIN SPI
Maxim Integrated
│ 47
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Typical Operating Circuits (continued)
24V
3.3V
1.8V
1µF
0.1µF
0.1µF
1µF
0.1µF
1µF
M1
M0
V
DDL
V
V
V
LF
DD24F
DD3F
7.5kΩ
REFDI
REFWB
EXTVM
24kΩ
V
DD
AFS
GPI
1.5kΩ
1.5kΩ
IN1
FIELD INPUT
FIELD INPUT
LCS
CS1
LED1
LSCLK
LSDI
SCLK
MOSI
MISO
GPO
MAX22192
MICRO
CONTROLLER
IN2
LSDO
LED2
LLATCH
1.8V
4.7kΩ
1.5kΩ
IN8
FIELD INPUT
LFAULT
SDOEN
GPI or INT
LED8
CS2
470Ω
470Ω
470Ω
LEDC2
LEDC1
LEDC0
GND
24VM
LEDR2
LEDR1
LEDR0
FCS FSCLK FSDO FSDI OSDI FLATCH FFAULT IFAULT OREADY IREADY GNDF GNDL
3.3V
3.3V
SCLK
SDO SDI
LATCH
4.7kΩ
3.3V
V
DD
4.7kΩ
FAULT
POWERED BY MAX22192 V
DD3F
1µF
0.1µF
V
L
READY
3.3V
1.8V
V
DD24
1µF
0.1µF
0.1µF
1µF
1.5kΩ
1.5kΩ
IN1
FIELD INPUT
MAX22190
LED1
V
V
DDA
DDB
CS
OUT1
IN1
FIELD INPUT
IN2
MAX12930
LED2
OUT2
IN2
GNDB
GNDA
1.5kΩ
IN8
FIELD INPUT
LED8
REFDI REFWB
M1
M
GNDF
7.5kΩ
24kΩ
16-CHANNEL, TYPE 1/3, ISOLATED, DIGITAL INPUTS WITH INDEPENDENT SLAVE SPI
Maxim Integrated
│ 48
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Ordering Information
Chip Information
PROCESS: BiCMOS
PART
TEMP RANGE
PIN-PACKAGE
MAX22192ARC+
-40°C to +125°C
70-GQFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
Maxim Integrated
│ 49
www.maximintegrated.com
MAX22192
Octal Industrial Digital Input with
Diagnostics and Digital Isolation
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
10/18
Initial release
—
Updated the Isolated Octal Digital Input figure, Figures 6, 10 and 15, Isolation
Channels and CRC Generation sections, Table 7, and Typical Operating Circuits
2, 23, 27–28
30, 43, 49–50
1
2
11/18
3/19
Updated the Safety Regulatory section and added the Safety Regulatory Approvals
table
1, 10
Updated Dynamic Electrical Characteristics, Safety Regulatory Approvals, Pin De-
scription and Input Filters sections, and Table 7; replaced the Isolated Octal Digital
Input diagram, Figure 6, Figure 15, Figures 17–19, both Typical Application Circuits,
Table 8, and the EMC Standard Compliance section; remove Table 9
2, 8, 10, 19,
21, 23, 42–50
3
9/20
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2020 Maxim Integrated Products, Inc.
│ 50
相关型号：
©2020 ICPDF网 联系我们和版权申明