MAX22532_技术文档

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MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

General Description

Benefits and Features

The MAX22530–MAX22532 are galvanically isolated, 4-

channel, multiplexed, 12-bit, analog-to-digital converters

(ADC) in the MAXSafe™ family product line. An

integrated, isolated, DC-DC converter powers all field-

side circuitry, and this allows field-side diagnostics even

when no input signal is present.

•

Enable

Analog/Binary Inputs

• Withstands 3.5kV

Robust

Detection

of

Multichannel

Isolation for 60s (V

) for

ISO

RMS

the SSOP Package

• Withstands 5kV

Isolation for 60s (V

) for

ISO

RMS

the Wide SOIC Package

• 5.5mm of Creepage and Clearance for 20-pin or

28-pin SSOP Package

• 8mm of Creepage and Clearance for 16-pin Wide

SOIC Package

The MAX22530–MAX22532 family continually digitizes

the input voltage on the field-side of an isolation barrier

and transmits the data across the isolation barrier to the

logic-side of the devices where the magnitude of the

input voltage is compared to programmable thresholds.

The 12-bit ADC core has a sample rate of 20ksps (typ)

per-channel. ADC data is available through the SPI

interface either directly or filtered. Filtering averages the

most recent 4 readings depending on the setting.

• Group II CTI Package Material

•

Reduces BOM and Board Space Through High

Integration

• Field-Side Self-Powered with Integrated DC-DC

Supply

• 12-bit, 20ksps Per-Channel ADC

• Programmable Threshold Comparators for each

Channel

• Isolation for both Data and DC-DC Supply

• Integrated 1.8V Reference

Each input has a comparator with programmable high

and low thresholds, and an interrupt is asserted when

any input crosses its programmed level based on the

mode setting. The comparator output pin (COUT_) is

high when the input voltage is above the upper threshold

and low when it is below the lower threshold in digital

input mode. Response time of the comparator to an input

change is less than 75ms (typ) with filtering disabled.

With filtering enabled, the comparator uses the moving

average of the last 4 ADC readings.

•

Increase System “Up Time” and Simplifies System

Design & Maintenance

• Field-Side ADC Functionality Diagnostics

• Field-Side Continuous Power Monitoring

• Communication System Self-Diagnostics

The MAX22530 in a 16-pin wide SOIC package provides

Flexible Control and Interface

• Programmable Upper and Lower Input Threshold

Enable Programmable Hysteresis

• Comparator Output (COUT_) Pins for Fastest

Response

8mm of creepage and clearance, and 5kV

isolation.

RMS

The MAX22531 in a 20-pin SSOP package and the

MAX22532 in a 28-pin SSOP package, both provide

5.5mm of creepage and clearance, and 3.5kV

RMS

• SPI Interface with CRC Option

isolation. All package material has

a minimum

• Precision Internal Reference ±1% (typ)

• -40°C to +125°C Operating Temperature Range

comparative tracking index (CTI) of 400, which gives it a

group II rating in creepage tables.

All devices are rated for operation at ambient

temperatures between -40°C to +125°C.

Safety Regulatory Approvals (Pending)

•

UL According to UL1577

cUL According to CSA Bulletin 5A

Applications

•

High-Voltage Binary Input

Substation Automation

Distribution Automation

Process Automation

Motion Control

Ordering Information appears at the end of the data

sheet.

19-100989; Rev 0; 3/21

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Four-Channel Isolated ADC

NOTE *:

COUT1 AND COUT2 ARE FOR MAX22531

COUT1, COUT2, COUT3, AND COUT4 ARE FOR MAX22532

REF

V

= 3.3V

DDL

MAX22530/MAX22531/MAX22532

INPUT

REFERENCE

V

= 1.8V

REF

COUT_*

AIN1

AIN2

AIN3

AIN4

INT

CS

12-BIT ADC

MCU

LOGIC AND SPI

INTERFACE

SCLK

SDI

AGND

LOGIC

CONTROL

SDO

V

= 3.3V

DDPL

µPOWER ISOLATED

DC-DC

V

DDF

C

DDF

GNDF

GNDL

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Maxim Integrated | 2

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Absolute Maximum Ratings

V

to GNDL........................................................-0.3V to 6V

Continuous Power Dissipation (Multilayer Board) (T

=

DDL

A

+70°C, derate 11.9mW/°C above +70°C. 20-pin SSOP)

.....................................................................................964mW

V

to GNDL......................................................-0.3V to 6V

DDPL

SDI,

,

(To GNDL) ........................................-0.3V to 6V

+ 0.3V)

Continuous Power Dissipation (Multilayer Board) (T

+70°C, derate 6.96mW/°C above +70°C. 28-pin SSOP)

................................................................................556.72mW

=

A

SDO, COUT_ (To GNDL).....................-0.3V to (V

DDL

V

to GNDF .......................................................-0.3V to 6V

DDF

Operating Temperature Range ...................... -40°C to +125°C

Maximum Junction Temperature.................................. +150°C

Storage Temperature Range ......................... -65°C to +150°C

Lead Temperature (soldering, 10s).............................. +300°C

Soldering Temperature (reflow).................................... +260°C

REF, AIN_ to AGND...............................................-0.3V to 2V

AGND to GNDF...................................................-0.3V to 0.3V

Continuous Power Dissipation (Multilayer Board) (T

=

A

+70°C, derate 14.1mW/°C above +70°C. 16-pin Wide SOIC)

.................................................................................. 1127mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or

any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

16 W SOIC

Package Code

W16MS+14

21-0042

Outline Number

Land Pattern Number

90-0107

THERMAL RESISTANCE, FOUR-LAYER BOARD

Junction-to-Ambient (θ

)

68.8°C/W

41.6°C/W

JA

Junction-to-Case Thermal Resistance (θ

)

JC

20 SSOP

Package Code

A20MS+7

21-0056

90-0094

Outline Number

Land Pattern Number

THERMAL RESISTANCE, FOUR-LAYER BOARD

Junction-to-Ambient (θ

)

216°C/W

49°C/W

JA

Junction-to-Case Thermal Resistance (θ

)

JC

28 SSOP

Package Code

A28MS+5

21-0056

90-0095

Outline Number

Land Pattern Number

THERMAL RESISTANCE, FOUR-LAYER BOARD

Junction-to-Ambient (θ

)

143.70°C/W

47.90°C/W

JA

Junction-to-Case Thermal Resistance (θ

)

JC

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the

www.maximintegrated.com

Maxim Integrated | 3

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics

(V

- V

= 1.71V to 5.5V, V

- V

GNDL

= 3.0V to 5.5V, C

= 1μF, C

= 1μF. Limits are 100% tested at T

+25°C.

A =

DDL

GNDL

DDPL

DDF

REF

Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) (Note

1, Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LOGIC-SIDE POWER SUPPLY

Logic Power Supply

Logic Supply Current

V

1.71

5.5

2.5

V

DDL

I

1

mA

DDL

Logic-Supply UVLO

Threshold

Logic-Supply UVLO

Hysteresis

V

1.5

1.6

1.66

V

DDL_UVLO

50

mV

DDL_UHYS

Logic Power-Up Time

Isolated DC-DC Supply

t

Valid SPI access

0.6

3.3

1

ms

V

LPU

V

3.0

2.7

5.5

DDPL

Isolated DC-DC Supply

Current

Isolated DC-DC Supply

UVLO Threshold

Isolated DC-DC Supply

UVLO Hysteresis

I

V

= 3.3V

7

10

mA

V

DDPL

V

2.8

100

2.95

DDPL_UVLO

mV

DDPL_UHYS

FIELD-SIDE PARAMETERS

Supply Voltage

V

Internally generated

= 1 µF

2.7

3.1

5.5

10

V

DDF

Isolated DC-DC Power

Up Time

t

C

ms

PWRUP

DDF

ADC AND COMPARATOR

Input-Voltage Range

ADC Resolution

V

0

1.8

V

AIN

12

Bits

V

= 98% V , excluding offset error

REF

AIN

Gain Error

GE

-0.2

-0.1

+0.2

%FS

and reference error

Offset Error

OE

DNL

INL

V

= 2% V , offset calculated

+0.1

±1.5

±2.0

+600

22

%FS

LSB

nA

AIN

REF

Differential Nonlinearity

Integral Nonlinearity

Input-Leakage Current

Throughput per Channel

Included in the gain and offset window

IN

LKG

-600

18

20

75

ksps

AIN# step input to COUT transition (Note

3)

Latency (No filtering)

µs

AIN# step input to COUT transition (Note

3)

Latency (4 Readings)

CMTI

300

50

µs

(Note 4)

kV/µs

INTERNAL VOLTAGE REFERENCE

Nominal Output Voltage

V

T

= +25°C

1.78

-1.5

1.80

1.82

+1.5

V

REF

A

V

= -25°C to +85°C

%

REF_TOL

A

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Maxim Integrated | 4

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

(V

DDL

- V

GNDL

= 1.71V to 5.5V, V

- V

GNDL

= 3.0V to 5.5V, C

= 1μF, C

= 1μF. Limits are 100% tested at T

+25°C.

A =

DDPL

DDF

REF

Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) (Note

1, Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output-Voltage

Accuracy

T

= -40°C to +125°C

-2

+2

A

Output-Voltage

Temperature Drift

T

50

ppm/°C

CVOUT

LOGIC INTERFACE (SCLK, SDI, SDO,

, COUT,

)

Input Logic-High

Voltage

0.7 x

V

SCLK, SDI,

V

IH

V

DDL

0.3 x

Input Logic-Low Voltage

V

SCLK, SDI,

IL

V

DDL

Input Hysteresis

V

SCLK, SDI,

50

2

mV

µA

HYST

Input Leakage Current

I

IN_LKG

-1

+1

SCLK, SDI,

f = 1MHz

,

Input Capacitance

C

pF

V

IN

Output Logic-High

Voltage

V

-

DDL

0.4

V

SDO, COUT, sourcing 4mA

OH

Output Logic-Low

Voltage

Output High-Impedance

Leakage Current

V

SDO, COUT,

, SDO

, sinking 4mA

0.4

+1

V

OL

I

-1

µA

OLKG

SPI TIMING CHARACTERISTICS

SCLK Clock Frequency

SCLK Clock Period

f

t

10

MHz

ns

SCLK

100

40

SCLK Pulse-Width High

SCLK Pulse-Width Low

t

ns

SCLKH

t

40

ns

SCLKL

Fall-to-SCLK Rise

Time

t

20

80

ns

CS(LEAD)

SCLK Fall-to-

Time

Rise

t

CS(LAQ)

SDI Hold Time

SDI Setup Time

t

20

ns

DINH

t

DINSU

SDO Disable Time (

Rising to SDO Three-

State)

t

40

ns

DOUT(DIS)

Output Data

Propagation Delay

t

50

ns

DO

Inter-Access Gap

t

920

IAG

Note 1: All devices are 100% production tested at T = +25C. Specifications for all temperature limits are guaranteed by design.

A

Note 2: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to their

respective ground (GNDL or GNDF), unless otherwise noted.

Note 3: Latency numbers are based on the following condition: a full-scale step is applied at the ADC input and COUTHI_ (register

address 0x9 to 0xC) upper threshold (THU) is set to maximum value (0xFFFh). Latency is the delay from the step at the

ADC input to the digital comparator output.

Note 4: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to

both rising and falling common-mode voltage edges. Tested with the transient generator connected between GNDF and

GNDL (V

= 1000V).

CM

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Maxim Integrated | 5

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Timing Diagram

t

CSW

1

CSS

CSH0 CSS0

DS

DH

CL

CH

CP

CS

SCLK

SDI

1

2

3

4

5

6

7

8

9

10

30

31

32

W

B

A

5

A

4

A

3

A

2

A

1

A

0

A

0

D

15

C

2

C

1

C

0

NOTE B: BURST BIT

HIGH-Z

SDO

Figure 1. SPI Write Timing Diagram (with CRC Enabled)

t

CL

t

CSW

CSH0 CSS0

DS

DH

CH

CP

CSS1

CS

SCLK

SDI

1

2

3

4

5

6

7

8

9

10

N+6

N+7

N+8

R

B

A

5

A

1

A

4

3

2

0

NOTE B: BURST BIT

t

DOD

DOH

t

DOT

HIGH-Z

D

15

D

14

C

2

C

1

C

0

SDO

Figure 2. SPI Read Timing Diagram (with CRC Enabled)

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Maxim Integrated | 6

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Insulation Characteristics

16-pin Wide SOIC

PARAMETER

SYMBOL

CONDITIONS

Method B1 = V x 1.875

(t = 1s, partial discharge < 5pC)

VALUE

UNITS

IORM

Partial Discharge Test Voltage

V

2250

V

PR

P

Maximum Repetitive-Peak-

Isolation Voltage

Maximum Working-Isolation

Voltage

Maximum Transient-Isolation

Voltage

(Note 5)

1200

848

IORM

IOWM

IOTM

P

Continuous RMS voltage (Note 5)

(Note 5)

RMS

P

7000

f

= 60Hz, duration = 60s

SW

Maximum Withstanding-

Isolation Voltage

V

5000

V

ISO

RMS

P

(Note 5, Note 6)

Maximum Surge-Isolation

Voltage

Basic Insulation, 1.2/50μs pulse per

IEC61000-4-5

V

10000

V

IOSM

12

V

= 500V, T = 25°C

> 10

IO

A

11

Insulation Resistance

R

C

= 500V, 100°C ≤ T ≤ 125°C

> 10

Ω

IO

A

9

= 500V, T = 150°C

S

> 10

Barrier Capacitance Field Side-

to-Logic Side

f

= 1MHz (Note 7)

2

pF

IO

SW

Minimum Creepage Distance

Minimum Clearance Distance

Internal Clearance

CPG

CLR

8

mm

Distance through insulation

Material Group I (IEC 60112)

0.015

> 400

40/125/21

Comparative Tracking Index

Climate Category

CTI

Pollution Degree

(DIN VDE 0110, Table 1)

2

20-pin and 28-pin SSOP

PARAMETER

SYMBOL

CONDITIONS

VALUE

UNITS

Method B1 = V

(t = 1s, partial discharge < 5pC)

x 1.875

IORM

Partial Discharge Test Voltage

V

1182

V

PR

P

Maximum Repetitive-Peak-

Isolation Voltage

Maximum Working-Isolation

Voltage

Maximum Transient-Isolation

Voltage

Maximum Withstanding-

Isolation Voltage

(Note 5)

630

445

IORM

IOWM

IOTM

ISO

P

Continuous RMS voltage (Note 5)

(Note 5)

RMS

P

5300

3750

10000

f

= 60Hz, duration = 60s

SW

RMS

P

(Note 5, Note 6)

Basic Insulation, 1.2/50μs pulse per

IEC61000-4-5

Maximum Surge-Isolation

Voltage

IOSM

12

V

= 500V, T = 25°C

> 10

IO

A

11

Insulation Resistance

R

= 500V, 100°C ≤ T ≤ 125°C

> 10

Ω

IO

A

9

= 500V, T = 150°C

S

> 10

Barrier Capacitance Field Side-

to-Logic Side

C

f

= 1MHz (Note 7)

2

pF

SW

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Maxim Integrated | 7

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Minimum Creepage Distance

Minimum Clearance Distance

Internal Clearance

CPG

5.5

mm

CLR

Distance through insulation

Material Group I (IEC 60112)

0.015

Comparative Tracking Index

Climate Category

CTI

> 400

40/125/21

Pollution Degree

(DIN VDE 0110, Table 1)

2

V

, V

, and V

IORM

are defined by the IEC 60747-5-5 standard.

Note 5:

Note 6:

Note 7:

ISO IOWM

Product is qualified at V

for 60s and 100% production tested at 120% of V

for 1s.

ISO

Capacitance is measured with all pins on field-side and logic-side tied together.

ESD and Transient Immunity Characteristics

PARAMETER

SYMBOL

AIN_ to GNDF

AIN_ to AIN_

CONDITIONS

VALUE (TYP) UNITS

≥ 60kΩ input resistor, IEC 61000-4-5 1.2µs/50µs pulse

≥ 60kΩ input resistors, IEC 61000-4-5 1.2µs/50µs pulse

±7.2

kV

±4

Surge

Capacitive clamp to input cable pair (AIN_- GNDF) with 60kΩ

input divider resistor connected AIN_- GNDF, 1nF Y-CAP to

earth, IEC61000-4-4

≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC

61000-4-2

EFT

ESD

AIN_ to GNDF

AIN_ Contact

±4

±8

kV

≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC

61000-4-2

AIN_ Air Gap

±15

±3

Any pin to Any pin

Human Body Model

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Maxim Integrated | 8

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Typical Operating Characteristics

(V

- V

= 3.3V, V

- V

= 3.3V, C

= 1μF, C = 1μF, T = +25°C, unless otherwise noted.)

REF A

DDL

GNDL

DDPL

GNDL

DDF

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Maxim Integrated | 9

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

www.maximintegrated.com

Maxim Integrated | 10

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Pin Configurations

TOP VIEW

REF

AGND

AIN1

AIN2

AIN3

AIN4

1

2

3

4

5

6

7

8

16 INT

15 CS

MAX22530

14 SCLK

13 SDI

12 SDO

11

10

9

V

DDL

V

DDF

DDPL

GNDF

GNDL

16 W SOIC

TOP VIEW

+

1

2

3

4

5

6

7

8

9

20

INT

REF

CS

19

18

17

16

AGND

AIN1

SCLK

SDI

AIN2

MAX22531

SDO

AGND

AIN3

15 COUT2

14 COUT1

13

AIN4

AGND

V

DDL

12

V

DDF

DDPL

11 GNDL

10

GNDF

20 SSOP

TOP VIEW

+

1

2

3

4

28

27

26

25

GNDL

NC

GNDF

NC

REF

INT

AGND

CS

24 SCLK

AIN1

AGND

AIN2

5

6

7

MAX22532

SDI

23

22

21

SDO

COUT4

8

AGND

AIN3

20 COUT3

19 COUT2

18 COUT1

17

9

10

11

12

13

14

AGND

AIN4

AGND

V

DDL

16

V

DDPL

DDF

15 GNDL

GNDF

28 SSOP

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Maxim Integrated | 11

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Pin Descriptions

MAX22530 MAX22531 MAX22532

POWER

REF

NAME

FUNCTION

SUPPLY

Output of the DC-DC Converter. Bypass to GNDF with

7

9

13

V

1μF||0.01μF capacitors. The 0.01μF capacitor should be placed

as close as possible to the pin.

DDF

Field-Side Ground for Everything Except the ADC Front-End

and Voltage Reference

Power Input for the Logic-Side. Bypass with 1μF||0.01μF

capacitors to GNDL.

Power Input for the Isolated DC-DC Converter. The DC-DC

converter powers the field-side. Bypass with 1μF||0.01μF

capacitors to GNDL.

8

10

13

1, 14

17

GNDF

VDDF

VDDL

11

V

DDL

10

12

16

V

DDPL

9

–

11

15, 28

2, 27

GNDL

N.C.

Power and Signal Ground for All Logic-Side Pins

Not Connected

–

ANALOG

External Filter Capacitor. Connect a 1μF||0.01μF capacitor from

REF to AGND.

1

2

3

1

2

3

4

5

REF

AGND

AIN1

VDDF

Analog Ground Reference for AIN_ and REF

Analog Input Channel 1 The ADC measures the voltage on this

pin with respect to AGND

Analog Input Channel 2. The ADC measures the voltage on this

pin with respect to AGND.

Analog Input Channel 3. The ADC measures the voltage on this

pin with respect to AGND.

Analog Input Channel 4. The ADC measures the voltage on this

pin with respect to AGND.

4

5

6

-

4

6

7

9

AIN2

AIN3

VDDF

7

11

AIN4

6, 8, 10,

12

5, 8

AGND

Analog Ground Reference for AIN_ and REF

DIGITAL

12

13

14

16

17

18

22

23

24

SDO

SDI

Serial Data Out for SPI Interface (MISO)

VDDL

Serial Data Input for SPI Interface (MOSI)

Serial Clock for SPI Interface

SCLK

Chip Select for SPI Interface. Assert low to enable SPI functions

15

-

19

14

25

18

and SDO. SDO and COUT_ are high impedance when

high.

Digital Comparator Output. COUT1 is high when AIN1 is above

the upper threshold (COUTHI1) and low when AIN1 is below the

lower threshold (COUTLO1) in digital input mode. See the

Digital Status Mode section.

Digital Comparator Output. COUT2 is high when AIN2 is above

the upper threshold (COUTHI2) and low when AIN2 is below the

lower threshold (COUTLO2) in digital input mode. See the

Digital Status Mode section.

Digital Comparator Output. COUT3 is high when AIN3 is above

the upper threshold (COUTHI3) and low when AIN3 is below the

lower threshold (COUTLO3) in digital input mode. See the

Digital Status Mode section.

is

VDDL

COUT1

COUT2

COUT3

-

15

-

19

20

VDDL

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Maxim Integrated | 12

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Digital Comparator Output. COUT4 is high when AIN4 is above

the upper threshold (COUTHI4) and low when AIN4 is below the

lower threshold (COUTLO4) in digital input mode. See the

Digital Status Mode section.

Open-Drain Output that Asserts Low During a Number of

Different Error Conditions. The cause of the error is latched in

the INTERRUPT STATUS register. See the Diagnostic and

-

21

26

COUT4

VDDL

16

20

Fault Reporting Features section for details on clearing

.

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Maxim Integrated | 13

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Functional Diagrams

MAX22530/MAX22531/MAX22532

REF

V

DDL

REFERENCE

= 1.8V

COUT4*

COUT3*

COUT2*

COUT1*

V

REF

AIN1

AIN2

AIN3

AIN4

INT

CS

12-BIT ADC

LOGIC AND SPI

INTERFACE

SCLK

SDI

LOGIC CONTROL

SDO

AGND

V

DDF

V

DDPL

µPOWER ISOLATED DC-DC

AGND

NOTE *:

COUT1 AND COUT2 ARE FOR MAX22531

COUT1, COUT2, COUT3, AND COUT4 ARE FOR MAX22532

GNDF

GNDL

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Maxim Integrated | 14

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Detailed Description

The MAX22530–MAX22532 family consists up of 12-bit, 4-channel ADCs with either a 3.5kV

or 5kV

isolated SPI

RMS

interface depending upon the package option. Additional features include comparators with programmable upper and

lower threshold levels. The ADC and all field-side circuits are powered by an integrated, isolated, DC-DC converter that

allows field-side functionality to be verified even when there is no input signal or other field-side supply. This makes the

MAX22530–MAX22532 family ideally suited for high-density, multirange, group-isolated, binary-input modules, and

provides a complete solution to any system that requires monitoring inputs without a separate isolated power supply.

ADC

The devices’ ADC employs a 12-bit SAR architecture with a nominal sampling rate of 20ksps per channel and has an

input-voltage range of 0V to +1.8V with respect to AGND. After power-up, the ADC runs continually at the nominal

sampling rate. The 12-bit unfiltered ADC reading and filtered ADC reading are both available through the SPI interface.

Filtering averages the most recent 4 readings. For rapid response without requiring the SPI interface, the MAX22530–

MAX22532 family provides the output of a digital comparator (COUT_) that compares user-programmed thresholds to

the ADC reading or the filtered ADC reading. The comparator has two thresholds, the comparator output is high when the

input voltage is above the upper threshold and low when it is below the lower threshold in default digital-input mode. The

response time of the comparator is less than 75μs (typ) with filtering disabled. With filtering enabled, the comparator uses

the moving average of the last 4 ADC readings for a response time of 300μs (typ). The comparator output pin (COUT_)

changes based on the latest ADC reading, the upper threshold (COTHI_[11:0], register address 0x9, 0xA, 0xB and 0xC)

and the lower threshold (COTLO_[11:0], register address 0x10, 0xD, 0xE and 0xF) according to the CO_MODE_ setting.

If enabled, the interrupt pin

asserts whenever COUT_ changes.

Internal Voltage Reference

The MAX22530-MAX22532 family features a precision internal voltage reference. The 1.8V internal reference has a

maximum error of ±2% over the entire operating temperature range. The MAX22530-MAX22532 family is not intended to

be used with an external voltage reference.

Input Comparator with Programmable Thresholds and Two Operational Modes (CO_MODE)

The input signal can be recognized in two different ways; one is the digital input mode and the other is the digital status

mode. The mode of operation is set for each input channel in the COUTHI_ registers (address 0x9, 0xA, 0xB and 0xC)

with the CO_MODE bits.

Digital Input Mode

The Digital input mode (see Figure 3) treats the digitized input (from the ADC) as a digital signal of “1” or “0” with hysteresis

where the values for “1” and “0” are set by the upper- and lower-limit thresholds programmed into registers COUTHI_ and

COUTLO_ (see COUT_BLK in register map).

1. Upper limit and lower limit are used as hysteresis (like a Schmitt trigger input).

2. The status of COUT_ changes to “1” only when the ADC (or FADC) value crosses over the upper limit during a low-

to-high transition, and to “0” when it crosses below the lower limit during a high-to-low transition.

3. The status of COUT_ can be “0” or “1” between the lower and upper limits based on the previous status.

ANALOG INPUT/

ADC1 OUTPUT

COTHI1

COTLO1

COUT1

0

1

0

1

0

NOTE: IN PRACTICE, THERE IS A DELAY BETWEEN ANALOG INPUT AND DIGITIZED ADC OUTPUT (CONVERSION TIME).

Figure 3. Digital Input Mode

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Maxim Integrated | 15

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Digital Status Mode

The Digital status mode (see Figure 4) monitors the input in “Normal” status vs. “OVLO/UVLO” status:

1. The status of COUT_ is “0” when the digitized output of ADC (or FADC) is between the lower limit and the upper limit.

2. The status of COUT_ is “1” when the digitized output of ADC (or FADC) is higher than the upper limit or lower than the

lower limit.

ANALOG INPUT/

ADC1 OUTPUT

COTHI1

COTLO1

COUT1

1

0

1

0

1

0

1

0

1

0

1

NOTE: THERE IS A DELAY BETWEEN ANALOG INPUT AND DIGITIZED ADC OUTPUT (CONVERSION TIME).

Figure 4. Digital Status Mode

Isolated Power and Data Transfer

A simplified view of the isolated power and data transfer sections is shown in the Functional Diagram. The logic-side

supply V powers an integrated, inductively coupled DC-DC converter that generates a nominal field supply V of

DDPL

DDF

is not

3.1V with just enough output current to power the field-side of the MAX22530–MAX22532 family. Note that V

DDF

intended to power an external load.

Serial data is transferred by capacitively-isolated differential transceivers. To verify reliable communication through the

isolation barrier, a cyclic redundancy check (8-bit CRC) is embedded in the transmitted serial data streams. If a CRC fails,

the data is discarded, and no action is taken. If CRC fails, the SPICRC bits in the INTERRUPT STATUS register is set

and

is asserted if the ENCRC interrupt enable bit is set in the INTERRUPT ENABLE register.

Configuration and Monitoring

An SPI interface is used for transferring configuration, control, and diagnostic data as well as ADC readings between a

host (FPGA or microcontroller) and the MAX22530–MAX22532. The interface consists of four signals: SCLK,

, SDI

and SDO, and does not support daisy-chain configuration. An optional CRC improves reliability in the data communication

to and from the MAX22530–MAX22532. This feature, disabled by default after reset or power-up, can be enabled or

disabled at any time through the SPI interface. When enabled, it affects both read and write SPI transactions.

SPI Interface

SPI communication includes the following features (see Table 3):

•

Serial clock up to 10MHz

8

2

1

CRC function uses SMBus polynomial: C(x) = (x + x + x + 1) that is added if the ENCRC bit is set in the CONTROL

register.

•

Burst Mode for reading multiple registers

The functionality of each SPI pin can be summarized as follows:

•

Serial Clock (SCLK): Input for the master serial clock signal. The clock signal determines the speed of the data transfer

(up to 10MHz max). All receiving and transmitting is done synchronous to this clock.

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Maxim Integrated | 16

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

•

Chip Select ( ): The

SCLK transitions are ignored. During a

Serial Input (SDI): SDI or MOSI is the serial input port of the SPI shift register and data is clocked LSB first into the

shift register on the rising edge of SCLK. To provide sufficient setup/hold time, the driver should have SDI data

input enables the SPI interface. A logic-high on

forces SDO to high-impedance and any

logic-low state, data is transferred on the edges of SCLK.

transitions at the falling edge of SCLK. On the rising edge of

Serial Output (SDO): SDO or MISO is the serial output port of the SPI shift register, and is in a high-impedance state

until the pin goes to a logic-low state and at the end of the BURST data bit. Data is clocked LSB first out of the

shift register on the falling edge of SCLK.

, the input data is latched into the internal registers.

•

The MAX22530–MAX22532 offers burst and single-register SPI transactions. Single-register SPI transactions can be

used to access any register address and are 3-bytes long without CRC and 4-bytes long with CRC. The CRC byte is

calculated on the previous 3 bytes. The single-register SPI transaction format consists of a 6-bit register address, a

read/write bit, a burst mode bit, 16 bits of payload, and the optional CRC byte, as illustrated in Table 1 for write transaction

and in Table 2 for read transactions. Refer to Figure 1 and Figure 2 for SPI write and read timing diagrams.

Table 1. SPI Write Command

HEADER

PAYLOAD

A[5:0]

W/ = 1

BURST = 0

Data D[15:0]

CRC (optional), C[7:0]

Note: The BURST bit in the header is ignored in SPI write transactions

Table 2. SPI Read Command

HEADER

PAYLOAD

A[5:0]

W/ = 0

BURST = 0

Data D[15:0]

CRC (optional), C[7:0]

Burst mode can only be used for reading the filtered or unfiltered ADC data registers and the interrupt status register in

one SPI transaction. Burst SPI transactions are 11-bytes long without CRC and 12-bytes long with CRC. The CRC byte

is calculated on the previous 11 bytes. The burst SPI transaction format consists of the 6-bit register address for ADC1

or FADC1, a read/write bit, a burst mode bit, the contents of the four filtered or unfiltered ADC registers depending on the

6-bit address entered, the content of the interrupt status register, and the optional CRC byte, as illustrated in Table 3. The

burst bit is ignored for all other register addresses during read transactions.

The MAX22530–MAX22532 knows that it should receive 24, 32, 88, or 94 bits depending on the combination of CRC

setting and burst mode. If more SPI cycles than expected are received, the transaction is executed. If fewer SPI cycles

than expected are received, the transaction fails.

Table 3. SPI Burst Read Command

HEADER

PAYLOAD

F/ADC_1

D[15:0]

F/ADC_2

D[15:0]

F/ADC_3

D[15:0]

F/ADC_4

D[15:0]

INTERRUPT

STATUS[15:0]

8-bits CRC (optional),

C[7:0]

A[5:0] W/ = 0 BURST = 1

•

For burst read transactions, if Address A[5:0] is 0x01 (ADC_1), the data read is the unfiltered ADC data. If Address

A[5:0] is 0x05 (FADC_1), the data read is the filtered ADC data.

The burst bit is ignored for all other register addresses during read transactions.

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Maxim Integrated | 17

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Diagnostic and Fault Reporting Features

The MAX22530–MAX22532 continuously monitor multiple possible fault conditions, and a hardware alert is provided

through the open drain pin, which asserts low when an enabled fault is detected. The possible faults are: ADC

functionality error, SPI framing error, CRC errors from SPI communications, and loss of internal isolated data stream.

The bits in the INTERRUPT ENABLE (0x13) register determine how the output responds to the various error

conditions and asserts the output if the corresponding bit is enabled in the INTERRUPT ENABLE register.

If the corresponding bit in the INTERRUPT ENABLE register is not set, when an error is flagged, is not asserted, but

the bit in the INTERRUPT STATUS register (0x12) is still latched and remains set until the register is read, which

automatically clears all bits in the INTERRUPT STATUS register. Note that if a fault condition still exists when the register

is read, the cleared fault bit is immediately set again.

In a typical application,

triggers an interrupt routine in the microcontroller or FPGA, which reads the INTERRUPT

STATUS register to determine the cause of the interrupt.

ADC Functionality Error

ADC functionality is checked by looking for changes in the ADC output. To ensure that a change should have occurred,

a special test measurement is made while injecting a small current at the input of the ADC. This special measurement

used for ADC functionality verification is interleaved between normal measurements and does not affect the ADC

sampling time. If the ADC reading does not change, or data is outside of the limits for at least four frames, an ADC

functional failure is declared and bit FADC (bit 11) in the INTERRUPT STATUS (0x12) register is set.

SPI Framing Error

After

transitions from low to high, if the number of bits clocked in while

was low is not 24, 32, 88, or 96 bits, an SPI

framing error is declared and bit SPIFRM (bit 9) in the INTERRUPT STATUS (0x12) register is set. The instruction in the

SPI shift register is not decoded and no register value is changed.

Loss of Data Stream

The field-side sends ADC data across the isolation barrier to the logic-side every 50μs except for the startup period. Field-

side loss-of-data (FLD) interrupts are masked for the first 100ms of operation after power-on or reset, and after that if an

internal monitoring signal is not received, an error is flagged. If the periodic field-side data is not received, a loss-of-data-

stream fault is declared and bit FLD (bit 10) in the INTERRUPT STATUS (0x12) register is set. It is possible to recover

from a loss of data stream fault by asserting a hard reset using bit REST (bit 0) in the CONTROL (0x14) register, which

causes field-side power to be rebooted and returns all of the registers to their default state, requiring the MAX22530–

MAX22532 to go through the startup configuration process.

CRC Error from Internal Communication

Internal communication across the isolation barrier includes a CRC code to ensure that corrupt data does not cause

system problems. If the CRC indicates an error, the received data is discarded. If six consecutive CRCs fail, a CRC fault

is declared and bit SPICRC (bit 8) in the INTERRUPT STATUS (0x12) register is set.

Control Modes

The CONTROL (0x14) register includes a number of bits which the host can program and which take immediate effect on

the device.

Hardware Reset Control

If the control bit REST is set to 1, the field-side power supply is shut down and restarted, and the main reset input to the

digital core is asserted, resulting in setting the digital core back to its power-on reset state and all registers are brought

back to their default values, including the control bit, REST.

Software Reset Control

The software reset is initiated by setting bit SRES to 1. Unlike the hardware reset that is effective immediately after

assertion, SRES takes affect after the completion of the frame, during which it is asserted. At that time, the digital core is

reset and all registers are brought back to their default values. The field-side power supply is not affected by SRES.

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Maxim Integrated | 18

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

Clear POR Control

The CLRPOR bit can be set to 1 to clear the ‘Wake Up from Power-On Reset’ POR bit in the PROD_ID (0x00) register.

Note that a hardware reset (REST) causes the POR bit to be reasserted, but a software reset, SRES, has no effect on

the status bit POR.

DISPWR Control

Setting bit DISPWR to 1 disables field-side power (V

core is not affected.

), effectively stopping ADC conversions. The logic-side or digital

DDF

Filter Clearing Control

The control bits FLT_CLR_1 to FLT_CLR_4 can be set to 1 to clear the ADC moving average filter for that specific channel

at the start of the frame following this assertion. Once the filter reset operation takes place the control bits remain set at

0 for normal operation.

Comparator Limit Control

The control bit ECOM can be set to 1 to apply the settings of COUTHI1 and COUTLO1 to all four channels regardless of

what values are programmed in the high and low threshold registers for the other three channels. Setting the ECOM bit

to 1 does not change what the host reads back from the threshold registers for channels 2 to 4.

CRC Control

If control bit ENCRC is 0, CRC functionality is not enabled, and SPI transactions are 24-bits in length. But if control bit

ENCRC is 1, CRC functionality is enabled making each SPI transaction 32-bits in length. At power-on, or after a hardware

or software reset, the default CRC is disabled. All SPI transactions following the write transaction that sets ENCRC must

have the 8-bit CRC suffix.

Interrupts

In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or

FPGA) by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT

ENABLE (0x13) register to assert the interrupt pin,

in succession, and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit

15), or by enabling the EOC to be shown on the every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the

INTERRUPT STATUS (0x12) register is set to 1 and causes the pin to be asserted for a duration of 10µs at the end

pin is deasserted whether the INTERRUPT STATUS register

. The ADC core continually digitizes the inputs for the four channels

of channel 4 ADC (ADC_4) conversion. After 10µs the

is read or not.

At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the

comparator status and comparator-related interrupts.

If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers

(ADC1 to ADC4, or FADC1 to FADC4. See ADC_STATUS BLK in register map section) in addition to the INTERRUPT

STATUS register. Bit 15 in each ADC_ register is the ADCs bit. If ADCs is 0 the register contents have been updated

(new conversion data) since the last read operation. By performing a data read operation, the ADCs bit is automatically

set to 1, indicating the data has not been refreshed since the last read operation. Upon receiving the

interrupt service routine can perform a burst read, which automatically clears the bits in the INTERRUPT STATUS register,

thereby deasserting the pin.

signal, the host

If the host does not access the ADC_ data registers at least once per frame (whether by polling or responding to

being asserted) then data loss occurs, and the register contents are overwritten with new conversion data.

If the ADC_ data register refreshing event occurs while

is low (i.e., during an SPI transaction), the data refreshing

event is postponed until the deassertion of . This scheme eliminates possible data corruption and data loss. However,

it assumes that the rate of the SPI transaction is equal to or greater than the rate of ADC sampling (20ksps), and that the

duration of any SPI transaction is shorter than that of a 4-channel conversion frame. The host can safely read the ADC_

data registers during the 50µs following the assertion of the end-of-conversion interrupt.

The host can set the limits against which the ADC data is compared. The host can select if a given channel uses the

unfiltered (ADC_) or the filtered ADC (FADC_) data for comparison against the limits using the control bits CO_MODE

(bit 15) and CO_IN_SEL (bit 14) in each COUTHI_ register. The CO_MODE bits determine the comparator mode of

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Maxim Integrated | 19

MAX22530–MAX22532

Field-Side Self-Powered,

4-Channel, 12-bit, Isolated ADC

operation (Digital Data Mode if the bit is set to 0 or Digital Status Mode if the bit is set to 1) and CO_IN_SEL selects

between unfiltered ADC data (bit set to 0) of filtered ADC data (bit set to 1). The status of the comparison for each channel

can be read from register COUT STATUS (0x11).

In addition to the diagnostics bits, the comparator outputs can be programmed to assert the

pin if enabled. If a positive

edge is detected by the comparator, the bit CO_POS_ is set to 1 indicating the ADC_ data is greater than the upper limit

(COUTHI_). Similarly, if a negative edge is detected by the comparator, the bit CO_NEG_ is set to 1 indicating the ADC_

data is lower than the lower limit (COUTLO_).

Changes to comparator control register contents take effect on the next frame. For example, if COUTHI_4[11:0] is

changed during frame N, the new threshold value is used starting frame N+1.

To clear an interrupt and deactivate the

pin, the host must perform a read operation of the INTERRUPT STATUS

register. All bits in the INTERRUPT STATUS register are “Read Clears All.” Interrupts are cleared whether the CRC is

properly decoded by the host or not. Note that if a fault condition still exists when the register is read, the cleared fault bit

is immediately set again.

If an interrupt is not set at the time that the INTERRUPT STATUS register is read, and if that interrupt gets asserted while

the interrupt register is being read, that interrupt bit is not cleared upon the end of the SPI read transaction.

However, if an interrupt that is set at the time that the interrupt register is read, and if another identical interrupt gets

asserted while the interrupt register is being read, that interrupt bit is cleared upon the end of the SPI transaction. This

means that the host should read the interrupt register upon assertion of

per conversion cycles to avoid missing interrupts.

, or poll the interrupt registers several times

In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or

FPGA) by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT

ENABLE (0x13) register to assert the interrupt pin,

in succession, and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit

15), or by enabling the EOC to be shown on the every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the

INTERRUPT STATUS (0x12) register is set to 1 and causes the pin to be asserted for a duration of 10µs at the end

pin is deasserted whether the INTERRUPT STATUS register

. The ADC core continually digitizes the inputs for the four channels

of channel 4 ADC (ADC_4) conversion. After 10µs the

is read or not.

At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the

comparator status and comparator-related interrupts.

If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers

(ADC1 to ADC4, or FADC1 to FADC4) in addition to the INTERRUPT STATUS register. Bit 15 in each ADC_ register is

the ADCs bit. If ADCs is 0 the register contents have been updated (new conversion data) since the last read operation.

By performing a data read operation, the ADCs bit is automatically set to 1, indicating the data has not been refreshed

since the last read operation. Upon receiving the

which automatically clears the bits in the INTERRUPT STATUS register, thereby deasserting the

signal, the host interrupt service routine can perform a burst read,

pin.