MAX22702D [MAXIM]
Ultra-High CMTI Isolated Gate Drivers;
| 型号： | MAX22702D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-High CMTI Isolated Gate Drivers 栅 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
General Description
Benefits and Features
● Matching Propagation Delay
The MAX22700–MAX22702 are a family of single-chan-
nel isolated gate drivers with ultra-high common-mode
transient immunity (CMTI) of 300kV/µs (typ). The devices
are designed to drive silicon-carbide (SiC) or gallium-
nitride (GaN) transistors in various inverter or motor
control applications. All devices have integrated digital
galvanic isolation using Maxim’s proprietary process tech-
nology. The devices feature variants with output options
for gate driver common pin GNDB (MAX22700), Miller
clamp (MAX22701), and adjustable undervoltage-lockout
UVLO (MAX22702). In addition, variants are offered as
differential (D versions) or single-ended (E versions)
inputs. These devices transfer digital signals between
circuits with different power domains. All of the devices in
the family feature isolation for a withstand voltage rating
• 20ns Minimum Pulse Width
• 35ns Propagation Delay at Room Temperature
• 2ns Part-to-Part Propagation Delay Matching at
Room Temperature
• 5ns Part-to-Part Propagation Delay Matching over
-40°C to +125°C Temperature Range
● High CMTI (300kV/µs, typ)
● Robust Galvanic Isolation
• Withstands 3kV
for 60s (V
)
RMS
ISO
• Continuously Withstands 848V
• Withstands ±5kV Surge Between GNDA and V
(V
)
RMS IOWM
SSB
with 1.2/50μs Waveform
● Precision UVLO
● Options to Support a Broad Range of Applications
• 3 Output Options: GNDB, Miller Clamp, or
Adjustable UVLO
of 3kV
for 60 seconds.
RMS
All devices support a minimum pulse width of 20ns with a
maximum pulse width distortion of 2ns. The part-to-part
propagation delay is matched within 2ns (max) at +25°C
ambient temperature, and 5ns (max) over the -40°C
to +125°C operating temperature range. This feature
reduces the power transistor’s dead time, thus improving
overall efficiency.
• 2 Input Configurations: Single-Ended with Enable
(E versions) or Differential (D versions)
Applications
● Isolated Gate Driver for Inverters
● Motor Drives
The MAX22700 and the MAX22702 have a maximum
● UPS and PV Inverters
R
of 1.25Ω for the low-side driver, and the MAX22701
DSON
has an R
have a maximum R
See the Ordering Information for suffixes associated with
of 2.5Ω for the low-side driver. All devices
DSON
Safety Regulatory Approvals
● UL According to UL1577
of 4.5Ω for the high-side driver.
DSON
● cUL According to CSA Bulletin 5A
each option.
The MAX22700–MAX22702 can be used to drive SiC or
GaN FETs with different output gate drive circuitry and
B-side supply voltages. See the Typical Operating Circuits
for details.
Ordering Information appears at end of data sheet.
All of the devices in the MAX22700–MAX22702 family
are available in an 8-pin, narrow-body SOIC package with
4mm of creepage and clearance. The package material
has a minimum comparative tracking index (CTI) of 600V,
which gives it a group I rating in creepage tables. All
devices are rated for operation at ambient temperatures
of -40°C to +125°C.
19-100581; Rev 2; 9/19
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Absolute Maximum Ratings
V
to GNDA........................................................-0.3V to +6V
OUT to V
..........................................-0.3V to (V
+ 0.3V)
DDA
SSB
DDB
V
to GNDB......................................................-0.3V to +40V
Continuous Power Dissipation (T = +70°C)
DDB
A
GNDB to V
......................................................-0.3V to +40V
.......................................................-0.3V to +40V
Narrow SOIC (derate 9.39mW/°C above +70°C)......750.89mW
Operating Temperature Range......................... -40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range............................ -60°C to +150°C
Soldering Temperature (reflow).......................................+260°C
SSB
V
to V
DDB
SSB
INP, INN, IN, EN to GNDA.......................................-0.3V to +6V
V
to ADJ............................................................-0.3V to +6V
DDB
CLAMP to V
.....................................-0.3V to (V
+ 0.3V)
SSB
DDB
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 8 NARROW SOIC
Package Code
S8MS+23
21-0041
90-0096
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
106.54°C/W
44.91°C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(V
- V
= 5V, V
- V
= 20V, V
= V
= 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at
DDA
GNDA
DDB
SSB
GNDA
SSB A
T
= +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Voltage
V
V
Relative to GNDA
3
13
5.5
36
DDA
DDB
Relative to GNDB, MAX22700
Relative to V
Relative to V
, MAX22701
, MAX22702
13
36
SSB
V
6
36
SSB
V
Relative to GNDB, MAX22700
-16
13
0
SSB
Differential Supply
V
V
V
V
- V , MAX22700
SSB
36
DIFF
DDB
DDA
DDA
V
V
rising
falling
2.69
2.59
2.82
2.72
2.95
2.85
V
V
Undervoltage-Lockout
Threshold
UVLOAP
UVLOAN
Undervoltage-Lockout
Threshold Hysteresis
V
100
mV
UVLOA_HYST
Maxim Integrated
│ 2
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
DC Electrical Characteristics (continued)
(V
- V
= 5V, V
- V
= 20V, V
= V
= 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at
DDA
GNDA
DDB
SSB
GNDA
SSB A
T
= +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
11.6
11.6
1.79
TYP
13
MAX
UNITS
V
V
V
V
V
V
V
V
V
V
V
V
rising, relative to GNDB, MAX22700
falling, relative to GNDB, MAX22700
13.3
UVLOBP
UVLOBN
UVLOBP
UVLOBN
UVLOBP
UVLOBN
DDB
DDB
DDB
DDB
DDB
DDB
12
rising, relative to V
falling, relative to V
, MAX22701
, MAX22701
13
13.3
2.05
Undervoltage-Lockout
Threshold
SSB
V
12
SSB
rising, relative to ADJ, MAX22702
falling, relative to ADJ, MAX22702
2
1.84
1
MAX22700, MAX22701
MAX22702
Undervoltage-Lockout
Threshold Hysteresis
V
V
UVLOB_HYST
0.16
SUPPLY CURRENT
V
V
V
V
= 5V, INN/EN = V
DDA
5
3
5
3
6.5
4
A-Side Quiescent
Supply Current
DDA
DDA
DDA
DDA
I
mA
DDA
DDA
= 3.3V, INN/EN = V
DDA
= 5V, f
= 1MHz
6.5
4
PWM
A-Side Active Supply Current
I
I
mA
mA
= 3.3V, f
= 1MHz
PWM
B-Side Quiescent
Positive Supply Current
INN/EN = V
= 1MHz (Note 2)
3.5
6
6
DDB
DDA
B-Side Active
Positive Supply Current
I
f
10
mA
µA
DDB
PWM
B-Side Ground Current
I
MAX22700
-25
GNDB
LOGIC INTERFACE (INP, INN, IN, EN)
0.7 x
Input High Voltage
V
V
V
IH
V
DDA
0.3 x
Input Low Voltage
Input Hysteresis
V
IL
V
DDA
0.1 x
V
mV
HYS
V
DDA
-5
Input Pullup Current (Note 3)
Input Pulldown Current (Note 3)
Input Capacitance
I
INN, EN
-10
1.5
-1.5
10
µA
µA
pF
PU
I
INP, IN
5
2
PD
C
f
= 1MHz
PWM
IN
ADJ (MAX22702 ONLY)
Input Leakage Current
GATE DRIVER
I
V
- V = 3V
ADJ
-100
100
4.7
nA
ADJ
DDB
High-Side Transistor
On-Resistance
R
I
I
= -100mA (Note 3)
Ω
DSON_H
OUT
OUT
MAX22700/MAX22702
MAX22701
1.25
2.5
Ω
Ω
Low-Side Transistor
On-Resistance
= 100mA
R
DSON_L
(Note 3)
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
DC Electrical Characteristics (continued)
(V
- V
= 5V, V
- V
= 20V, V
= V
= 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at
DDA
GNDA
DDB
SSB
GNDA
SSB A
T
= +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
= -10mA (Note 3)
MIN
TYP
MAX
UNITS
Output-Voltage High
V
I
I
19.95
V
OH
OUT
MAX22700/MAX22702
0.01
0.02
= 10mA
OUT
Output-Voltage Low
V
V
A
OL
(Note 3)
C = 10nF, f = 1kHz (Note 2)
PWM
MAX22701
High-Side Transistor
Peak Output Current
I
2.35
4
OH
L
C = 10nF,
L
MAX22700/MAX22702
MAX22701
3.7
1.9
5.7
Low-Side Transistor
Peak Output Current
I
f
= 1kHz
A
V
OL
PWM
2.85
(Note 2)
Active Pulldown Voltage
V
I
= 150mA (Note 3)
2.2
OUTSD
OUT
MILLER CLAMP (MAX22701 ONLY)
Miller Clamp Transistor
On-Resistance
R
I
= 100mA (Note 3)
2.5
2.3
Ω
DSON_CLMP
CLAMP
Miller Clamp Threshold
Miller Clamp Turn-On Time
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
V
1.7
2
V
TH_CLMP
t
See Figure 4
20
ns
ON
T
160
25
°C
°C
SHDN
T
SHDN_HYS
Dynamic Characteristics
(V
- V
= 5V, V
- V
= 20V, V
= V
= 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at
DDA
GNDA
DDB
SSB
GNDA
SSB A
T
= +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CMTI
CONDITIONS
MIN
TYP
MAX
UNITS
kV/µs
ns
Common-Mode Transient Immunity
Minimum Pulse Width
(Note 5)
C = 200pF
300
PW
20
MIN
L
Maximum PWM Frequency
f
1
MHz
PWM
T
T
T
T
T
T
T
T
= +25°C to +125°C
= +25°C
34
34
31
34
34
31
39
36
36
39
36
36
2
A
A
A
A
A
A
A
A
C = 200pF,
L
t
35
35
PLH
output is not
connected to
CLAMP pin
(MAX22701)
(Note 4)
= -40°C to +25°C
= +25°C to +125°C
= +25°C
Propagation Delay
(Figure 3)
ns
ns
t
PHL
= -40°C to +25°C
= +25°C
Part-to-Part Propagation Delay
Matching (Figure 3)
C = 200pF
L
(Note 4)
= -40°C to +125°C,
t
PM
parts at the same
5
temperature
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Dynamic Characteristics (continued)
(V
- V
= 5V, V
- V
= 20V, V
= V
= 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at
DDA
GNDA
DDB
SSB
GNDA
SSB A
T
= +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
C = 200pF, |t - t
MIN
TYP
MAX
UNITS
ns
Pulse Width Distortion
Peak Eye Diagram Jitter
PWD
|
PLH PHL
2
L
T
1MHz square wave, C = 200pF
60
ps
JIT(PK)
L
Rise Time
(Figure 3)
t
C = 200pF, 20% to 80% (Note 2)
L
3.6
ns
R
MAX22700/
MAX22702
C = 200pF,
L
80% to 20%
(Note 2)
1.8
2.5
ns
ns
Fall Time
(Figure 3)
t
F
MAX22701
Note 1: All devices are 100% production tested at T = +25°C. Specifications over temperature are guaranteed by design and char-
A
acterization.
Note 2: Not production tested. Guaranteed by design and characterization.
Note 3: All currents into the device are positive. All currents out of the device are negative. All voltages are referenced to their
respective ground (GNDA or V
Note 4: Propagation delay is measured from 50% of the input to 2V at the output.
), unless otherwise noted.
SSB
Note 5: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to
both rising and falling common-mode voltage edges. CMTI is tested with the transient generator connected between GNDA
and V
(V
= 1000V).
SSB CM
ESD Protection
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ESD
Human Body Model, All Pins
±4
kV
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Table 1. Insulation Characteristics
PARAMETER
SYMBOL
CONDITIONS
Method B1 = V x 1.875
VALUE
UNITS
IORM
Partial Discharge Test Voltage
V
2250
V
V
PR
P
P
(t = 1s, partial discharge < 5pC)
Maximum Repetitive Peak Isolation Voltage
Maximum Working Isolation Voltage
Maximum Transient Isolation Voltage
Maximum Withstand Isolation Voltage
V
(Note 6)
1200
848
IORM
V
Continuous RMS voltage (Note 6)
t = 1s (Note 6)
V
V
IOWM
RMS
V
4242
3000
V
P
IOTM
V
f
= 60Hz, duration = 60s (Note 6, 7)
ISO
SW
RMS
kV
Basic insulation, 1.2/50µs pulse per
IEC 61000-4-5 (Note 6)
Maximum Surge Isolation Voltage
V
5
IOSM
12
V
V
V
= 500V, T = 25°C
>10
IO
IO
A
11
Insulation Resistance
RIO
= 500V, 100°C ≤ T ≤ 125°C
>10
Ω
A
9
= 500V at T = 150°C
S
>10
IO
Barrier Capacitance Side A to Side B
Minimum Creepage Distance
Minimum Clearance Distance
Internal Clearance
CIO
CPG
CLR
f
= 1MHz (Note 8)
1
4
pF
SW
Narrow SOIC
mm
mm
mm
Narrow SOIC
4
Distance through insulation
Material Group I (IEC 60112)
0.015
>600
40/125/21
Comparative Tracking Index
Climate Category
CTI
Pollution Degree
(DIN VDE 0110, Table 1)
2
Note 6: V
, V
, V
, V
, and V
are defined by the IEC 60747-5-5 standard.
ISO IOTM IOSM IOWM
IORM
Note 7: Product is qualified at V
for 60s and 100% production tested at 120% of V
for 1s.
ISO
ISO
Note 8: Capacitance is measured with all pins on side A and side B tied together.
Safety Regulatory Approvals
UL
The MAX22700–MAX22702 are certified under UL1577. For more details, refer to file E351759.
Rated up to 3000V isolation voltage for single protection.
RMS
cUL (Equivalent to CSA notice 5A)
The MAX22700–MAX22702 are certified up to 3000V
for single protection. For more details, refer to file E351759.
RMS
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
determine the junction temperature. Thermal imped-
Safety Limits
ance values (θ and θ ) are available in the Package
JA
JC
Damage to the IC can result in a low-resistance path
to ground or to the supply and, without current limiting,
the MAX22700–MAX22702 could dissipate excessive
amounts of power. Excessive power dissipation can dam-
age the die and result in damage to the isolation barrier,
potentially causing long-term reliability issues. Table 2
shows the safety limits for the MAX22700–MAX22702.
Information section of the data sheet and power dissipa-
tion calculations are discussed in the Calculating Power
Dissipation section. Calculate the junction temperature
(T ) as:
J
T = T + (P × θ )
JA
J
A
D
Figure 1 and Figure 2 show the thermal derating curve
for safety limiting the power and the current of the device.
Ensure that the junction temperature does not exceed
+150°C.
The maximum safety temperature (T ) for the device is
S
the +150°C maximum junction temperature specified in
the Absolute Maximum Ratings. The power dissipation
(P ) and junction-to-ambient thermal impedance (θ
D
)
JA
THERMAL DERATING CURVE
FOR SAFETY POWER LIMITING
THERMAL DERATING CURVE
FOR SAFETY CURRENT LIMITING
fig01
fig02
1400
350
MULTILAYER BOARD
1200
MULTILAYER BOARD
300
1000
800
600
400
200
0
250
200
150
100
50
0
0
25
50
75 100 125 150 175 200
0
25
50
75 100 125 150 175 200
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 1. Thermal Derating Curve for Safety Power Limiting
Figure 2. Thermal Derating Curve for Safety Current Limiting
Table 2. Safety Limiting Values for the MAX22700–MAX22702
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
UNIT
T = 150°C, T = 25°C, IN = Low,
J
A
V
V
= 36V
= 20V
32
mA
DDB
DDB
Safety Operating Current on
B-Side Pins
I
OUT = V
, OUT = Low during
OUT
DDB
57
mA
mA
thermal shutdown
Safety Current on Any Pins (No
Damage to Isolation Barrier)
I
T = 150°C, T = 25°C
300
S
J
A
Total Safety Power Dissipation
Maximum Safety Temperature
P
T
T = 150°C, T = 25°C
1173
150
mW
°C
S
J
A
S
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Test Circuits and Timing Diagrams
V
V
DDB
DDA
V
V
DDB
DDA
MAX2270_E
V
IN
DDA
IN
OUT1
IN
50%
50%
OUT
TEST
SOURCE
C
200pF
L
EN
GNDA
GNDA
t
t
PHL
PLH
V
SSB
V
DDB
OUT1
OUT2
2V
2V
V
SSB
t
t
PM
PM
V
V
DDB
DDA
V
DDB
80%
20%
MAX2270_E
IN
2V
2V
OUT2
V
SSB
OUT
C
200pF
L
EN
GNDA
t
t
F
R
V
SSB
(A)
(B)
Figure 3. Test Circuit (A) and Timing Diagram (B)
V
DDA
INPUT
SOURCE
GNDA
V
V
DDB
DDA
V
V
DDB
DDA
V
DDB
MAX22701E
CLAMP
TEST
SOURCE
50Ω
IN
C
200pF
L
INPUT
SOURCE
V
SSB
TEST
SOURCE
EN
V
DDB
GNDA
V
SSB
V
= 2V
TH_CLMP
CLAMP
V
SSB
t
= 20ns
ON
(A)
(B)
Figure 4. MAX22701 Miller Clamp Test Circuit (A) and Timing Diagram (B)
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Characteristics
(V
- V
= 5V, V
- V
= 20V, V
= V
, T = +25°C, unless otherwise noted.)
DDA
GNDA
DDB
SSB
GNDA
SSB A
HIGH-SIDE PEAK OUTPUT CURRENT
vs. VDDB SUPPLY VOLTAGE
LOW-SIDE PEAK OUTPUT CURRENT
vs. VDDB SUPPLY VOLTAGE
HIGH-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
toc01
toc02
toc03
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
8
7
6
5
4
3
2
1
5
4
3
2
1
0
CL = 0.1µF, SERIES RESISTOR RS = 0.5Ω
CL = 0.1µF, SERIES RESISTOR RS = 0.5Ω
MAX22700/MAX22701, IOUT = 100mA
MAX22700/2
VDDB = 13V
VDDB = 20V
MAX22701
V
= 36V
DDB
12
16
20
24
28
32
36
6
12
18
24
30
36
-50
-25
0
25
50
75
100 125
VDDB SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
VDDB SUPPLY VOLTAGE (V)
HIGH-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
LOW-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
LOW-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
toc04
toc05
toc06
5
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
MAX22700/MAX22702, IOUT = 100mA
VDDB = 6V ONLY APPLIES TO MAX22702
MAX22702, IOUT = 100mA
MAX22701, IOUT = 100mA
VDDB = 6V
VDDB = 6V
VDDB = 13V
V
VDDB = 13V
VDDB = 20V
VDDB = 36V
VDDB = 13V
VDDB = 20V
VDDB = 36V
VDDB = 20V
VDDB = 36V
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
VDDB SUPPLY CURRENT
vs. TEMPERATURE
VDDB SUPPLY CURRENT
vs. TEMPERATURE
toc08
toc07
5.5
5.0
4.5
4.0
3.5
3.0
2.5
4.0
3.8
3.6
3.4
3.2
3.0
MAX22702
INP/IN = GNDA, INN/EN = VDDA, CL = 0pF
MAX22700/MAX22701
INP/IN = GNDA, INN/EN = VDDA, CL = 0pF
VDDB = 13V
V
= 6V
DDB
VDDB = 20V
V=13V
DDB
V=25V
DDB
V=20V
DDB
V
= 36V
DDB
V=36V
DDB
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
│ 9
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Characteristics (continued)
(V
- V
= 5V, V
- V
= 20V, V
= V , T = +25°C, unless otherwise noted.)
SSB A
DDA
GNDA
DDB
SSB
GNDA
VDDB SUPPLY CURRENT
vs. PWM FREQUENCY
VDDB SUPPLY CURRENT
vs. LOAD CAPACITANCE
VDDA SUPPLY CURRENT
vs. TEMPERATURE
toc09
toc10
toc11
10
9
5.0
8
7
6
5
4
3
2
1
VDDB = 3V
VDDB = 3.3V
VDDB = 5V
INP/IN = GNDA,
CL = 200pF, VDDB = 20V
INPUT = 100kHz SQUARE WAVE, VDDB = 20V
INN/EN = VDDA
,
4.5
4.0
3.5
3.0
2.5
2.0
CL = 0pF
8
VDDB = 5.5V
7
6
5
4
3
2
0
200
400
600
800
1000
0
40
80
120
160
200
-50
-25
0
25
50
75
100 125
PWM FREQUENCY (kHz)
LOAD CAPACITANCE (pF)
TEMPERATURE (°C)
VDDA SUPPLY CURRENT
vs. PWM FREQUENCY
RISE TIME AND FALL TIME
vs. LOAD CAPACITANCE
RISE TIME AND FALL TIME
vs. LOAD CAPACITANCE
toc12
toc13
toc14
6.0
5.5
5.0
4.5
4.0
3.5
3.0
25
20
15
10
5
50
SERIES RESISTOR RS = 5Ω
SERIES RESISTOR RS = 0Ω
tF
40
30
20
10
0
tR
tR
tF
0
0
200
400
600
800
1000
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CAPACITANCE (nF)
LOAD CAPACITANCE (nF)
PWM FREQUENCY (kHz)
PROPAGATION DELAY
vs. TEMPERATURE
PROPAGATION DELAY
vs. TEMPERATURE
toc16
toc15
38
37
36
35
34
33
38
37
36
35
34
33
SERIES RESISTOR RS = 0Ω,
CL = 200pF, tPHL
VDDB = 6V ONLY APPLIES TO MAX22702
SERIES RESISTOR RS = 0Ω,
CL = 200pF, tPLH
VDDB = 6V ONLY APPLIES TO MAX22702
VDDB = 6V
VDDB = 6V
VDDB = 15V
VDDB = 15V
V= 20V
DDB
V=20V
DDB
V
= 36V
DDB
V
= 36V
DDB
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
│ 10
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Characteristics (continued)
(V
- V
= 5V, V
- V
= 20V, V
= V , T = +25°C, unless otherwise noted.)
SSB A
DDA
GNDA
DDB
SSB
GNDA
PART-TO-PART
PROPAGATION DELAY MATCHING
vs. VDDB SUPPLY VOLTAGE
PART-TO-PART
PROPAGATION DELAY MATCHING
vs. VDDA SUPPLY VOLTAGE
PART-TO-PART
PROPAGATION DELAY MATCHING
vs. TEMPERATURE
toc17
toc18
toc19
1.0
0.6
1.0
1.0
0.6
SERIES RESISTOR RS = 0Ω, CL = 200pF
SERIES RESISTOR RS = 0Ω, CL = 200pF,
VDDB < 13V ONLY APPLIES TO MAX22702
SERIES RESISTOR RS = 0Ω, CL = 200pF
VDDB = 20V
0.6
0.2
RISING EDGE
FALLING EDGE
FALLING EDGE
0.2
0.2
-0.2
-0.6
-1.0
-0.2
-0.6
-1.0
-0.2
-0.6
-1.0
FALLING EDGE
RISING EDGE
RISING EDGE
-50
-25
0
25
50
75
100 125
6
12
18
24
30
36
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
VDDB SUPPLY VOLTAGE (V)
VDDA SUPPLY VOLTAGE (V)
PART-TO-PART
PROPAGATION DELAY MATCHING
VDDB UVLO vs. R2
vs. LOAD CAPACITANCE
toc20
toc21
1.0
15
12
9
MAX22702, R1 = 20kΩ (SEE FIGURE 13)
SERIES RESISTOR RS = 0Ω
0.6
0.2
VDDB RISING
RISING EDGE
-0.2
-0.6
-1.0
6
VDDB FALLING
FALLING EDGE
3
0
0
40
80
120
160
200
20
40
60
80
100
120
LOAD CAPACITANCE (pF)
R2 RESISTANCE (kΩ)
PART-TO-PART
PART-TO-PART
PROPAGATION DELAY MATCHING
FALLING EDGE
PROPAGATION DELAY MATCHING
RISING EDGE
toc23
toc22
SERIES RESISTOR RS = 10Ω, CL = 200pF
SERIES RESISTOR RS = 10Ω, CL = 200pF
5V/div
5V/div
VOUT1
VOUT2
VOUT1
VOUT2
10ps/div
10ps/div
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Pin Configurations
TOP VIEW
+
+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
V
V
SSB
DDA
INP
SSB
DDA
IN
MAX22700D
MAX22700E
GNDB
OUT
GNDB
OUT
EN
INN
GNDA
GNDA
V
V
DDB
DDB
NARROW SOIC
NARROW SOIC
TOP VIEW
+
+
1
8
1
8
V
V
V
V
SSB
DDA
INP
SSB
DDA
IN
MAX22701D
MAX22701E
2
3
4
7
6
5
CLAMP
OUT
2
3
4
7
6
5
CLAMP
OUT
EN
INN
GNDA
GNDA
V
V
DDB
DDB
NARROW SOIC
NARROW SOIC
TOP VIEW
+
+
1
8
1
8
V
V
V
V
SSB
DDA
INP
SSB
DDA
IN
MAX22702D
MAX22702E
2
3
4
7
6
5
ADJ
2
3
4
7
6
5
ADJ
EN
INN
OUT
OUT
GNDA
GNDA
V
V
DDB
DDB
NARROW SOIC
NARROW SOIC
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Pin Description
PIN
MAX22700D MAX22700E MAX22701D MAX22701E MAX22702D MAX22702E
REF
SUPPLY
REF
GROUND
NAME
V
1
2
1
—
—
2
1
2
1
—
—
2
1
2
1
—
—
2
V
V
V
V
V
V
V
V
V
V
V
V
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDB
DDB
DDB
DDB
DDB
DDB
INP
INN
IN
3
3
3
—
—
4
—
—
4
—
—
4
EN
3
3
3
GNDA
4
4
4
V
5
5
5
5
5
5
V
V
V
V
V
V
DDB
SSB
SSB
SSB
SSB
SSB
SSB
OUT
GNDB
CLAMP
ADJ
6
6
6
6
6
6
7
7
—
7
—
7
—
—
7
—
—
7
—
—
8
—
—
8
—
8
—
8
V
8
8
SSB
NAME
FUNCTION
POWER
Power Supply Input for Side A (Transmitter Side). Bypass V
capacitors as close as possible to the pin.
to GNDA with 1nF || 0.1µF || 1µF ceramic
DDA
V
DDA
GNDA
Ground Reference for Side A (Transmitter Side).
Positive Power Supply Input for Side B (Driver Side). Bypass V
capacitors as close as possible to the pin. Place an additional 22µF capacitor between V
to V
with 1nF || 0.1µF || 1µF ceramic
DDB
SSB
V
DDB
and V
.
SSB
DDB
V
Negative Power Supply Input for Side B (Driver Side).
SSB
(MAX22700) Gate Driver Common Pin. Connect to the power transistor’s source pin. The B-side UVLO is
referenced to GNDB in the MAX22700 versions.
GNDB
INPUTS
Non-Inverting PWM Input on Side A (D Versions). Has a weak internal pulldown. Connect the differential PWM
control inputs to INP and INN. Refer to Table 3 for Inputs vs. Output Truth table.
INP
INN
Inverting PWM Input on Side A (D Versions). Has a weak internal pullup to V
. Connect the differential PWM
DDA
control inputs to INP and INN. Refer to Table 3 for Inputs vs. Output Truth table.
Single-Ended PWM Input on Side A (E Versions). Has a weak internal pulldown. Refer to Table 4 for Inputs vs.
Output Truth table.
IN
EN
Active-Low Enable on Side A (E Versions). Has a weak internal pullup to V
.
DDA
(MAX22702) Adjustable UVLO Input on Side B. Connect external resistors between V
tween ADJ and the power transistor’s source pin to adjust the B-side UVLO.
and ADJ and be-
DDB
ADJ
INPUT/OUTPUT
CLAMP
(MAX22701) Active Miller Clamp Input/Output on Side B. Prevents false turn-on of the power transistor.
Gate Driver Output on Side B.
OUTPUT
OUT
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Functional Diagrams
V
V
V
V
DDB
DDA
DDB
DDA
MAX22701E
MAX22701D
IN
INP
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
UVLO
AND
LOGIC
INPUTS
OUT
OUT
EN
INN
V
V
SSB
SSB
GNDA
CLAMP
GNDA
CLAMP
2V
2V
V
V
SSB
SSB
V
V
V
V
DDB
DDA
DDB
DDA
MAX22700E
MAX22702E
MAX22700D
MAX22702D
IN
INP
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
UVLO
AND
LOGIC
INPUTS
OUT
OUT
EN
INN
V
V
SSB
SSB
GNDA
GNDA
GNDB/ADJ
GNDB/ADJ
MAX22702 provides an adjustable B-side UVLO, offering
design flexibility with different types of external power
transistors.
Detailed Description
The MAX22700–MAX22702 are a family of single-chan-
nel isolated gate drivers with an ultra-high CMTI of
300kV/µs (typ). All devices have integrated digital galvan-
All devices support a minimum pulse width of 20ns with
maximum pulse-width distortion of 2ns. The part-to-part
propagation delay is matched within 2ns maximum at
+25°C ambient temperature, and is guaranteed to be
within 5ns maximum over the temperature range of -40°C
to +125°C.
ic isolation with an isolation rating of 3kV
in an 8-pin,
RMS
narrow-body SOIC package. This family of devices offers
high common-mode transient immunity, high electromag-
netic interference (EMI) immunity, and stable temperature
performance through Maxim’s proprietary process tech-
nology. The devices feature variants with output options
for gate driver common pin GNDB (MAX22700), Miller
clamp (MAX22701), and adjustable UVLO (MAX22702).
In addition, variants are offered as differential inputs INP
and INN (D versions) or single-ended input IN with enable
EN (E versions). Refer to the Ordering Information for details.
All MAX22700–MAX22702 have a default-low output. The
default is the state the output assumes when the input is
either not powered or is open-circuit. The output is set to
logic-low when side A or side B supply is in UVLO, the
device is in thermal shutdown, or EN is high (E versions).
Output Driver Stage
The MAX22700 has a gate driver common pin (GNDB)
The output driver stage of the MAX22700-MAX22702 fea-
tures a pullup structure and a pulldown structure. The pul-
lup structure consists of a PMOS transistor and a NMOS
transistor in parallel (see the Functional Diagrams). The
that is a reference ground for V
and V
. V
DDB
SSB SSB
has a voltage range between -16V and 0V with reference
to GNDB. The MAX22701 has an active Miller clamp
pin, CLAMP, which prevents false turn-on of the exter-
nal power transistor caused by the Miller current. The
PMOS transistor has a maximum R
of 4.5Ω. The
DSON
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
NMOS transistor only turns on for a short period of time
during the output low-to-high transition and provides a
boost current to enable the fast turn-on of the device. The
NMOS transistor has a much lower on-resistance than
the PMOS transistor; thus the parallel combination of the
NMOS and the PMOS enables a faster turn-on during the
output low-to-high transition.
Functional Diagrams. The two internal transistors in the
output driver are configured for push-pull operation and
feature an active pulldown function to turn off the external
power transistor when either side of the power supply is
in UVLO. This prevents the external power transistor from
falsely turning on during startup or UVLO.
INN vs. EN Function
The pulldown structure of the MAX22700–MAX22702
consists of a NMOS transistor. The NMOS transistor
in the MAX22700 and the MAX22702 has a maximum
The MAX2270_D features differential PWM inputs (INP
and INN). The differential inputs reject input glitches and
prevent false turn-on of the output. The output will hold
the previous value when a glitch is detected on either
input (Figure 5). The MAX2270_E features a single-ended
input (IN) and an active-low input enable (EN). The EN
pin allows the output (OUT) to be quickly set to logic-
low, turning off the external power transistor. The output
remains at logic-low until the PWM input (IN) receives a
logic-high signal (Figure 6).
R
of 1.25Ω, while the NMOS in the MAX22701 has
DSON
an R
of 2.5Ω. For the MAX22701, when both OUT
DSON
and CLAMP pins are connected to the gate of the exter-
nal power transistor, an additional NMOS is connected
in parallel to the pulldown NMOS transistor to prevent
false turn-on of the external power transistor by provid-
ing an additional low-impedance path to V
. Refer to
SSB
Active Miller Clamp (MAX22701 Only) section and the
Functional Diagrams for details.
Current sources are used at both A-side inputs to prevent
the output from falsely turning on by input glitches or
noise. The INN pin has a weak pullup and the INP has a
weak pulldown in the MAX2270_D devices. The EN pin
has a weak pullup and the IN pin has a weak pulldown in
the MAX2270_E devices. Refer to Table 3 and Table 4 for
the Inputs vs. Output Truth Tables.
Digital Isolation
The MAX22700–MAX22702 provide basic galvanic isola-
tion for digital signals transmitted between two ground
domains, and block high-voltage/high-current transients.
The devices withstand differences of up to 3kV
for up to
RMS
60 seconds, and up to 1200V
of continuous isolation.
PEAK
Undervoltage-Lockout (UVLO)
The devices have two supply inputs (V
and V
)
DDB
DDA
The V
and V
supplies are both internally moni-
DDA
DDB
that independently set the logic levels on either side of
the device. V and V are referenced to GNDA and
tored for undervoltage conditions. Undervoltage events
can occur during power-up, power-down, or during nor-
mal operation due to a sagging supply voltage. When
an undervoltage condition is detected on either supply,
the output is set to logic-low (default state) to turn off the
external power transistor, regardless of the state of the
MAX22700–MAX22702 inputs. The B-side UVLO has an
DDA
DDB
V , respectively. Logic input and output levels match
SSB
the supply voltages used in the associated power domain.
The difference in ground potential between the two power
domains may be as large as V
of time and will withstand surge voltages up to 5kV. Data
transfer integrity is maintained for a differential ground
potential change up to 300kV/µs (typ).
for extended periods
IOWM
internal filter to reject any V
glitches less than 32µs
DDB
(typ) (see Figure 11 and Figure 12). Figure 7 through
Figure 10 show the behavior of the outputs during power-
up and power-down.
Unidirectional Channel and Active Pulldown
The MAX22700–MAX22702 have an unidirectional chan-
nel that passes data in one direction, as indicated in the
Table 3. MAX2270_D Inputs vs. Output
Truth Table
Table 4. MAX2270_E Inputs vs. Output
Truth Table
INP
Low
Low
High
High
INN
Low
High
Low
High
OUT
Hold
Low
IN
EN
OUT
Low
Low
High
High
Low
High
Low
High
Low
Low (Default)
High
High
Hold
Low (Default)
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
H
GLITCH
INP
INN
LOGIC OUTPUT
INP
INN
INP
L
GLITCH
L
L
L
H
L
HOLD
L
H
L
INN
H
FILTERED
H
H
H
OUT
OUT
L
FILTERED
H
HOLD
(a)
(b)
H
INP
INN
INP
INN
L
S
INP
INN
LOGIC
OUTPUT
GLITCH
H
R
L
GLITCH
FILTERED
H
FILTERED
L
POR
OUT
OUT
(d)
(c)
Figure 5. MAX2270_D Differential Inputs
H
GLITCH
IN
EN
LOGIC OUTPUT
IN
IN
L
GLITCH
L
L
L
H
L
L
L
H
EN
L
EN
H
H
H
H
L
OUT
OUT
L
FILTERED
H
OUTPUT TURNS OFF
(a)
(b)
H
IN
LOGIC
OUTPUT
IN
EN
L
IN
GLITCH
H
EN
EN
L
GLITCH
H
OUT
L
FILTERED
OUT
OUTPUT TURNS OFF
(c)
(d)
Figure 6. MAX2270_E Single-Ended Input with Enable
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
VDDB POWER-UP AND POWER-DOWN
INPUT SET TO HIGH
VDDA POWER-UP AND POWER-DOWN
INPUT SET TO HIGH
fig07
fig08
EN OR INN = LOW
EN OR INN = LOW
VDDA
5V/div
VDDA
5V/div
VDDB
10V/div
VDDB
10V/div
VIN
VIN
5V/div
5V/div
VOUT
VOUT
10V/div
10V/div
400µs/div
400µs/div
Figure 7. V
Undervoltage Lockout Behavior (Input High)
Figure 8. V
Undervoltage Lockout Behavior (Input High)
DDB
DDA
VDDB POWER-UP AND POWER-DOWN
VDDA POWER-UP AND POWER-DOWN
INPUT SET TO LOW
INPUT SET TO LOW
fig09
fig10
EN OR INN = LOW
EN OR INN = LOW
VDDA
5V/div
VDDA
5V/div
VDDB
10V/div
5V/div
VDDB
10V/div
5V/div
VIN
VIN
VOUT
VOUT
10V/div
10V/div
400µs/div
400µs/div
Figure 9. V
Undervoltage Lockout Behavior (Input Low)
Figure 10. V
Undervoltage Lockout Behavior (Input Low)
DDB
DDA
VDDB GLITCH FILTER
VDDB GLITCH FILTER
fig11
fig12
EN OR INN = LOW, VDDB GLITCH 32µs
EN OR INN = LOW, VDDB GLITCH 28µs
VDDA
5V/div
VDDA
5V/div
VDDB
VDDB
10V/div
5V/div
10V/div
VIN
VIN
5V/div
VDDB UVLO IS
10V/div
VDDB UVLO IS NOT
10V/div
VOUT
VOUT
TRIGGERED
TRIGGERED
400µs/div
400µs/div
Figure 12. V
UVLO Triggered
Undervoltage Lockout Glitch Filter,
Figure 11. V
UVLO Not Triggered
Undervoltage Lockout Glitch Filter,
DDB
DDB
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Thermal Shutdown
Adjustable UVLO (MAX22702 Only)
The MAX22700–MAX22702 operate at an ambient tem-
perature up to +125°C on a properly designed multilayer
PCB. Operating at higher voltages or with heavy output
loads will increase the junction temperature and power
dissipation, and also reduce the maximum allowable
operating temperature. See the Package Information,
Absolute Maximum Ratings and Safety Limits sections
for details.
The MAX22702 features an adjustable B-side UVLO to
accommodate UVLO requirements of different types of
external power transistors. To set a user-defined B-side
UVLO, connect external resistors between V
and ADJ,
DDB
and between ADJ and the external power transistor ground
so that:
V
= 2 × (1 + R2 ÷ R1)
ADJ_UVLO
where R1 is placed between V
and ADJ, and R2 is
DDB
The MAX22700–MAX22702 will be in thermal shutdown
when the junction temperature of the device exceeds
+160°C (typ). During thermal shutdown, the output is set to
logic-low to turn off the external power transistor regardless
of the state of the MAX22700–MAX22702 inputs.
placed between ADJ and the external power transistor
ground (see Figure 13).
For example, to set the B-side UVLO to 13V, connect
20kΩ (R1) between V
and ADJ. R2 will be:
DDB
(13 ÷ 2 - 1) × 20 = 110kΩ
Active Miller Clamp (MAX22701 Only)
The MAX22701 features an active Miller clamp to prevent
false turn-on of the external power transistor caused by
the Miller current. When the external high-side transistor
is turned on after the external low-side transistor is turned
off, the internal Miller clamp transistor starts to engage
when the Miller clamp pin voltage drops below the 2V
threshold, and it provides a low-impedance path to direct
Applications Information
Power-Supply Sequencing
The MAX22700–MAX22702 do not require special power-
supply sequencing. The logic levels are set independently
on either side by V
and V
. Each supply can be
DDA
DDB
present over the entire specified range regardless of the
level or presence of the other supply.
the Miller current to V
clamp timing diagram.
. Refer to Figure 4 for a Miller
SSB
V
DDB
V
DDA
1nF 0.1µF 22µF
1nF 0.1µF 1µF
HIGH VOLTAGE
V
V
V
SSB
SSB SSB
V
V
DDB
DDA
MAX22702
INP/IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
OUT
INN/EN
V
DDB
V
SSB
GNDA
R1
R2
V
SSB
ADJ
GNDB
ARE REFERENCED TO GNDB. V
NOTE: V
DDB
AND V
SSB
- V
< 5V (TYP)
ADJ
DDB
Figure 13. Example Circuit for MAX22702 Adjustable UVLO
Maxim Integrated
│ 18
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
voltage and the data rate, and the “load current”, which
depends on the load impedance. Current into a capacitive
load is a function of the load capacitance, the switching
frequency, and the supply voltage.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass V
and V
with 1nF, 0.1µF, and 1µF
DDA
DDB
low-ESR and low-ESL ceramic capacitors with sufficient
voltage rating in parallel to GNDA and V , respectively.
I
= C × f
× V
SW DDB
SSB
CL
L
To ensure the best performance, place the decoupling
capacitors as close to the power-supply pins as possible.
where:
is the current required to drive the capacitive load.
I
CL
On the B side, it is recommended to place the 1nF and
C is the load capacitance on the output pin.
L
1µF capacitors close to the V
pin, and place the 0.1µF
SSB
f
is the switching frequency in Hz.
capacitor close to the V
pin. It is also recommended
SW
DDB
to include a 22µF reservoir capacitor (tantalum or elec-
V
is the B-side supply voltage.
DDB
trolytic type) between V
and V
in case the V
SSB DDB
DDB
The total power dissipation (P ) can be calculated as:
D
power supply is located far away from the V
pin. All
DDB
P
D
= V
× I
+ V
× I
bypass capacitors on V
a 50V voltage rating.
are required to have at least
DDA
DDA
DDB DDB
DDB
where I
B-side supply current.
is the A-side supply current and I
is the
= 5V,
DDA
DDB
Layout Considerations
Example: A MAX22701 is operating with V
V
capacitive load. V
a 10kHz data rate and a 5V supply voltage according
to Figure 14. V must supply the sum of the no load
current and the load current. The no load current is about
3.77mA with a 10kHz data rate and a 20V supply voltage
according to Figure 15. The load current is equal to 1nF ×
10kHz × 20V = 0.2mA. V
3.97mA. The total power dissipation is 5V × 4.56mA +
20V × 3.97mA = 102.2mW.
DDA
The PCB designer should follow some critical recom-
mendations in order to get the best performance from the
design.
= 20V. The output is operating at 10kHz with 1nF
DDB
must supply about 4.56mA with
DDA
● Keep the input/output traces as short as possible.
To maintain low signal-path inductance, avoid using
vias.
DDB
● Place the gate driver as close to the external power
transistor as possible to decrease the trace induc-
tance and avoid output ringing.
must therefore supply about
DDB
● Have a solid ground plane underneath the high-
speed signal layer.
Gate Driver Output Resistors
● Keep the area underneath the MAX22700–
MAX22702 free from ground and signal planes. Any
galvanic or metallic connection between side A and
side B defeats the isolation.
External series resistors (R
and R
) between the
ON
OFF
MAX22700–MAX22702 output and the gate of the power
transistor are required in gate driver applications. These
resistors control the turn-on and turn-off time of the power
transistor to optimize switching efficiency and EMI perfor-
mance.
● Have a solid ground plane next to V
pin with
SSB
multiple V
vias to reduce the parasitic inductance
SSB
and minimize the ringing on the output signal.
The R
resistance and external FET’s gate capacitance
ON
determine the turn-on time. The parallel combination of
both R and R resistance and the external FET’s
gate capacitance determine the turn-off time. Turn-off
Calculating Power Dissipation
The required current for the A side of the MAX22700–
ON
OFF
MAX22702 depends on the V
supply voltage and
DDA
time is usually much faster than turn-on time to avoid
the data rate. The required current for the B side of the
MAX22700–MAX22702 depends on the V supply
shoot-through. Figure 16 shows a typical R
and R
and R
ON
OFF
OFF
DDB
network for the MAX22700–MAX22702. R
ON
voltage, the data rate, and the load condition. The typical
current for different V and V supply voltages at any
values should be adjusted based on the required slew
rate and the external FET’s gate capacitance.
DDA
DDB
data rate without external load can be estimated from the
graphs in Figure 14 and Figure 15. Please note that the
data in Figure 14 and Figure 15 are extrapolated from sup-
ply current measurements in a typical operating condition.
The gate driver output resistors also help limit ringing caused
by parasitic inductances and capacitances due to PCB lay-
out and device package leads. Output ringing can happen
during high voltage dV/dt and high current di/dt switching.
The total current for the B side is the sum of the “no load”
current (shown in Figure 15) which is a function of the
Increasing R
and R
can help reduce the ringing.
ON
OFF
Maxim Integrated
│ 19
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
and MAX22702 as GaN gate drivers. A boost current is
required during the GaN device’s turn-on period; hence
a capacitor is placed in series with one of the resistors at
the output. This capacitor needs to be discharged during
the turn-off period. Therefore, a diode is placed in parallel
to the resistor to provide a discharge path. On the layout,
it is recommended to place the gate driver very close to
the GaN device to minimize series inductance and reduce
gate drive loop area. To prevent ringing and support high
peak currents when turning on GaN devices, good decou-
Driving GaN Transistors
The high CMTI rating of 300kV/µs (typ) and the propaga-
tion delay matching of 5ns (max) between the high-side
and low-side drivers make the MAX22701 and MAX22702
ideal to drive GaN devices. The MAX22702 also features
an adjustable B-side UVLO to accommodate the low gate
drive voltage of GaN devices.
As shown in the Typical Operating Circuits, a positive
supply (V
) and a negative supply (V
) with refer-
SSB
DDB
ence to GNDB are required to meet the gate voltage
requirement of GaN devices when using the MAX22701
pling is required on the V
and V
pins.
DDB
SSB
VDDA SUPPLY CURRENT
vs. DATA RATE
VDDB SUPPLY CURRENT
vs. DATA RATE
fig14
fig15
6
10
9
VDDB = 6V
VDDB = 13V
VDDB = 6V ONLY
APPLIES TO MAX22702
5
4
3
VDDB = 20V
VDDB = 30V
VDDB = 36V
8
7
CL = 0pF
6
VDDA = 3.3V
VDDA = 3.6V
VDDA = 5V
2
1
0
5
VDDA = 5.5V
4
3
0
200
400
600
800
1000
0
200
400
600
800
1000
DATA RATE (kHz)
DATA RATE (kHz)
Figure 14. VDDA Supply Current vs. Data Rate (typ)
Figure 15. VDDB Supply Current vs. Data Rate (typ)
V
DDB
V
DDA
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
V
V
V
SSB SSB SSB
V
V
DDB
DDA
MAX22700 – MAX22702
INP/IN
UVLO,
R
ON
UVLO
AND
LOGIC
INPUTS
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
OUT
INN/EN
R
OFF
V
SSB
GNDA
V
SSB
GNDB/CLAMP/ADJ
GNDB
Figure 16. Typical Gate Driver Output Network with R
and R
OFF
ON
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
V
DDB
DDA
MAX22700E
V
DDA
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
SiC
EN
PWML
GNDA
HIGH-SIDE
NEGATIVE SUPPLY
V
SSB
GNDA
V
SSB1
GNDB
HIGH-SIDE SUPPLY GROUND
OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
V
DDB2
1nF 0.1µF 22µF
V
V
DDB
DDA
MAX22700E
V
V
V
SSB2 SSB2 SSB2
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
OUT
SiC
EN
V
SSB
LOW-SIDE
GNDA
NEGATIVE SUPPLY
V
SSB2
GNDB
LOW-SIDE SUPPLY GROUND
Maxim Integrated
│ 21
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
V
DDB
DDA
MAX22700D
V
DDA
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
SiC
PWMH
HIGH-SIDE
NEGATIVE SUPPLY
V
SSB
GNDA
GNDA
V
SSB1
GNDB
HIGH-SIDE SUPPLY GROUND
OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
V
DDB2
1nF 0.1µF 22µF
V
V
DDB
DDA
MAX22700D
V
V
V
SSB2 SSB2 SSB2
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWML
UVLO
AND
LOGIC
INPUTS
OUT
SiC
PWML
V
SSB
LOW-SIDE
NEGATIVE SUPPLY
GNDA
V
SSB2
GNDB
LOW-SIDE SUPPLY GROUND
GNDA
Maxim Integrated
│ 22
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
V
DDB
DDA
MAX22701E
V
DDA
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
SiC
EN
PWML
GNDA
V
SSB
GNDA
CLAMP
2V
V
SSB
HIGH-SIDE
NEGATIVE SUPPLY
V
SSB1
OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
V
DDB2
1nF 0.1µF 22µF
V
V
DDB
DDA
MAX22701E
V
V
V
SSB2 SSB2 SSB2
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
OUT
SiC
EN
V
SSB
GNDA
CLAMP
2V
GNDA
V
SSB
LOW-SIDE
NEGATIVE SUPPLY
V
SSB2
Maxim Integrated
│ 23
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
V
DDB
DDA
MAX22701D
V
DDA
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
SiC
PWMH
V
SSB
GNDA
GNDA
CLAMP
2V
V
SSB
HIGH-SIDE
NEGATIVE SUPPLY
V
SSB1
OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
V
DDB2
1nF 0.1µF 22µF
V
V
DDB
DDA
MAX22701D
V
V
V
SSB2 SSB2 SSB2
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWML
UVLO
AND
LOGIC
INPUTS
OUT
SiC
PWML
V
SSB
GNDA
CLAMP
2V
GNDA
V
SSB
LOW-SIDE
NEGATIVE SUPPLY
V
SSB2
Maxim Integrated
│ 24
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
V
DDB
DDA
MAX22702E
V
DDA
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
SiC
EN
V
DDB1
PWML
GNDA
V
HIGH-SIDE
NEGATIVE
SUPPLY
SSB
GNDA
R1
R2
V
SSB1
ADJ
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
OUTPUT
V
DDB2
GNDB1
1nF 0.1µF 22µF
V
V
DDB
DDA
MAX22702E
V
V
V
SSB2 SSB2 SSB2
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
OUT
SiC
EN
V
DDB2
V
SSB
LOW-SIDE
NEGATIVE
SUPPLY
GNDA
R1
R2
V
SSB2
ADJ
GNDA
GNDB2
ARE REFERENCED TO GNDB. V
NOTE: V
AND V
- V
< 5V (TYP)
ADJ
DDB
SSB
DDB
Maxim Integrated
│ 25
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
V
DDB
DDA
MAX22702D
V
DDA
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
SiC
V
DDB1
PWMH
V
SSB
HIGH-SIDE
NEGATIVE
SUPPLY
GNDA
R1
R2
GNDA
V
SSB1
ADJ
1nF 0.1µF 1µF
OUTPUT
LOW-SIDE POSITIVE SUPPLY
V
DDB2
GNDB1
1nF 0.1µF 22µF
V
V
DDB
DDA
MAX22702D
V
V
V
SSB2 SSB2 SSB2
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWML
UVLO
AND
LOGIC
INPUTS
OUT
SiC
V
DDB2
PWML
V
SSB
LOW-SIDE
NEGATIVE
SUPPLY
GNDA
R1
R2
V
SSB2
ADJ
GNDA
GNDB2
ARE REFERENCED TO GNDB. V
NOTE: V
AND V
- V
< 5V (TYP)
ADJ
DDB
SSB
DDB
Maxim Integrated
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
V
DDB
DDA
MAX22701D
V
DDA
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
GaN
(PANASONIC)
PWMH
GNDB1
V
SSB
HIGH-SIDE
COMMON
GROUND
GNDA
GNDA
CLAMP
2V
V
SSB
HIGH-SIDE
NEGATIVE SUPPLY
V
SSB1
OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
V
DDB2
1nF 0.1µF 1µF
V
V
DDB
DDA
MAX22701D
V
V
V
SSB2 SSB2 SSB2
INP
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWML
UVLO
AND
LOGIC
INPUTS
OUT
GaN
(PANASONIC)
PWML
GNDB2
V
SSB
LOW-SIDE
COMMON
GROUND
GNDA
GNDA
CLAMP
2V
V
SSB
LOW-SIDE
NEGATIVE SUPPLY
V
SSB2
MAX22701D AS GaN GATE DRIVER
Maxim Integrated
│ 27
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
V
DDB1
1nF 0.1µF 1µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
V
V
V
SSB1 SSB1 SSB1
V
DDA
V
DDB
MAX22702E
V
DDA
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
PWMH
UVLO
AND
LOGIC
INPUTS
OUT
GaN
EN
PWML
GNDA
V
DDB1
GNDB1
V
SSB
HIGH-SIDE
NEGATIVE
SUPPLY
HIGH-SIDE
COMMON
GROUND
GNDA
V
SSB1
ADJ
LOW-SIDE POSITIVE SUPPLY
OUTPUT
1nF 0.1µF 1µF
V
DDB2
GNDB1
1nF 0.1µF 1µF
V
V
DDB
DDA
MAX22702E
V
V
V
SSB2 SSB2 SSB2
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
OUT
GaN
EN
V
DDB2
GNDB2
V
SSB
LOW-SIDE
NEGATIVE
SUPPLY
LOW-SIDE
COMMON
GROUND
GNDA
V
SSB2
ADJ
GNDA
MAX22702E AS GaN GATE DRIVER
GNDB2
NOTE: V
AND V
ARE REFERENCED TO GNDB. V
- V
< 5V (TYP)
ADJ
DDB
SSB
DDB
Maxim Integrated
│ 28
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Ordering Information
ISOLATION
VOLTAGE
TEMP
RANGE
(°C)
LOW-SIDE
PART NUMBER
INPUTS
PIN 7
UVLO
PIN-PACKAGE
R
(Ω)
DSON
1.25
1.25
2.5
(ꢀV
)
RMS
Differential,
INP and INN
MAX22700DASA+*
MAX22700EASA+*
MAX22701DASA+*
MAX22701EASA+
MAX22702DASA+*
MAX22702EASA+*
GNDB
GNDB
CLAMP
CLAMP
ADJ
13V to GNDB
13V to GNDB
3
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Narrow SOIC
8 Narrow SOIC
8 Narrow SOIC
8 Narrow SOIC
8 Narrow SOIC
8 Narrow SOIC
Single ended,
IN and EN
3
3
3
3
3
Differential,
INP and INN
13V to V
13V to V
SSB
SSB
Single ended,
IN and EN
2.5
Differential,
INP and INN
Adjustable
Adjustable
1.25
1.25
Single ended,
IN and EN
ADJ
*Future product—contact factory for availability.
+Denotes a lead (Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
Maxim Integrated
│ 29
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MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
7/19
Initial release
—
Updated the Absolute Maximum Ratings and Package Information sections, Table
2, and Figure 1
1
2
8/19
9/19
2, 7
1, 4
Updated the General Description, Benefits and Features, DC Electrical Charac-
teristics, and Dynamic Characteristics sections
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 30
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