MAX2769BETI/V+_技术文档

19-5875; Rev 1; 8/11

E V A L U A T I O N K I T A V A I L A B L E

MAX2769B

Universal GPS Receiver

General Description

Features

The MAX2769B is a next-generation Global Navigation

SatelliteSystem(GNSS)receivercoveringGPS,GLONASS,

Galileo, and Compass navigation satellite systems on

a single chip. This single-conversion GNSS receiver is

designed to provide high performance for industrial and

automotive applications.

S AEC-Q100 Automotive Qualified

S GPS/GLONASS/Galileo/Compass Systems

S 40pF Output Clock Drive Capability

S No External IF SAW or Discrete Filters Required

S Programmable IF Frequency

Designed on Maxim’s advanced, low-power SiGe BiCMOS

process technology, the MAX2769B offers the highest

performance and integration at a low cost. Incorporated

on the chip is the complete receiver chain, including a

dual-input LNA and mixer, followed by the image-rejected

filter, PGA, VCO, fractional-N frequency synthesizer,

crystal oscillator, and a multibit ADC. The total cascaded

noise figure of this receiver is as low as 1.4dB.

S Fractional-N Synthesizer with Integrated VCO

Supports Wide Range of Reference Frequencies

S Dual-Input Uncommitted LNA for Separate Passive

and Active Antenna Inputs

S 1.4dB Cascade Noise Figure

S Integrated Crystal Oscillator

S Integrated Active Antenna Sensor

S 2.7V to 3.3V Supply Voltage

The MAX2769B completely eliminates the need for exter-

nal IF filters by implementing on-chip monolithic filters

and requires only a few external components to form a

complete low-cost GPS RF receiver solution.

S Small, 28-Pin, RoHS-Compliant, Thin QFN Lead-

Free Package (5mm x 5mm)

The MAX2769B is the most flexible receiver on the mar-

ket. The integrated delta-sigma fractional-N frequency

synthesizer allows programming of the IF frequency

Ordering Information appears at end of data sheet.

within a ±±30z (f

= ±2M0z) accuracy while operat-

XTAL

Block Diagram

ing with any reference or crystal frequencies that are

available in the host system. The ADC outputs CMOS

logic levels with 1 or 2 quantized bits for both I and Q

channels, or up to ± quantized bits for the I channel. I and

Q analog outputs are also available.

21

20

19

18

17

16

15

The MAX2769B is packaged in a 5mm x 5mm, 28-pin thin

QFN package with an exposed paddle.

14

13

12

11

10

9

V

N.C.

22

23

CCD

V

CC_IF

CC_CP

Applications

MAX2769B

Automotive Navigation Systems

Location-Enabled Mobile 0andsets

PNDs (Personal Navigation Devices)

CPOUT

IDLE 24

FILTER

V

LNA2

25

CC_VCO

VCO

LNA2

LNA1

Telematics (Asset Tracking, Inventory

Management)

PGM 26

CS

Marine/Avionics Navigation

Software GPS

LNA1

N.C.

27

28

SCLK

SDATA

8

Laptops and Netbooks

+

1

2

3

4

5

6

7

For related parts and recommended products to use with this part,

refer to www.maxim-ic.com/MAX2769B.related.

�� Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

MAX2769B

Universal GPS Receiver

ABSOLUTE MAXIMUM RATINGS

CC_

Other Pins Except LNA_, MIXIN, XTAL, and LNAOUT to

Ground............................. -3.±V to +(Operating V

V

to Ground....................................................-3.±V to +4.2V

Operating Temperature Range.......................... -43NC to +85NC

Junction Temperature .....................................................+153NC

Storage Temperature Range............................ -65NC to +153NC

Lead Temperature (soldering, 13s) ................................+±33NC

Soldering Temperature (reflow) ......................................+263NC

+ 3.±V)

CC_

Maximum RF Input Power.............................................+15dBm

Continuous Power Dissipation (T = +73NC)

A

TQFN (derates 27mW/NC above +73NC) ...................2533mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-

tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

CAUTION! ESD SENSITIVE DEVICE

DC ELECTRICAL CHARACTERISTICS

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43NC to +85NC, PGM = Ground. Registers are set to the default power-up states. Typical

CC_

A

values are at V

= 2.85V and T = +25NC, unless otherwise noted.) (Note 1)

CC_

A

PARAMETER

Supply Voltage

CONDITIONS

MIN

2.7

18

TYP

2.85

27

MAX

±.±

UNITS

V

Default mode, LNA1 is active (Note 2)

Default mode, LNA2 is active (Note 2)

Idle ModeK, IDLE = low, SHDN = high

Shutdown mode, SHDN = low

±1

15

25

±3.5

mA

Supply Current

5

233

FA

Voltage Drop at ANTBIAS from

Sourcing 23mA at ANTBIAS

ANTBIAS is shorted to ground

3.2

V

CC_RF

Short-Circuit Protection Current at

ANTBIAS

57

mA

Active Antenna Detection Current To assert logic-high at ANTFLAG

1.1

DIGITAL INPUT AND OUTPUT

Digital Input Logic-0igh

Digital Input Logic-Low

1.5

V

Measure at the SHDN pin

3.4

Idle Mode is a trademark of Maxim Integrated Products, Inc.

�� Maxim Integrated Products

2

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.

MAX2769B

Universal GPS Receiver

AC ELECTRICAL CHARACTERISTICS*

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

A

input is driven from a 53I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set

to 51dB gain by serial-interface word GAININ = 111313. Maximum IF output load is not to exceed 13kI||7.5pF on each pin. Typical

values are at V

= 2.85V and T = +25NC, unless otherwise noted.) (Note 1)

A

CC_

PARAMETER

CASCADED RF PERFORMANCE

RF Frequency

CONDITIONS

MIN

TYP

MAX

UNITS

M0z

dB

L1 band

1575.42

1.4

LNA1 input active, default mode (Note ±)

LNA2 input active, default mode (Note ±)

Measured at the mixer input

Noise Figure

2.7

13.±

Out-of-Band ±rd-Order Input

Intercept Point

Measured at the mixer input (Note 4)

Measured at the mixer input

-7

dBm

In-Band Mixer Input Referred 1dB

Compression Point

-85

Mixer Input Return Loss

Image Rejection

13

25

dB

LO leakage

-131

-13±

96

Spurs at LNA1 Input

dBm

Reference harmonics leakage

Measured from the mixer to the baseband analog output

Maximum Voltage Gain

Variable Gain Range

FILTER RESPONSE

91

55

13±

dB

59

FBW = 33

4

Passband Center Frequency

Passband ±dB Bandwidth

FBW = 13

M0z

FBW = 31

9.27

2.5

4.2

9.66

9

FBW = 33

FBW = 13

FBW = 31

Lowpass ±dB Bandwidth

Stopband Attenuation

FBW = 11

M0z

dB

±rd-order filter, bandwidth = 2.5M0z, measured at 4M0z offset

5th-order filter, bandwidth = 2.5M0z, measured at 4M0z offset

±3

43

49.5

LNA

LNA1 INPUT

Power Gain

Noise Figure

Input IP±

19

3.8±

-1.1

13

dB

(Note 5)

dBm

dB

Output Return Loss

Intput Return Loss

8

dB

�� Maxim Integrated Products

3

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.

MAX2769B

Universal GPS Receiver

AC ELECTRICAL CHARACTERISTICS* (continued)

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

A

input is driven from a 53I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set

to 51dB gain by serial-interface word GAININ = 111313. Maximum IF output load is not to exceed 13kI||7.5pF on each pin. Typical

values are at V

= 2.85V and T = +25NC, unless otherwise noted.) (Note 1)

A

CC_

PARAMETER

LNA2 INPUT

CONDITIONS

MIN

TYP

MAX

UNITS

Power Gain

1±

1.14

1

dB

Noise Figure

Input IP±

(Note 5)

3.2V < V

dBm

dB

Output Return Loss

Input Return Loss

FREQUENCY SYNTHESIZER

19

11

dB

LO Frequency Range

< (V

- 3.±V)

1553

1613

M0z

TUNE

CC_

LO Tuning Gain

57

M0z/V

M0z

—

Reference Input Frequency

Main Divider Ratio

8

±6

1

44

±2,767

132±

Reference Divider Ratio

—

ICP = 3

ICP = 1

3.5

1

Charge-Pump Current

mA

TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER

Frequency Range

8

2

±2

M0z

V

Output Logic-Level 0igh (V

)

With respect to ground, I

= 13FA (DC-coupled)

O0

Output Logic-Level Low (V

)

With respect to ground, I = 13FA (DC-coupled)

3.8

V

OL

Capacitive Slew Current

Output Load

11

mA

kI||pF

Load = 13kW + 43pF, f

= ±2M0z

CLKOUT

13||43

Reference Input Level

Sine wave

/4, /2, /1

(x2, max input frequency of 16M0z)

3.5

÷4

V

P-P

Clock Output Multiply/Divide

Range

x2

—

ADC

ADC Differential Nonlinearity

ADC Integral Nonlinearity

AGC enabled, ±-bit output

Q3.1

LSB

Note 1: MAX2769B is production tested at T = +25NC and +85NC. All min/max specifications are guaranteed by design and char-

A

acterization from -43NC to +85NC, unless otherwise noted. Default register settings are not production tested or guaran-

teed. User must program the registers upon power-up.

Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an

active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically dis-

abled and LNA2 becomes active. PLL is in an integer-N mode with f

= f

/16 = 1.32±M0z and ICP = 3.5mA. The

COMP

TCXO

complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4M0z and bandwidth of 2.5M0z.

Output data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.

Note 3: The LNA output connects to the mixer input without a SAW filter between them.

Note 4: Two tones are located at 12M0z and 24M0z offset frequencies from the GPS center frequency of 1575.42M0z at -63dBm/

tone. Passive pole at the mixer output is programmed to be 1±M0z.

Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12M0z and 24M0z offset frequencies from the

GPS center frequency of 1575.42M0z at -63dBm per tone.

�� Maxim Integrated Products

4

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

A

CC_

input is driven from a 53I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set

to 51dB gain by serial-interface word GAININ = 111313. Maximum IF output load is not to exceed 13kI||7.5pF on each pin. Typical

values are at V

= 2.85V and T = +25NC, unless otherwise noted.)

CC_

A

CASCADED GAIN AND NOISE FIGURE

CASCADED RECEIVER GAIN

vs. PGA GAIN CODE

LNA1 |S21| AND |S12|

vs. FREQUENCY

vs. TEMPERATURE

MAX2769B toc02

120

100

80

2.0

1.5

1.0

0.5

0

40

30

120

115

110

105

100

95

|S21|

T = -40°C

A

20

AGC GAIN

10

T = +25°C

A

0

NOISE FIGURE

-10

-20

-30

-40

-50

|S12|

T = +85°C

A

60

40

90

0

5

10 15 20 25 30 35 40 45 50 55 60 65

PGA GAIN CODE (DECIMAL FORMAT)

-40

-15

10

35

60

85

0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50

FREQUENCY (GHz)

TEMPERATURE (°C)

LNA1 GAIN AND NOISE FIGURE

vs. TEMPERATURE

LNA1 GAIN AND NOISE FIGURE

vs. LNA1 BIAS DIGITAL CODE

LNA1 INPUT 1dB COMPRESSION POINT

vs. LNA1 BIAS DIGITAL CODE

MAX2769B toc04

MAX2769B toc05

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

25

20

15

10

5

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

5.0

2.5

19.6

19.4

19.2

19.0

18.8

18.6

18.4

18.2

18.0

17.8

LNA BIAS = 1000

GAIN

0

-2.5

-5.0

-7.5

-10.0

-12.5

-15.0

NOISE FIGURE

GAIN

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

-40

-15

10

35

60

85

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

LNA BIAS DIGITAL CODE (DECIMAL)

TEMPERATURE (°C)

LNA BIAS DIGITAL CODE (DECIMAL)

�� Maxim Integrated Products

5

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

A

CC_

input is driven from a 53I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set

to 51dB gain by serial-interface word GAININ = 111313. Maximum IF output load is not to exceed 13kI||7.5pF on each pin. Typical

values are at V

= 2.85V and T = +25NC, unless otherwise noted.)

CC_

A

LNA INPUT RETURN LOSS

vs. FREQUENCY

LNA2 |S21| AND |S12|

vs. FREQUENCY

LNA2 GAIN AND NOISE FIGURE

vs. TEMPERATURE

MAX2769B toc08

30

20

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

-10

-20

-30

-40

-50

13.6

13.4

13.2

13.0

12.8

12.6

12.4

12.2

LNA BIAS = 10

|S21|

LNA1

10

0

|S12|

-10

-20

-30

-40

-50

NOISE FIGURE

LNA2

GAIN

35

0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50

FREQUENCY (GHz)

-40

-15

10

60

85

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2

FREQUENCY (GHz)

TEMPERATURE (°C)

LNA OUTPUT RETURN LOSS

MIXER INPUT REFERRED IP1dB

vs. OFFSET FREQUENCY

vs. FREQUENCY

0

PGA GAIN = 32dB

-10

-20

-30

-40

-50

-60

-70

-80

-90

-5

PGA GAIN = 51dB

LNA1

-10

-15

LNA2

P

= -100dBm

RF

-20

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2

FREQUENCY (GHz)

0

50

100

150

200

250

300

OFFSET FREQUENCY (MHz)

�� Maxim Integrated Products

6

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

A

CC_

input is driven from a 53I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set

to 51dB gain by serial-interface word GAININ = 111313. Maximum IF output load is not to exceed 13kI||7.5pF on each pin. Typical

values are at V

= 2.85V and T = +25NC, unless otherwise noted.)

CC_

A

MIXER INPUT REFERRED NOISE FIGURE

vs. PGA GAIN

1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY

MAX2769B toc12a

MAX2769B toc12b

0

-5

16

14

12

10

8

-10

-15

-20

6

800

825

850

875

900

925

950

1800 1850 1900 1950 2000 2050 2100

5

15

25

35

45

55

65

JAMMER FREQUENCY (MHz)

PGA GAIN (dB)

3RD-ORDER POLYPHASE FILTER MAGNITUDE

RESPONSE vs. BASEBAND FREQUENCY

5TH-ORDER POLYPHASE FILTER MAGNITUDE

RESPONSE vs. BASEBAND FREQUENCY

MIXER INPUT REFERRED GAIN

vs. PGA GAIN CODE

10

100

80

60

40

20

FBW = 00b

0

-10

-20

-30

-40

-50

-60

-70

0

-10

-20

-30

-40

-50

-60

T = -40°C

A

T = +25°C

A

T = +85°C

A

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

0

5

10 15 20 25 30 35 40 45 50 55 60 65

PGA GAIN CODE (DECIMAL FORMAT)

BASEBAND FREQUENCY (MHz)

�� Maxim Integrated Products

7

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

A

CC_

input is driven from a 53I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set

to 51dB gain by serial-interface word GAININ = 111313. Maximum IF output load is not to exceed 13kI||7.5pF on each pin. Typical

values are at V

= 2.85V and T = +25NC, unless otherwise noted.)

CC_

A

3RD-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 01)

5TH-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 01)

3RD-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 10)

10

0

10

0

10

0

-10

-20

-30

-40

-50

-60

-10

-20

-30

-40

-50

-60

-10

-20

-30

-40

-50

-60

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

FREQUENCY (MHz)

5TH-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 10)

2-BIT ADC TRANSFER CURVE

3-BIT ADC TRANSFER CURVE

10

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

7

6

5

4

3

2

1

0

-10

-20

-30

-40

-50

-60

-0.5

0

2

4

6

8

10 12 14 16 18 20

-1.0 -0.8 -0.6 -0.4 -0.2

0

0.2 0.4 0.6 0.8 1.0

-1.0 -0.8 -0.6 -0.4 -0.2

0

0.2 0.4 0.6 0.8 1.0

FREQUENCY (MHz)

DIFFERENTIAL VOLTAGE (V)

�� Maxim Integrated Products

8

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to ±.±V, T = -43°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

A

CC_

input is driven from a 53I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set

to 51dB gain by serial-interface word GAININ = 111313. Maximum IF output load is not to exceed 13kI||7.5pF on each pin. Typical

values are at V

= 2.85V and T = +25NC, unless otherwise noted.)

CC_

A

CRYSTAL OSCILLATOR FREQUENCY

vs. DIGITAL TUNING CODE

DIGITAL OUTPUT CMOS LOGIC

DIGITAL OUTPUT DIFFERENTIAL LOGIC

MAX2769B toc23

MAX2769B toc24

16,368.10

16,368.05

16,368.00

16,367.95

16,367.90

16,367.85

CLK

2V/div

CLK

1V/div

T = +25°C

A

SIGN DATA

2V/div

SIGN+

1V/div

T = -40°C

A

MAGNITUDE

DATA

2V/div

SIGN-

1V/div

T = +85°C

A

20ns/div

40ns/div

0

4

8

12 16 20 24 28 32

DIGITAL TUNING CODE (DECIMAL)

CRYSTAL OSCILLATOR FREQUENCY

VARIATION vs. TEMPERATURE

TEMPERATURE SENSOR VOLTAGE

vs. TEMPERATURE

CLOCK OUTPUT DRIVER WITH

40pF LOAD

MAX2769B toc28

10

8

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

6

4

2

0

-2

-4

-6

-8

-10

20ns/div

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

�� Maxim Integrated Products

9

MAX2769B

Universal GPS Receiver

Typical Application Circuit

BASEBAND

OUTPUT

C11

C10

C7

TOP VIEW

C6

C5

21

20

19

18

17

16

15

V

CCD

14

N.C.

22

23

24

25

26

27

28

C8

CC_CP

V

CC_IF

13

12

11

10

9

MAX2769B

CPOUT

IDLE

C1

C2

C9

C0

FILTER

V

LNA2

PGM

CC_VCO

VCO

LNA2

LNA1

C4

CS

LNA1

N.C.

SERIAL

INPUT

SCLK

SDATA

8

+

1

2

3

4

5

6

7

C3

C13

ACTIVE

ANTENNA BIAS

C12

Table 1. Component List

DESIGNATION

C3, C9

C1

QUANTITY

DESCRIPTION

2

1

6

2

1

3.47nF AC-coupling capacitors

27pF PLL loop filter capacitor

3.47nF PLL loop filter capacitor

C2

C±–C8

C13, C11

C12

3.1FF supply voltage bypass capacitor

13nF AC-coupling capacitor

3.47nF AC-coupling capacitor

3.1nF supply voltage bypass capacitor

23kIPLL loop filter resistor

C1±

R1

�� Maxim Integrated Products 10

MAX2769B

Universal GPS Receiver

Pin Configuration

TOP VIEW

21 20 19 18 17 16 15

14

13

N.C. 22

23

V

CCD

V

CC_CP

CC_IF

IDLE

LNA2

PGM

LNA1

N.C.

12 CPOUT

24

25

26

27

28

V

11

10

9

CC_VCO

MAX2769B

CS

SCLK

SDATA

EP

+

8

1

2

3

4

5

6

7

TQFN

Pin Description

NAME

FUNCTION

Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the

ANTBIAS pin.

1

ANTFLAG

2

±

LNAOUT

ANTBIAS

LNA Output. The LNA output is internally matched to 53I.

Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna.

RF Section Supply Voltage. Bypass to ground with 133nF and 133pF capacitors in parallel as close

as possible to the pin.

4

V

CC_RF

5

6

7

8

MIXIN

LD

Mixer Input. The mixer input is internally matched to 53I.

Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked.

Operation Control Logic Input. A logic-low shuts off the entire device.

Data Digital Input of ±-Wire Serial Interface

SHDN

SDATA

Clock Digital Input of ±-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising

edge of the SCLK.

9

SCLK

�� Maxim Integrated Products 11

MAX2769B

Universal GPS Receiver

Pin Description (continued)

13

NAME

CS

FUNCTION

Chip-Select Logic Input of ±-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS

high when the loading action is completed.

11

V

VCO Supply Voltage. Bypass to ground with a 133nF capacitor as close as possible to the pin.

CC_VCO

Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and

C (see the Typical Application Circuit).

12

CPOUT

PLL Charge-Pump Supply Voltage. Bypass to ground with a 133nF capacitor as close as possible to

the pin.

1±

14

V

CC_CP

Digital Circuitry Supply Voltage. Bypass to ground with a 133nF capacitor as close as possible to the

pin.

V

CCD

15

16

17

18

19

23

21

22

2±

XTAL

CLKOUT

Q1

XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used.

Reference Clock Output

Q-Channel Voltage Outputs. Bits 3 and 1 of the Q-channel ADC output or analog differential voltage

output.

Q3

V

ADC Supply Voltage. Bypass to ground with a 133nF capacitor as close as possible to the pin.

CC_ADC

I3

I-Channel Voltage Outputs. Bits 3 and 1 of the I-channel ADC output or analog differential voltage

output.

I1

N.C.

No Connection. Leave this pin unconnected.

V

IF Section Supply Voltage. Bypass to ground with a 133nF capacitor as close as possible to the pin.

CC_IF

Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is

active, and all other blocks are off.

24

25

IDLE

LNA2

LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 53I.

Logic Input. Connect to ground to use the serial interface. A logic-high allows programming to 8

hard-coded by device states connecting SDATA, CS, and SCLK to supply or ground according to

Table ±.

26

PGM

LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 53I(see

the Typical Application Circuit).

27

28

—

LNA1

N.C.

EP

No connection. Leave this pin open.

Exposed Pad. Ultra-low-inductance connection to ground. Place several vias to the PCB ground

plane.

�� Maxim Integrated Products 12

MAX2769B

Universal GPS Receiver

Detailed Description

Integrated Active Antenna Sensor

The MAX2769B includes a low-dropout switch to bias an

external active antenna. To activate the antenna switch

output, set ANTEN in the Configuration 1 register to logic

1. This closes the switch that connects the antenna bias

BASEBAND

CLOCK

CLKOUT

16

10nF

pin to V

to achieve a low 233mV dropout for a

CC_RF

MAX2769B

23mA load current. A logic-low in ANTEN disables the

antenna bias. The active antenna circuit also features

short-circuit protection to prevent the output from being

shorted to ground.

XTAL

15

23pF

Low-Noise Amplifier (LNA)

The MAX2769B integrates two low-noise amplifiers.

LNA1 is typically used with a passive antenna. This LNA

requires an AC-coupling capacitor. In the default mode,

the bias current is set to 4mA, the typical noise figure and

IIP± are approximately 3.8dB and -1.1dBm, respectively.

LNA2 is typically used with an active antenna. The LNA2

is internally matched to 53. and requires a DC-blocking

capacitor. Bits LNAMODE in the Configuration 1 register

control the modes of the two LNAs. See Table 6 and

Table 7 for the LNA mode settings.

Figure 1. Schematic of the Crystal Oscillator in the MAX2679B

EV Kit

operates by counting the number of magnitude bits over

512 ADC clock cycles and comparing the magnitude bit

count to the reference value provided through a control

word (GAINREF). The desired magnitude bit density is

expressed as a value of GAINREF in a decimal format

divided by the counter length of 512. For example, to

achieve the magnitude bit density of ±±%, which is opti-

mal for a 2-bit converter, program the GAINREF to 173,

so that 173/512 = ±±%.

Mixer

The MAX2769B includes a quadrature mixer to output

low-IF or zero IF I and Q signals. The quadrature mixer

is internally matched to 53I and requires a low-side LO

injection. The output of the LNA and the input of the mixer

are brought off-chip to facilitate the use of a SAW filter.

Baseband Filter

The baseband filter of the receiver can be programmed

to be a lowpass filter or a complex bandpass filter.

The lowpass filter can be configured as a ±rd-order

Butterworth filter for a reduced group delay by setting

bit F±OR5 in the Configuration 1 register to be 1 or a

5th-order Butterworth filter for a steeper out-of-band

rejection by setting the same bit to be 3. The two-sided

±dB corner bandwidth can be selected to be 2.5M0z,

4.2M0z, 9.66M0z, or by programming bits FBW in the

Configuration 1 register. When the complex filter is

enabled by changing bit FCENX in the Configuration 1

register to 1, the lowpass filter becomes a bandpass

filter and the center frequency can be programmed by

bits FCEN and FCENMSB in the Configuration 1 register.

Programmable Gain Amplifier (PGA)

The MAX2769B integrates a baseband programmable

gain amplifier that provides 59dB of gain control range.

The PGA gain can be programmed through the serial

interface by setting bits GAININ in the Configuration

± register. Set bits 12 and 11 (AGCMODE) in the

Configuration 2 register to 13 to control the gain of the

PGA directly from the ±-wire interface.

Automatic Gain Control (AGC)

The MAX2769B provides a control loop that automatically

programs PGA gain to provide the ADC with an input

power that optimally fills the converter and establishes a

desired magnitude bit density at its output. An algorithm

�� Maxim Integrated Products 13

MAX2769B

Universal GPS Receiver

Table 2. Output Data Format

SIGN/MAGNITUDE

UNSIGNED BINARY

TWO’S COMPLEMENT BINARY

INTEGER

VALUE

1b

3

2b

31

33

13

11

±b

1b

1

2b

11

13

31

33

±b

1b

3

2b

31

33

11

13

±b

7

5

311

313

331

333

133

131

113

111

113

131

113

311

313

331

333

311

313

331

333

111

113

131

133

3

1

3

±

3

1

3

1

3

1

3

-1

-±

-5

-7

1

3

1

3

1

3

1

3

1

Integer Divider = 78(d) = 333 333 3133 1113 (binary)

Synthesizer

The MAX2769B integrates a 23-bit sigma-delta fractional-

N synthesizer allowing the device to tune to a required

VCO frequency with an accuracy of approximately

Q±30z. The synthesizer includes a 13-bit reference

divider with a divisor range programmable from 1 to

132±, a 15-bit integer portion main divider with a divisor

range programmable from ±6 to ±2767, and also a 23-bit

fractional portion main divider. The reference divider is

programmable by bits RDIV in the PLL integer division

ratio register (see Table 11), and can accommodate ref-

erence frequencies from 8M0z to ±2M0z. The reference

divider needs to be set so the comparison frequency falls

between 3.35M0z to ±2M0z.

Fractional Divider = 3.771 x 223 = 838452 (decimal) =

1133 3131 3113 3333 3133

In the fractional mode, the synthesizer should not be

operated with integer division ratios greater than 251.

Crystal Oscillator

The MAX2769B includes an on-chip crystal oscillator. A

parallel mode crystal is required when the crystal oscilla-

tor is being used. It is recommended that an AC-coupling

capacitor be used in series with the crystal and the XTAL

pin to optimize the desired load capacitance and to

center the crystal-oscillator frequency. Take the para-

sitic loss of interconnect traces on the PCB into account

when optimizing the load capacitance. For example, the

MAX2769B EV kit utilizes a 16.±68M0z crystal that is

designed for a 12pF load capacitance. A series capaci-

tor of 2±pF is used to center the crystal oscillator frequen-

cy, see Figure 1. In addition, the 5-bit serial-interface

word, XTALCAP in the PLL Configuration register, can

be used to vary the crystal-oscillator frequency electroni-

cally. The range of the electronic adjustment depends on

how much the chosen crystal frequency can be pulled

by the varying capacitor. The frequency of the crystal

oscillator used on the MAX2769B EV kit has a range of

approximately 2330z.

The PLL loop filter is the only external block of the syn-

thesizer. A typical PLL filter is a classic C-R-C network

at the charge-pump output. The charge-pump output

sink and source current is 3.5mA by default, and the

LO tuning gain is 57M0z/V. As an example, see the

Typical Application Circuit for the recommended loop-

filter component values for f

bandwidth = 53k0z.

= 1.32±M0z and loop

COMP

The desired integer and fractional divider ratios can be

calculated by dividing the LO frequency (f ) by f

.

COMP

LO

f

can be calculated by dividing the TCXO frequency

COMP

(f ) by the reference division ratio (RDIV). For exam-

TCXO

The MAX2769B provides a reference clock output. The

frequency of the clock can be adjusted to crystal-oscilla-

tor frequency, a quarter of the oscillator frequency, a half

ple, let the TCXO frequency be 23M0z, RDIV be 1, and

the nominal LO frequency be 1575.42M0z. The following

method can be used when calculating divider ratios sup-

porting various reference and comparison frequencies:

of the oscillator frequency (f

P 16M0z), or twice the

XTAL

oscillator frequency, by programming bits REFDIV in the

PLL Configuration register.

f

23M0z

1

TCXO

Comparison Frequency =

=

= 23M0z

RDIV

f

1575.42M0z

23M0z

LO

LOFrequencyDivider =

=

= 78.771

f

COMP

�� Maxim Integrated Products 14

MAX2769B

Universal GPS Receiver

data mapping. The variable T = 1 designates the location

of the magnitude threshold for the 2-bit case.

ADC

The MAX2769B features an on-chip ADC to digitize the

downconverted GPS signal. The maximum sampling

rate of the ADC is approximately 53Msps. The sampled

output is provided in a 2-bit format (1-bit magnitude and

1-bit sign) by default and also can be configured as a

1-bit or 2-bit in both I and Q channels, or 1-bit, 2-bit, or

±-bit in the I channel only. The ADC supports the digital

outputs in three different formats: the unsigned binary,

the sign and magnitude, or the two’s complement format

by setting bits FORMAT in Configuration register 2. MSB

bits are output at I1 or Q1 pins and LSB bits are output at

I3 or Q3 pins, for I or Q channel, respectively. In the case

of ±-bit, output data format is selected in the I channel

only, the MSB is output at I1, the second bit is at I3, and

the LSB is at Q1.

ADC Fractional Clock Divider

A 12-bit fractional clock divider is located in the clock

path prior to the ADC and can be used to generate the

ADC clock that is a fraction of the reference input clock.

In a fractional divider mode, the instantaneous division

ratio alternates between integer division ratios to achieve

the required fraction. For example, if the fractional output

clock is 4.5 times slower than the input clock, an average

division ratio of 4.5 is achieved through an equal series

of alternating divide-by-4 and divide-by-5 periods. The

fractional division ratio is given by:

f

/f = L

/(4396 - M

+ L

)

OUT IN

COUNT

where L

and M

are the 12-bit counter val-

COUNT

ues programmed through the serial interface.

Figure 2 illustrates the ADC quantization levels for 2-bit

and ±-bit cases and also describes the sign/magnitude

011

01

010

001

00

000

-7

-6

-2

-1

-5

-4

-3

3

4

5

1

2

6

7

100

10

T = 1

101

110

11

111

Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases

�� Maxim Integrated Products 15

MAX2769B

Universal GPS Receiver

data, and so on. In this case, the serial clock must be at

least twice as fast as the ADC clock. If a 4-bit serialization

of bit , bit , bit , and bit is chosen, the serial clock must

DSP Interface

GPS data is output from the ADC as the four logic signals

(bit , bit , bit , and bit ) that represent sign/magnitude,

3

1

2

±

3

1

2

±

be at least four times faster than the ADC clock.

unsigned binary, or two’s complement binary data in

the I (bit and bit ) and Q (bit and bit ) channels. The

3

1

2

±

The ADC data is loaded in parallel into four holding

registers that correspond to four ADC outputs. 0olding

registers are 16 bits long and are clocked by the ADC

clock. At the end of the 16-bit ADC cycle, the data is

transferred into four shift registers and shifted serially to

the output during the next 16-bit ADC cycle. Shift regis-

ters are clocked by a serial clock that must be chosen

fast enough so that all data is shifted out before the next

set of data is loaded from the ADC. An all-zero pattern

follows the data after all valid ADC data are streamed

to the output. A DATASYNC signal is used to signal the

beginning of each valid 16-bit data slice. In addition,

there is a TIME_SYNC signal that is output every 128 to

16,±84 cycles of the ADC clock.

resolution of the ADC can be set up to ± bits per channel.

For example, the 2-bit I and Q data in sign/magnitude

format is mapped as follows: bit = I

, bit = I

,

3

SIGN

1

MAG

bit = Q

, and bit = Q

. The data can be serial-

2

SIGN

±

MAG

3

ized in 16-bit segments of bit , followed by bit , bit , and

1

2

bit . The number of bits to be serialized is controlled by

±

the bits STRMBITS in the Configuration ± register. This

selects between bit ; bit and bit ; bit and bit ; and

3

1

3

2

bit , bit , bit , and bit cases. If only bit is serialized, the

2

3

1

±

3

data stream consists of bit data only. If a serialization of

3

bit and bit (or bit ) is selected, the stream data pattern

3

1

2

consists of 16 bits of bit data followed by 16 bits of bit

(or bit ) data, which, in turn, is followed by 16 bits of bit

2

3

1

3

STRM_EN

PIN 21

I

PIN 20

OUTPUT

ADC

DRIVER

PIN 17

Q

PIN 18

DATA_OUT

BIT 0

CLK_SER

BIT 1

BIT 2

BIT 3

DATA_SYNC

TIME_SYNC

STRM_EN

STRM_START

STRM_STOP

STRM_EN

STRM_COUNT<2:0>

DIEID<1:0>

STRM_BITS<1:0>

FRM_COUNT<27:0>

STAMP_EN

CONTROL

SIGNALS

FROM 3-WIRE

INTERFACE

DAT_SYNCEN

TIME_SYNCEN

STRM_RST

CLK_ADC CLK_SER

ADCCLK_SEL

L_CNT<11:0>

M_CNT<11:0>

CLK_IN CLK_OUT

THROUGH

REF/XTAL

PIN 15

/2

/4

x2

FRCLK_SEL

SERCLK_SEL

REFDIV<1:0>

Figure 3. DSP Interface Top-Level Connectivity and Control Signals

�� Maxim Integrated Products 16

MAX2769B

Universal GPS Receiver

Preconfigured Device States

When a serial interface is not available, the device can

be used in preconfigured states that don’t require pro-

gramming through the serial interface. Connecting the

PGM pin to logic-high and SCLK, SDATA, and CS pins

to either logic-high or low sets the device in one of the

preconfigured states according to Table ±.

Serial Interface, Address, and

Bit Assignments

A serial interface is used to program the MAX2769B for

configuring the different operating modes.

The serial interface is controlled by three signals: SCLK

(serial clock), CS (chip select), and SDATA (serial data).

The control of the PLL, AGC, test, and block selection

is performed through the serial-interface bus from the

baseband controller. A ±2-bit word, with the MSB (D27)

being sent first, is clocked into a serial shift register when

the chip-select signal is asserted low. The timing of the

interface signals is shown in Figure 5 and Table 4 along

with typical values for setup and hold time requirements.

Power-On Reset (POR)

The MAX2769B incorporates power-on reset circuitry to

ensure that register settings are loaded upon power-up.

To ensure proper operation, the rising edge of PGM must

occur no sooner than when V

nominal value; see Figure 4 for details.

reaches 93% of its final

CC_

Table 3. Preconfigured Device States

DEVICE ELECTRICAL CHARACTERISTICS

3-WIRE CONTROL PINS

3

1

2

±

4

5

6

7

16.±68

±2.7±6

19.2

16

±2

96

26

16

26

15±6

7857

1488

15±6

1538

I

1

2

±

Differential

CMOS

4.392

9.27375

2.5

4.2

9.66

5th

±rd

5th

3

1

3

1

3

1

3

1

3

1

3

1

3

1

CMOS

27.456

16.±68

27.456

CMOS

V

CC_

100%

90%

0%

TIME (s)

PGM

PGM RISING EDGE ANYTIME

AFTER V HAS REACHED

PGM = 0

CC_

90% OF ITS NOMINAL VALUE.

TIME (s)

Figure 4. V

Power-On Reset

CC_

�� Maxim Integrated Products 17

MAX2769B

Universal GPS Receiver

CS

t

CSH

t

CSS

CSW

SCLK

t

DH

t

CH

DS

t

CL

DATA

MSB

DATA

LSB

ADDR

MSB

ADDR

LSB

SDATA

Figure 5. 3-Wire Timing Diagram

Table 4. Serial-Interface Timing Requirements

SYMBOL

PARAMETER

TYP VALUE

UNITS

ns

t

13

25

13

1

Falling edge of CS to rising edge of the first SCLK time.

Data to serial-clock setup time.

Data to clock hold time.

CSS

t

ns

DS

D0

C0

t

ns

Serial clock pulse-width high.

ns

t

Clock pulse-width low.

ns

CL

t

ns

Last SCLK rising edge to rising edge of CS.

CS high pulse width.

CS0

t

clock

CSW

Table 5. Default Register Settings Overview

REGISTER

NAME

ADDRESS

(A3:A0)

DATA

CONF1

CONF2

CONF±

PLLCONF

DIV

3333

3331

3313

3311

3133

3131

3113

3111

1333

1331

Configures RX and IF sections, bias settings for individual blocks.

Configures AGC and output sections.

Configures support and test functions for IF filter and AGC.

PLL, VCO, and CLK settings.

PLL main and reference division ratios, other controls.

PLL fractional division ratio, other controls.

DSP interface number of frames to stream.

Fractional clock-divider values.

FDIV

STRM

CLK

TEST1

TEST2

Reserved for test mode.

�� Maxim Integrated Products 18

MAX2769B

Universal GPS Receiver

Table 6. Default Register Settings

POWER-ON

PRECONFIGURED DEVICE STATE, PGM = 1 (hex)

REGISTER ADDRESS

RESET,

PGM = 0

(hex)

NAME

(A3:A0)

0

1

2

3

4

5

6

7

CONF1

CONF2

CONF±

PLLCONF

DIV

3333

3331

3313

3311

3133

3131

3113

3111

1333

1331

A2919A±

355328C

A2919A± A2919A± A2919A7 A2919A± A2919A± A29±57± A29±57± A29B26B

355121C 355328C 355121C 355328C 355328C 8553±3C 8553±3C 8553±3C

EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC

9EC3338

3C33383

8333373

8333333

13361B2

1E3F431

28C3432

9EC3338 9EC3338 9EC3338 9EC3338 9EC3338 9EC3338 9EC3338 9EC3338

3C33383 3C33383 3C33383 3C33133 ±D62±33 3BA33D3 3C33383 3BC83D3

8333373 8333373 8333373 8333373 8333373 8333373 8333373 8333373

8333333 8333333 8333333 8333333 8333333 8333333 8333333 8333333

13361B2 13361B2 13361B2 13361B2 13361B2 13361B2 13361B2 13361B2

1E3F431 1E3F431 1E3F431 1E3F431 1E3F431 1E3F431 1E3F431 1E3F431

28C3432 28C3432 28C3432 28C3432 28C3432 28C3432 28C3432 7CC343±

FDIV

STRM

CLK

TEST1

TEST2

Detailed Register Definitions

Table 7. Configuration 1 (Address: 0000)

DEFAULT

DATA BIT LOCATION

VALUE

DESCRIPTION

(PGM = 0)

Chip enable. Set 1 to enable the device and 3 to disable the entire device except the

serial bus.

C0IPEN

27

1

IDLE

26

3

1333

13

Idle enable. Set 1 to put the chip in the idle mode and 3 for operating mode.

RESERVED

25:22

21:23

19:18

17:16

—

13

31

Mixer pole selection. Set 1 to program the passive filter pole at mixer output at ±6M0z, or

set 3 to program the pole at 1±M0z.

MIXPOLE

15

3

LNA mode selection, D14:D1± = 33: LNA selection gated by the antenna bias circuit, 31:

LNA2 is active; 13: LNA1 is active; 11: both LNA1 and LNA2 are off.

LNAMODE

14:1±

33

MIXEN

ANTEN

12

11

1

Mixer enable. Set 1 to enable the mixer and 3 to shut down the mixer.

Antenna bias enable. Set 1 to enable the antenna bias and 3 to shut down the antenna bias.

IF center frequency programming. Default for f

= ±.392M0z, BW = 2.5M0z. The

CENTER

FCEN

13:5

331131 MSB of FCEN is located in Register Test Mode 2 (Table 16).

331131 = ±.392M0z, 331311 = 4.392M0z, 313311 = 13.3M0z

IF filter center bandwidth selection. D4:D± = 33: 2.5M0z; 13: 4.2M0z; 31: 9.66M0z;

11: Reserved.

FBW

4:±

2

33

Filter order selection. Set 3 to select the 5th-order Butterworth filter. Set 1 to select the ±rd-

order Butterworth filter.

F±OR5

3

Polyphase filter selection. Set 1 to select complex bandpass filter mode. Set 3 to select

lowpass filter mode.

FCENX

FGAIN

1

3

1

IF filter gain setting. Set 3 to reduce the filter gain by 6dB.

�� Maxim Integrated Products 19

MAX2769B

Universal GPS Receiver

Table 8. Configuration 2 (Address: 0001)

DEFAULT

DATA BIT

IQEN

LOCATION

27

VALUE

(PGM = 0)

DESCRIPTION

I and Q channels enable. Set 1 to enable both I and Q channels and 3 to enable I

channel only.

3

AGC gain reference value expressed by the number of MSB counts (magnitude bit

density). 13131313 = 2±4 magnitude bit density reference, 1313133 = 84 magnitude bit

density reference, 133111313 = ±14 magnitude bit density reference.

GAINREF

26:15

173d

RESERVED

AGCMODE

14:1±

12:11

33

Reserved.

AGC mode control. Set D12:D11 = 33: independent I and Q; 31: reserved; 13: gain is set

directly from the serial interface by GAININ; 11: reserved.

Output data format. Set D13:D9 = 33: unsigned binary; 31: sign and magnitude; 1X:

two’s complement binary.

FORMAT

BITS

13:9

8:6

31

313

33

Number of bits in the ADC. Set D8:D6 = 333: 1 bit, 331: reserved; 313: 2 bits;

311: reserved, 133: ± bits.

Output driver configuration. Set D5:D4 = 33: CMOS logic, 31: reserved; 1X: analog

outputs.

DRVCFG

5:4

RESERVED

DIEID

±

2

1

3

—

1:3

33

Identifies a version of the IC.

Table 9. Configuration 3 (Address: 0010)

DEFAULT

DATA BIT

LOCATION

VALUE

DESCRIPTION

(PGM = 0)

PGA gain value programming from the serial interface in steps of dB per LSB. 333333 =

PGA gain set to 3dB, 131311 = 42dB, 131133 = 4±dB, 131113 = 45dB, 111313 = 57dB,

111111 = 62dB.

GAININ

27:22

111313

RESERVED

21

23

19

18

17

16

1

3

1

—

0ILOADEN

RESERVED

Set 1 to enable the output driver to drive high loads.

—

RESERVED

0ighpass coupling enable. Set 1 to enable the highpass coupling between the filter

and PGA, or 3 to disable the coupling.

F0IPEN

15

1

RESERVED

14

1±

12

1

3

—

DSP interface for serial streaming of data enable. This bit configures the IC such that the

DSP interface is inserted in the signal path. Set 1 to enable the interface or 3 to disable

the interface.

STRMEN

11

3

�� Maxim Integrated Products 20

MAX2769B

Universal GPS Receiver

Table 9. Configuration 3 (Address: 0010) (continued)

DEFAULT

VALUE

DATA BIT

LOCATION

DESCRIPTION

(PGM = 0)

The positive edge of this command enables data streaming to the output. It also enables

clock, data sync, and frame sync outputs.

STRMSTART

13

3

The positive edge of this command disables data streaming to the output. It also

disables clock, data sync, and frame sync outputs.

STRMSTOP

RESERVED

STRMBITS

9

3

8:6

5:4

111

31

—

Number of bits streamed. D5:D4 = 33: reserved; 31: 1 MSB, 1 LSB; 13: reserved, Q

MSB; 11: 1 MSB, 1 LSB, Q MSB, Q LSB.

The signal enables the insertion of the frame number at the beginning of each frame. If

disabled, only the ADC data is streamed to the output.

STAMPEN

±

2

1

This signal enables the output of the time sync pulses at all times when streaming is

enabled by the STRMEN command. Otherwise, the time sync pulses are available only

when data streaming is active at the output, for example, in the time intervals bound by

the STRMSTART and STRMSTOP commands.

TIMESYNCEN

This control signal enables the sync pulses at the DATASYNC output. Each pulse is

DATSYNCEN

STRMRST

1

3

coincident with the beginning of the 16-bit data word that corresponds to a given output

bit.

This command resets all the counters irrespective of the timing within the

stream cycle.

Table 10. PLL Configuration (Address: 0011)

DEFAULT

DATA BIT

LOCATION

VALUE

DESCRIPTION

(PGM = 0)

RESERVED

REFOUTEN

RESERVED

27

26

25

24

2±

1

3

1

—

Clock buffer enable. Set 1 to enable the clock buffer or 3 to disable the clock buffer.

—

Clock output divider ratio. Set D22:D21 = 33: clock frequency = XTAL frequency x 2;

31: clock frequency = XTAL frequency/4; 13: clock frequency = XTAL frequency/2;

11: clock frequency = XTAL.

REFDIV

22:21

11

Current programming for XTAL oscillator/buffer. Set D23:D19 = 33: reserved; 31: buffer

normal current; 13: reserved; 11: oscillator high current.

IXTAL

23:19

31

RESERVED

LDMUX

18:14

1±:13

13333

3333

—

PLL lock-detect enable.

�� Maxim Integrated Products 21

MAX2769B

Universal GPS Receiver

Table 10. PLL Configuration (Address: 0011) (continued)

DEFAULT

VALUE

DATA BIT

LOCATION

DESCRIPTION

(PGM = 0)

ICP

9

8

3

Charge-pump current selection. Set 1 for 1mA and 3 for 3.5mA.

PFDEN

Set 3 for normal operation or 1 to disable the PLL phase frequency detector.

RESERVED

INT_PLL

7

3

—

6:4

±

333

1

—

PLL mode control. Set 1 to enable the integer-N PLL or 3 to enable the fractional-N PLL.

PWRSAV

RESERVED

2

3

PLL power-save mode. Set 1 to enable the power-save mode or 3 to disable.

1

3

—

3

Table 11. PLL Integer Division Ratio (Address 0100)

DEFAULT

DATA BIT

LOCATION

VALUE

DESCRIPTION

(PGM = 0)

NDIV

RDIV

27:1±

12:±

2:3

15±6d

16d

PLL integer division ratio.

PLL reference division ratio.

—

RESERVED

333

Table 12. PLL Division Ratio (Address 0101)

DEFAULT

DATA BIT

LOCATION

VALUE

DESCRIPTION

(PGM = 0)

FDIV

27:8

7:3

83333h

PLL fractional divider ratio.

—

RESERVED

31113333

Table 13. Reserved (Address 0110)

DEFAULT

DATA BIT

LOCATION VALUE

(PGM = 0)

DESCRIPTION

RESERVED

27:3

8333333h —

�� Maxim Integrated Products 22

MAX2769B

Universal GPS Receiver

Table 14. Clock Fractional Division Ratio (Address 0111)

DEFAULT

VALUE

DATA BIT

LOCATION

DESCRIPTION

(PGM = 0)

Sets the value for the L counter. 333133333333 = 256 fractional clock divider,

133333333333 = 2348 fractional clock divider.

L_CNT

M_CNT

FCLKIN

ADCCLK

27:16

15:4

±

256d

Sets the value for the M counter. 311333311311 = 156± fractional clock divider,

133333333 = 2348 fractional clock divider.

156±d

Fractional clock divider. Set 1 to select the ADC clock to come from the fractional clock

divider, or 3 to bypass the ADC clock from the fractional clock divider.

3

ADC clock selection. Set 3 to select the ADC and fractional divider clocks to come from

the reference divider/multiplier.

2

RESERVED

MODE

1

3

1

3

—

DSP interface mode selection.

Table 15. Test Mode 1 (Address 1000)

DEFAULT

DATA BIT

LOCATION

VALUE

(PGM = 0)

DESCRIPTION

RESERVED

27:3

1E3F431

—

Table 16. Test Mode 2 (Address 1001)

DEFAULT

VALUE

DATA BIT

LOCATION

(PGM = 0)

RESERVED

FCENMSB

27:1

3

28C3432

3

—

When combined with FCEN, this bit represents the MSB of a 7-bit FCEN word.

Applications Information

Power-Supply Layout

To minimize coupling between different sections of the

IC, a star power-supply routing configuration with a large

The LNA and mixer inputs require careful consideration

in matching to 53I lines. Proper supply bypassing,

grounding, and layout are required for reliable perfor-

mance from any RF circuit.

decoupling capacitor at a central V

node is recom-

CC_

mended. The V

each going to a separate V

traces branch out from this node,

CC_

node in the circuit. Place

CC_

Layout Issues

The MAX2769B EV kit can be used as a starting point

for layout. For best performance, take into consideration

grounding and routing of RF, baseband, and power-

supply PCB proper line. Make connections from vias

to the ground plane as short as possible. On the high-

impedance ports, keep traces short to minimize shunt

capacitance. EV kit Gerber files can be requested at

www.maxim-ic.com.

a bypass capacitor as close as possible to each supply

pin This arrangement provides local decoupling at each

V

CC_

pin. Use at least one via per bypass capacitor for

a low-inductance ground connection. Do not share the

capacitor ground vias with any other branch.

Refer to Maxim’s Wireless and RF Application Notes

for more information.

�� Maxim Integrated Products 23

MAX2769B

Universal GPS Receiver

Chip Information

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maxim-ic.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates Ro0S status only.

Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of Ro0S status.

PROCESS: SiGe BiCMOS

Ordering Information

PACKAGE

TYPE

PACKAGE OUTLINE

LAND

PATTERN NO.

PART

TEMP RANGE

PIN-PACKAGE

CODE

NO.

MAX2769BETI/V+

-43NC to +85NC

28 TQFN-EP*

28 TQFN-EP

T2855+±

21-0140

90-0023

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

/V denotes an automotive qualified part.

�� Maxim Integrated Products 24

MAX2769B

Universal GPS Receiver

Revision History

REVISION

NUMBER

REVISION

DATE

PAGES

CHANGED

DESCRIPTION

3

1

5/11

8/11

Initial release

—

Corrected part number in Ordering Information section.

24

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

25

©

2311 Maxim Integrated Products

Maxim is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX2769BETI/V+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Universal GPS Receiver 通用的GPS接收器线路驱动器或接收器驱动程序和接口接口集成电路信息通信管理全球定位系统
文件：	总25页 (文件大小：3207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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