MAX3094EEUE+ [MAXIM]
Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO16, TSSOP-16;![MAX3094EEUE+](http://pdffile.icpdf.com/pdf2/p00287/img/icpdf/MAX3093ECUE-_1742944_icpdf.jpg)
型号: | MAX3094EEUE+ |
厂家: | ![]() |
描述: | Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO16, TSSOP-16 光电二极管 接口集成电路 |
文件: | 总13页 (文件大小:185K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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19-1779; Rev 2; 10/02
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
________________General Description
____________________________Features
♦ ESD Protection
The MAX3093E/MAX3094E are rugged, low-power,
quad, RS-422/RS-485 receivers featuring electrostatic
discharge (ESD) protection for use in harsh environ-
ments. All receiver inputs are protected to ±±5ꢀk using
IEC ±000-4-2 Air-Gap Discharge, ±8ꢀk using IEC ±000-
4-2 Contact Discharge, and ±±5ꢀk using the ꢁuman
Body Model. The MAX3093E operates from a +5k sup-
ply, while the MAX3094E operates from a +3.3k supply.
Receiver propagation delays are guaranteed to within
±8ns of a predetermined value, thereby ensuring
device-to-device matching across production lots.
±±15kV—Eꢀ ±ꢁꢁꢁ0-0ꢂ ꢃir0ꢄGa DiꢅcꢆGrꢇe
±ꢈ5kV—Eꢀ ±ꢁꢁꢁ0-0ꢂ ꢀontGct DiꢅcꢆGrꢇe
±±15kVꢉHuGn ꢊoꢋd ꢌoꢋeꢍ
♦ ꢄHGrGnteeꢋ ProaGꢇGtion0DeꢍGd ToꢍerGnce
ꢊetween ꢃꢍꢍ —ꢀꢅ
±ꢈnꢅ ꢎꢌꢃAXꢁꢏXEꢐ
±±ꢁnꢅ ꢎꢌꢃAXꢁꢏ-Eꢐ
♦ Sinꢇꢍe +Xk OaerGtion ꢎꢌꢃAXꢁꢏ-Eꢐ
Sinꢇꢍe +1k OaerGtion ꢎꢌꢃAXꢁꢏXEꢐ
♦ ±60Pin TSSOP
The devices feature a ±nA low-power shutdown mode
in which the receiver outputs are high impedance.
When active, these receivers have a fail-safe feature
that guarantees a logic-high output if the input is open
circuit. They also have a quarter-unit-load input imped-
ance that allows ±28 receivers on a bus.
♦ ±ꢁꢌbaꢅ DGtG RGte
♦ ꢃꢍꢍow Ha to ±ꢂꢈ Receiverꢅ on tꢆe ꢊHꢅ
♦ ±nꢃ Low0Power SꢆHtꢋown ꢌoꢋe
♦ ꢂ.-uꢃ OaerGtinꢇ SHaaꢍd ꢀHrrent
♦ Pin0ꢀouaGtibꢍe UaꢇrGꢋeꢅ to ’X-ꢀꢈ6
The MAX3093E/MAX3094E are pin-compatible, low-
power upgrades to the industry-standard ’34C86. They
are available in space-saving TSSOP, narrow SO, and
PDIP pacꢀages.
_______________Ordering Information
PꢃRT
TEꢌP RꢃNꢄE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
P—N0PꢃꢀKꢃꢄE
ꢌꢃAXꢁꢏXECUE
MAX3093ECSE
MAX3093ECPE
MAX3093EEUE
MAX3093EESE
MAX3093EEPE
ꢌꢃAXꢁꢏ-ECUE
MAX3094ECSE
MAX3094ECPE
MAX3094EEUE
MAX3094EESE
MAX3094EEPE
±6 TSSOP
________________________Applications
±6 Narrow SO
±6 Plastic DIP
±6 TSSOP
±6 Narrow SO
±6 Plastic DIP
±6 TSSOP
±6 Narrow SO
±6 Plastic DIP
±6 TSSOP
±6 Narrow SO
±6 Plastic DIP
Telecommunications Equipment
Rugged RS-422/RS-485/RS-423 Bus Receiver
Receivers for ESD-Sensitive Applications
Level Translators
________________Functional Diagram
V
CC
ENBD
ENAC
MAX3093E
MAX3094E
-in Configuration
A+
A-
TOP VIEW
A
A
B
C
D
YA
A-
A+
1
2
3
4
5
6
7
8
16 V
CC
B+
B-
15 B-
YB
YC
YD
B
YA
14 B+
13 YB
12 ENBD
11 YD
10 D+
ENAC
YC
MAX3093E
MAX3094E
C+
C-
C
C+
D+
D
C-
D-
GND
9
D-
GND
TSSOP/SO/D—P
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
ꢃꢊSOLUTE ꢌꢃA—ꢌUꢌ RꢃT—NꢄS
Supply koltage (k ).............................................................+7k
Operating Temperature Ranges
CC
Control Input koltage (ENAC, ENBD).........-0.3k to (k
+ 0.3k)
MAX309_EC_ _ ..................................................0°C to +70°C
MAX309_EE_ _ ...............................................-40°C to +85°C
Junction Temperature......................................................+±50°C
Storage Temperature Range.............................-65°C to +±60°C
Lead Temperature (soldering, ±0s) .................................+300°C
CC
Receiver Input koltage (_+, _-)............................................±25k
Receiver Output koltage (Y_).....................-0.3k to (k + 0.3k)
CC
Output Short-Circuit Duration (Y_, one output) ..........Continuous
Continuous Power Dissipation (T = +70°C)
A
TSSOP (derate 9.4mW/°C above +70°C) ....................755mW
SO (derate 8.7mW/°C above +70°C)...........................696mW
Plastic DIP (derate ±0.5mW/°C above +70°C) ............762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Dꢀ ELEꢀTR—ꢀꢃL ꢀꢉꢃRꢃꢀTER—ST—ꢀSVꢌꢃAXꢁꢏXE
(k
= +5k ±5ꢂ, T = T
A
to T
, unless otherwise noted. Typical values are at k
= +5.0k, T = +25°C.) (Note ±)
CC A
CC
MIN
MAX
PꢃRꢃꢌETER
SYꢌꢊOL
ꢀOND—T—ONS
≤ ±2k
CM
ꢌ—N
TYP
ꢌꢃA
UN—TS
mk
Receiver Differential Input
Threshold
k
Tꢁ
-7k ≤ k
-200
200
Receiver Input ꢁysteresis
k
= 0
45
mk
CM
CC
k
k
= ±2k
= -7k
250
IN
Receiver Input Current (_+, _-)
I
IN
k
= 0 or 5.25k
µA
-200
IN
Enable Input Current
(ENAC/ENBD)
±±
µA
k
Enable Input ꢁigh koltage
(ENAC/ENBD)
k
Iꢁ
2.0
Enable Input Low koltage
(ENAC/ENBD)
k
0.8
0.4
k
IL
I
= -4mA, k = 200mk,
ID
OUT
Receiver Output ꢁigh koltage
Receiver Output Low koltage
k
Oꢁ
k
CC
- ±.5
k
output enabled, Figure ±
I
= 4mA, k = -200mk,
OUT
ID
k
OL
k
output enabled, Figure ±
Three-State Current at Receiver
Output
I
0 ≤ k
0 ≤ k
≤ k , output disabled
±±
µA
OZR
OUT
CC
Output Short-Circuit Current
Receiver Input Resistance
I
≤ k , output enabled
±7
48
±75
mA
ꢀΩ
mA
µA
OSR
OUT
CC
R
-7k ≤ k
≤ ±2k
IN
CM
No load, output enabled
Output disabled
2.4
0.00±
±±5
±±5
±8
3.5
±0
Supply Current
I
CC
ꢁuman Body Model
ESD Protection
(Note 2)
IE C±000-4-2 Air-Gap Discharge
IE C±000-4-2 Contact Discharge
ꢀk
ꢂ
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
SW—Tꢀꢉ—Nꢄ ꢀꢉꢃRꢃꢀTER—ST—ꢀSVꢌꢃAXꢁꢏXE
(k
= +5k ±5ꢂ, T = T
A
to T
, unless otherwise noted. Typical values are at k
= +5.0k, T = +25°C.)
CC A
CC
MIN
MAX
PꢃRꢃꢌETER
SYꢌꢊOL
ꢀOND—T—ONS
= +5k ±5ꢂ, T = T
ꢌ—N
65
78
76
7±
65
82
80
74
68
TYP
ꢌꢃA
98
94
92
87
8±
98
96
90
84
UN—TS
k
to T
MAX
CC
CC
A
MIN
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= +85°C
= +70°C
= +25°C
= -40°C
= +85°C
= +70°C
= +25°C
= -40°C
86
k
= 5.25k
= 4.75k
79
73
90
Input-to-Output Propagation
Delay
t
, t
|k | = 3k,
PLꢁ PꢁL
ID
ns
Figure 2
k
CC
82
76
Device-to-Device Propagation-
Delay Matching
±6
ns
ns
ns
ns
ns
|k | = 3k, Figure 2, matched conditions
ID
Propagation-Delay Sꢀew
t
Figure 2
Figure 3
Figure 3
Figure 3
Figure 3
-2
600
600
60
±±0
800
800
±00
±00
SK
(t
- t
)
PLꢁ PꢁL
Output Enable Time to
Low Level
t
ZL
Output Enable Time to
ꢁigh Level
t
Zꢁ
Output Disable Time from
Low Level
t
LZ
Output Disable Time from
ꢁigh Level
t
60
ns
ꢁZ
Maximum Data Rate
fMAX
±0
Mbps
Dꢀ ELEꢀTR—ꢀꢃL ꢀꢉꢃRꢃꢀTER—ST—ꢀSVꢌꢃAXꢁꢏ-E
(k
= +3.0k to +3.6k, T = T
A
to T
, unless otherwise noted. Typical values are at k
= +3.3k, T = +25°C.) (Note ±)
CC A
CC
MIN
MAX
PꢃRꢃꢌETER
SYꢌꢊOL
ꢀOND—T—ONS
≤ ±2k
CM
ꢌ—N
TYP
ꢌꢃA
UN—TS
mk
Receiver Differential Input
Threshold
k
Tꢁ
-7k ≤ k
-200
200
Receiver Input ꢁysteresis
k
= 0
45
mk
CM
CC
k
k
= ±2k
= -7k
250
IN
Receiver Input Current (_+, _-)
I
IN
k
= 0 or 3.6k
µA
-200
IN
Enable Input Current
(ENAC/ENBD)
±±
µA
k
Enable Input ꢁigh koltage
(ENAC/ENBD)
k
Iꢁ
2.0
Enable Input Low koltage
(ENAC/ENBD)
k
IL
0.8
k
I
= -±.5mA, k = 200mk,
ID
OUT
Receiver Output ꢁigh koltage
k
Oꢁ
k
CC
- 0.4
k
output enabled, Figure ±
_______________________________________________________________________________________
X
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
Dꢀ ELEꢀTR—ꢀꢃL ꢀꢉꢃRꢃꢀTER—ST—ꢀSVꢌꢃAXꢁꢏ-E ꢎcontinHeꢋꢐ
(k
= +3.0k to +3.6k, T = T
A
to T
, unless otherwise noted. Typical values are at k
= +3.3k, T = +25°C.) (Note ±)
CC
MIN
MAX
CC A
PꢃRꢃꢌETER
SYꢌꢊOL
ꢀOND—T—ONS
ꢌ—N
TYP
ꢌꢃA
UN—TS
I
= 2.5mA, k = -200mk,
OUT
ID
Receiver Output Low koltage
k
OL
0.4
k
output enabled, Figure ±
Three-State Current at Receiver
Output
I
0 ≤ k
0 ≤ k
≤ k , output disabled
±±
µA
OZR
OUT
CC
Output Short-Circuit Current
Receiver Input Resistance
I
≤ k , output enabled
±4
48
±60
mA
ꢀΩ
mA
µA
OSR
OUT
CC
R
-7k ≤ k
≤ ±2k
IN
CM
No load, outputs enabled
Outputs disabled
2.4
0.00±
±±5
±±5
±8
4.0
±0
Supply Current
I
CC
ꢁuman Body Model
ESD Protection
(Note 2)
IEC ±000-4-2 Air-Gap Discharge
IEC ±000-4-2 Contact Discharge
ꢀk
SW—Tꢀꢉ—Nꢄ ꢀꢉꢃRꢃꢀTER—ST—ꢀSVꢌꢃAXꢁꢏ-E
(k
= +3.0k to +3.6k, T = T
A
to T
, unless otherwise noted. Typical values are at k
= +3.3k, T = +25°C.)
CC A
CC
MIN
MAX
PꢃRꢃꢌETER
SYꢌꢊOL
ꢀOND—T—ONS
= +3.3k ±5ꢂ, T = T
ꢌ—N
69
TYP
ꢌꢃA
±23
±08
±06
98
UN—TS
k
to T
MAX
CC
A
MIN
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= +85°C
= +70°C
= +25°C
= -40°C
= +85°C
= +70°C
= +25°C
= -40°C
88
98
86
k
= 3.60k
= 3.00k
CC
CC
78
88
79
Input-to-Output Propagation
Delay
t
, t
|k | = 3k,
PLꢁ PꢁL
ID
69
89
ns
Figure 2
±03
±00
9±
±±3
±23
±20
±±±
±02
k
±0±
92
82
Device-to-Device Propagation-
Delay Matching
20
ns
ns
ns
ns
ns
|k | = 3k, Figure 2, matched conditions
ID
Propagation-Delay Sꢀew
t
Figure 2
Figure 3
Figure 3
Figure 3
Figure 3
-±
600
600
80
±±0
±000
±000
±80
SK
(t
- t
)
PLꢁ PꢁL
Output Enable Time to
Low Level
t
ZL
Output Enable Time to
ꢁigh Level
t
Zꢁ
Output Disable Time from
Low Level
t
LZ
Output Disable Time from
ꢁigh Level
t
80
±80
ns
ꢁZ
Maximum Data Rate
fMAX
±0
Mbps
Note ±: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device
ground, unless otherwise noted.
Note ꢂ: Receiver inputs (_+, _-).
-
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
Typical Operating Characteristics
(k
CC
= +5k for MAX3093E, k
= +3.3k for MAX3094E, T = +25°C, unless otherwise noted.)
CC A
OUTPUT LOW VOLTAGE
vs. TEMPERATURE
OUTPUT CURRENT vs.
OUTPUT LOW VOLTAGE
OUTPUT CURRENT vs.
OUTPUT HIGH VOLTAGE
1.0
-50
30
I
= 8mA
OUT
0.9
MAX3093E
25
20
15
10
5
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
-30
-20
-10
0
MAX3093E
MAX3094E
MAX3094E
MAX3093E
MAX3094E
2
0
-40
-15
10
35
60
85
0
1
2
3
4
5
0
1
3
4
5
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
5
4
3
2
1
0
3.0
2.8
2.6
2.4
2.2
2.0
20
15
10
5
MAX3093E
MAX3093E/MAX3094E
MAX3094E
MAX3093E
MAX3094E
I
= -8mA
-15
OUT
0
-40
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX3093E
MAX3094E
PROPAGATION DELAY vs. TEMPERATURE
PROPAGATION DELAY vs. TEMPERATURE
120
110
100
90
140
130
120
110
100
90
⏐V ⏐ = 3V
⏐V ⏐ = 3V
ID
ID
C = 15pF
L
C = 15pF
L
80
70
80
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
1
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
Typical Operating Characteristics (continued)
(k
CC
= +5k for MAX3093E, k
= +3.3k for MAX3094E, T = +25°C, unless otherwise noted.)
CC A
SHUTDOWN TIMING
MAX3093/94E TOC09
MAX3093E
Y VOLTAGE
5V/div
2V/div
2V/div
MAX3094E
Y VOLTAGE
G VOLTAGE
TIME (200ns/div)
CIRCUIT OF FIGURE 3,
S1 OPEN, S2 CLOSED, S3 = 1V
-in Description
P—N
±
NꢃꢌE
A-
FUNꢀT—ON
Inverting Receiver A Input
2
A+
Noninverting Receiver A Input
Receiver A Output. Enabled when ENAC = high. YA will be logic high if A+ > A- by 200mk, and low if
A+ < A- by 200mk. It will be logic high if A+ and A- remain floating. Otherwise, the state is undetermined.
YA goes high impedance when ENAC = low.
3
YA
4
5
ENAC
YC
Receiver Output A and C Enable ꢁigh. A logic high on this input enables receivers A and C.
Receiver C Output. Same functionality as YA.
Noninverting Receiver C Input
Inverting Receiver C Input
Ground
6
C+
7
C-
8
GND
D-
9
Inverting Receiver D Input
Noninverting Receiver D Input
±0
D+
Receiver D Output. Enabled when ENBD = high. YD will be logic high if D+ > D- by 200mk, and low if
D+ < D- by 200mk. It will be a logic high if D+ and D- remain floating. Otherwise, the state is undetermined.
YD goes high impedance when ENBD = low.
±±
YD
±2
±3
±4
±5
±6
ENBD
YB
Receiver Output B and D Enable ꢁigh. A logic high on this input enables receivers B and D.
Receiver B Output. Same functionality as YD.
Noninverting Receiver B Input
B+
B-
Inverting Receiver B Input
k
CC
Positive Supply
6
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
OUT
V
ID
V
= 3V
| |
ID
R
C
L
15pF
V
ID
R
ENAC = V or ENBD = V
CC
CC
V
OL
V
OH
I
I
OH
(-)
OL
3.0V
0
(+)
IN
1.5V
1.5V
t
t
PHL
PLH
V
0
CC
Figure 1. Receiver V
and V
OL
OH
V /2
CC
V /2
CC
OUT
Figure 2. Receiver Propagation Delay
S1
S3
+1V
-1V
V
CC
1kΩ
V
ID
R
S2
C
15pF
ENAC,
ENBD
L
3V
3V
0
ENAC
ENBD
1.5V
1.5V
ENAC
ENBD
0
t
t
t
ZL
t
LZ
ZH
HZ
V
CC
V
OH
OUT
V /2
CC
V /2
CC
OUT
0.25V
V
OL
0
0.25V
S1 OPEN
S2 CLOSED
S3 = 1V
S1 CLOSED
S2 OPEN
S3 = -1V
Figure 3. Receiver Enable and Disable Times
_______________________________________________________________________________________
7
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
The main difference between tests done using the
ꢁuman Body Model and IEC ±000-4-2 is higher peaꢀ
_______________Detailed Description
±±15k EꢀD -rotection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against ESDs encoun-
tered during handling and assembly. The
MAX3093E/MAX3094E receiver inputs have extra
protection against static electricity found in normal
operation. Maxim’s engineers have developed state-
of-the-art structures to protect these pins against ±±5ꢀk
ESD without damage. After an ESD event, the
MAX3093E/MAX3094E continue worꢀing without latchup.
current in IEC ±000-4-2. Because series resistance is
lower in the IEC ±000-4-2 ESD test model (Figure 5a), the
ESD-withstand voltage measured to this standard is gen-
erally lower than that measured using the ꢁuman Body
Model. Figure 5b shows the current waveform for the
±8ꢀk IEC ±000-4-2 Level 4 ESD Contact Discharge test.
The Air-Gap test involves approaching the device with a
charge probe. The Contact-Discharge method connects
the probe to the device before the probe is energized.
Machine Model
The Machine Model for ESD testing uses a 200pF stor-
age capacitor and zero-discharge resistance. It mimics
the stress caused by handling during manufacturing
and assembly. All pins (not just RS-485 inputs) require
this protection during manufacturing. Therefore, the
Machine Model is less relevant to the I/O ports than are
the ꢁuman Body Model and IEC ±000-4-2.
ESD protection can be tested in several ways. The
receiver inputs are characterized for protection to the
following:
• ±±5ꢀk using the ꢁuman Body Model
• ±8ꢀk using the Contact Discharge Method specified
in IEC ±000-4-2 (formerly IEC 80±-2)
• ±±5ꢀk using the Air-Gap Method specified in
IEC ±000-4-2 (formerly IEC 80±-2)
Lowꢁ-ower ꢀhutdown Mode
The function tables show the functionality of the enable
inputs. The MAX3093E/MAX3094E enter shutdown
when ENAC and ENBD are low. In shutdown, all out-
puts go high impedance and the devices typically draw
less than ±nA. The devices exit shutdown by taꢀing
either ENAC or ENBD high. The typical shutdown exit
time is 600ns.
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
Human Body Model
Figure 4a shows the ꢁuman Body Model, and Figure
4b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
±00pF capacitor charged to the ESD voltage of interest,
which is then discharged into the device through a
±.5ꢀΩ resistor.
FHnction TGbꢍeꢅ
OUTPUT
Yꢃ OR Yꢀ
DEk—ꢀE
ꢌODE
ENꢃꢀ
ENꢊD
ꢎ—N+ 0 —N0ꢐ
±
±
±
0
0
X
X
X
±
0
≥ 200mk
±
0
On
On
IEC 1000-4-2
≤ -200mk
Since January ±996, all equipment manufactured and/or
Open
±
On
sold in the European community has been required to
meet the stringent IEC ±000-4-2 specification. The IEC
±000-4-2 standard covers ESD testing and performance
of finished equipment; it does not specifically refer to inte-
grated circuits. The MAX3093E/MAX3094E help you
design equipment that meets Level 4 (the highest level) of
IEC ±000-4-2, without additional ESD-protection compo-
nents.
X
X
ꢁigh-Z
ꢁigh
On
Shutdown
OUTPUT
Yꢊ OR YD
DEk—ꢀE
ꢌODE
ENꢊD
ENꢃꢀ
ꢎ—N+ 0 —N0ꢐ
±
±
±
0
0
X
X
X
±
0
≥ 200mk
±
0
On
On
≤ -200mk
Open
±
On
X
X
ꢁigh-Z
ꢁigh-Z
On
Shutdown
X = don’t care, High-Z = high impedance
ꢈ
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
R
R
1MΩ
D
C
R
R
C
D
1.5kΩ
50MΩ to 100MΩ
330Ω
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
s
100pF
STORAGE
CAPACITOR
C
s
150pF
STORAGE
CAPACITOR
SOURCE
SOURCE
Figure 5a. IEC 1000-4-2 ESD Test Model
Figure 4a. Human Body ESD Test Model
I
100%
90%
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
AMPERES
36.8%
10%
0
10%
TIME
0
t
t = 0.7ns to 1ns
RL
r
t
30ns
t
DL
60ns
CURRENT WAVEFORM
Figure 4b. Human Body Model Current Waveform
Figure 5b. IEC 1000-4-2 ESD-Generator Current Waveform
_______________________________________________________________________________________
ꢏ
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
Applications Information
-ropagationꢁDelay Matching
V
CC
The MAX3093E/MAX3094E exhibit propagation delays
that are closely matched from one device to another,
even between devices from different production lots. This
feature allows multiple data lines to receive data and
clocꢀ signals with minimal sꢀewing with respect to each
other. The MAX3093E receiver propagation delays are
trimmed to a predetermined value ±8ns, while the
MAX3094E delays are trimmed to a predetermined value
±±0ns.
1kΩ
MAX3093E
MAX3094E
_+
_-
150Ω
±28 Receivers on the Bus
The standard RS-485 input impedance is ±2ꢀΩ (one-
unit load). The standard RS-485 transmitter can drive
32 unit loads. The MAX3093E/MAX3094E present a ±/4-
unit-load input impedance (48ꢀΩ), which allows up to
±28 receivers on a bus. Any combination of these RS-
485 receivers with a total of 32-unit loads can be con-
nected to the same bus.
1kΩ
Figure 6. External Fail-Safe Implementation
Failꢁꢀafe Implementation
The MAX3093E/MAX3094E receiver inputs guarantee a
logic high output when the inputs are open circuit (no
termination resistor used). This occurs when the trans-
mitter is removed from the bus or when all transmitter
outputs are high impedance. ꢁowever, when the line is
terminated and the transmitters are disabled, the differ-
ential voltage between the _+ and _- inputs falls below
the ±200mk RS-485 sensitivity threshold. Consequent-
ly, the outputs become undefined. To maintain a fail-
safe receiver output while using a terminating resistor,
input _+ must be biased at least 200mk above input B.
The resistor-divider networꢀ shown in Figure 6 is rec-
ommended.
Chip Information
TRANSISTOR COUNT: 676
±ꢁ ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
-ac5age Information
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.uGxiu0ic.cou/aGc5Gꢇeꢅ.)
PACKAGE OUTLINE, TSSOP 4.40mm BODY
±
2±-0066
I
±
______________________________________________________________________________________ ±±
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
-ac5age Information (continued)
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.uGxiu0ic.cou/aGc5Gꢇeꢅ.)
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.069
0.010
0.019
0.010
MIN
1.35
0.10
0.35
0.19
MAX
1.75
0.25
0.49
0.25
0.053
0.004
0.014
0.007
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
DIM
D
MIN
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0 -8
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
±ꢂ ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±0Mbps, 3k/1k,
Lowꢁ-ower Quad Rꢀꢁ422/Rꢀꢁ481 Receivers
-ac5age Information (continued)
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.uGxiu0ic.cou/aGc5Gꢇeꢅ.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated -roducts, ±20 ꢀan Gabriel Drive, ꢀunnyvale, CA 94086 408ꢁ737ꢁ7600_____________________±X
© 2002 Maxim Integrated Products
Printed USA
is a registered trademarꢀ of Maxim Integrated Products.
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MAX3095CEE+T
Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16
MAXIM
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