MAX3140_V01 [MAXIM]
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers;
| 型号： | MAX3140_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers |
| 文件： | 总36页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1453; Rev 1; 9/10
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
General Description
Features
The MAX3140 is a complete universal asynchronous
receiver-transmitter (UART) and a true fail-safe RS-
485/RS-422 transceiver combined in a single 28-pin
QSOP package for space-, cost-, and power-con-
strained applications. The MAX3140 saves additional
board space as well as microcontroller (µC) I/O pins by
featuring an SPI™/QSPI™/MICROWIRE™-compatible
serial interface. It is pin-programmable for configuration
in all RS-485/RS-422 networks.
o Integrated UART and RS-485/RS-422 Transceiver
in a Single 28-Pin QSOP
o SPI/MICROWIRE-Compatible Interface Saves µC
I/O Pins
o True Fail-Safe Receiver Output Eliminates
Complex Network Termination
o Pin-Programmable RS-485/RS-422 Features
Half/Full-Duplex Operation
Slew-Rate Limiting for Reduced EMI
115kbps/500kbps/10Mbps Data Rates
Receiver/Transmitter Phase for Twisted-Pair
Polarity Reversal
The MAX3140 includes a single RS-485/RS-422 driver
and receiver featuring true fail-safe circuitry, which
guarantees a logic-high receiver output when the
receiver inputs are open or shorted. This feature pro-
vides immunity to faults without requiring complex ter-
mination. The MAX3140 provides software-selectable
control of half- or full-duplex operation, data rate, slew
rate, and transmitter and receiver phase. The RS-485
driver slew rate is programmable to minimize EMI and
results in maximum data rates of 115kbps, 500kbps,
and 10Mbps. Independent transmitter/receiver phase
control enables software correction of twisted-pair
polarity reversal. A 1/8-unit-load receiver input imped-
ance allows up to 256 transceivers on the bus.
o Full-Featured UART
Programmable Up to 230k baud with a
3.6864MHz Crystal
8-Word Receive FIFO Minimizes Processor
Overhead
9-Bit Address-Recognition Interrupt
o Allows Up to 256 Transceivers on the Bus
o Low 20µA Hardware Shutdown Mode
o Hardware/Software-Compatible with MAX3100
and MAX3089
The MAX3140’s UART includes an oscillator circuit
derived from an external crystal, and a baud-rate gen-
erator with software-programmable divider ratios for all
common baud rates from 300 baud to 230k baud. The
UART features an 8-word-deep receive FIFO that mini-
mizes processor overhead and provides a flexible inter-
rupt with four maskable sources, including address
recognition on 9-bit networks. Two control lines are
included for hardware handshaking—one input and
one output.
Ordering Information
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
28 QSOP
MAX3140CEI+
MAX3140EEI+
-40°C to +85°C
28 QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Application Circuit
The MAX3140 operates from a single +5V supply and
typically consumes only 645µA with the receiver active.
Hardware-invoked shutdown reduces supply current to
only 20µA. The UART and RS-485/RS-422 functions can
be used together or independently since the two func-
tions share only supply and ground connections (the
MAX3140 is hardware- and software-compatible with the
MAX3100 and MAX3089).
MAX3140
CONTROL
LOGIC
RS-485
RS-422
SPI/
MICRO-
WIRE
R
t
CS
SCLK
DIN
UART
µP
Applications
DOUT
Industrial-Control
Transceivers for EMI-
Sensitive Applications
Local Area Networks
IRQ
HVAC and Building Control Embedded Systems
Point-of-Sale Devices Intelligent Instrumentation
R
t
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
HALF/FULL-DUPLEX
RS-485/RS-422
H/F SRLTXP RXP
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
ABSOLUTE MAXIMUM RATINGS
CC
Input Voltage to GNꢁ (CS% SHDN% X1% CTS% RX% ꢁIN% SCLK%
RE% ꢁD% H/F% SRL% TXP% RXP% ꢁl) .............-0.3V to (V
Output Voltage to GNꢁ
V
to GNꢁ ..........................................................................+6V
X2% ꢁOUT% IRQ Short-Circuit ꢁuration
(to V or GNꢁ)......................................................Continuous
CC
+ 0.3V)
Continuous Power ꢁissipation (T = +70°C)
CC
A
28-pin QSOP (derate 10.8mW/°C above +70°C)..........860mW
Operating Temperature Ranges
ꢁOUT% RTS% TX% X2% RO...........................-0.3V to (V
+ 0.3V)
CC
IRQ ........................................................................-0.3V to +6V
ꢁriver Output Voltage (Y% Z) ............................................... 13V
Receiver Input Voltage% Half ꢁuplex (Y% Z)......................... 13V
Receiver Input Voltage% Full ꢁuplex (A% B) ......................... 25V
TX% RTS Output Current ...................................................100mA
MAX3140CDI .......................................................0°C to +70°C
MAX3140DDI ....................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering% 10sec) .............................+300°C
Soldering Temperature (reflow) .......................................+260°C
MAX3140
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only% and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Dxposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V 5ꢀ% ꢁD = V % RE = GNꢁ% SHDN = V % f
= 1.8432MHz% T = T
to T
% unless otherwise noted. Typical values
CC
CC
CC XTL
A
MIN
MAX
are measured with V
= +5V% UART configured for 9600 baud% T = +25°C.) (Note 1)
CC
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
4.75
5.25
1.9
1.6
2
V
CC
ꢁD = V
0.7
CC
SRL = V
CC
SHDN = V
SHꢁNi bit = 0%
no load
;
CC
ꢁD = GNꢁ
ꢁD = V
0.64
0.74
0.69
Supply Current
I
mA
CC
CC
SRL = GNꢁ
or open
ꢁD = GNꢁ
1.8
I
I
Supply Current with Only UART
Shut ꢁown
CC
SHꢁN
SHꢁN
0.47
1
mA
µA
SHDN = GNꢁ or SHꢁNi bit = 1
UART
Supply Current with Both
RS-485 Transceiver and UART
Shut ꢁown
SHDN = GNꢁ or SHꢁNi bit = 1;
CC
20
ꢁD = GNꢁ; RE = V
(FULL)
CC
UART OSCILLATOR INPUT (X1)
Input High Voltage
V
0.7V
V
V
IH1
CC
Input Low Voltage
V
0.2V
CC
IL1
SHꢁNi bit = 0
SHꢁNi bit = 1
25
2
Input Current
I
V
X1
= 0 or V
CC
µA
pF
IN1
Input Capacitance
C
5
IN1
UART LOGIC INPUTS (DIN, SCLK, CS, SHDN, CTS, RX)
Input High Voltage
V
0.7V
V
V
IH2
CC
Input Low Voltage
V
0.3V
CC
IL2
Input Hysteresis
V
250
5
mV
µA
pF
HYST2
Input Leakage Current
Input Capacitance
I
1
LKG1
C
IN2
UART OUTPUTS (DOUT, TX, RTS)
V
- 0.5
- 0.5
I
I
I
I
= 5mA; ꢁOUT% RTS
= 10mA; TX only
CC
SOURCD
Output High Voltage
V
V
V
OH1
V
CC
SOURCD
0.4
0.9
1
= 4mA; ꢁOUT% RTS
= 25mA; TX only
SINK
SINK
Output Low Voltage
Output Leakage
V
OL1
I
µA
pF
CS = V ; ꢁ
only
LKG2
CC OUT
Output Capacitance
C
OUT1
5
2
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V 5ꢀ% ꢁD = V % RE = GNꢁ% SHDN = V % f
= 1.8432MHz% T = T
to T
% unless otherwise noted. Typical values
MAX
CC
CC
CC XTL
A
MIN
are measured with V
= +5V% UART configured for 9600 baud% T = +25°C.) (Note 1)
CC
A
PARAMETER
UART IRQ OUTPUT (Open ꢁrain)
Output Low Voltage
Output Leakage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OL2
I
= 4mA
0.4
1
V
SINK
I
V
= V
CC
µA
pF
LKG3
IRQ
Output Capacitance
RS-485 DRIVER
C
OUT2
5
V
Oꢁ1
No load% Figure 1
5
ꢁifferential Output Voltage
R = 50Ω (RS-422)% Figure 1
R = 27Ω (RS-422)% Figure 1
2.0
1.5
V
V
Oꢁ2
Change in Magnitude of
ꢁifferential Output Voltage
ΔV
R = 50Ω or R = 27Ω% Figure 1 (Note 2)
R = 50Ω or R = 27Ω% Figure 1
0.2
3
V
V
V
V
Oꢁ
Common-Mode Output
Voltage
V
OC
Change In Magnitude of
Common-Mode Voltage
ΔV
R = 50Ω or R = 27Ω% Figure 1 (Note 2)
0.2
OC
2.0
2.4
ꢁD% ꢁl% RE
Input High Voltage
V
IH1
H/F% TXP% RXP
Input Low Voltage
ꢁI Input Hysteresis
V
0.8
V
ꢁD% ꢁl% RD% H/F% TXP% RXP
IL1
V
HYS
I
IN1
IN2
SRL = V
or unconnected
100
mV
CC
2
ꢁD% ꢁI% RE
Input Current
µA
I
10
40
H/F% TXP% RXP% internal pull-down
SRL Input High Voltage
SRL Input Middle Voltage
SRL Input Low Voltage
V
V
- 0.8
V
V
V
IH2
CC
V
IM2
(Note 3)
0.4 · V
0.6 · V
CC
CC
V
0.8
IL2
SRL = V
75
CC
SRL Input Current
I
µA
µA
µA
IN3
SRL = GNꢁ (Note 3)
ꢁD = GNꢁ
-75
V
V
V
V
= 12V
= -7V
= 12V
= -7V
125
-75
IN
IN
IN
IN
Full-ꢁuplex Input Current
(A and B)
I
IN4
V
CC
= GNꢁ or 5.25V
ꢁD = GNꢁ
= GNꢁ or 5.25V
125
Full-ꢁuplex Output Leakage
(Y and Z)
I
O
V
CC
-100
-250
-7V ≤ V
≤ V
CC
OUT
Short-Circuit Output Current
I
(Note 4)
0 ≤ V
0 ≤ V
≤ 12V
250
-50
mA
OSꢁ
OUT
OUT
≤ V
25
CC
RS-485 RECEIVER
ꢁifferential Threshold Voltage
Input Hysteresis
V
-7V ≤ V
≤ +12V
-200
-125
25
mV
mV
V
TH
CM
ΔV
TH
Output High Voltage
Output Low Voltage
V
I
I
= 4mA% V = -50mV
V
- 1.5
OH
SOURCD
Iꢁ
CC
V
= 4mA% V = -200mV
0.4
1
V
OL
SINK
Iꢁ
Three-State Output Current
Input Resistance
I
0.4V ≤ V ≤ 2.4V
µA
kΩ
mA
OZR
O
R
-7V ≤ V
≤ 12V
96
IN
CM
Output Short-Circuit Current
I
0 ≤ V
≤ V
CC
7
95
OSR
RO
_______________________________________________________________________________________
3
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
UART SWITCHING CHARACTERISTICS
(V
= +5V 5ꢀ% f
= 1.8432MHz% T = T
to T
% unless otherwise noted. Typical values are measured with V
= +5V%
CC
XTL
A
MIN
MAX
CC
UART configured for 9600 baud% T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UART AC TIMING (Figure 1)
t
C
C
= 100pF
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Low to ꢁOUT Valid
CS High to ꢁOUT Tri-State
CS to SCLK Setup Time
CS to SCLK Hold Time
SCLK Fall to ꢁOUT Valid
ꢁIN to SCLK Setup Time
ꢁIN to SCLK Hold Time
SCLK Period
ꢁV
LOAꢁ
t
= 100pF% R
= 100pF
= 10kΩ
CS
TR
LOAꢁ
MAX3140
t
100
0
CSS
t
CSH
t
C
LOAꢁ
100
ꢁO
t
100
0
ꢁS
ꢁH
t
t
238
100
100
CP
CH
SCLK High Time
t
SCLK Low Time
t
CL
SCLK Rising Ddge to CS
FaIling
t
100
ns
ns
CS0
CS1
CS Rising Ddge to SCLK
Rising
t
200
200
t
ns
ns
ns
CS High Pulse Width
Output Rise Time
Output Fall Time
CSW
t
r
10
10
TX% RTS% ꢁOUT; C
= 100pF
LOAꢁ
t
f
TX% RTS% ꢁOUT% IRQ; C
= 100pF
LOAꢁ
4
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
SWITCHING CHARACTERISTICS—SRL = Unconnected
(V
= +5V 5ꢀ% T = T
A
to T
% unless otherwise noted. Typical values are at V
= +5V and T = +25°C.)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
500
500
TYP
2030
2030
MAX
2600
2600
UNITS
t
t
ꢁPLH
ꢁPHL
Figures 3 and 5% R
= 54Ω%
= 54Ω%
= 54Ω%
ꢁIFF
ꢁriver Input to Output
ns
C
= C = 100pF
L1
L2
ꢁriver Output Skew
Figures 3 and 5% R
ꢁIFF
t
-3
200
ns
ns
ꢁSKDW
C
L1
= C = 100pF
t
- t
L2
ꢁPLH ꢁPHL
|
|
Figures 3 and 5% R
ꢁIFF
ꢁriver Rise or Fall Time
t % t
ꢁR ꢁF
667
115
1320
2500
C
L1
= C = 100pF
L2
Maximum ꢁata Rate
f
kbps
ns
MAX
ꢁriver Dnable to Output High
ꢁriver Dnable to Output Low
ꢁriver ꢁisable Time from Low
ꢁriver ꢁisable Time from High
t
Figures 4 and 6% C = 100pF% S2 closed
3500
3500
100
ꢁZH
L
t
Figures 4 and 6% C = 100pF% S1 closed
ns
ꢁZL
ꢁLZ
ꢁHZ
L
t
Figures 4 and 6% C = 15pF% S1 closed
ns
L
t
Figures 4 and 6% C = 15pF% S2 closed
100
ns
L
t
t
%
Figures 7 and 9% V
rise and fall time of V ≤ 15ns
≥ 2.0V%
Iꢁ
RPLH
Iꢁ
|
|
Receiver Input to Output
127
3
200
30
ns
ns
RPHL
t
- t
ꢁifferential
Figures 7 and 9% V
rise and fall time of V ≤ 15ns
Iꢁ
≥ 2.0V%
RPLH RPHL
Iꢁ
|
|
|
|
t
RSKꢁ
Receiver Skew
Receiver Dnable to Output Low
t
Figures 2 and 8% C = 100pF% S1 closed
20
20
20
50
50
50
ns
ns
ns
RZL
L
Receiver Dnable to Output High
Receiver ꢁisable Time from Low
t
Figures 2 and 8% C = 100pF% S2 closed
L
RZH
t
Figures 2 and 8% C = 100pF% S1 closed
L
RLZ
Receiver ꢁisable Time from
High
t
Figures 2 and 8% C = 100pF% S2 closed
L
20
50
ns
ns
ns
RHZ
Time to Shutdown
t
(Note 5)
50
200
600
SHꢁN
ꢁriver Dnable from Shutdown to
Output High
t
t
Figures 4 and 6% C = 15pF% S2 closed
6000
ꢁZH(SHꢁN)
L
ꢁriver Dnable from Shutdown to
Output Low
t
Figures 4 and 6% C = 15pF% S1 closed
6000
3500
3500
ns
ns
ns
ꢁZL(SHꢁN)
L
Receiver Dnable from Shutdown
to Output High
Figures 2 and 8% C = 100pF% S2 closed
RZH(SHꢁN)
L
Receiver Dnable from Shutdown
to Output Low
t
Figures 2 and 8% C = 100pF% S1 closed
L
RZL(SHꢁN)
_______________________________________________________________________________________
5
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
SWITCHING CHARACTERISTICS—SRL = V
CC
(V
= +5V 5ꢀ% T = T
A
to T
% unless otherwise noted. Typical values are at V
= +5V and T = +25°C.)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
250
250
TYP
720
720
MAX
1000
1000
UNITS
t
t
ꢁPLH
ꢁPHL
Figures 3 and 5% R
= 54Ω%
= 54Ω%
= 54Ω%
ꢁIFF
ꢁriver Input to Output
ꢁriver Output Skew
ns
C
= C = 100pF
L1
L2
Figures 3 and 5% R
ꢁIFF
t
-3
100
950
ns
ns
ꢁSKDW
C
L1
= C = 100pF
t
- t
L2
ꢁPLH ꢁPHL
|
|
MAX3140
Figures 3 and 5% R
ꢁIFF
ꢁriver Rise or Fall Time
t
t
200
500
530
ꢁR% ꢁF
C
L1
= C = 100pF
L2
Maximum ꢁata Rate
f
kbps
ns
MAX
ꢁriver Dnable to Output High
ꢁriver Dnable to Output Low
ꢁriver ꢁisable Time from Low
ꢁriver ꢁisable Time from High
t
Figures 4 and 6% C = 100pF% S2 closed
2500
2500
100
ꢁZH
L
t
Figures 4 and 6% C = 100pF% S1 closed
ns
ꢁZL
ꢁLZ
ꢁHZ
L
t
Figures 4 and 6% C = 15pF% S1 closed
ns
L
t
Figures 4 and 6% C = 15pF% S2 closed
L
100
ns
t
t
%
Figures 7 and 9% V ≥ 2.0V%
RPLH
Iꢁ
|
|
Receiver Input to Output
127
3
200
30
ns
ns
RPHL
rise and fall time of V ≤ 15ns
Iꢁ
t
- t
ꢁifferential
Figures 7 and 9% V ≥ 2.0V%
Iꢁ
RPLH RPHL
|
|
|
|
t
RSKꢁ
Receiver Skew
Receiver Dnable to Output Low
rise and fall time of V ≤ 15ns
Iꢁ
t
Figures 2 and 8% C = 100pF% S1 closed
20
20
20
50
50
50
ns
ns
ns
RZL
L
Receiver Dnable to Output High
Receiver ꢁisable Time from Low
t
Figures 2 and 8% C = 100pF% S2 closed
L
RZH
t
Figures 2 and 8% C = 100pF% S1 closed
L
RLZ
Receiver ꢁisable Time from
High
t
Figures 2 and 8% C = 100pF% S2 closed
L
20
50
ns
RHZ
Time to Shutdown
t
(Note 5)
50
200
600
ns
ns
SHꢁN
ꢁriver Dnable from Shutdown to
Output High
t
t
Figures 4 and 6% C = 15pF% S2 closed
4500
ꢁZH(SHꢁN)
L
ꢁriver Dnable from Shutdown to
Output Low
t
Figures 4 and 6% C = 15pF% S1 closed
4500
ns
ꢁZL(SHꢁN)
L
Receiver Dnable from Shutdown
to Output High
Figures 2 and 8% C = 100pF% S2 closed
3500
3500
ns
ns
RZH(SHꢁN)
L
Receiver Dnable from Shutdown
to Output Low
t
Figures 2 and 8% C = 100pF% S1 closed
L
RZL(SHꢁN)
6
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
SWITCHING CHARACTERISTICS—SRL = GND
(V
= +5V 5ꢀ% T = T
A
to T
% unless otherwise noted. Typical values are at V
= +5V and T = +25°C.)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
34
MAX
60
UNITS
t
ꢁPLH
ꢁPHL
Figures 3 and 5% R
= 54Ω%
= 54Ω%
= 54Ω%
ꢁIFF
ꢁriver Input to Output
ꢁriver Output Skew
ns
C
= C = 100pF
L1
L2
t
34
60
Figures 3 and 5% R
ꢁIFF
t
-2.5
14
10
25
ns
ns
ꢁSKDW
C
L1
= C = 100pF
t
- t
L2
ꢁPLH ꢁPHL
|
|
Figures 3 and 5% R
ꢁIFF
ꢁriver Rise or Fall Time
t
t
ꢁR% ꢁF
C
L1
= C = 100pF
L2
Maximum ꢁata Rate
f
10
Mbps
ns
MAX
ꢁriver Dnable to Output High
ꢁriver Dnable to Output Low
ꢁriver ꢁisable Time from Low
ꢁriver ꢁisable Time from High
t
Figures 4 and 6% C = 100pF% S2 closed
150
150
100
100
ꢁZH
L
t
Figures 4 and 6% C = 100pF% S1 closed
ns
ꢁZL
ꢁLZ
ꢁHZ
L
t
Figures 4 and 6% C = 15pF% S1 closed
ns
L
t
Figures 4 and 6% C = 15pF% S2 closed
L
ns
t
t
%
Figures 7 and 9% V ≥ 2.0V%
RPLH
Iꢁ
|
|
Receiver Input to Output
106
0
150
10
ns
ns
RPHL
rise and fall time of V ≤ 15ns
Iꢁ
t
- t
ꢁifferential
Figures 7 and 9% V ≥ 2.0V%
Iꢁ
RPLH RPHL
|
|
|
|
t
RSKꢁ
Receiver Skew
Receiver Dnable to Output Low
rise and fall time of V ≤ 15ns
Iꢁ
t
Figures 2 and 8% C = 100pF% S1 closed
20
20
20
50
50
50
ns
ns
ns
RZL
L
Receiver Dnable to Output High
Receiver ꢁisable Time from Low
t
Figures 2 and 8% C = 100pF% S2 closed
L
RZH
t
Figures 2 and 8% C = 100pF% S1 closed
L
RLZ
Receiver ꢁisable Time from
High
t
Figures 2 and 8% C = 100pF% S2 closed
L
20
50
ns
RHZ
Time to Shutdown
t
(Note 5)
50
200
600
250
ns
ns
SHꢁN
ꢁriver Dnable from Shutdown to
Output High
t
t
Figures 4 and 6% C = 15pF% S2 closed
L
ꢁZH(SHꢁN)
ꢁriver Dnable from Shutdown to
Output Low
t
Figures 4 and 6% C = 15pF% S1 closed
250
ns
ꢁZL(SHꢁN)
L
Receiver Dnable from Shutdown
to Output High
Figures 2 and 8% C = 100pF% S2 closed
3500
3500
ns
ns
RZH(SHꢁN)
L
Receiver Dnable from Shutdown
to Output Low
t
Figures 2 and 8% C = 100pF% S1 closed
L
RZL(SHꢁN)
Note 1: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device
ground unless otherwise noted.
Note 2: ΔV
and ΔV
are the changes in V and V % respectively% when the ꢁl input changes state.
Oꢁ OC
Oꢁ
OC
Note 3: The SRL pin is internally biased to V /2 by a 100kΩ/100kΩ resistor-divider. It is guaranteed to be V /2 if left unconnected.
CC
CC
Note 4: Maximum current level applies to peak current just prior to foldback-current limiting; minimum current level applies during
current limiting.
Note 5: The device is put into shutdown by bringing RE high and ꢁD low. If the enable inputs are in this state for less than 50ns% the
device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least 600ns% the device is guaranteed
to have entered shutdown.
_______________________________________________________________________________________
7
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Typical Operating Characteristics
(V
CC
= +5V% T = +25°C% unless otherwise noted.)
A
UART SUPPLY CURRENT
vs. TEMPERATURE
UART SHUTDOWN CURRENT
vs. TEMPERATURE
UART SUPPLY CURRENT
vs. BAUD RATE
1000
10
400
350
1.8432MHz CRYSTAL
1.8432 MHz
CRYSTAL
1.8432MHz CRYSTAL
TRANSMITTING AT 115.2 kbps
900
800
700
600
9
8
7
6
TRANSMITTING
MAX3140
300
250
200
150
100
50
STANDBY
500
400
300
5
4
3
200
100
0
2
1
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
100
1000
10k
100k
1M
TEMPERATURE (°C)
TEMPERATURE (°C)
BAUD RATE (bps)
RS-485 TRANSCEIVER NO-LOAD
SUPPLY CURRENT vs. TEMPERATURE
UART SUPPLY CURRENT vs.
EXTERNAL CLOCK FREQUENCY
TX, RTS, DOUT OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE
525
700
600
90
80
70
60
50
A: SRL = GND
500
475
DE = V
CC
RTS
TX
500
450
425
400
375
350
A
400
300
200
100
0
DE = GND
B
DOUT
40
30
20
10
0
A
B
325
300
B: SRL = OPEN OR V
CC
-60 -40 -20
0
20 40 60 80 100
0
1
2
3
4
5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT LOW VOLTAGE (V)
TEMPERATURE (°C)
EXTERNAL CLOCK FREQUENCY (MHz)
RS-485 OUTPUT CURRENT
vs. RECEIVER OUTPUT HIGH VOLTAGE
RS-485 TRANSCEIVER SHUTDOWN
CURRENT vs. TEMPERATURE
RS-485 OUTPUT CURRENT
vs. RECEIVER OUTPUT LOW VOLTAGE
30
25
20
15
10
5
20
18
60
50
40
30
20
10
0
16
14
12
10
8
6
4
2
0
0
0
1
2
3
4
5
-60 -40 -20
0
20 40 60 80 100
0
1
2
3
4
5
OUTPUT HIGH VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
8
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Typical Operating Characteristics (continued)
(V
CC
= +5V% T = +25°C% unless otherwise noted.)
A
RS-485 RECEIVER OUTPUT LOW VOLTAGE
vs. TEMPERATURE
RS-485 RECEIVER OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
RS-485 RECEIVER PROPAGATION DELAY
(500kbps MODE) vs. TEMPERATURE
0.50
4.5
4.4
4.3
140
I
= 8mA
RO
I
= 8mA
C
LOAD
= 100pF
RO
0.45
0.40
135
130
0.35
0.30
0.25
4.2
4.1
125
120
115
4.0
3.9
3.8
0.20
0.15
0.10
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RS-485 DRIVER PROPAGATION DELAY
(500kbps MODE) vs. TEMPERATURE
RS-485 RECEIVER PROPAGATION DELAY
(10Mbps MODE) vs. TEMPERATURE
RS-485 DRIVER PROPAGATION DELAY
(115kbps MODE) vs. TEMPERATURE
920
880
840
800
760
720
680
640
600
560
520
112
2.20
2.15
2.10
2.05
2.00
1.95
C
= 100pF
LOAD
R = 54Ω
t
R = 54Ω
t
110
108
106
104
102
100
98
96
94
1.90
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RS-485 DRIVER DIFFERENTIAL
OUTPUT VOLTAGE vs. TEMPERATURE
RS-485 DRIVER OUTPUT CURRENT
vs. DIFFERENTIAL OUTPUT VOLTAGE
RS-485 DRIVER PROPAGATION DELAY
(10Mbps MODE) vs. TEMPERATURE
100
1.90
1.89
60
55
50
45
R = 54Ω
t
R = 54Ω
t
10
1
1.88
1.87
1.86
1.85
1.84
1.83
40
35
30
25
0.1
0.01
20
0
1
2
3
4
5
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Typical Operating Characteristics (continued)
(V
CC
= +5V% T = +25°C% unless otherwise noted.)
A
RS-485 RECEIVER PROPAGATION DELAY
OUTPUT CURRENT vs.
RS-485 DRIVER OUTPUT LOW VOLTAGE
OUTPUT CURRENT vs.
RS-485 DRIVER OUTPUT HIGH VOLTAGE
(SRL = GND)
MAX3140-21
140
-100
-90
-80
-70
120
100
MAX3140
V - V
A
B
(2V/div)
-60
-50
80
60
-40
-30
RO
(5V/div)
40
20
0
-20
-10
0
0
2
4
6
8
10
12
-8
-6
-4
-2
0
2
4
6
50ns/div
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
RS-485 DRIVER PROPAGATION DELAY
RS-485 RECEIVER PROPAGATION DELAY
(SRL = OPEN)
(SRL = OPEN OR V
)
CC
MAX3140-22
MAX3140-23
DI
(5V/div)
V - V
A
B
(2V/div)
V - V
Y
Z
(2.5V/div)
RO
(5V/div)
50ns/div
2μs/div
RS-485 DRIVER PROPAGATION DELAY
RS-485 DRIVER PROPAGATION DELAY
(SRL = V
(SRL = GND)
)
CC
MAX3140-24
MAX3140-25
DI
DI
(5V/div)
(5V/div)
V - V
Y
V - V
Z
Y
Z
(2.5V/div)
(2.5V/div)
500ns/div
50ns/div
10 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Pin Description
PIN
NAME
FUNCTION
FULL
HALF
DUPLEX
DUPLEX
UART Crystal Connection. Leave X2 unconnected for external clock. See the Crystals%
Oscillators% and Ceramic Resonators section.
1
1
X2
UART Crystal Connection. X1 also serves as an external clock input. See the Crystals%
Oscillators% and Ceramic Resonators section.
2
3
4
2
3
4
X1
UART Clear-to-Send Active-Low Input. Read via the CTS bit.
CTS
RTS
UART Request-to-Send Active-Low Output. Controlled by the RTS bit. Use to control the dri-
ver enable in RS-485 networks.
UART Asynchronous Serial-ꢁata (receiver) Input. The serial information received from the modem
or RS-232/RS-485 receiver. A transition on RX while in shutdown generates an interrupt (Table 1).
5
6
7
8
9
5
6
7
8
9
RX
TX
UART Asynchronous Serial-ꢁata (transmitter) Output
RS-485 Half/Full-ꢁuplex Selector Pin. Connect H/F to V
for half-duplex mode; connect H/F
CC
H/F
GNꢁ
RO
to GNꢁ or leave it unconnected for full-duplex mode.
Ground
RS-485 Receiver Output. When RE is low and if A - B ≥ -50mV% RO will be high; if A - B ≤
-200mV% RO will be low.
RS-485 Receiver Output Dnable. ꢁrive RE low to enable RO; RO is high impedance when RE
is high. ꢁrive RE high and ꢁD low to enter low-power shutdown mode.
10
11
12
10
11
12
RE
ꢁD
ꢁI
RS-485 ꢁriver Output Dnable. ꢁrive ꢁD high to enable driver outputs. These outputs are high
impedance when ꢁD is low. ꢁrive RE high and ꢁD low to enter low-power shutdown mode.
RS-485 ꢁriver Input. With ꢁD high% a low on ꢁI forces noninverting output low and inverting
output high. Similarly% a high on ꢁI forces noninverting output high and inverting output low.
RS-485 Transceiver Slew-Rate-Limit Selector Pin. Connect SRL to GNꢁ for a 10Mbps com-
13
13
SRL
munication rate% connect SRL to V
for a 500kbps rate% or leave SRL unconnected for a
CC
115kbps rate.
14
15
14
15
N.C.
TXP
No Connection. Not internally connected.
RS-485 Transmitter Phase. Connect TXP to GNꢁ or leave it unconnected for normal transmit-
ter phase/polarity. Connect TXP to V
to invert the transmitter phase/polarity.
CC
16
—
17
18
—
19
—
20
—
—
16
17
—
18
—
19
—
20
Y
Y
RS-485 Noninverting ꢁriver Output
RS-485 Noninverting Receiver Input and RS-485 Noninverting ꢁriver Output*
No Connection. Not internally connected.
RS-485 Inverting ꢁriver Output
N.C.
Z
Z
RS-485 Inverting Receiver Input and RS-485 Inverting ꢁriver Output*
RS-485 Inverting Receiver Input
B
B
RS-485 Receiver Input Resistors*
A
RS-485 Noninverting Receiver Input
A
RS-485 Receiver Input Resistors*
______________________________________________________________________________________ 11
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Pin Description (continued)
PIN
NAME
FUNCTION
FULL
HALF
DUPLEX
DUPLEX
RS-485 Receiver Phase. Connect RXP to GNꢁ or leave it unconnected for normal receiver
21
21
RXP
phase/polarity. Connect RXP to V
to invert the receiver phase/polarity.
CC
22
23
24
25
22
23
24
25
V
CC
Positive Supply (4.75V to 5.25V)
MAX3140
ꢁIN
UART SPI/MICROWIRD Serial-ꢁata Input. Schmitt-trigger input.
UART SPI/MICROWIRD Serial-ꢁata Output. High impedance when CS is high.
UART SPI/MICROWIRD Serial-Clock Input. Schmitt-trigger input.
ꢁOUT
SCLK
UART Active-Low Chip-Select Input. ꢁOUT goes high impedance when CS is high. IRQ% TX%
and RTS are always active. Schmitt-trigger input.
26
27
26
27
CS
UART Active-Low Interrupt Output. Open-drain interrupt output to microprocessor.
IRQ
UART Hardware Shutdown Input. When shut down (SHDN = 0)% the UART oscillator turns off
immediately without waiting for the current transmission to end% reducing the supply current
to just leakage currents.
28
28
SHDN
*In half-duplex mode% the driver outputs serve as receiver inputs. The full-duplex receiver inputs ( A and B) still have a 1/8-unit load% but
do not affect the receiver output.
Transceiver Function Tables
RECEIVING
INPUTS
TRANSMITTING
INPUTS
ꢁD
OUTPUTS
OUTPUTS
RXP
0
ꢁD
X
A-B
≥ -0.05V
≤ -0.2V
≥ -0.05V
≤ -0.2V
X
Y-Z
X
RO
1
H/F
0
RE
0
TXP
0
ꢁI
1
Z
Y
RE
X
1
1
1
1
0
0
0
1
0
0
0
X
X
0
0
X
0
1
0
0
1
0
X
X
0
1
X
1
1
0
0
1
0
1
0
X
X
1
1
X
0
1
0
0
X
≥ -0.05V
≤ -0.2V
≥ -0.05V
≤ -0.2V
1
X
0
X
X
High-Z
High-Z
1
0
0
X
X
0
X
1
Shutdown (High-Z)
1
1
0
X
X
0
1
1
0
X
X
1
Open/
Shorted
0
1
0
0
0
1
0
0
0
X
X
X
X
1
1
0
Open/
Shorted
X
Open/
Shorted
X
Open/
Shorted
1
X
X
1
X
X
0
1
1
X
1
0
X
X
X
0
X
High-Z
Shutdown
(High-Z)
X
12 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Y
1k
TEST POINT
R
R
RECEIVER
OUTPUT
V
CC
S1
S2
V
OD
C
L
15pF
1k
V
OC
Z
Figure 1. ꢁriver ꢁC Test Load
Figure 2. Receiver Dnable/ꢁisable Timing Test Load
V
CC
DE
C
L1
V
CC
S1
S2
500Ω
Y
Z
R
DIFF
DI
OUTPUT
UNDER TEST
V
ID
C
L
C
L2
Figure 4. ꢁriver Dnable/ꢁisable Timing Test Load
Figure 3. ꢁriver Timing Test Circuit
3V
3V
DE
DI
1.5V
1.5V
1.5V
1.5V
V
0
0
t
t
PHL
PLH
t
t
, t
LZ
ZL(SHDN) ZL
Z
Y, Z
V
O
2.3V
+0.5V
OL
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
V
OL
Y
1/2 V
O
1/2 V
10%
O
V
= V (Y) - V (Z)
DIFF
Y, Z
V
O
0
O
V
-0.5V
OH
2.3V
V
DIFF
90%
90%
0
10%
-V
t
, t
t
HZ
ZH(SHDN) ZH
t
t
F
R
t
t
- t
SKEW = | PLH PHL |
Figure 6. ꢁriver Dnable and ꢁisable Times
______________________________________________________________________________________ 13
Figure 5. ꢁriver Propagation ꢁelays
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
3V
RE
1.5V
1.5V
0
V
OH
RO
1.5V
1.5V
V
OL
OUTPUT
t
t
, t
LZ
ZL(SHDN) ZL
V
RO
CC
t
t
PLH
PHL
A
B
1V
1.5V
V
V
+ 0.5V
- 0.5V
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
OL
MAX3140
-1V
INPUT
RO
1.5V
OH
0
t
, t
t
HZ
ZH(SHDN) ZH
Figure 8. Receiver Dnable and ꢁisable Times
Figure 7. Receiver Propagation ꢁelays
B
RECEIVER
OUTPUT
V
ID
R
ATE
A
Figure 9. Receiver Propagation ꢁelay Test Circuit
pair reversal. The slew rate of the RS-485/RS-422 trans-
ceiver is selectable% limiting the maximum data rate to
115kbps% 500kbps% or 10Mbps. The RS-485/RS-422 dri-
vers are output short-circuit current limited% and thermal
shutdown circuitry protects the RS-485/RS-422 drivers
against excessive power dissipation.
_______________Detailed Description
The MAX3140 combines an SPI/QSPI/MICROWIRD-
compatible UART (MAX3100) and an RS-485/RS-422
transceiver (MAX3089) in one package. The UART sup-
ports data rates up to 230k baud for both standard
UART bit streams as well as IrꢁA% and includes an
8-word receive FIFO. Also included is a parity-bit inter-
rupt useful in 9-bit address recognition.
The UART and RS-485/RS422 functions can be used
together or independently since the two functions only
share supply and ground connections. This part oper-
ates from a single +5V supply.
The RS-485/RS-422 transceiver has a true fail-safe
receiver and allows up to 256 transceivers on the bus.
Other features include pin-selectable full/half-duplex
operation and a phase control to correct for twisted-
14 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
SPI Interface
The MAX3140 is compatible with SPI% QSPI (CPOL = 0%
CPHA = 0)% and MICROWIRD serial-interface standards
(Figure 11). The MAX3140 has a unique full-duplex
architecture that expects a 16-bit word for ꢁIN and
simultaneously produces a 16-bit word for ꢁOUT
regardless of which read/write register used. The ꢁIN
stream is monitored for its first two bits to tell the UART
the type of data transfer being executed (see the
WRITD CONFIGURATION register% RDAꢁ CONFIG-
URATION register% WRITD ꢁATA register% and RDAꢁ
ꢁATA register sections). ꢁIN (MOSI) is latched on
UART
The universal asynchronous receiver transmitter
(UART) interfaces the SPI/MICROWIRD-compatible syn-
chronous serial data from a microprocessor (µP) to
asynchronous% serial-data communication ports (RS-
485% IrꢁA). Figure 10 shows the MAX3140 functional
diagram. Included in the UART function is an
SPI/MICROWIRD interface% a baud-rate generator% and
an interrupt generator.
A
P
r
RX BUFFER
9
MAX3140
RE
RO
9
9
INTERRUPT
LOGIC
B
Y
P
RX FIFO
IRQ
r
RXP
9
9
P
r
RX
RX SHIFT REGISTSER
GND
DOUT
X2
X1
BAUD-RATE
GENERATOR
4
SPI
INTERFACE
SCLK
CS
TXP
DI
P
t
TX SHIFT REGISTSER
TX
9
Z
P
t
DIN
TX BUFFER
SRL
DE
9
CTS
RTS
H/F
I/O
NOTE: SWITCH POSITIONS INDICATE H/F = GND
Figure 10. Functional ꢁiagram
MSB 14
MSB 14
13
13
12
12
11
11
10
10
9
8
8
7
6
5
4
3
2
1
LSB
LSB
DIN
9
7
6
5
4
3
2
1
DOUT
CS
SCLK
COMPATIBLE
WITH MAX3140
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 1, CPHA = 1)
SCLK
NOT COMPATIBLE
WITH MAX3140
SCLK
SCLK
Figure 11. Compatible CPOL and CPHA Modes
______________________________________________________________________________________ 15
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
SCLK’s rising edge. ꢁOUT (MISO) is read into the µP
on SCLK’s rising edge. The first bit (bit 15) of ꢁOUT
transitions on CS’s falling edge% and bits 14–0 transition
on SCLK’s falling edge. Figure 12 shows the detailed
serial timing specifications for the synchronous SPI
port.
clearing of internal registers% are executed only on CS’s
rising edge. Dvery time CS goes low% a new 16-bit
stream is expected. Figure 13 shows an example of
using the WRITD CONFIGURATION register.
Table 1 describes the bits located in the WRITD CON-
FIGURATION% RDAꢁ CONFIGURATION% WRITD ꢁATA%
and RDAꢁ ꢁATA registers. This table also describes
whether the bit is a read or write bit and what the
power-on reset states (POR) of the bits are. Figure 14
shows an example of parity and word length control.
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit)%
the sequence is aborted (i.e.% data does not get written
to individual registers). Most operations% such as the
MAX3140
CS
• • •
t
t
t
t
CSH
CS1
CSS
CH
t
t
CL
CSO
SCLK
• • •
t
DS
t
DH
DIN
• • •
• • •
t
DV
t
t
TR
DO
DOUT
Figure 12. ꢁetailed Serial Timing Specifications for the Synchronous Port
DATA
UPDATED
CS
SCLK
1
2
3
4
5
6
7
8
RAM
0
9
10
11
12
13
14
15
16
1
1
T
FEN SHDN
TM
0
RM
PM
0
IR
0
ST
PE
L
0
B3
B2
B1
0
B0
DIN
DOUT
R
0
0
0
0
0
0
0
0
Figure 13. SPI Interface (Write Configuration)
PE = 0, L = 0
START D0
D1
D2
D2
D3
D3
D4
D5
D5
D6
D6
D7
STOP STOP IDLE
IDLE
IDLE
PE = 0, L = 1
START D0
START D0
D1
D4
D4
D4
STOP STOP IDLE
PE = 1, L = 0
D1
D2
D2
D3
D3
D5
D5
D6
D6
D7
Pt
STOP STOP IDLE
IDLE
PE = 1, L = 1
START D0
D1
Pt
STOP STOP IDLE
IDLE
TIME
SECOND STOP BIT IS OMITTED IF ST = 0.
Figure 14. Parity and Word Length Control
16 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Table 1. Bit Descriptions
BIT
NAME
BIT
TYPE
POR
STATE
DESCRIPTION
B0–B3
B0–B3
write
read
0000
0000
Baud-Rate ꢁivisor Select Bits. Sets the baud clock’s value (Table 6).
Baud-Rate ꢁivisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.
No
change
Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic
high).
CTS
read
write
read
Transmit-Buffer Register. Dight data bits written into the transmit-buffer register. ꢁ7t is ignored
when L = 1.
ꢁ0t–ꢁ7t
ꢁ0r–ꢁ7r
XXXXXXXX
00000000
Dight data bits read from the receive FIFO or the receive-buffer register. When L = 1% ꢁ7r is
always 0.
write
read
write
read
0
0
0
0
FEN
FEN
IR
FIFO Dnable. Dnables the receive FIFO when FEN = 0. When FEN = 1% FIFO is disabled.
FIFO-Dnable Readback. FEN’s state is read.
Dnables the IrꢁA timing mode when IR = 1.
IR
Reads the value of the IR bit.
Bit to set the word length of the transmitted or received data. L = 0 results in 8-bit words
(9-bit words if PD = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PD = 1).
L
L
write
read
0
0
Reads the value of the L bit.
Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PD = 1. In 9-bit net-
works% the MAX3140 does not calculate parity. If PD = 0% then this bit (Pt) is ignored in transmit
mode (see the 9-Bit Networks section).
Pt
Pr
write
read
X
X
Receive-Parity Bit. This bit is the extra bit received if PD = 1. Therefore% PD = 1 results in 9-bit
transmissions (L = 0). If PD = 0% then Pr is set to 0. Pr is stored in the FIFO with the receive
data (see the 9-Bit Networks section).
Parity-Dnable Bit. Appends the Pt bit to the transmitted data when PD = 1% and sends the Pt
bit as written. No parity bit is transmitted when PD = 0. With PD = 1% an extra bit is expected to
be received. This data is put into the Pr register. Pr = 0 when PD = 0. The MAX3140 does not
calculate parity.
PD
write
0
PD
PM
PM
read
write
read
0
0
0
Reads the value of the Parity-Dnable bit.
Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 7).
Reads the value of the PM bit (Table 7).
Receive Bit or FIFO Not Dmpty Flag. R = 1 means new data is available to be read or is being
read from the receive register or FIFO. If performing a RDAꢁ ꢁATA or WRITD ꢁATA operation%
the R bit will clear on the falling edge of SCLK's 16th pulse if no new data is available.
R
read
0
write
read
write
read
0
0
0
0
RM
RM
Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 7).
Reads the value of the RM bit (Table 7).
RAM
RAM
Mask for RA/FD bit. IRQ is asserted if RAM = 1 and RA/FD = 1 (Table 7).
Reads the value of the RAM bit (Table 7).
Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS
bit = 0 sets the RTS pin = logic high).
RTS
write
0
______________________________________________________________________________________ 17
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Table 1. Bit Descriptions (continued)
BIT
NAME
BIT
TYPE
POR
STATE
DESCRIPTION
Receiver-Activity/Framing-Drror Bit. In shutdown mode% this is the RA bit. In normal operation%
this is the FD bit. In shutdown mode% a transition on RX sets RA = 1. In normal mode% a fram-
ing error sets FD = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FD is set when a framing error occurs% and cleared upon receipt of the next proper-
ly framed character independent of the FIFO being enabled. When the device wakes up% it is
likely that a framing error will occur. This error is cleared with a WRITD CONFIGURATION. The
FD bit is not cleared on a RDAꢁ ꢁATA operation. When an FD is encountered% the UART
resets itself to the state where it is looking for a start bit.
RA/FD
read
0
MAX3140
Software-Shutdown Bit. Dnter software shutdown with a WRITD CONFIGURATION where
SHꢁNi = 1. Software shutdown takes effect after CS goes high% and causes the oscillator to
stop as soon as the transmitter becomes idle. Software shutdown also clears R% T% RA/FD%
ꢁ0r–ꢁ7r% ꢁ0t–ꢁ7t% Pr% Pt% and all data in the receive FIFO. RTS and CTS can be read and
updated while in shutdown. Dxit software shutdown with a WRITD CONFIGURATION where
SHꢁNi = 0. The oscillator restarts typically within 50ms of CS going high. RTS and CTS are
unaffected. Refer to the Pin ꢁescription for hardware shutdown (SHDN input).
SHꢁNi
write
read
0
0
Shutdown Read-Back Bit. The RDAꢁ CONFIGURATION register outputs SHꢁNo = 1 when the
UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is
sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This bit
is also set immediately when the device is shut down through the SHDN pin.
SHꢁNo
Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.
ST
ST
T
write
read
read
0
0
1
Reads the value of the ST bit.
Transmit-Buffer-Dmpty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.
Transmit-Dnable Bit. If TE = 1% then only the RTS pin is updated on CS’s rising edge. The con-
tents of RTS% Pt% and ꢁ0t–ꢁ7t transmit on CS’s rising edge when TE = 0.
write
0
TE
write
read
0
0
TM
TM
Mask for T Bit. IRQ is asserted if TM = 1 and T = 1 (Table 7).
Reads the value of the TM bit (Table 7).
Notice to High-Level Programmers
The proper way to implement these commands is to
use driver code—usually in the form of an assembly
language interrupt service routine and a callable rou-
tine used by high-level routines. This driver handles the
interrupts and manages the receive and transmit
buffers for the MAX3140. When a PUTCHAR executes%
this driver is called and it safely buffers any characters
received when the current character is transmitted.
Likewise% when a GDTCHAR executes% it checks its own
receive buffer before getting data from the MAX3140.
See the C-language outline of a MAX3140 software dri-
ver in Listing 1.
The MAX3140 follows the SPI convention of providing a
bidirectional data path for writes and reads. Whenever
the data is written% data is also read back. This speeds
operation over the SPI bus% as required% when operat-
ing at high baud rates. In most high-level languages%
like C% there are commands for writing and reading
stream I/O devices like the console or serial port. In C
specifically% there is a “PUTCHAR” command that
transmits a character and a “GDTCHAR” command that
receives a character. Implementing direct write and
read commands in C with no underlying driver code
causes an intended PUTCHAR command to become a
PUTGDTCHAR command. These C commands assume
that they’ll receive some form of BIOS-level support.
18 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
WRITE CONFIGURATION Register
(D15, D14 = 1, 1)
Setting the WRITD CONFIGURATION register clears the
receive FIFO and the R% T% RA/FD% ꢁ0r–ꢁ7r% ꢁ0t–ꢁ7t%
Pr% and Pt registers. Bits RTS and CTS remain
unchanged. The new configuration is valid on CS’s ris-
ing edge if the transmit buffer is empty (T = 1) and
transmission is over. If the latest transmission has not
been completed (T = 0)% the registers are updated
when the transmission is over.
Configure the UART by writing a 16-bit word to the
WRITD CONFIGURATION register% which programs the
baud rate% data-word length% parity enable% and enable
of the 8-word receive FIFO. Set bits 15 and 14 of the
ꢁIN configuration word to 1 to enable the WRITD CON-
FIGURATION mode. Bits 13–0 of the ꢁIN configuration
word set the configuration of the UART. Table 2 shows
the bit assignment for the WRITD CONFIGURATION
register. The WRITD CONFIGURATION register allows
selection between normal UART timing and IrꢁA timing%
shutdown control% and contains four interrupt mask bits.
The WRITD CONFIGURATION register bits (FEN%
SHꢁNi% IR% ST% PD% L% B3–B0) take effect after the cur-
rent transmission is over. The mask bits (TM% RM% PM%
RAM) take effect immediately after SCLK’s 16th rising
edge.
Table 2. WRITE CONFIGURATION Register Bit Assignment (D15, D14 = 1, 1)
BIT
ꢁIN
15
1
14
1
13
FEN
0
12
SHꢁNi
0
11
TM
0
10
RM
0
9
PM
0
8
RAM
0
7
IR
0
6
ST
0
5
PD
0
4
L
0
3
B3
0
2
B2
0
1
B1
0
0
B0
0
ꢁOUT
R
T
Notes:
bit 7: DIN
IR = 1% IrꢁA mode is enabled.
bit 15, 14: DIN
IR = 0% IrꢁA mode is disabled.
1% 1 = Write Configuration
bit 6: DIN
bit 13: DIN
ST = 1% Transmit two stop bits
ST = 0% Transmit one stop bit
FEN = 0% FIFO is enabled
FEN= 1% FIFO is disabled
bit 5: DIN
bit 12: DIN
PD = 1% Parity is enabled for both transmit (state of Pt) and
receive.
SHꢁNi = 1% Dnter software shutdown
SHꢁNi = 0% Dxit software shutdown
PD = 0% Parity is disabled for both transmit and receive.
bit 11: DIN
bit 4: DIN
TM = 1% Transmit-buffer-empty interrupt is enabled.
TM = 0% Transmit-buffer-empty interrupt is disabled.
L = 1% 7-bit words (8-bit words if PD = 1)
L = 0% 8-bit words (9-bit words if PD = 1)
bit 10: DIN
bit 3–0: DIN
RM = 1% ꢁata available in the receive register or FIFO interrupt
is enabled.
B3–B0 = XXXX Baud-Rate ꢁivisor select bits. See Table 6.
RM = 0% ꢁata available in the receive register or FIFO interrupt
is disabled.
bit 15: DOUT
R = 1% ꢁata is available to be read from the receive.
register or FIFO.
bit 9: DIN
PM = 1% Parity-bit-received interrupt is enabled.
PM = 0% Parity-bit-received interrupt is disabled.
R = 0% Receive register and FIFO are empty.
bit 14: DOUT
bit 8: DIN
T = 1% Transmit buffer is empty.
T = 0% Transmit buffer is full.
RAM = 1% Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
bit 13–0: DOUT
RAM = 0% Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
Zeros
______________________________________________________________________________________ 19
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Bits 15 and 14 of the ꢁOUT WRITD CONFIGURATION
word (R and T) are sent out of the MAX3140 along with
14 trailing zeros. The use of the R and T bits is optional%
but ignore the 14 trailing zeros.
READ CONFIGURATION Register (D15, D14 = 0, 1)
Use the RDAꢁ CONFIGURATION register to read back
the last configuration written to the UART. In this mode%
bits 15 and 14 of the ꢁIN configuration word are
required to be 0 and 1% respectively% to enable the
RDAꢁ CONFIGURATION mode. Clear bits 13–1 of the
ꢁIN word. Bit 0 is the test bit to put the UART in test
mode (see the Test Mode section). Table 3 shows the
bit assignment for the RDAꢁ CONFIGURATION regis-
ter.
Warning! The UART requires stable crystal oscillator
operation before configuration (typically ~25ms after
power-up). At power-up% compare the WRITD CONFIG-
URATION bits with the RDAꢁ CONFIGURATION bits in
a software loop until both match. This ensures that the
oscillator is stable and the UART is configured correctly.
MAX3140
Table 3. READ CONFIGURATION Register Bit Assignment (D15, D14 = 0, 1)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
0
L
3
2
1
0
0
ꢁIN
0
1
0
0
0
0
0
0
0
0
0
0
0
TDST
B0
ꢁOUT
R
T
SHꢁNo
IR
ST
PD
B3
B2
B1
FEN
TM
RM
PM
RAM
Notes:
bit 8: DOUT
RAM = 1% Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
bit 15: DOUT
R = 1% ꢁata is available to be read from the receive register or
FIFO.
RAM = 0% Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
R = 0% Receive register and FIFO are empty.
bit 7: DOUT
bit 14: DOUT
IR = 1% IrꢁA mode is enabled.
IR = 0% IrꢁA mode is disabled.
T = 1% Transmit buffer is empty.
T = 0% Transmit buffer is full.
bit 6: DOUT
bit 13: DOUT
ST = 1% Transmit two stop bits.
ST = 0% Transmit one stop bit.
bit 5: DOUT
FEN = 0% FIFO is enabled
FEN = 1% FIFO is disabled
bit 12: DOUT
PD = 1% Parity is enabled for both transmit (state of Pt) and
receive.
SHꢁNo = 1% Software shutdown is enabled.
SHꢁNo = 0% Software shutdown is disabled.
PD = 0% Parity is disabled for both transmit and receive.
bit 11: DOUT
bit 4: DOUT
TM = 1% Transmit-buffer-empty interrupt is enabled.
TM = 0% Transmit-buffer-empty interrupt is disabled.
L = 1% 7-bit words (8-bit words if PD = 1)
L = 0% 8-bit words (9-bit words if PD = 1)
bit 10: DOUT
bit 3–0: DOUT
RM = 1% ꢁata available in the receive register or FIFO interrupt
B3–B0 = XXXX Baud-Rate ꢁivisor select bits. See Table 6.
is enabled.
bit 15, 14: DIN
RM = 0% ꢁata available in the receive register or FIFO interrupt
is disabled.
0% 1 = Read Configuration
bit 9: DOUT
bit 13–1: DIN
Zeros
PM = 1% Parity-bit-received interrupt is enabled.
PM = 0% Parity-bit-received interrupt is disabled.
bit 0: DIN
If TDST = 1 and CS = 0% then RTS = 16xBaudCLK
TDST = 0% ꢁisables TDST mode.
20 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Test Mode
The device enters a test mode if bit 0 of the ꢁIN config-
uration word equals 1 when performing a RDAꢁ CON-
FIGURATION. In this mode% if CS = 0% the RTS pin
transmits a clock that is 16 times the baud rate. The TX
pin is low as long as CS remains low while in test mode.
Table 3 shows the bit assignment for the RDAꢁ CON-
FIGURATION register.
that is being received from the RX FIFO. Table 4 shows
the bit assignment for the WRITD ꢁATA register. To
change the RTS pin’s output state without transmitting
data% set the TE bit high. If performing a WRITD ꢁATA
operation% the R bit clears on the falling edge of SCLK’s
16th clock pulse if no new data is available.
READ DATA Register (D15, D14 = 0, 0)
Use the RDAꢁ ꢁATA register for receiving data from
the RX FIFO. When using this register% bits 15 and 14 of
ꢁIN must both be 0. Clear bits 13–0 of the ꢁIN RDAꢁ
ꢁATA word. Table 5 shows the bit assignments for the
RDAꢁ ꢁATA register. Reading all available data clears
the R bit and interrupt IRQ. If performing a RDAꢁ ꢁATA
operation% the R bit clears on the falling edge of SCLK’s
16th clock pulse if no new data is available.
WRITE DATA Register (D15, D14 = 1, 0)
Use the WRITD ꢁATA register for transmitting to the TX
buffer and receiving from the RX buffer (and RX FIFO
when enabled). When using this register% the ꢁIN and
ꢁOUT WRITD ꢁATA words are used simultaneously
and bits 13–11 for both the ꢁIN and ꢁOUT WRITD
ꢁATA words are meaningless zeros. The ꢁIN WRITD
ꢁATA word contains the data that is being transmitted%
and the ꢁOUT WRITD ꢁATA word contains the data
Table 4. WRITE DATA Register Bit Assignment (D15, D14 = 1, 0)
BIT
ꢁIN
15
1
14
0
13
0
12
0
11
0
10
TE
9
8
7
6
5
4
3
2
1
0
RTS
CTS
Pt
Pr
ꢁ7t
ꢁ7r
ꢁ6t
ꢁ6r
ꢁ5t
ꢁ5r
ꢁ4t
ꢁ4r
ꢁ3t
ꢁ3r
ꢁ2t
ꢁ2r
ꢁ1t
ꢁ1r
ꢁ0t
ꢁ0r
ꢁOUT
R
T
0
0
0
RA/FD
Notes:
bit 15: DOUT
R = 1% ꢁata is available to be read from the receive register or
FIFO.
5, 14: DIN
1% 0 = Write ꢁata
R = 0% Receive register and FIFO are empty.
bit 13–11: DIN
bit 14: DOUT
Zeros
T = 1% Transmit buffer is empty.
T = 0% Transmit buffer is full.
bit 10: DIN
TE = 1% ꢁisables transmit% and only RTS will be updated.
TE = 0% Dnables transmit.
bit 13–11: DOUT
Zeros
bit 9: DIN
bit 10: DOUT
RTS = 1% Configures RTS = 0 (Logic Low).
RTS = 0% Configures RTS = 1 (Logic High).
RA/FD = Receive-activity (UART shutdown)/Framing-error
(normal operation) bit.
bit 8: DIN
bit 9: DOUT
Pt = 1% Transmit parity bit is high. If PD = 1% a high parity bit will
be transmitted. If PD = 0% then no parity bit will be transmitted.
CTS = CTS input state. If CTS = 0% then CTS = 1 and vice versa.
bit 8: DOUT
Pt = 0% Transmit parity bit is low. If PD = 1% a low parity bit will be
transmitted. If PD = 0% then no parity bit will be transmitted.
Pr = Received parity bit. This is only valid if PD = 1.
bit 7–0: DOUT
bit 7–0: DIN
ꢁ7t–ꢁ0t = Received ꢁata bits. ꢁ7r = 0 for L = 1.
ꢁ7t–ꢁ0t = Transmitting ꢁata bits. ꢁ7t is ignored when L = 1.
______________________________________________________________________________________ 21
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Table 5. READ DATA Register Bit Assignment (D15, D14 = 0, 0)
BIT
ꢁIN
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
ꢁOUT
R
T
0
0
0
RA/FD
CTS
Pr
ꢁ7r
ꢁ6r
ꢁ5r
ꢁ4r
ꢁ3r
ꢁ2r
ꢁ1r
ꢁ0r
Notes:
bit 13–11: DOUT
Zeros
bit 15, 14: DIN
MAX3140
0% 0 = Read ꢁata
bit 10: DOUT
RA/FD = Receive-activity (UART shutdown)/Framing-error
(normal operation) bit
bit 13–0: DIN
Zeros
bit 9: DOUT
bit 15: DOUT
CTS = CTS input state. If CTS = 0% then CTS = 1 and vice versa.
R = 1% ꢁata is available to be read from the receive register or
FIFO.
bit 8: DOUT
Pr = Received parity bit. This is only valid if PD = 1.
R = 0% Receive register and FIFO are empty.
bit 7–0: DOUT
bit 14: DOUT
ꢁ7t–ꢁ0t = Received ꢁata bits. ꢁ7r = 0 for L = 1.
T = 1% Transmit buffer is empty.
T = 0% Transmit buffer is full.
Baud-Rate Generator
The baud-rate generator determines the rate at which
the transmitter and receiver operate. Bits B3–B0 in the
WRITD CONFIGURATION register determine the baud-
rate divisor (BRꢁ)% which divides the X1 oscillator
frequency. The on-board oscillator operates with either
a 1.8432MHz or a 3.6864MHz crystal% or is driven at X1
with a 45ꢀ to 55ꢀ duty-cycle square wave. Table 6
shows baud-rate divisors for given input codes% as well
as the baud rate for 1.8432MHz and 3.6864MHz crys-
tals. The generator’s clock is 16 times the baud rate.
Table 6. Baud-Rate Selection Table*
BAUD
RATE
BAUD
RATE
BAUD
B3 B2 B1 B0
DIVISION
RATIO
(f
OSC
=
(f
OSC
=
1.8432MHz) 3.6864MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0**
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
115.2k**
57.6k
28.8k
14.4k
7200
3600
1800
900
230.4k**
115.2k
57.6k
28.8k
14.4k
7200
3600
1800
76.8k
38.4k
19.2k
9600
4800
2400
1200
600
4
8
16
32
64
128
3
Interrupt Sources and Masks
Using the RDAꢁ ꢁATA or WRITD ꢁATA register clears
the interrupt IRQ% assuming the conditions that initiated
the interrupt no longer exist. Table 7 gives the details
for each interrupt source. Figure 15 shows the function-
al diagram for the interrupt sources and mask blocks.
38.4k
19.2k
9600
4800
2400
1200
600
6
Two examples of setting up an IRQ for the MAX3140
are shown below.
12
24
48
96
192
384
Dxample 1: Setting up only the transmit buffer-empty
interrupt.
Send the 16-bit word below into ꢁIN of the MAX3140
using the WRITD CONFIGURATION register. This 16-bit
word configures the MAX3140 for 9600bps% 8-bit words%
no parity% and one stop bit with a 1.8432MHz crystal.
300
*Standard baud rates shown in bold
**ꢁefault baud rate
binary 1100100000001010
HDX C80A
22 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Table 7. Interrupt Sources and Masks—Bit Descriptions
BIT
NAME
MASK
BIT
MEANING
WHEN SET
DESCRIPTION
The Pr bit reflects the value in the word currently in the receive-buffer register
(oldest data available). The Pr bit is set when parity is enabled (PD = 1) and the
received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PD
= 0)% or when parity is enabled and the received bit is 0. An interrupt is issued
based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next
value read by a RDAꢁ ꢁATA operation.
Pr
R
Received parity bit = 1
ꢁata available
PM
RM
The R bit is set when new data is available to be read or when data is being read
from the receive register/FIFO. FIFO is cleared when all data has been read. An
interrupt is asserted as long as R = 1 and RM = 1.
This is the RA (RX-transition) bit in shutdown% and the FD (framing-error) bit in
operating mode. RA is set if there has been a transition on RX since entering
shutdown. RA is cleared when the MAX3140 exits shutdown. IRQ is asserted
when RA is set and RAM = 1.
Transition on RX when
in shutdown; framing
error when not in
shutdown
RA/FD
RAM
FD is determined solely by the currently received data% and is not stored in FIFO.
The FD bit is set if a zero is received when the first stop bit is expected. FD is
cleared upon receipt of the next properly framed character. IRQ is asserted
when FD is set and RAM = 1.
The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted
low if TM = 1 and the transmit buffer becomes empty. This source is cleared on
the rising edge of SCLK‘s 16th pulse when using a RDAꢁ ꢁATA or WRITD ꢁATA
operation. Although the interrupt is cleared% poll T to determine transmit-buffer
status.
Transmit buffer is
empty
T
TM
S
R
NEW DATA AVAILABLE
DATA READ
Q
RM MASK
S
TRANSMIT BUFFER EMPTY
DATA READ
Q
R
TM MASK
IRQ
S
PE = 1 AND RECEIVED PARITY BIT = 1
PE = 0 OR RECEIVED PARITY BIT = 0
Q
R
N
PM MASK
TRANSITION ON RX
SHUTDOWN
RAM MASK
FRAMING ERROR
SHUTDOWN
RAM MASK
Figure 15. Functional ꢁiagram for Interrupt Sources and Mask Blocks
______________________________________________________________________________________ 23
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Dxample 2: Setting up only the data-available (or data-
being-read) interrupt.
RS-485/RS-422 Transceiver
The RS-485/RS-422 transceiver is equipped with
numerous features allowing it to be configured for any
RS-485/RS-422 application. Figure 10 shows the
MAX3140 functional diagram. Included in the RS-
485/RS-422 transceiver function is full- and half-duplex
selectability% true fail-safe circuitry% programmable
slew-rate limiting% receiver input filtering% and phase
control circuitry.
Send the 16-bit word below into ꢁIN of the MAX3140
using the WRITD CONFIGURATION register. This 16-bit
word configures the MAX3140 for 9600bps% 8-bit
words% no parity% and one stop bit with a 1.8432MHz
crystal.
binary 1100010000001010
HDX C40A
MAX3140
Full Duplex or Half Duplex
The MAX3140 operates in either full- or half-duplex
mode. ꢁrive the H/F pin low% leave it unconnected
(internal pull-down)% or connect it to GNꢁ for full-duplex
operation or drive it high for half-duplex operation. In
half-duplex mode% the receiver inputs are switched to
the driver outputs% connecting outputs Y and Z to inputs
A and B% respectively. In half-duplex mode% the internal
full-duplex receiver input resistors are still connected to
inputs A and B.
Receive FIFO
The MAX3140 contains a receive FIFO for data received
by the UART to minimize processor overhead. The
receive FIFO is 8 words deep and clears automatically if
it overflows. Shutting down the UART also clears the
receive FIFO. Upon power-up% the receive FIFO is
enabled. To disable the receive FIFO% set the FEN bit
high when writing to the WRITD CONFIGURATION regis-
ter. To check whether the FIFO is enabled or disabled%
read back the FEN bit using the RDAꢁ CONFIGURA-
TION.
True Fail-Safe Circuitry
The MAX3140 guarantees a logic-high receiver output
when the receiver inputs are shorted or open% or when
they are connected to a terminated transmission line
with all drivers disabled. This is done by setting the
receiver threshold between -50mV and -200mV. If the
differential receiver input voltage (A-B) is greater than
or equal to -50mV% RO is logic high. If A-B is less than
or equal to -200mV% RO is logic low. In the case of a
terminated bus with all transmitters disabled% the
receiver’s differential input voltage is pulled to 0 by the
termination. With the receiver thresholds of the
MAX3140% this results in a logic high with a 50mV mini-
mum noise margin. Unlike previous fail-safe devices%
the -50mV to -200mV threshold complies with the
200mV DIA/TIA-485 standard.
UART Shutdown
In shutdown% the oscillator turns off to reduce power
consumption (I
< 1mA). The UART enters
CCSHꢁN UART
shutdown in one of two ways: by a software command
(SHꢁNi bit = 1) or by a hardware command (SHDN =
logic low). The hardware shutdown immediately termi-
nates any transmission in progress. The software shut-
down% requested by setting SHꢁNi bit = 1% is entered
upon completing the transmission of the data in both
the transmit-shift register and the transmit-buffer regis-
ter. The SHꢁNo bit is set when the UART enters shut-
down (either hardware or software). The microcontroller
(µC) can monitor the SHꢁNo bit to determine when all
data has been transmitted% then shut down RS-485
transceivers at that time.
Programmable Slew-Rate Limiting
The MAX3140 has several programmable operating
modes. Transmitter rise and fall times are programma-
ble at 2500ns% 750ns% or 25ns% resulting in maximum
data rates of 115kbps% 500kbps% or 10Mbps% respec-
tively. To select the desired data rate% drive SRL to one
of three possible states by using a three-state driver% by
Shutdown clears the receive FIFO% R% RA/FD% ꢁ0r–ꢁ7r%
Pr% and Pt registers and sets the T bit high.
Configuration bits (RM% TM% PM% RAM% IR% ST% PD% L% B0-
3% and RTS) can be modified when SHꢁNo = 1 and
CTS can also be read. Dven though RA is reset upon
entering shutdown% it goes high when a transition is
detected on the RX pin. This allows the UART to moni-
tor activity on the receiver when in shutdown.
connecting it to V
or GNꢁ% or by leaving it uncon-
CC
nected. For 115kbps operation% set the three-state
device in high-impedance mode or leave SRL uncon-
nected. For 500kbps operation% drive SRL high or con-
nect it to V . For 10Mbps operation% drive SRL low or
CC
connect it to GNꢁ. SRL can be changed during opera-
tion without interrupting data communications.
The command to power up (SHꢁNi = 0) turns on the
oscillator when CS goes high if SHDN = logic high% with
a start-up time of at least 25ms. This is done by writing
to the WRITD CONFIGURATION register% which clears
all registers but RTS and CTS. Since the crystal oscilla-
tor typically requires at least 25ms to start% the first
received characters can be garbled and a framing
error may occur.
24 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Receiver Input Filtering
The receivers of the MAX3140% when operating in
115kbps or 500kbps mode% incorporate input filtering in
addition to input hysteresis. This filtering enhances
noise immunity with differential signals that have very
slow rise and fall times. Receiver propagation delay
increases by 20ꢀ due to this filtering.
1ꢀ for reliable operation with other systems. This is
accomplished easily with a crystal% and in most cases
is achieved with ceramic resonators. Table 8 lists differ-
ent types of crystals and resonators and their suppliers.
The MAX3140’s oscillator supports parallel-resonant
mode crystals and ceramic resonators% or can be driven
from an external clock source. Internally% the oscillator
consists of an inverting amplifier with its input (X1) tied
to its output (X2) by a bias network that self-biases the
Phase Control Circuitry
Occasionally% twisted-pair lines are connected back-
ward from normal orientation. The MAX3140 has two
pins that invert the phase of the driver and the receiver
to correct for this problem. For normal operation% drive
TXP and RXP low% connect them to ground% or leave
them unconnected (internal pull-down). To invert the
inverter at approximately V /2. The external feedback
CC
circuit% usually a crystal from X2 to X1% provides 180° of
phase shift% causing the circuit to oscillate. As shown in
the standard application circuit% the crystal or resonator
is connected between X1 and X2% with the load capaci-
tance for the crystal being the series combination of C1
and C2. For example% for a 1.8432MHz crystal with a
specified load capacitance of 11pF% use 22pF capaci-
tors on either side of the crystal to ground. Series-res-
onant mode crystals have a slight frequency error%
typically oscillating 0.03ꢀ higher than specified series-
resonant frequency when operated in parallel mode.
driver phase% drive TXP high or connect it to V . To
CC
invert the receiver phase% drive RXP high or connect it
to V . Note that the receiver threshold is positive
CC
when RXP is high.
Applications Information
Crystals, Oscillators, and
Ceramic Resonators
Note: It is very important to keep crystal% resonator%
and load-capacitor leads and traces as short and
direct as possible. Make the X1 and X2 trace lengths
and ground tracks short% with no intervening traces.
This helps minimize parasitic capacitance and noise
pickup in the oscillator% and reduces DMI. Minimize
capacitive loading on X2 to minimize supply current.
The MAX3140’s X1 input can be driven directly by an
external CMOS clock source. The trip level is approxi-
The MAX3140 includes an oscillator circuit derived
from an external crystal for baud-rate generation. For
standard baud rates% use a 1.8432MHz or 3.6864MHz
crystal. The 1.8432MHz crystal results in lower operat-
ing current; however% the 3.6864MHz crystal may be
more readily available in surface-mount packages.
Ceramic resonators are low-cost alternatives to crystals
and operate similarly% though the Q and accuracy are
lower. Some ceramic resonators are available with inte-
gral load capacitors% which can further reduce cost.
The trade-off between crystals and ceramic resonators
is in initial frequency accuracy and temperature drift.
Keep the total error in the baud-rate generator below
mately equal to V /2. Make no connection to X2 in this
CC
mode. If a TTL or non-CMOS clock source is used% AC-
couple with a 10nF capacitor to X1. A 2V peak-to-peak
swing on the input is required for reliable operation.
Table 8. Component and Supplier List
FREQUENCY
(MHz)
TYPICAL
C1, C2 (pF)
PART
NUMBER
PHONE
NUMBER
DESCRIPTION
SUPPLIER
Through-Hole Crystal
(HC-49/U)
1.8432
1.8432
25
47
DCS International% Inc.
Murata North America
DCS-18-13-1
CSA1.84MG
(913) 782-7787
(800) 831-9172
Through-Hole
Ceramic Resonator
Through-Hole Crystal
(HC-49/US)
3.6864
3.6864
3.6864
33
39
DCS International% Inc.
DCS International% Inc.
AVX/Kyocera
DCS-36-18-4
DCS-36-20-5P
PBRC-3.68B
(913) 782-7787
(913) 782-7787
(803) 448-9411
SMT Crystal
SMT Ceramic
Resonator
None
(integral)
______________________________________________________________________________________ 25
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
9-Bit Networks
The MAX3140 supports a common multidrop communi-
cation technique referred to as 9-bit mode. In this
mode% the parity bit is set to indicate a message that
contains a header with a destination address. Set the
MAX3140’s parity mask to generate interrupts for this
condition. Operating a network in this mode reduces
the processing overhead of all nodes by enabling the
slave controllers to ignore most message traffic. This
relieves the remote processor to handle more useful
tasks.
SIR IrDA Mode
The MAX3140’s IrꢁA mode communicates with other
IrꢁA SIR-compatible devices% or reduces power con-
sumption in opto-isolated applications.
In IrꢁA mode% a bit period is shortened to 3/16 of a
baud period (1.61µs at 115%200 baud) (Figure 16). A
data zero is transmitted as a pulse of light (TX = logic
low% RX = logic high).
MAX3140
In receive mode% the RX signal’s sampling is done
halfway into the transmission of a high level. The sam-
pling is done once% instead of three times% as in normal
mode. The MAX3140 ignores pulses shorter than
approximately 1/16 of the baud period. The IrꢁA device
that is communicating with the MAX3140 must transmit
pulses at 3/16 of the baud period. For compatibility with
other IrꢁA devices% set the format to 8-bit data% one
stop% no parity.
In 9-bit mode% the MAX3140 is set up with eight bits
plus parity. The parity bit in all normal messages is
clear% but is set in an address-type message. The
MAX3140’s parity-interrupt mask generates an interrupt
on high parity when enabled. When the master sends
an address message with the parity bit set% all
MAX3140 nodes issue an interrupt. All nodes then
retrieve the received byte to compare to their assigned
address. Once addressed% the node continues to
process each received byte. If the node was not
addressed% it ignores all message traffic until a new
address is sent out by the master.
256 RS-485 Transceivers on the Bus
The standard RS-485 receiver input impedance is 12kΩ
(one unit load)% and the standard driver can drive up to
32 unit loads. The MAX3140 has a 1/8-unit-load receiver
input impedance (96kΩ)% allowing up to 256 trans-
ceivers to be connected in parallel on one communica-
tion line. Any combination of these devices and/or other
RS-485 transceivers with a total of 32 unit loads or less
can be connected to the line.
The parity/9th-bit interrupt is controlled only by the data
in the receive register and is not affected by data in the
FIFO% so the most effective use of the parity/9th-bit
interrupt is with FIFO disabled. With the FIFO disabled%
received nonaddress words are ignored and not even
read from the UART.
Reduced EMI and Reflections for the
RS-485/RS-422 Driver
The MAX3140 with SRL = V
or unconnected% is slew-
CC
rate limited% minimizing DMI and reducing reflections
caused by improperly terminated cables. Figure 17
shows the driver output waveform and its Fourier analy-
NORMAL UART
TX
1
0
1
0
0
1
1
0
1
IrDA
TX
IrDA
RX
20dB/div
NORMAL
RX
0
1
0
1
0
0
1
1
0
1
DATA BITS
UART FRAME
0
100kHz/div
1MHz
Figure 17. ꢁriver Output Waveform and FFT Plot of MAX3140
with SRL = GNꢁ% Transmitting at 20kHz
Figure 16. IrꢁA Timing
26 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
A
A
20dB/div
20dB/div
O
100kHz/div
1MHz
O
100kHz/div
1MHz
Figure 18. ꢁriver Output Waveform and FFT Plot of MAX3140
Figure 19. ꢁriver Output Waveform and FFT Plot of MAX3140
with SRL = Unconnected% Transmitting a 20kHz Signal
with SRL = V % Transmitting a 20kHz Signal
CC
sis of a 20kHz signal transmitted with SRL = GNꢁ. High-
frequency harmonic components with large amplitudes
are evident. Figure 18 shows the same signal for SRL =
Dnable times t
and t
in the Switching Char-
ZL
ZH
acteristics tables assume the device was not in a low-
power shutdown state. Dnable times t and
ZH(SHꢁN)
V
% transmitting under the same conditions. Figure
t
assume the device was shut down. It takes
CC
ZL(SHꢁN)
18’s high-frequency harmonic components are much
lower in amplitude% compared with Figure 17’s% and the
potential for DMI is significantly reduced. Figure 19
shows the same signal for SRL = unconnected% trans-
mitting under the same conditions. In general% a trans-
mitter’s rise time relates directly to the length of an
unterminated stub% which can be driven with only minor
waveform reflections% The following equation expresses
this relationship conservatively:
drivers and receivers longer to become enabled from
low-power shutdown mode (t % t ) than
ZH(SHꢁN) ZH(SHꢁN)
from driver/receiver-disable mode (t % t ).
ZH ZL
Driver Output Protection
Two mechanisms prevent excessive output current and
power dissipation caused by faults or by bus con-
tention. The first% a foldback current limit on the output
stage% provides immediate protection against short cir-
cuits over the whole common-mode voltage range (see
Typical Operating Characteristics). The second% a ther-
mal shutdown circuit% forces the driver outputs into a
high-impedance state if the die temperature becomes
excessive.
Length = tRISD / (10 · 1.5ns/ft)
where t
is the transmitter’s rise time.
RISD
For example% consider a rise time of 1320ns. This
results in excellent waveforms with a stub length up to
90 feet. A system can work well with longer unterminat-
ed stubs% even with severe reflections% if the waveform
settles out before the UART samples them.
Line Length vs. Data Rate
The RS-485/RS-422 standard covers line lengths up to
4000 feet. For line lengths greater than 4000 feet% use
the repeater application shown in Figure 20.
RS-485/RS-422 Transceiver
Low-Power Shutdown Mode
Figures 21% 22% and 23 show the system differential volt-
age for the parts driving 4000 feet of 26AWG twisted-
pair wire into 120Ω loads.
Low-power shutdown mode is initiated by bringing both
RE high and ꢁD low. RE and ꢁD may be driven simulta-
neously; the MAX3140 is guaranteed not to enter shut-
down if RE is high and ꢁD is low for less than 50ns. If
the inputs are in this state for at least 600ns% the device
is guaranteed to enter shutdown.
______________________________________________________________________________________ 27
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
network is shown in Figure 25. A typical full-duplex cir-
cuit for the MAX3140 is shown in Figure 26% and a corre-
sponding full-duplex network is shown in Figure 27.
Since the MAX3140’s internal UART has IrꢁA capability%
a standard IR transceiver (e.g.% the MAX3120) can be
used to provide IrꢁA communication (Figure 28).
Typical Applications
The MAX3140 is designed for bidirectional data com-
munications on multipoint bus transmission lines. The
RS-485 transceiver can be used in any RS-485 applica-
tion due to its numerous features and its programmabili-
ty. A typical half-duplex circuit for the MAX3140 is
shown in Figure 24% and a corresponding half-duplex
MAX3140
MAX3140
(FULL DUPLEX)
DI
5V/div
A
120Ω
120Ω
RO
RE
R
DATA IN
V - V
1V/div
5V/div
B
A
B
DE
Z
DI
RO
DATA OUT
D
Y
5μs/div
Figure 20. Line Repeater in Full-ꢁuplex Mode
Figure 21. System ꢁifferential Voltage at 50kHz ꢁriving 4000
Feet of Cable with SRL = Unconnected
DI
5V/div
DI
5V/div
V - V
1V/div
5V/div
V - V
1V/div
5V/div
A
B
A
B
RO
RO
2μs/div
1μs/div
Figure 22. System ꢁifferential Voltage at 100kHz ꢁriving 4000
Feet of Cable with SRL = V
Figure 23. System ꢁifferential Voltage at 200kHz ꢁriving 4000
Feet of Cable with SRL = GNꢁ
CC
28 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
V
CC
10k
V
+5V
CC
IRQ
DIN
DOUT
SCLK
CS
H/F
μP
SHDN
CTS
UART
RTS
TX
RX
V
CC
X1
X2
MAX3140
100k
RO
R
Z
HALF-DUPLEX
RS-485 I/O
Y
DI
D
DE
RXP
TXP
RE*
SRL
*NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY.
Figure 24. Typical Half-ꢁuplex Operating Circuit
120Ω
120Ω
DE
DI
Z
B
A
DI
D
D
DE
B
A
Y
B
A
RO
RE
RO
RE
R
R
R
R
D
D
MAX3140
DE
DI
RO
RE
DI
RO RE
DE
Figure 25. Typical Half-ꢁuplex RS-485 Network
______________________________________________________________________________________ 29
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
V
CC
10k
V
CC
IRQ
DIN
SHDN
H/F
μP
DOUT
SCLK
CS
MAX3140
UART
CTS
X1
X2
RTS
TX
RX
MAX3140
A
B
RO
DI
R
FULL-DUPLEX
RS-422 I/O
Y
Z
D
DE
RE*
RXP
TXP
SRL
*NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY WITH AN I/O OF A μP.
Figure 26. Typical Full-ꢁuplex Operating Circuit
A
Y
120Ω
120Ω
120Ω
RO
RE
R
DI
D
B
Z
Z
DE
DE
B
RE
RO
120Ω
DI
R
D
Y
A
A
A
B
B
R
R
MAX3140
RE RO
RE RO
Figure 27. Typical Full-ꢁuplex RS-422 Network
30 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
V
CC
10k
V
+5V
CC
MAX3120
H/F
IRQ
DIN
DOUT
SCLK
CS
TX
RX
UART
IN
IrDA
MODE
IrDA
I/O
μP
MAX3140
X1
X2
V
CC
100k
SOFTWARE
NON-IrDA
UART
RO
DI
R
RX
TX
Z
HALF-DUPLEX
RS-485 I/O
Y
D
DE
RXP
TXP
RTS
RE*
UNCONNECTED SRL
*NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY.
Figure 28. Typical IR and RS-485 Operating Circuit
______________________________________________________________________________________ 31
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
The user must supply code for managing the transmit
and receive queues% as well as the low-level hardware
interface itself. The interrupt control hardware must be
initialized before this driver is called.
Software Driver
Listing 1 is a C-language outline of an interrupt-driven
software driver that interfaces to a MAX3140% providing
an intermediate layer between the bit-manipulation sub-
routine and the familiar PutChar/GetChar subroutines.
Listing 1. Outline for a MAX3140 Software Driver
MAX3140
32 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Listing 1. Outline for a MAX3140 Software Driver (continued)
______________________________________________________________________________________ 33
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Listing 1. Outline for a MAX3140 Software Driver (continued)
MAX3140
34 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
MAX3140
Pin Configuration
Package Information
For the latest package outline information and land patterns%
go to www.maxim-ic.com/packages. Note that a “+”% “#”% or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character% but the drawing
pertains to the package regardless of RoHS status.
TOP VIEW
+
X2
X1
1
2
3
4
5
6
7
8
9
28 SHDN
27 IRQ
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
CTS
RTS
RX
26 CS
25 SCLK
24 DOUT
28 QSOP
D28M+1
21-0055
90-0173
MAX3140
TX
23 DIN
22
21 RXP
H/F
GND
RO
V
CC
20
19
18
A
B
Z
RE 10
DE 11
DI 12
17 N.C.
16
15 TXP
SRL 13
N.C. 14
Y
QSOP
______________________________________________________________________________________ 35
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/99
Initial release
Changed the maximum value of the “Driver Rise or Fall Time” parameter in the
Switching Characteristics—SRL = V table
—
1
9/10
6
CC
MAX3140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products% Inc.
相关型号：
MAX314CPE+
SPST, 4 Func, 1 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, MO-058AB, MS-001AA, DIP-16
MAXIM
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