MAX32630IWG+ [MAXIM]
Ultra-Low Power, High-Performance Cortex-M4F Microcontroller for Wearables;
| 型号： | MAX32630IWG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Low Power, High-Performance Cortex-M4F Microcontroller for Wearables 微控制器 外围集成电路 |
| 文件： | 总27页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
General Description
Benefits and Features
®
®
The MAX32630/MAX32631 is an ARM Cortex -M4F
32-bit microcontroller with a floating point unit, ideal for
the emerging category of wearable medical and fitness
applications. The architecture combines ultra-low power
high-efficiency signal processing functionality with signifi-
cantly reduced power consumption and ease of use. The
device features four powerful and flexible power modes.
A peripheral management unit (PMU) enables intelligent
peripheral control with up to six channels to significantly
reduce power consumption. Built-in dynamic clock gating
and firmware-controlled power gating allows the user to
optimize power for the specific application. Multiple SPI,
● High-Efficiency Microcontroller for Wearable Devices
• Internal Oscillator Operates Up to 96MHz
• Low Power 4MHz Oscillator System Clock Option
for Always-On Monitoring Applications
• 2MB Flash Memory
• 512KB SRAM
• 8KB Instruction Cache
• 1.2V Core Supply Voltage
• 1.8V to 3.3V I/O
• Optional 3.3V ±5% USB Supply Voltage
● Power Management Maximizes Uptime for Battery
Applications
2
®
UART and I C serial interfaces, as well as 1-Wire mas-
ter and USB, allow for interconnection to a wide variety of
external sensors. A four-input, 10-bit ADC with selectable
references is available to monitor analog input from exter-
nal sensors and meters. The small 100-ball WLP package
provides a tiny, 4.37mm x 4.37mm footprint.
• 106μA/MHz Active Current Executing from Cache
• Wakeup to 96MHz Clock or 4MHz Clock
• 600nA Low Power Mode (LP0) Current with RTC
Enabled
• 3.5μW Ultra-Low Power Data Retention Sleep
Mode (LP1) with Fast 5μs Wakeup to 96MHz
The MAX32630/MAX32631 include a hardware AES
engine. The MAX32631 is a secure version of the
MAX32630. It incorporates a trust protection unit (TPU)
with encryption and advanced security features. These
features include a modular arithmetic accelerator (MAA)
for fast ECDSA, a hardware PRNG entropy generator,
and a secure boot loader.
● Optimal Peripheral Mix Provides Platform Scalability
• SPIX Execute in Place (XIP) Engine for Memory
Expansion with Minimal Footprint
• Three SPI Masters, One SPI Slave
• Four UARTs
2
2
• Three I C Masters, One I C Slave
• 1-Wire Master
• Full-Speed USB 2.0 Engine with Internal
Transceiver
Applications
● Sports Watches
• Sixteen Pulse Train (PWM) Engines
• Six 32-Bit Timers and 3 Watchdog Timers
• Up to 66 General-Purpose I/O Pins
• One 10-Bit Delta-Sigma ADC Operating at 7.8ksps
• AES-64, -128, -256
● Fitness Monitors
● Wearable Medical Patches
● Portable Medical Devices
● Sensor Hubs
• CMOS-Level 32kHz RTC Output
● Secure Valuable IP and Data with Robust Internal
Hardware Security (MAX32631 Only)
• Trust Protection Unit (TPU) Including MAA Sup-
ports ECDSA and Modular Arithmetic
• PRNG Seed Generator
Ordering Information appears at end of data sheet.
ARM is a registered trademark and registered service mark and
Cortex is a registered trademark of ARM Limited.
• Secure Boot Loader
1-Wire is a registered trademark of Maxim Integrated Products,
Inc.
19-8478; Rev 0; 3/16
MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Simplified Block Diagram
MAX32630/MAX32631
GPIO WITH
INTERRUPTS
ARM CORTEX-M4F
96MHz
SRSTN
NVIC
6 × 32 BIT TIMERS
TCK/SWCLK
TMS/SWDIO
TDO
JTAG SWD (SERIAL
WIRE DEBUG)
16 × PULSE TRAIN
ENGINE
MEMORY
TDI
SHARED PAD
FUNCTIONS
2MB FLASH
3 × SPI MASTER
TIMERS/PWM
CAPTURE/COMPARE
POR,
BROWNOUT
MONITOR,
SUPPLY VOLTAGE
MONITORS
RSTN
512KB SRAM
8KB CACHE
UP TO 66 GPIO/SPECIAL
FUNCTION
USB
SPI
SPI XIP
I2C
1 × SPI SLAVE
1 × SPI XIP
UART
V
V
DDA
1-WIRE
RTC OUTPUT
SSA
PERIPHERAL
MANAGEMENT UNIT
2
V
DDIOH
3 × I C MASTER 1
VOLTAGE
REGULATION AND
POWER CONTROL
EXTERNAL
INTERRUPTS
× I2C SLAVE
MAXIMUM OF
3 PORTS
V
DDIO
DD12
DD18
V
V
3 × WINDOWED
WATCHDOG TIMERS
V
RTC
V
SS
4 × UART
CLOCK
32KOUT
32KIN
GENERATION
96MHz INT OSC/
SYSTEM CLOCK
RTC AND WAKE UP
TIMERS
1-WIRE MASTER
CRC 16/32
DP
USB 2.0 FULL
SPEED
EXT REF
DM
CONTROLLER
1.2V
AES-128,-192,-
256
V
DDB
V
REF
UNIQUE ID
AIN0
AIN1
AIN2
TRUST PROTECTION UNIT (TPU)
MAA
AIN3
10-BIT
ΣΔ ADC
÷5
÷5
÷4
SECURE NV KEY
V
DDB
V
DD18
V
DD12
V
RTC
PRNG
MAX32631 ONLY
÷2
Maxim Integrated
│ 2
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Absolute Maximum Ratings
(All voltages with respect to V , unless otherwise noted.)
AIN[3:2].................................................................-0.3V to +3.6V
SS
V
V
V
V
V
V
.................................................................-0.3V to +1.89V
.................................................................-0.3V to +1.26V
V
...................................................................-0.3V to +3.6V
.................................................................-0.3V to +3.6V
DD18
DD12
DDA
DDIO
V
DDIOH
relative to V
........................................-0.3V to +1.89V
Total Current into All V
Total Current into V ......................................................100mA
Power Pins (sink)................100mA
SSA
DD18
...................................................................-0.3V to +1.89V
....................................................................-0.3V to +3.6V
.....................................................................-0.3V to +3.6V
RTC
DDB
REF
SS
Output Current (sink) by Any I/O Pin..................................25mA
Output Current (source) by Any I/O Pin............................-25mA
Operating Temperature Range........................... -20°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
32KIN, 32KOUT....................................................-0.3V to +3.6V
RSTN, SRSTN, DP, DM, GPIO, JTAG.................-0.3V to +3.6V
AIN[1:0].................................................................-0.3V to +5.5V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
100 WLP
Package Code
W1004D4+1
Outline Number
21-0452
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Single-Layer Board
Junction-to-Ambient (θ
)
N/A
N/A
JA
Junction-to-Case Thermal Resistance (θ
)
JC
Thermal Resistance, Four-Layer Board
Junction-to-Ambient (θ
)
38.9°C/W
N/A
JA
Junction-to-Case Thermal Resistance (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 3
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Electrical Characteristics
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
1.71
1.14
1.71
1.75
1.71
1.71
TYP
1.8
1.2
1.8
1.8
1.8
1.8
MAX
1.89
1.26
1.89
1.89
3.6
UNITS
V
V
DD18
DD12
V
DDA
Supply Voltage
V
V
RTC
V
DDIO
V
V
must be ≥ V
DDIO
3.6
DDIOH
DDIOH
Power Fail Reset
Voltage
V
Monitors V
Monitors V
1.62
1.7
V
V
V
RST
POR
DRV
DD18
DD18
Power-On Reset
Voltage
V
V
1.5
RAM Data Retention
Voltage
0.93
Measured on the V
pin and execut-
DD12
V
Dynamic
ing code from cache memory, all inputs
DD12
I
106
173
μA/MHz
DD12_DLP3
Current, LP3 Mode
are tied to V or V , outputs do not
SS
DD18
source/sink any current, PMU disabled
Measured on the V pin and execut-
DD12
ing code from cache memory, all inputs
are tied to V or V , outputs do not
SS
DD18
source/sink any current, 96MHz oscillator
selected as system clock
V
Fixed Current,
DD12
I
μA
DD12_FLP3
LP3 Mode
Measured on the V
pin and execut-
DD12
ing code from cache memory, all inputs
are tied to V or V , outputs do not
72
SS
DD18
source/sink any current, 4MHz oscillator
selected as system clock
Measured on the V
+ V
device
DD18
DDA
pins and executing code from cache mem-
ory, all inputs are tied to V or V
,
DD18
366
SS
outputs do not source/sink any current,
96MHz oscillator selected as system clock
V
Fixed Current,
DD18
I
μA
DD18_FLP3
LP3 Mode
Measured on the V
+ V
device
DD18
DDA
pins and executing code from cache mem-
ory, all inputs are tied to V or V
outputs do not source/sink any current,
4MHz oscillator selected as system clock
,
DD18
33
27
SS
V
Dynamic
Measured on the V
pin, ARM in sleep
DD12
DD12
I
μA/MHz
DD12_DLP2
Current, LP2 Mode
mode, PMU with two channels active
Maxim Integrated
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Measured on the V
pin, ARM in sleep
DD12
mode, PMU with two channels active,
173
96MHz oscillator selected as system clock
V
Fixed Current,
DD12
I
I
μA
DD12_FLP2
LP2 Mode
Measured on the V
pin, ARM in sleep
DD12
mode, PMU with two channels active,
4MHz oscillator selected as system clock
72
Measured on the V
+ V
device
DD18
DDA
pins, ARM in sleep mode, PMU with two
channels active, 96MHz oscillator selected
as system clock
366
V
Fixed Current,
DD18
μA
DD18_FLP2
LP2 Mode
Measured on the V
+ V
device
DD18
DDA
pins. ARM in sleep mode, PMU with two
channels active, 4MHz oscillator selected
as system clock
33
V
Fixed Current,
DD12
I
I
Standby state with full data retention
1.86
120
505
14
μA
nA
nA
nA
nA
DD12_FLP1
LP1 Mode
V
Fixed Current,
DD18
Standby state with full data retention
DD18_FLP1
LP1 Mode
V
Fixed Current,
RTC enabled, retention regulator powered
by V
DD12
RTC
I
I
DDRTC_FLP1
LP1 Mode
V
Fixed Current,
DD12
I
I
DD12_FLP0
DD18_FLP0
LP0 Mode
V
Fixed Current,
DD18
120
LP0 Mode
RTC enabled
RTC disabled
505
105
V
Fixed Current,
RTC
nA
DDRTC_FLP0
LP0 Mode
LP2 Mode Resume
Time
t
t
t
0
5
μs
μs
μs
LP2_ON
LP1_ON
LP0_ON
LP1 Mode Resume
Time
LP0 Mode Resume
Time
Polling flash ready
11
JTAG
Input Low Voltage for
TCK, TMS, TDI
0.3 x
V
V
V
V
IL
V
DDIO
Input High Voltage for
TCK, TMS, TDI
0.7 x
V
IH
V
DDIO
Output Low Voltage for
TDO
V
0.2
0.4
OL
OH
Output High Voltage for
TDO
V
DDIO
0.4
-
V
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
CLOCKS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
System Clock
Frequency
f
t
0.001
98
MHz
ns
CK
CK
System Clock Period
1/f
CK
Factory default
94
96
98
Internal Relaxation
Oscillator Frequency
f
MHz
Firmware trimmed, required for USB com-
pliance
INTCLK
95.76
96
4
96.24
Internal RC Oscillator
Frequency
f
3.9
4.1
MHz
kHz
RCCLK
RTC Input Frequency
f
32kHz watch crystal
LP2 or LP3 mode
LP0 or LP1 mode
32.768
0.7
32KIN
I
I
RTC_LP23
RTC_LP01
RTC Operating Current
μA
0.35
250
RTC Power-Up Time
t
ms
RTC_ ON
GENERAL-PURPOSE I/O
0.3 ×
V
DDIO
0.3 ×
V
V
selected as I/O supply
DDIO
Input Low Voltage for All
GPIO Pins
V
V
V
IL
selected as I/O supply
DDIOH
V
DDIOH
0.3 x
Input Low Voltage for
RSTN
V
V
IL
V
RTC
Input Low Voltage for
SRSTN
0.3 x
IL
V
DDIO
0.7 ×
V
DDIO
0.7 ×
V
V
selected as I/O supply
DDIO
Input High Voltage for
All GPIO Pins
V
V
IH
selected as I/O supply
DDIOH
V
DDIOH
0.7 x
Input High Voltage for
RSTN
V
V
V
V
IH
V
RTC
Input High Voltage for
SRSTN
0.7 x
IH
V
DDIO
Input Hysteresis
(Schmitt)
V
300
0.2
mV
IHYS
V
= V
= 1.71V, V
selected
DDIO
DDIOH
DDIO
as I/O supply, I = 4mA, normal drive
0.4
OL
configuration
Output Low Voltage for
All GPIO Pins
V
= V
= 1.71V, V
selected
DDIO
DDIOH
DDIO
V
V
OL
as I/O supply I = 24mA, fast drive con-
figuration
0.2
0.2
0.4
, OL
V
= 1.71V V
= 2.97V, V
DDIO
DDIOH DDIOH
0.45
selected as I/O supply, I = 300μA
OL
Maxim Integrated
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to -20°C are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Combined I , All GPIO
OL
Pins
I
48
mA
OL_TOTAL
I
V
= -2mA, V
= V
= 1.71V,
OH
DDIO
DDIOH
V
-
-
DDIO
0.4
selected as I/O supply, normal drive
DDIO
configuration
Output High Voltage for
All GPIO Pins
I
= -8mA, V
= V
= 1.71V,
OH
VDDIO
DDIO
DDIOH
V
V
V
V
V
OH
OH
DDIO
0.4
selected as I/O supply, fast drive
configuration
= -300μA, V
I
= 3.6V, V
DDIOH
OH
DDIOH
DDIOH
selected as I/O supply
- 0.45
Ouput High Voltage for
All GPIO Pins
V
= 1.71V, V
= 3.6V. V
V
-
DDIO
DDIOH
DDIO
DDIO
0.45
V
selected as I/O supply, I
= -2mA
OH
Combined I , All GPIO
OH
Pins
I
-48
mA
pF
OH_TOTAL
Input/Output Pin Ca-
pacitance for All Pins
C
3
IO
V
= 1.89V, V
= 3.6V, V
DDIO
DDIOH DDIOH
Input Leakage Current
Low
I
selected as I/O supply, V = 0V, internal
pullup disabled
-100
-100
+100
+100
nA
nA
IL
IN
V
= 1.89V, V
= 3.6V, V
DDIO
DDIOH DDIOH
I
selected as I/O supply, V = 3.6V, internal
IH
IN
pulldown disabled
Input Leakage Current
High
V
= 0V, V
= 0V, V
selected
selected
DDIO
DDIOH
DDIO
I
-1
-2
+1
+2
OFF
as I/O supply, V < 1.89V
IN
μA
V
= V
= 1.71V, V
DDIO
DDIOH
DDIO
I
IH3V
as I/O supply, V = 3.6V
IN
Input Pullup Resistor
RSTN, SRSTN, TMS,
TCK, TDI
R
25
kΩ
PU
Input Pullup/Pulldown
Resistor for All GPIO
Pins
R
R
Normal resistance
Highest resistance
25
1
kΩ
PU1
PU2
MΩ
FLASH MEMORY
Page Size
2MB flash
8
kB
t
Mass erase
Page erase
30
30
M_ERASE
Flash Erase Time
ms
t
P_ERASE
Flash Programming
Time per Word
t
60
μs
PROG
Flash Endurance
Data Retention
10
10
kcycles
years
t
T = +85°C
A
RET
Maxim Integrated
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
ADC Electrical Characteristics
(Internal bandgap reference selected, ADC_SCALE = ADC_REFSCL = 1, unless otherwise specified. Specifications marked GBD are
guaranteed by design and not production tested.)
PARAMETER
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
10
ADC Clock Rate
f
t
0.1
8
MHz
μs
ACLK
ACLK
ADC Clock Period
1/f
ACLK
AIN[3:0], ADC_CHSEL = 0–3, BUF_BY-
PASS = 0
V
-
DDA
0.05
0.05
0.05
AIN[1:0], ADC_CHSEL = 4–5, BUF_BY-
PASS = 0
5.5
Input Voltage Range
V
V
AIN
AIN[3:0], ADC_CHSEL = 0–3, BUF_BY-
PASS = 1
V
V
SSA
SSA
DDA
AIN[1:0], ADC_CHSEL = 4–5, BUF_BY-
PASS = 1
V
5.5
Input Impedance
R
AIN[1:0], ADC_CHSEL = 4-5, ADC active
45
kΩ
μA
AIN
AIN
Switched capactiance input current, ADC
active, ADC buffer bypassed
4.5
Input Dynamic Current
I
Switched capacitance input current, ADC
active, ADC buffer enabled
50
nA
Fixed capacitance to V
SSA
1
pF
fF
Analog Input
Capacitance
C
AIN
Dynamically switched capacitance
250
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
±2
±1
LSb
LSb
LSb
LSb
dB
DNL
V
±1
±2
OS
Gain Error
GE
Signal to Noise Ratio
SNR
58.5
Signal to Noise and
Distortion
SINAD
THD
58.5
68.5
74
dB
dB
dB
µA
μA
Total Harmonic
Distortion
Spurious Free Dynamic
Range
SFDR
ADC active, reference buffer enabled, input
buffer disabled
ADC Active Current
I
240
53
ADC
Input Buffer Active
Current
I
INBUF
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
ADC Electrical Characteristics (continued)
(Internal bandgap reference selected, ADC_SCALE = ADC_REFSCL = 1, unless otherwise specified. Specifications marked GBD are
guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Any powerup of: ADC clock, ADC bias,
reference buffer or input buffer to
CpuAdcStart
10
µs
ADC Setup Time
t
ADC_SU
Any power-up of: ADC clock or ADC bias to
CpuAdcStart
48
t
t
ACLK
ACLK
ADC Output Latency
ADC Sample Rate
t
f
1025
ADC
ADC
7.8
4
ksps
AIN0 or AIN1, ADC inactive or channel not
selected
0.12
0.02
ADC Input Leakage
I
ADC_LEAK
nA
AIN2 or AIN3, ADC inactive or channel not
selected.
1
AIN0/AIN1 Resistor
Divider Error
ADC_CHSEL = 4 or 5, not including ADC
offset/gain error
±2
1.2
LSb
V
Full-Scale Voltage
V
ADC code = 0x3FF
FS
External Reference
Voltage
V
ADC_XREF = 1
1.17
1.23
1.29
V
REF_EXT
Bandgap Temperature
Coefficient
V
Box method
30
4.1
250
ppm
μA
fF
TEMPCO
REF_EXT
Reference Dynamic
Current
I
ADC_XREF = 1, ADC active
Reference Input
Capacitance
Dynamically switched capacitance, ADC_
XREF = 1, ADC active
C
REFIN
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
SPI MASTER/SPIX MASTER Electrical Characteristics
(Guaranteed by design and not production tested.)
PARAMETER
Operating Frequency
SCLK Period
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
f
t
48
MCK
MCK
1/f
MCK
SCLK Output Pulse-
Width High/Low
t
, t
t
t
t
/2
ns
ns
ns
ns
ns
MCH MCL
MCK
MCK
MOSI Output Hold Time
After SCLK Sample
Edge
t
/2
/2
MOH
MOSI Output Valid to
Sample Edge
t
MOV
MCK
3
MISO Input Valid to
SCLK Sample Edge
Setup
t
MIS
MIH
MISO Input to SCLK
Sample Edge
t
0
SPI Timing:
SHIFT
SAMPLE
SHIFT SAMPLE
SS
t
MCK
SCLK
CKPOL/
CKPHA
0/1 OR 1/0
t
t
t
MCL
MCH
MCH
SCLK
CKPOL/
CKPHA
0/0 OR 1/1
t
MOH
t
t
MLH
MOV
MOSI/
SDIO
MSB
MSB-1
LSB
(OUTPUT)
t
t
MIH
MIS
MISO/
SDIO
(INPUT)
MSB
MSB-1
LSB
Figure 1. SPI Master/SPIX Master Communications Timing Diagram
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USB Electrical Characteristics
(Guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
USB PHY Supply Volt-
age
V
2.97
3.3
3.63
V
DDB
Single-Ended Input High
Voltage DP, DM
V
2
V
V
IHD
Single-Ended Input Low
Voltage DP, DM
V
0.8
0.3
ILD
OLD
OHD
Output Low Voltage DP,
DM
V
R = 1.5kΩ from DP to 3.6V
V
L
Output High Voltage
DP, DM
V
R = 15kΩ from DP and DM to V
2.8
0.2
0.8
0.8
V
L
SS
Differential Input Sensi-
tivity DP, DM
V
DP to DM
V
DI
Common-Mode Voltage
Range
V
Includes V range
2.5
2.0
V
CM
DI
Single-Ended Receiver
Threshold
V
V
SE
Single-Ended Receiver
Hysteresis
V
V
200
mV
V
SEH
CRS
Differential Output Sig-
nal Cross-Point Voltage
C = 50pF
L
1.3
300
28
2.0
44
DP, DM Off-State Input
Impedance
R
kΩ
Ω
LZ
Driver Output Imped-
ance
R
Steady-state drive
DRV
Idle
0.9
1.575
3.09
DP Pull-up Resistor
R
kΩ
PU
Receiving
1.425
USB Timing Electrical Characteristics
(AC Electrical Specifications are guaranteed by design and are not production tested, V
= V
to 1.89V, V
= 3.63V, T =-20°C
DD18
RST
DDB A
to +85°C, Guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DP, DM Rise Time
(Transmit)
t
C = 50pF
4
20
ns
R
L
DP, DM Fall Time
(Transmit)
t
C = 50pF
4
20
ns
%
F
L
Rise/Fall Time Matching
(Transmit)
t ,t
C = 50pF
90
110
R F
L
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2
Electrical Characteristics - I C BUS
(Guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
Standard mode
MIN
TYP
100
400
MAX
UNITS
SCL Clock Frequency
f
kHz
SCL
Fast mode
0.7 ×
V
DDIO
0.7 ×
Fast mode, V
selected as I/O supply
DDIO
Fast mode, V
selected as I/O supply
DDIOH
V
DDIOH
0.7 ×
Input High Voltage
V
V
IH_I2C
Standard mode, V
supply
selected as I/O
DDIO
V
DDIO
0.7 ×
Standard mode, V
supply
selected as I/O
DDIOH
V
DDIOH
0.3 ×
V
DDIO
0.3 ×
Fast mode, V
selected as I/O supply
DDIO
Fast mode, V
selected as I/O supply
DDIOH
V
DDIOH
0.3 ×
Input Low Voltage
V
V
IL_I2C
Standard mode, V
supply
selected as I/O
DDIO
V
DDIO
0.3 ×
Standard mode, V
supply
selected as I/O
DDIOH
V
DDIOH
Input Hysteresis
(Schmitt)
V
Fast-mode
300
0.2
0.2
mV
V
IHYS_I2C
V
= V
= 1.71V, V
selected
DDIO
DDIOH
DDIO
as I/O supply, I = 4mA, normal drive
configuration
0.4
OL
Output Logic-Low (Open
Drain or Open Collector)
V
OL_I2C
V
= 1.71V V
= 2.97V, V
DDIO
DDIOH DDIOH
0.45
selected as I/O supply, I = 300μA
OL
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Ultra-Low Power, High-Performance
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Typical Operating Characteristics
(V
= 1.2V, V
= 1.8V)
DD12
DD18
IDD12 vs. FREQUENCY
(INTERNAL 96MHz OSCILLATOR)
IDD12 vs. FREQUENCY
(INTERNAL 4MHz OSCILLATOR)
toc01
toc02
12
10
8
600
VDD12 = 1.2V
VDD12 = 1.2V
500
400
300
200
100
0
6
4
2
0
0
20
40
60
80
100
0
1
2
3
4
FREQUENCY (MHz)
FREQUENCY (MHz)
TOTAL POWER vs. FREQUENCY
(INTERNAL 4MHz OSCILLATOR)
TOTAL POWER vs. FREQUENCY
(INTERNAL 96MHz OSCILLATOR)
toc04
toc03
700
600
500
400
300
200
100
0
14
TOTAL POWER =
(IDD18 x 1.8V) + (IDD12 x 1.2V)
TOTAL POWER =
(IDD18 x 1.8V) + (IDD12 x 1.2V)
12
10
8
LP3
LP3
LP2
6
LP2
4
2
0
0
1
2
3
4
0
20
40
60
80
100
FREQUENCY (MHz)
FREQUENCY (MHz)
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Pin Configuration
100-WLP
TOP VIEW (BUMPS ON BOTTOM)
10
1
2
3
4
5
6
7
8
9
+
A
B
C
D
E
F
N.C.
AIN0
AIN1
AIN2
AIN3
N.C.
V
V
V
V
DD18
DDIOH
SSA
REF
SRSTN
P0.1
P8.1
P8.0
P7.7
P7.6
P7.5
P7.4
P7.3
RSTN
P0.0
P0.5
P0.7
P1.3
P1.6
P2.1
TCK
P5.7
P0.2
P1.1
P1.4
P2.4
P2.5
TMS
P5.5
P5.6
P1.5
P3.0
P2.6
P2.7
TDO
P5.4
P5.3
P3.1
P3.5
P3.4
P3.2
TDI
32KIN
V
V
SS
DDA
P6.0
P0.3
P0.6
P1.2
P1.7
P2.2
P5.2
P5.0
P5.1
P3.7
P4.4
P4.1
32KOUT
V
V
RTC
P0.4
V
DDB
SS
P1.0
DP
DM
V
DDIO
P4.7
P4.5
P4.2
V
DD12
G
H
P4.6
P4.3
V
SS
V
DDIO
J
P7.2
N.C.
P2.0
P7.0
P2.3
P6.7
P3.3
P6.4
P3.6
P6.3
P4.0
P6.2
P6.1
N.C.
V
V
V
SS
DD18
SS
P7.1
K
P6.6
P6.5
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Bump Description
BUMP
NAME
FUNCTION
POWER PINS
USB Transceiver Supply Voltage. This pin must be bypassed to V with a 1.0μF capacitor as close
as possible to the package.
SS
D9
F2
V
DDB
1.2V Nominal Supply Voltage. This pin must be bypassed to V with a 1.0μF capacitor as close as
SS
V
DD12
possible to the package.
RTC Supply Voltage. This pin must be bypassed to V with a 1.0μF capacitor as close as possible
to the package.
SS
C9
V
RTC
DDA
Analog Supply Voltage. This pin must be bypassed to V
sible to this pin.
with a 1.0μF capacitor as close as pos-
SSA
B4
V
1.8V Supply Voltage. This pin must be bypassed to V with a 1.0μF capacitor as close as possible
to the package.
SS
J5, A9
H2, E10
V
DD18
DDIO
I/O Supply Voltage. 1.8V ≤ V
≤ 3.6V. See EC table for V
specification. This pin must be
DDIO
DDIO
V
bypassed to V with a 1.0μF capacitor as close as possible to the package.
SS
I/O Supply Voltage, High. 1.8V ≤ V
≤ 3.6V, always with V
≥ V
. See EC table for
DDIOH
DDIOH
DDIO
A2
A4
V
V
specification. This pin must be bypassed to VSS with a 1.0μF capacitor as close as pos-
DDIOH
DDIOH
sible to the package.
V
ADC Reference. This pin must be left unconnected if an external reference is not used.
REF
B9, D10, G2,
J6, J2
V
Digital Ground
Analog Ground
SS
A3
CLOCK PINS
C10
V
SSA
32KOUT
32KIN
32KHz Crystal Oscillator Output
32kHz Crystal Oscillator Input. Connect a 6pF 32kHz crystal between 32KIN and 32KOUT for RTC
operation. Optionally, an external clock source can be driven on 32KIN if the 32KOUT pin is left
unconnected. A 32kHz crystal or external clock source is required for proper USB operation.
B10
USB PINS
USB DP Signal. This bidirectional pin carries the positive differential data or single-ended data. This
pin is weakly pulled high internally when the USB is disabled.
E9
DP
USB DM Signal. This bidirectional pin carries the negative differential data or single-ended data.
This pin is weakly pulled high internally when the USB is disabled.
F9
DM
JTAG PINS
B5
B6
B7
B8
TCK/SWCLK JTAG Clock or Serial Wire Debug Clock. This pin has an internal 25KΩ pullup to V
.
DDIO
TMS/SWDIO JTAG Test Mode Select or Serial Wire Debug I/O. This pin has an internal 25KΩ pullup to V
.
DDIO
TDO
TDI
JTAG Test Data Output
JTAG Test Data Input. This pin has an internal 25kΩ pullup to V
.
DDIO
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Ultra-Low Power, High-Performance
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Bump Description (continued)
BUMP
NAME
FUNCTION
RESET PINS
Hardware Power Reset (Active-Low) Input. The device remains in reset while this pin is in its active
state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all
logic on all supplies except for real-time clock circuitry) and begins execution. This pin is internally
B3
RSTN
connected with an internal 25kΩ pullup to the V
supply. This pin should be left unconnected if
RTC
the system design does not provide a reset signal to the device.
Software Reset, Active-Low Input/Output. The device remains in software reset while this pin is in
its active state. When the pin transitions to its inactive state, the device performs a reset to the ARM
core, digital registers and peripherals (resetting most of the core logic on the V
supply). This
DD12
reset does not affect the POR only registers, RTC logic, ARM debug engine or JTAG debugger al-
lowing for a soft reset without having to reconfigure all registers.
B2
SRSTN
After the device senses SRSTN as a logic 0, the pin automatically reconfigures as an output sourc-
ing a logic 0. The device continues to output for 6 system clock cycles and then repeats the input
sensing/output driving until SRSTN is sensed inactive.
This pin is internally connected with an internal 25kΩ pullup to the V
supply. This pin should be
DDIO
left unconnected if the system design does not provide a reset signal to the device.
GENERAL-PURPOSE I/O AND SPECIAL FUNCTIONS (See the Applications Information section for GPIO Matrix)
C3
C2
D5
D4
D2
D3
E4
E3
E2
E5
F4
F3
F5
E6
G3
G4
J3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
GPIO Port 0.0
GPIO Port 0.1
GPIO Port 0.2
GPIO Port 0.3
GPIO Port 0.4
GPIO Port 0.5
GPIO Port 0.6
GPIO Port 0.7
GPIO Port 1.0
GPIO Port 1.1
GPIO Port 1.2
GPIO Port 1.3
GPIO Port 1.4
GPIO Port 1.5
GPIO Port 1.6
GPIO Port 1.7
GPIO Port 2.0
GPIO Port 2.1
GPIO Port 2.2
GPIO Port 2.3
GPIO Port 2.4
GPIO Port 2.5
GPIO Port 2.6
H3
H4
J4
G5
H5
G6
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Ultra-Low Power, High-Performance
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Bump Description (continued)
BUMP
H6
F6
NAME
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
FUNCTION
GPIO Port 2.7
GPIO Port 3.0
GPIO Port 3.1
GPIO Port 3.2
GPIO Port 3.3
GPIO Port 3.4
GPIO Port 3.5
GPIO Port 3.6
GPIO Port 3.7
GPIO Port 4.0
GPIO Port 4.1
GPIO Port 4.2
GPIO Port 4.3
GPIO Port 4.4
GPIO Port 4.5
GPIO Port 4.6
GPIO Port 4.7
GPIO Port 5.0
GPIO Port 5.1
GPIO Port 5.2
GPIO Port 5.3
GPIO Port 5.4
GPIO Port 5.5
GPIO Port 5.6
GPIO Port 5.7
GPIO Port 6.0
GPIO Port 6.1
GPIO Port 6.2
GPIO Port 6.3
GPIO Port 6.4
GPIO Port 6.5
GPIO Port 6.6
GPIO Port 6.7
GPIO Port 7.0
GPIO Port 7.1
GPIO Port 7.2
GPIO Port 7.3
GPIO Port 7.4
GPIO Port 7.5
E7
H7
J7
G7
F7
J8
F8
J9
H8
H10
H9
G8
G10
G9
F10
D8
E8
C8
D7
C7
C6
D6
C5
C4
J10
K9
K8
K7
K6
K5
K4
K3
K2
J1
H1
G1
F1
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Bump Description (continued)
BUMP
E1
NAME
P7.6
P7.7
P8.0
P8.1
N.C.
N.C.
N.C.
N.C.
FUNCTION
GPIO Port 7.6
GPIO Port 7.7
GPIO Port 8.0
GPIO Port 8.1
Not Connected.
Not Connected.
Not Connected.
Not Connected.
D1
C1
B1
A1
A10
K1
K10
ANALOG INPUT PINS
A5
A6
A7
A8
AIN0
ADC Input 0. 5V tolerant input.
ADC Input 1. 5V tolerant input.
ADC Input 2
AIN1
AIN2
AIN3
ADC Input 3
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● Two parallel 16-bit add/sub
● Two parallel MACs
Detailed Description
The MAX32630/MAX32631 is a low-power, mixed signal
microcontroller based on the ARM Cortex-M4 32-bit core
with a maximum operating frequency of 96MHz. The
MAX32631 is a secure version of the MAX32630, incor-
porating a trust protection unit (TPU) with encryption and
advanced security features.
● 32- or 64-bit accumulate
● Signed, unsigned, data with or without saturation
Analog-to-Digital Converter
The 10-bit delta-sigma ADC provides 4 external inputs
and can also be configured to measure all internal power
supplies. It operates at a maximum of 7.8ksps. AIN0 and
AIN1 are 5V tolerant, making them suitable for monitoring
batteries.
Application code executes from an onboard 2MB program
flash memory, with up to 512KB SRAM available for gen-
eral application use. An 8KB instruction cache improves
execution throughput, and a transparent code scrambling
scheme is used to protect customer intellectual property
residing in the program flash memory. Additionally, a SPI
execute in place (XIP) external memory interface allows
application code and data (up to 16MB) to be accessed
from an external SPI memory device.
An optional feature allows samples captured by the ADC
to be automatically compared against user-programmable
high and low limits. Up to four channel limit pairs can be
configured in this way. The comparison allows the ADC
to trigger an interrupt (and potentially wake the CPU
from a low-power sleep mode) when a captured sample
goes outside the preprogrammed limit range. Since this
comparison is performed directly by the sample limit
monitors, it can be performed even while the main CPU is
suspended in a low power mode.
A 10-bit delta-sigma ADC is provided with a multiplexer
front end for four external input channels (two of which
are 5V tolerant) and six internal channels. An onboard
temperature sensor block allows direct die temperature
measurement without requiring any external system
components. Dedicated divided supply input channels
allow direct monitoring of onboard power supplies such
The ADC reference is selectable:
● Internal bandgap
as V
, V
, V
, and V
by the ADC. Built-in
DD12 DD18 DDB
RTC
limit monitors allow converted input samples to be com-
pared against user-configurable high and low limits, with
an option to trigger an interrupt and wake the CPU from a
low power mode if attention is required.
● External reference
● V
. This option disables the reference buffer to
DD18
minimize power consumption.
Pulse Train Engine
A wide variety of communications and interface periph-
erals are provided, including a USB 2.0 slave interface,
three master SPI interfaces, one slave SPI interface, four
Sixteen independent pulse train generators provide either
a square wave or a repeating pattern from 2 bits to 32
bits in length. The frequency of each enabled pulse train
generator is also set separately, based on a divide down
(divide by 2, divide by 4, divide by 8, etc.) of the input
pulse train module clock.
2
UART interfaces with multidrop support, three master I C
2
interfaces, and a slave I C interface.
ARM Cortex-M4F Processor
The ARM Cortex-M4F processor is ideal for the emerging
category of wearable medical and wellness applications.
The architecture combines high-efficiency signal process-
ing functionality with low power, low cost, and ease of use.
Any single pulse train generator or any desired group of
pulse train generators can be restarted at the beginning of
their patterns and synchronized with one another ensur-
ing simultaneous startup. Additionally, each pulse train
can operate in a single shot mode.
The Cortex-M4F DSP supports single instruction multiple
data (SIMD) path DSP extensions, providing:
● Four parallel 8-bit add/sub
● Floating point single precision
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table. The 32kHz output can be directed out to pin P1.7
and remains active in all low power modes including LP0.
Clocking Scheme
The high-frequency internal relaxation oscillator operates
at a nominal frequency of 96MHz. It is the primary clock
source for the digital logic and peripherals. Select a 4MHz
internal oscillator to optimize active power consump-
tion. Wakeup is possible from either the 4MHz internal
oscillator or the 96MHz internal oscillator. An external
32.768kHz timebase is required when using the RTC or
USB features of the device. The time base can be gen-
erated by attaching a 32kHz crystal connected between
32KIN and 32KOUT, or an external clock source can also
be applied to the 32KIN pin. The external clock source
must meet the electrical/timing requirements in the EC
Interrupt Sources
The ARM nested vector interrupt controller (NVIC) pro-
vides a high-speed, deterministic interrupt response,
interrupt masking, and multiple interrupt sources. Each
peripheral is connected to the NVIC and can have mul-
tiple interrupt flags to indicate the specific source of the
interrupt within the peripheral. 55 distinct interrupts can
be grouped by firmware into 8 levels of priority (including
internal and external interrupts). There are 9 interrupts for
the GPIO ports, one for each port.
XTAL DRIVER OR
EXTERNAL CLOCK
32KIN
32kHz
REAL-TIME
CLOCK
RTC
OSCILLATOR
32kHz
CRYSTAL
32KOUT
NANO-RING
OSCILLATOR
~8kHz
POWER
SEQUENCER
32.768kHz
OUTPUT CLOCK
GPIO 1.7
ALWAYS-ON DOMAIN
(96MHz SYSCLK
ONLY)
48MHz
FIRMWARE
FREQUENCY
CALIBRATION
DIVIDE BY 2
USB PHY
INTERNAL
96MHz
OSCILLATOR
15kHz–96MHz
CORE
CLOCK
SCALER
ARM
CORTEX-M4
CORE
CLOCK
SCALER
INTERNAL
4MHz
OSCILLATOR
ADC
CLOCK
SCALER
8MHz
SYSTEM
CLOCK
SELECT
ADC
INTERNAL 44MHz
CRYPTOGRAPHIC
OSCILLATOR
44MHz
TPU
TRUST PROTECTION UNIT (MAX32621 ONLY)
Figure 2. MAX32630/MAX32631 Clock Scheme
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
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● Real-time clock
Real-Time Clock and Wake-Up Timer
A real-time clock (RTC) keeps the time of day in absolute
seconds. The 32-bit seconds register can count up to
approximately 136 years and be translated to calendar
format by application software. A time-of-day alarm and
independent subsecond alarm can cause an interrupt or
wake the device from stop mode. The minimum wake-up
● Power management clock
A third watchdog timer (WDT3) is provided for recovery
from runaway code or system unresponsiveness. This
recovery watchdog uses a 16-bit timer to generate the
watchdog reset. When enabled, this watchdog must be
written prior to timeout, resulting in a watchdog timeout.
The WDT3 flag is set on reset if a watchdog expiration
caused the system reset. The clock source for the recov-
ery watchdog is the 8kHz nano ring, and the granularity
of the timeout period is intended only for system recovery.
interval is 244μs. The V
supports SRAM retention in
RTC
power mode LP0.
CRC Module
A CRC hardware module is included to provide fast calcu-
lations and data integrity checks by application software.
The CRC module supports both the CRC-16-CCITT and
Programmable Timers
Six 32-bit timers provide timing, capture/compare, or gen-
eration of pulse-width modulated (PWM) signals. Each of
the 32-bit timers can also be split into two 16-bit timers,
enabling 12 standard 16-bit timers.
32
26
4
23
2
22
16
12
11
10
CRC-32 (X + X + X + X + X + X + X + X
8
7
5
+ X + X + X + X + X + X + 1) polynomials.
Watchdog Timers
32-bit timer features:
Two independent watchdog timers (WDT1 and WDT2)
with window support are provided. The watchdog timers
are independent and have multiple clock source options
to ensure system security. The watchdog uses a 32-bit
timer with prescaler to generate the watchdog reset. When
enabled, the watchdog timers must be written prior to time-
out or within a window of time if window mode is enabled.
Failure to write the watchdog timer during the programmed
timing window results in a watchdog timeout. The WDT1
or WDT2 flags are set on reset if a watchdog expiration
caused the system reset. The clock source options for the
watchdog timers WDT1 and WDT2 include:
● 32-bit up/down autoreload
● Programmable 16-bit prescaler
● PWM output generation
● Capture, compare, and capture/compare capability
● GPIOs can be assigned as external timer inputs,
clock gating or capture, limited to an input frequency
of 1/4 of the peripheral clock frequency
● Timer output pin
● Configurable as 2x 16-bit general purpose timers
● Timer interrupt
● Scaled system clock
32-BIT TIMER BLOCK
APB
BUS
TIMER CONTROL
REGISTER
TIME INTERRUPT
REGISTER
32-BIT COMPARE
REGISTER
TIMER
INTERRUPT
COMPARE
APB
CLOCK
INTERRUPT
PWM AND TIMER
OUTPUT
32-BIT TIMER
(WITH PRESCALER)
CONTROL
TIMER
OUTPUT
COMPARE
32-BIT
PWM/COMPARE
TIMER
INPUT
Figure 4. Timer Block Diagram, 32-Bit Mode
Maxim Integrated
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Serial Peripheral Interface—Master
Serial Peripherals
USB Controller
The integrated USB slave controller is compliant with the
full-speed (12Mb/s) USB 2.0 specification. The integrated
USB physical interface (PHY) reduces board space and
system cost. An integrated voltage regulator enables
The SPI master-mode-only (SPIM) interface operates
independently in a single or multiple slave system and is
fully accessible to the user application.
The SPI ports provide a highly configurable, flexible, and
efficient interface to communicate with a wide variety of
SPI slave devices. The three SPI master ports (SPI0,
SPI1, SPI2) support the following features:
smart switching between the main supply and V
connected to a USB host controller.
when
DDB
●
SPI modes (0, 3) for single-bit communication
The USB controller supports DMA for the endpoint buf-
fers. A total of 7 endpoint buffers are supported with con-
figurable selection of IN or OUT in addition to endpoint 0.
● 3- or 4-wire mode for single-bit slave device commu-
nication
An external 32kHz crystal or clock source is required
for USB operation, even if the RTC function is not used.
Although the USB timing is derived from the internal
96MHz oscillator, the default accuracy is not sufficient
for USB operation. Periodic firmware adjustments of
the 96MHz oscillator, using the 32kHz timebase as a
reference, are necessary to comply with the USB timing
requirements.
● Full-duplex operation in single-bit, 4-wire mode
● Dual and Quad I/O supported
● Up to 5 slave select lines per port
● Up to 2 slave ready lines
● Programmable interface timing
● Programmable SCK frequency and duty cycle
● High-speed AHB access to transmit and receive
2
I C Master and Slave Ports
using 32-byte FIFOs
2
The I C interface is a bidirectional, two-wire serial bus
that provides a medium-speed communications network.
It can operate as a one-to-one, one-to-many or many-
to-many communications medium. Three I C master
engines and one I C-selectable slave engine interface
to a wide variety of I C-compatible peripherals. These
engines support both Standard-mode and Fast-mode I C
standards. The slave engine shares the same I/O port
as the master engines and is selectable through the I/O
configuration settings. It provides the following features:
● SS assertion and deassertion timing with respect to
leading/trailing SCK edge
2
Serial Peripheral Interface—Slave
2
The SPI slave (SPIS) port provide a highly configurable,
flexible, and efficient interface to communicate with a wide
variety of SPI master devices. The SPI slave interface
supports the following features:
2
2
● Supports SPI modes 0 and 3
● Full-duplex operation in single-bit, 4-wire mode
● Slave select polarity fixed (active low)
● Dual and Quad I/O supported
● Master or slave mode operation
● Supports standard (7-bit) addressing or 10-bit
addressing
● Support for clock stretching to allow slower slave
● High-speed AHB access to transmit and receive
devices to operate on higher speed busses
using 32-byte FIFOs
● Multiple transfer rates
● Four interrupts to monitor FIFO levels
• Standard-mode: 100kbps
• Fast-mode: 400kbps
● Internal filter to reject noise spikes
Serial Peripheral Interface Execute in Place (SPIX)
Master
The SPI execute in place (SPIX) master allows the CPU
to transparently execute instructions stored in an external
SPI flash. Instructions fetched through the SPIX master
are cached just like instructions fetched from internal
program memory. The SPIX master can also be used to
access large amounts of external static data that would
otherwise reside in internal data memory.
● Receiver FIFO depth of 16 bytes
● Transmitter FIFO depth of 16 bytes
Maxim Integrated
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
UART
Peripheral Management Unit (PMU)
All four universal asynchronous receiver-transmitter
(UART) interfaces support full-duplex asynchronous com-
munication with optional hardware flow control (HFC)
modes to prevent data overruns. If HFC mode is enabled
on a given port, the system uses two extra pins to imple-
ment the industry standard request to send (RTS) and
clear to send (CTS) methodology. Each UART is individu-
ally programmable.
The PMU is a DMA-based link list processing engine that
performs operations and data transfers involving memory
and/or peripherals in the advanced peripheral bus (APB)
and advanced high-performance bus (AHB) peripheral
memory space while the main CPU is in a sleep state.
This allows low-overhead peripheral operations to be
performed without the CPU, significantly reducing overall
power consumption. Using the PMU with the CPU in a
sleep state provides a lower noise environment critical for
obtaining optimum ADC performance.
● 2-wire interface or 4-wire interface with flow control
● 32-byte send/receive FIFO
Key features of the PMU engine include:
● Full-duplex operation for asynchronous data transfers
● Programmable interrupt for receive and transmit
● Independent baud-rate generator
● Programmable 9th bit parity support
● Multidrop support
● Six independent channels with round-robin schedul-
ing allows for multiple parallel operations
● Programmed using SRAM-based PMU op codes
● PMU action can be initiated from interrupt conditions
from peripherals without CPU
● Start/stop bit support
● Integrated AHB bus master
● Hardware flow control using RTS/CTS
● Maximum baud rate 1843.2kB
● Coprocessor-like state machine
Additional Documentation
Trust Protection Unit (TPU) (MAX32631 Only)
Engineers must have the following documents to fully use
this device:
The TPU enhances cryptographic data security for valu-
able intellectual property (IP) and data. A high-speed,
dedicated, hardware-based math accelerator (MAA) per-
forms mathematical computations that support strong
cryptographic algorithms including:
● This data sheet, containing pin descriptions, feature
overviews, and electrical specifications
● The device-appropriate user guide, containing detailed
information and programming guidelines for core features
and peripherals
● AES-128
● AES-192
● Errata sheets for specific revisions noting deviations
from published specifications
● AES-256
For information regarding these documents, visit Technical
Support at support.maximintegrated.com/micro.
● 1024-bit DSA
● 2048-bit (CRT)
Development and Technical Support
The device provides a pseudo-random number genera-
tor that can be used to create cryptographic keys for any
application. A user-selectable entropy source further
increases the randomness and key strength.
Contact technical support for information about highly
versatile, affordable development tools, available from
Maxim Integrated and third-party vendors.
The secure bootloader protects against unauthorized
access to program memory.
● Evaluation kits
● Software development kit
● Compilers
● Integrated development environments (IDEs)
● USB interface modules for programming and debugging
For technical support, go to support.maximintegrated.
com/micro
Maxim Integrated
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Applications Information
Table 1. General-Purpose I/O Matrix
QUATER-
NARY FUNC-
TION
PRIMARY
FUNCTION
SECONDARY
FUNCTION
TERTIARY
FUNCTION
PULSE
TRAIN
GPIO INTER-
TIMER INPUT
RUPT
P0.0 UART0A_RX
P0.1 UART0A_TX
P0.2 UART0A_CTS
P0.3 UART0A_RTS
P0.4 SPIM0A_SCK
UART0B_TX
UART0B_RX
UART0B_RTS
UART0B_CTS
PT_PT0
TIMER_TMR0 GPIO_INT(P0)
TIMER_TMR1 GPIO_INT(P0)
TIMER_TMR2 GPIO_INT(P0)
TIMER_TMR3 GPIO_INT(P0)
TIMER_TMR4 GPIO_INT(P0)
PT_PT1
PT_PT2
PT_PT3
PT_PT4
SPIM0A_MOSI/
SDIO0
P0.5
PT_PT5
PT_PT6
TIMER_TMR5 GPIO_INT(P0)
TIMER_TMR0 GPIO_INT(P0)
SPIM0A_MISO/
SDIO1
P0.6
P0.7 SPIM0A_SS0
P1.0 SPIM1A_SCK
PT_PT7
PT_PT8
TIMER_TMR1 GPIO_INT(P0)
TIMER_TMR2 GPIO_INT(P1)
SPIX0A_SCK
SPIM1A_MOSI/
SDIO0
SPIX0A_
SDIO0
P1.1
PT_PT9
TIMER_TMR3 GPIO_INT(P1)
SPIM1A_MISO/
SDIO1
SPIX0A_
SDIO1
P1.2
PT_PT10
PT_PT11
PT_PT12
TIMER_TMR4 GPIO_INT(P1)
TIMER_TMR5 GPIO_INT(P1)
TIMER_TMR0 GPIO_INT(P1)
P1.3 SPIM1A_SS0
SPIX0A_SS0
SPIX0A_
SDIO2
P1.4 SPIM1A_SDIO2
SPIX0A_
SDIO3
P1.5 SPIM1A_SDIO3
PT_PT13
TIMER_TMR1 GPIO_INT(P1)
P1.6 I2CM0A/S0A_SDA
P1.7 I2CM0A/S0A_SCL
P2.0 UART1A_RX
P2.1 UART1A_TX
PT_PT14
PT_PT15
PT_PT0
PT_PT1
PT_PT2
PT_PT3
PT_PT4
TIMER_TMR2 GPIO_INT(P1)
TIMER_TMR3 GPIO_INT(P1)
TIMER_TMR4 GPIO_INT(P2)
TIMER_TMR5 GPIO_INT(P2)
TIMER_TMR0 GPIO_INT(P2)
TIMER_TMR1 GPIO_INT(P2)
TIMER_TMR2 GPIO_INT(P2)
UART1B_TX
UART1B_RX
UART1B_RTS
UART1B_CTS
P2.2 UART1A_CTS
P2.3 UART1A_RTS
P2.4 SPIM2A_SCK
SPIM2A_MOSI/
SDIO0
P2.5
PT_PT5
PT_PT6
TIMER_TMR3 GPIO_INT(P2)
TIMER_TMR4 GPIO_INT(P2)
SPIM2A_MISO/
SDIO1
P2.6
P2.7 SPIM2A_SS0
P3.0 UART2A_RX
P3.1 UART2A_TX
P3.2 UART2A_CTS
P3.3 UART2A_RTS
PT_PT7
PT_PT8
PT_PT9
PT_PT10
PT_PT11
PT_PT12
TIMER_TMR5 GPIO_INT(P2)
TIMER_TMR0 GPIO_INT(P3)
TIMER_TMR1 GPIO_INT(P3)
TIMER_TMR2 GPIO_INT(P3)
TIMER_TMR3 GPIO_INT(P3)
TIMER_TMR4 GPIO_INT(P3)
UART2B_TX
UART2B_RX
UART2B_RTS
UART2B_CTS
P3.4 I2CM1A/S0B_SDA SPIM2A_SS1
Maxim Integrated
│ 24
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Table 1. General-Purpose I/O Matrix (continued)
QUATER-
NARY FUNC-
TION
PRIMARY
FUNCTION
SECONDARY
FUNCTION
TERTIARY
FUNCTION
PULSE
TRAIN
GPIO INTER-
TIMER INPUT
RUPT
P3.5 I2CM1A/S0B_SCL
P3.6 SPIM1A_SS1
P3.7 SPIM1A_SS2
P4.0 OWM_I/O
SPIM2A_SS2
SPIX_SS1
PT_PT13
PT_PT14
PT_PT15
PT_PT0
PT_PT1
TIMER_TMR5 GPIO_INT(P3)
TIMER_TMR0 GPIO_INT(P3)
TIMER_TMR1 GPIO_INT(P3)
TIMER_TMR2 GPIO_INT(P4)
TIMER_TMR3 GPIO_INT(P4)
SPIX_SS2
SPIM2A_SR0
SPIM2A_SR1
P4.1 OWM_PUPEN
SPIS0A_
SDIO2
P4.2 SPIM0A_SDIO2
P4.3 SPIM0A_SDIO3
P4.4 SPIM0A_SS1
P4.5 SPIM0A_SS2
P4.6 SPIM0A_SS3
PT_PT2
PT_PT3
PT_PT4
PT_PT5
PT_PT6
TIMER_TMR4 GPIO_INT(P4)
TIMER_TMR5 GPIO_INT(P4)
TIMER_TMR0 GPIO_INT(P4)
TIMER_TMR1 GPIO_INT(P4)
TIMER_TMR2 GPIO_INT(P4)
SPIS0A_
SDIO3
SPIS0A_
SCLK
SPIS0A_
MOSI/SDIO0
SPIS0A_
MISO/SDIO1
P4.7 SPIM0A_SS4
P5.0
SPIS0A_SSEL
SPIM2B_SCK
PT_PT7
PT_PT8
TIMER_TMR3 GPIO_INT(P4)
TIMER_TMR4 GPIO_INT(P5)
SPIM2B_
MOSI/SDIO0
P5.1
PT_PT9
TIMER_TMR5 GPIO_INT(P5)
SPIM2B_
MISO/SDIO1
P5.2
P5.3
P5.4
PT_PT10
PT_PT11
PT_PT12
TIMER_TMR0 GPIO_INT(P5)
TIMER_TMR1 GPIO_INT(P5)
TIMER_TMR2 GPIO_INT(P5)
SPIM2B_SS0 UART3A_RX
UART3B_TX
UART3B_RX
SPIM2B_
UART3A_TX
SDIO2
SPIM2B_
SDIO3
P5.5
P5.6
UART3A_CTS UART3B_RTS PT_PT13
TIMER_TMR3 GPIO_INT(P5)
SPIM2B_SR
UART3A_RTS UART3B_CTS PT_PT14
TIMER_TMR4 GPIO_INT(P5)
TIMER_TMR5 GPIO_INT(P5)
TIMER_TMR0 GPIO_INT(P6)
TIMER_TMR1 GPIO_INT(P6)
P5.7 I2CM2A/S0C_SDA SPIM2B_SS1
P6.0 I2CM2A/S0C_SCL SPIM2B_SS2
PT_PT15
PT_PT0
PT_PT1
P6.1 SPIM2C_SCK
SPIS0B_SCK
SPIM2C_MOSI/
SDIO0
SPIS0B_
MOSI/SDIO0
P6.2
PT_PT2
TIMER_TMR2 GPIO_INT(P6)
SPIM2C_MISO/
SDIO1
SPIS0B_
MISO/SDIO1
P6.3
PT_PT3
PT_PT4
PT_PT5
TIMER_TMR3 GPIO_INT(P6)
TIMER_TMR4 GPIO_INT(P6)
TIMER_TMR5 GPIO_INT(P6)
P6.4 SPIM2C_SS0
SPIS0B_SSEL
SPIS0B_
SDIO2
P6.5 SPIM2C_SDIO2
SPIS0B_
SDIO3
P6.6 SPIM2C_SDIO3
P6.7 SPIM2C_SR0
PT_PT6
PT_PT7
TIMER_TMR0 GPIO_INT(P6)
TIMER_TMR1 GPIO_INT(P6)
I2CM2B/
SE_SDA
Maxim Integrated
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Table 1. General-Purpose I/O Matrix (continued)
QUATER-
NARY FUNC-
TION
PRIMARY
FUNCTION
SECONDARY
FUNCTION
TERTIARY
FUNCTION
PULSE
TRAIN
GPIO INTER-
TIMER INPUT
RUPT
I2CM2B/
SE_SCL
P7.0 SPIM2C_SS1
P7.1 SPIM2C_SS2
P7.2 SPIM2C_SR1
P7.3 SPIS0C_SCK
PT_PT8
TIMER_TMR2 GPIO_INT(P7)
TIMER_TMR3 GPIO_INT(P7)
TIMER_TMR4 GPIO_INT(P7)
TIMER_TMR5 GPIO_INT(P7)
TIMER_TMR0 GPIO_INT(P7)
I2CM1B/
SD_SDA
PT_PT9
I2CM1B/
SD_SCL
PT_PT10
PT_PT11
PT_PT12
I2CM2C/
SG_SDA
SPIS0C_MOSI/
I2CM2C/
SG_SCL
P7.4
SDIO0
SPIS0C_MISO/
SDIO1
P7.5
PT_PT13
PT_PT14
PT_PT15
TIMER_TMR1 GPIO_INT(P7)
TIMER_TMR2 GPIO_INT(P7)
TIMER_TMR3 GPIO_INT(P7)
P7.6 SPIS0C_SS0
I2CM1C/
SF_SDA
P7.7 SPIS0C_SDIO2
I2CM1C/
SF_SCL
P8.0 SPIS0C_SDIO3
P8.1
PT_PT0
PT_PT1
TIMER_TMR4 GPIO_INT(P8)
GPIO_INT(P8)
TIMER_TMR5
Ordering Information
TRUST PROTECTION UNIT
(TPU)
PART
FLASH
SRAM
PIN-PACKAGE
MAX32630IWG+
MAX32631IWG+
MAX32630IWG+T
MAX32631IWG+T
2MB
2MB
2MB
2MB
512KB
512KB
512KB
512KB
No
Yes
No
100 WLP
100 WLP
100 WLP
100 WLP
Yes
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Maxim Integrated
│ 26
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MAX32630/MAX32631
Ultra-Low Power, High-Performance
Cortex-M4F Microcontroller for Wearables
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
3/16
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2016 Maxim Integrated Products, Inc.
│ 27
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