MAX3280EAUK/V+ [MAXIM]
Line Receiver, BICMOS, PDSO5,;
| 型号： | MAX3280EAUK/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, BICMOS, PDSO5, 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总10页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
GenePalVSescPiption
FeatuPes
The MAX3280E/MAX3281E/MAX3283E/MAX3284E are
single receivers designed for RS-485 and RS-422 com-
munication. These devices guarantee data rates up to
52Mbps, even with a 3V power supply. Excellent propa-
gation delay (15ns max) and package-to-package
skew time (8ns max) make these devices ideal for mul-
tidrop clock distribution applications.
o ESD Protection:
1ꢀ5k ꢁHman ꢂody Model
65k ꢃEꢄ 1ꢅꢅꢅ-4-2, ꢄontact Discꢆarge
125k ꢃEꢄ 1ꢅꢅꢅ-4-2, ꢇir-ꢈap Discꢆarge
o ꢈHaranteed ꢀ2Mbps Data Rate
o ꢈHaranteed 1ꢀns Receiver Propagation Delay
o ꢈHaranteed 2ns Receiver S5ew
The MAX3280E/MAX3281E/MAX3283E/MAX3284E
have true fail-safe circuitry, which guarantees a logic-
high receiver output when the receiver inputs are
opened or shorted. The receiver output will be a logic
high if all transmitters on a terminated bus are disabled
(high impedance). These devices feature 1/4-unit-load
receiver input impedance, allowing up to 128 receivers
on the same bus.
o ꢈHaranteed 8ns Pac5age-to-Pac5age S5ew Time
o k Pin for ꢄonnection to FPꢈꢇs/ꢇSꢃꢄs
L
o ꢇllow Up to 128 Transceivers on tꢆe ꢂHs
(1/4-Hnit-load)
o Tiny SOT23 Pac5age
The MAX3280E is a single receiver available in a 5-pin
SOT23 package. The MAX3281E/MAX3283E single
receivers have a receiver enable (EN or EN) function
and are offered in a 6-pin SOT23 package. The
MAX3284E features a voltage logic pin that allows com-
patibility with low-voltage logic levels, as in digital
FPGAs/ASICs. On the MAX3284E, the voltage threshold
o TrHe Fail-Safe Receiver
o -7k to +12k ꢄommon-Mode Range
o 3k to ꢀ.ꢀk Power-SHpply Range
o Enable (ꢁigꢆ and Low) Pins for RedHndant
Operation
for a logic high is user-defined by setting V in the
L
o Tꢆree-State OHtpHt Stage (MꢇX3281E/MꢇX3283E)
o Tꢆermal Protection ꢇgainst OHtpHt Sꢆort ꢄircHit
range from 1.65V to V . The MAX3284E is also
CC
offered in a 6-pin SOT23 package.
Applications
OPdePingVInfoPmation
Clock Distribution
Telecom Racks
Base Stations
PIN-
TOP
PART
TEMP RANGE
PACKAGE MARK
MAX3280EAUK+T -40°C to +125°C 5 SOT23
MAX3280EAUK/V+T -40°C to +125°C 5 SOT23
MAX3281EAUT+T -40°C to +125°C 6 SOT23
MAX3283EAUT+T -40°C to +125°C 6 SOT23
MAX3284EAUT+T -40°C to +125°C 6 SOT23
+ADVM
+AFME
+ABAT
+ABAU
+ABAV
Industrial Control
Local Area Networks
Pin ꢄonfigHrations appear at end of data sꢆeet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
/V denotes an automotive qualified part.
ꢁelectoPVGuide
PꢇRT
k
ENꢇꢂLE
—
DꢇTꢇ RꢇTE
52Mbps
PꢇꢄKꢇꢈE
5-Pin SOT23
6-Pin SOT23
6-Pin SOT23
6-Pin SOT23
L
MAX3280E
MAX3281E
MAX3283E
MAX3284E
—
—
—
✔
Active High
Active Low
—
52Mbps
52Mbps
52Mbps (Note 1)
Note 1: MAX3284E data rate is dependent on V .
L
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-2320; Rev 2; 12/12
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
ꢇꢂSOLUTE MꢇXꢃMUM RꢇTꢃNꢈS
(All Voltages Referenced to GND)
Continuous Power Dissipation (T = +70°C)
A
Supply Voltage (V ) ...............................................-0.3V to +6V
Control Input Voltage (EN, EN).................................-0.3V to +6V
V Input Voltage .......................................................-0.3V to +6V
L
5-Pin SOT23 (derate 7.1mW/°C above +70°C)............571mW
6-Pin SOT23 (derate 8.7mW/°C above +70°C)............696mW
Operating Temperature Range
CC
MAX328_EA__ ..............................................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Receiver Input Voltage (A, B)..............................-7.5V to +12.5V
Receiver Output Voltage (RO)....................-0.3V to (V
Receiver Output Voltage
+ 0.3V)
CC
(RO) (MAX3284E) .....................................-0.3V to (V + 0.3V)
L
Receiver Output Short-Circuit Current .......................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELEꢄTRꢃꢄꢇL ꢄꢁꢇRꢇꢄTERꢃSTꢃꢄS
(V = 3V to 5.5V, V = V , T = T
to T
, unless otherwise noted. Typical values are at V = 5V and T = +25°C.) (Notes 2, 3)
CC
L
CC
A
MIN
MAX
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
Supply Voltage
Supply Current
V
3.0
CC
CC
I
No load
9
15
mA
V
V Input Range
V
L
MAX3284E
1.65
V
CC
L
V Supply Current
L
I
L
No load (MAX3284E)
10
µA
RECEIVER
V
V
= +12V
= -7V
250
IN
IN
Input Current (A and B)
I
V
CC
= V or 5.5V
GND
µA
A, B
-200
Receiver Differential Threshold
Voltage
V
-7V ꢀ V
ꢀ +12V (Note 4)
-200
2
-125
25
-50
mV
TH
CM
Receiver Input Hysteresis
Receiver Enable Input Low
Receiver Enable Input High
Receiver Enable Input Leakage
ꢁV
V
A
+ V = 0V
mV
V
TH
ENIL
ENIH
LEAK
B
V
MAX3281E, MAX3283E only
MAX3281E, MAX3283E only
MAX3281E, MAX3283E only
0.4
10
V
V
I
µA
MAX3280E/MAX3281E/MAX3283E,
= -4mA, RO high
V
- 0.4
CC
I
OH
Receiver Output High Voltage
Receiver Output Low Voltage
V
V
V
OH
MAX3284E, I
RO high
= -1mA, 1.65V ꢀ V ꢀ V
,
OH
L
CC
V - 0.4
L
MAX3280E/MAX3281E/MAX3283E,
= 4mA, RO low
0.4
0.4
5
I
OL
V
OL
MAX3284E, I = 1mA, 1.65V ꢀ V ꢀ V ,
CC
OL
L
RO low
Three-State Output Current at
Receiver
I
0 ꢀ V ꢀ V , RO = high impedance
µA
kꢂ
OZR
O
CC
Receiver Input Resistance
R
-7V ꢀ V
ꢀ +12V (Note 5)
48
IN
CM
Receiver Output Short-Circuit
Current
I
0 ꢀ V
ꢀ V
CC
130
mA
OSR
RO
ESD PROTECTION
Human Body Model
15
12
6
ESD Protection (A, B)
kV
IEC1000-4-2 (Air-Gap Discharge)
IEC1000-4-2 (Contact Discharge)
2
Maxim Integrated
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
SWꢃTꢄꢁꢃNꢈ ꢄꢁꢇRꢇꢄTERꢃSTꢃꢄS
(V = 3V to 5.5V, V = V , T = T
to T
, unless otherwise noted. Typical values are at V = 5V and T = +25°C.) (Notes 2, 3)
CC
L
CC
A
MIN
MAX
CC
A
PARAMETER
SYMBOL
CONDITIONS
C = 15pF (Notes 5, 6)
MIN
52
TYP
MAX
UNITS
Maximum Data Rate
Receiver Propagation Delay
Receiver Output |t - t
f
Mbps
MAX
L
t
Figure 1, C = 15pF, V = 2V, V
= 0V
= 0V
7
8
15
15
2
PLH
PHL
L
ID
CM
ns
ns
t
Figure 1, C = 15pF, V = 2V, V
L ID
CM
|
t
Figure 1, C = 15pF, T = +25°C
L A
PLH PHL
PSKEW
Same power supply, maximum
temperature difference between
devices = +30°C.
Device-to-Device Propagation
Delay Matching
8
ns
ENABLE/DISABLE TIME FOR MAX3281E/MAX3283E
Receiver Enable to Output Low
Receiver Enable to Output High
Receiver Disable Time from Low
Receiver Disable Time from High
t
Figure 2, C = 15pF
500
500
500
500
ns
ns
ns
ns
PRZL
PRZH
L
t
Figure 2, C = 15pF
L
t
Figure 2, C = 15pF
L
PRLZ
PRHZ
t
Figure 2, C = 15pF
L
Note 2: Parameters are 100% production tested at +25°C, limits over temperature are guaranteed by design.
Note 3: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to device
ground, unless otherwise noted.
Note 4: V
is the common-mode input voltage. V is the differential input voltage.
CM
ID
Note ꢀ: Not production tested. Guaranteed by design.
Note 6: See Table 2 for MAX3284E data rates with V < V
.
CC
L
TypicalVOpePatingVChaPactePistics
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
RECEIVER OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
RECEIVER OUTPUT LOW VOLTAGE
vs. OUTPUT CURRENT
RECEIVER OUTPUT HIGH VOLTAGE
vs. OUTPUT CURRENT
5.0
4.5
4.0
3.5
3.0
2.5
5
4
3
2
1
0
5
V
= 5V
CC
4
3
2
1
0
V
= 5V
CC
V
= 3.3V
CC
V
= 5V
V
= 3.3V
CC
CC
V
= 3.3V
CC
V
= 1V, B = GND, I = -4mA
OH
A
-50 -25
0
25
50
75 100 125
0
10
20
30
40
50
60
-50
-40
-30
-20
-10
0
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Maxim Integrated
3
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
TypicalVOpePatingVChaPactePisticsV(continued)
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
RECEIVER OUTPUT LOW VOLTAGE
vs. TEMPERATURE
RECEIVER PROPAGATION DELAY (t
vs. TEMPERATURE
)
RECEIVER PROPAGATION DELAY (t
)
PHL
PLH
vs. TEMPERATURE
200
9
10
9
8
7
6
5
4
150
100
50
V
= 3.3V
CC
V
= 5V
V
CC
V
= 5V
V
CC
V
= 5V
CC
8
= 3.3V
CC
= 3.3V
CC
7
6
A = GND, V = 1V, I = 4mA
B
OL
0
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX3284E MAXIMUM DATA RATE
vs. VOLTAGE LOGIC LEVEL
SUPPLY CURRENT vs. TEMPERATURE
9
8
7
6
5
60
50
40
30
20
V
= 5V
CC
V
= 3.3V
CC
-50 -25
0
25
50
75 100 125
1.5
2.5
3.5
4.5
5.5
TEMPERATURE (°C)
VOLTAGE LOGIC LEVEL (V)
V SUPPLY CURRENT
L
vs. TEMPERATURE
SUPPLY CURRENT vs. DATA RATE
10
1
10
8
I
, V = V = 5V
L
CC CC
V
= V = 5V
L
CC
V
= V = 3.3V
L
DATA RATE = 52Mbps CC
I
, V = V = 3.3V
L
CC CC
DATA RATE = 52Mbps
6
0.1
I , V = V = 5V
L
CC
L
4
V
= V = 5V
L
CC
DATA RATE = 100kbps
0.01
0.001
2
V
= V = 3.3V
L
I , V = V = 3.3V
CC
L
CC
L
DATA RATE = 100kbps
0
10
100
1000
10,000
100,000
-50 -25
0
25
50
75 100 125
DATA RATE (kbps)
TEMPERATURE (°C)
4
Maxim Integrated
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
-inVSescPiption
PIN
NAME
FUNCTION
ꢀ 5.5V. Bypass with a 0.1µF
MAX3280E MAX3281E MAX3283E MAX3284E
Positive Supply: 3V ꢀ V
capacitor to GND.
CC
1
2
1
2
1
2
3
4
5
1
2
V
CC
GND
RO
B
Ground
Receiver Output. RO will be high if (V - V ) ꢀ -50mV. RO will
A
B
3
3
3
be low if (V - V ) ꢀ -200mV.
A
B
4
4
4
Inverting Receiver Input
Receiver Output Enable. Drive EN low to enable RO. When
EN is high, RO is high impedance.
—
—
—
EN
Receiver Output Enable. Drive EN high to enable RO. When
EN is low, RO is high impedance.
—
5
—
—
EN
Low-Voltage Logic-Level Supply Voltage. V is a user-defined
L
—
5
—
6
—
6
5
6
V
voltage, ranging from 1.65V to V . RO output high is pulled
CC
up to V . Bypass with a 0.1µF capacitor to GND.
L
L
A
Noninverting Receiver Input
15kV ESD without damage. After an ESD event, this
family of parts continues working without latchup.
SetailedVSescPiption
The MAX3280E/MAX3281E/MAX3283E/MAX3284E are
single, true fail-safe receivers designed to operate at
data rates up to 52Mbps. The fail-safe architecture guar-
antees a high output signal if both input terminals are
open or shorted together. See the True Fail-Safe section.
This feature assures a stable and predictable output
logic state with any transmitter driving the line. These
receivers function with a 3.3V or 5V supply voltage and
feature excellent propagation delay times (15ns).
ESD protection can be tested in several ways. The
receiver inputs are characterized for protection to the
following:
•
•
15kV using the Human Body Model
6kV using the Contact Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
•
12kV using the Air-Gap Discharge method speci-
fied in IEC 1000-4-2 (formerly IEC 801-2)
The MAX3280E is a single receiver available in a 5-pin
SOT23 package. The MAX3281E (EN, active high) and
MAX3283E (EN, active low) are single receivers that
also contain an enable pin. Both the MAX3281E and
MAX3283E are available in a 6-pin SOT23 package.
EꢁSVTestVConditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
The MAX3284E is a single receiver that contains a V
L
HumanVBodyVModel
Figure 3a shows the Human Body Model, and Figure
3b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩ resistor.
pin, which allows communication with low-level logic
included in digital FPGAs. The MAX3284E is available
in a 6-pin SOT23 package.
The MAX3284E’s low-level logic application allows
users to set the logic levels. A logic high level of 1.65V
will limit the maximum data rate to 20Mbps.
1ꢀ5kVEꢁSV-Potection
ESD-protection structures are incorporated on the
receiver input pins to protect against ESD encountered
during handling and assembly. The MAX3280E/
MAX3281E/MAX3283E/MAX3284E receiver inputs (A,
B) have extra protection against static electricity found
in normal operation. Maxim’s engineers developed
state-of-the-art structures to protect these pins against
IECV1000D4D2
Since January 1996, all equipment manufactured
and/or sold in the European community has been
required to meet the stringent IEC 1000-4-2 specifica-
tion. The IEC 1000-4-2 standard covers ESD testing
and performance of finished equipment; it does not
specifically refer to integrated circuits. The
MAX3280E/MAX3281E/MAX3283E/MAX3284E help
Maxim Integrated
5
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
users design equipment that meets Level 3 of IEC 1000-
Table 1. MꢇX3281E/MꢇX3283E Enable
Table
4-2, without additional ESD-protection components.
The main difference between tests done using the
PꢇRT
MAX3281E
MAX3283E
ENꢇꢂLE = ꢁꢃꢈꢁ
Active
ENꢇꢂLE = LOW
High Z
Human Body Model and IEC 1000-4-2 is higher peak
current in IEC 1000-4-2. Because series resistance is
lower in the IEC 1000-4-2 ESD test model (Figure 4a),
the ESD-withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 4b shows the current waveform for
the 8kV IEC 1000-4-2 Level 4 ESD Contact Discharge
test. The Air-Gap test involves approaching the device
with a charger probe. The Contact Discharge method
connects the probe to the device before the probe is
energized.
High Z
Active
LowDkoltageVLogicVLevelsV
(MAX3284EVonly)
An increasing number of applications now operate at
low-voltage logic levels. To enable compatibility with
these low-voltage logic level applications, such as digi-
tal FPGAs, the MAX3284E V pin is a user-defined sup-
L
ply voltage that designates the voltage threshold for a
logic high.
MachineVModel
The Machine Model for ESD testing uses a 200pF stor-
age capacitor and zero-discharge resistance. It mimics
the stress caused by handling during manufacturing
and assembly. All pins (not just the RS-485 inputs)
require this protection during manufacturing. Therefore,
the Machine Model is less relevant to the I/O ports than
are the Human Body Model and IEC 1000-4-2.
At lower V voltages, the data rate will also be lower. A
L
logic-high level of 1.65V will receive data at 20Mbps.
Table 2 gives data rates at various voltages at V .
L
Table 2. MꢇX3284E Data Rate Table
k
ꢄꢄ
= 3k TO ꢀ.ꢀk
k
MꢇXꢃMUM DꢇTꢇ RꢇTE
TPueVFailDꢁafeV
The MAX3280E/MAX3281E/MAX3283E/MAX3284E
guarantee a logic-high receiver output when the receiv-
er inputs are shorted or open, or when they are con-
nected to a terminated transmission line with all drivers
disabled. This guaranteed logic high is achieved by
setting the receiver threshold between -50mV and
-200mV. If the differential receiver input voltage
L
1.65V
2.2V
20Mbps
33Mbps
52Mbps
≥3.3V
ApplicationsVInfoPmation
(V - V ) is greater than or equal to -50mV, RO is logic
A
B
-PopagationVSelayVMatching
high. If (V - V ) is less than or equal to -200mV, RO is
A
B
The MAX3280E/MAX3281E/MAX3283E/MAX3284E
logic low.
(V
= V ) exhibit propagation delays that are closely
L
CC
In the case of a terminated bus with all transmitters dis-
abled, the receiver’s differential input voltage is pulled
to ground by the termination. This results in a logic high
with a 50mV minimum noise margin. Unlike previous
fail-safe devices, the -50mV to -200mV threshold com-
plies with the 200mV EIA/TIA-485 standard.
matched from one device to another, even between
devices from different production lots. This feature
allows multiple data lines to receive data and clock sig-
nals with minimal skew with respect to each other.
Figure 5 shows the typical propagation delays. Small
receiver skew times, the difference between the low-to-
high and high-to-low propagation delay, help maintain a
symmetrical ratio (50% duty cycle). The receiver skew
ReceivePVEnableV
(MAX3281EVandVMAX3283EVonly)
time | t
- t
| is under 2ns for either a 3.3V supply
PLH PHL
The MAX3281E and MAX3283E feature a receiver out-
put enable (EN, MAX3281E or EN, MAX3283E) input
that controls the receiver. The MAX3281E receiver
enable (EN) pin is active high, meaning the receiver
outputs are active when EN is high. The MAX3283E
receiver enable (EN) pin is active low. Receiver outputs
are high impedance when the MAX3281E’s EN pin is
low and when the MAX3283E’s EN pin is high.
or a 5V supply.
MultidPopVCloc5VSistPibution
Low package-to-package skew (8ns max) makes the
MAX3280E/MAX3281E/MAX3283E/MAX3284E
(V
CC
= V ) ideal for multidrop clock distribution. When
L
distributing a clock signal to multiple circuits over long
transmission lines, receivers in separate locations, and
possibly at two different temperatures, would ideally
6
Maxim Integrated
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
provide the same clock to their respective circuits.
Thus, minimal package-to-package skew is critical. The
skew must be kept well below the period of the clock
signal to ensure that all of the circuits on the network
are synchronized.
(48kΩ), which allows up to 128 receivers on the bus.
Any combination of these RS-485 receivers with a total
of 32 unit loads can be connected to the same bus.
ThePmalV-PotectionV
The MAX3280E/MAX3281E/MAX3283E/MAX3284E fea-
ture thermal protection. Thermal protection sets the out-
put stage in high-impedance mode when a short circuit
occurs at the output, limiting both the power dissipation
and temperature. The thermal temperature threshold is
+165°C, with a hysteresis of 20°C.
128VReceivePsVonVtheVBus
The standard RS-485 input impedance is 12kΩ (one-
unit load). The standard RS-485 transmitter can drive
32 unit loads. The MAX3280E/MAX3281E/MAX3283E/
MAX3284E present a 1/4-unit-load input impedance
TestVCiPcuits/TimingVSiagPams
V
OH
V /2
CC
V /2
CC
RO
V
OL
OUTPUT
t
t
PLH
PHL
1V
A
INPUT
-1V
B
f
IN
= 1MHz
t , t ≤ 3ns
r
f
Figure 1. Receiver Propagation Delay
S3
S1
1.5V
-1.5V
V
CC
1kΩ
V
ID
R
S2
C
L
GENERATOR
50Ω
V
V
0
V
CC
CC
S1 OPEN
S2 CLOSED
S3 = 1.5V
S1 CLOSED
S2 OPEN
S3 = -1.5V
V
/2
V
/2
CC
CC
0
EN
EN
t
PRZH
t
PRZL
V
OUT
OH
CC
CC
V
/2
CC
V
/2
CC
OUT
0
V
V
OL
V
CC
S1 CLOSED
S2 OPEN
S3 = -1.5V
S1 OPEN
S2 CLOSED
S3 = 1.5V
V
/2
CC
V
/2
CC
0
V
V
EN
0
EN
t
PRHZ
t
PRLZ
V
OUT
OH
CC
OL
0.25V
OUT
0.25V
0
FOR MAX3281E THE ENABLE SIGNAL IS INVERTED.
Figure 2. MAX3281E/MAX3283E Receiver Enable/Disable Timing
Maxim Integrated
7
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
TestVCiPcuits/TimingVSiagPamsV(continued)
R
C
R
D
1MΩ
1.5kΩ
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
s
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 3a. Human Body ESD Test Model
Figure 3b. Human Body Model Current Waveform
R
R
D
330Ω
I
C
50Ω to 100Ω
100%
90%
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
SOURCE
10%
Figure 4a. IEC 1000-4-2 ESD Test Model
t
t = 0.7ns to 1ns
r
30ns
60ns
Figure 4b. IEC 1000-4-2 ESD Generator Current Waveform
A, 1V/div
RO, 2.5V/div
B = GND
10ns
Figure 5. Receiver Propagation Delay Driven by External RS-
485 Device
8
Maxim Integrated
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
-inVConfiguPations
TOP VIEW
+
+
+
V
1
2
3
5
4
A
B
V
1
2
3
6
5
4
A
V
CC
1
2
3
6
5
4
A
V
B
CC
CC
MAX3280E
MAX3281E
MAX3283E
MAX3284E
GND
RO
GND
RO
EN (EN)
B
GND
RO
L
SOT23-5
SOT23-6
SOT23-6
( ) ARE FOR MAX3283E
TypicalVOpePatingVCiPcuit
ChipVInfoPmation
PROCESS: BiCMOS
TRANSMITTER
DATA IN
RO1
120Ω
MAX3283E
-ac5ageVInfoPmation
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/pac5ages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
EN
RO2
MAX3281E
PꢇꢄKꢇꢈE
TYPE
PꢇꢄKꢇꢈE
ꢄODE
OUTLꢃNE
NO.
LꢇND
PꢇTTERN NO.
5 SOT23
6 SOT23
U5+2
U6+1
21-ꢅꢅꢀ7
21-ꢅꢅꢀ8
9ꢅ-ꢅ174
9ꢅ-ꢅ17ꢀ
MAX3281E/MAX3283E IN REDUNDANT
RECEIVER APPLICATION
EN
Maxim Integrated
9
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
1ꢀ5kVEꢁSD-PotectedVꢀ2Mbps,V3kVtoVꢀ.ꢀk,VꢁOT23
RꢁD48ꢀ/RꢁD422VTPueVFailDꢁafeVReceivePs
RevisionVHistoPy
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1/02
Initial release
—
1, 9
1
Added lead-free parts to the Ordering Information, deleted the transistor count from the
Chip Information section
1
2
3/11
2/12
Added automotive qualified part to Ordering Information
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
10 ________________________________MaximVIntegPatedVV160VRioVRobles,VꢁanVJose,VCAV9ꢀ134VUꢁAVV1D408D601D1000
© 2012 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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