MAX3395EEBC+ [MAXIM]
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| 型号： | MAX3395EEBC+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 暂无描述 转换器 电平转换器 驱动 |
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19-3884; Rev 2; 2/07
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
General Description
Features
The MAX3394E/MAX3395E/MAX3396E bidirectional
level translators provide level shifting required for data
transfer in a multivoltage system. Internal slew-rate
enhancement circuitry features 10mA current-sink and
15mA current-source drivers to isolate capacitive loads
from lower current drivers. In open-drain systems, slew-
rate enhancement enables fast data rates with larger
pullup resistors and increased bus load capacitance.
♦
15kV ESD Protection on I/O V
Lines
CC_
♦ Bidirectional Level Translation Without Direction
Pin
♦ I/O V and I/O V
10mA Sink-/15mA Source-
L_
CC_
Current Capability
♦ Slew-Rate Enhancement Circuitry Supports
Larger Capacitive Loads or Larger External Pullup
Resistors
♦ 6Mbps Push-Pull/1Mbps Open-Drain Guaranteed
Externally applied voltages, V
and V , set the logic-
L
CC
high levels for the device. A logic-low signal on one I/O
side of the device appears as a logic-low signal on the
opposite I/O side, and vice-versa. Each I/O line is
Data Rate
♦ Wide Supply-Voltage Range: Operation Down to
pulled up to V
or V by an internal pullup resistor,
L
allowing the devices to be driven by either push-pull or
open-drain drivers.
CC
+1.2V on V and +1.65V on V
L
CC
♦ Low Supply Current in Tri-State Output Mode
(3µA typ)
The MAX3394E/MAX3395E/MAX3396E feature a tri-
state output mode, thermal-shutdown protection, and
15kV ꢀuman ꢁody Model ꢂꢀꢁMꢃ EꢄS protection on
♦ Low Quiescent Current
♦ Thermal-Shutdown Protection
♦ UCSP, TDFN, and TQFN Packages
the V
side for greater protection in applications that
CC
route signals externally.
Ordering Information
The MAX3394E/MAX3395E/MAX3396E accept V
volt-
CC
ages from +1.65V to +5.5V, and V voltages from +1.2V
L
PART
PIN-PACKAGE
8 TSFN-EP**
9 UCꢄP
PKG CODE
T833-1
ꢁ9-5
to V , making them ideal for data transfer between low
CC
MAX3394EETA+T
MAX3394EEꢁL+T
MAX3395EETC+
MAX3395EEꢁC+T
MAX3396EEꢁP+T*
MAX3396EETP+*
voltage AꢄIC/PLSs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396E operate at a guaran-
teed data rate of 6Mbps with push-pull drivers and
1Mbps with open-drain drivers.
12 TQFN-EP**
12 UCꢄP
T1244-4
ꢁ12-1
The MAX3394E is a dual-level translator available in
9-bump UCꢄP™ and 8-pin 3mm x 3mm TSFN packages.
The MAX3395E is a quad-level translator available in 12-
bump UCꢄP, and 12-pin 4mm x 4mm TQFN packages.
The MAX3396E is an octal-level translator available in 20-
bump UCꢄP and 20-pin 5mm x 5mm TQFN packages.
The MAX3394E/MAX3395E/MAX3396E operate over the
extended -40°C to +85°C temperature range.
20 UCꢄP
ꢁ20-1
20 TQFN-EP**
T2055-4
Note: All devices specified over the -40°C to +85°C operating
range.
+Senotes leadꢂPbꢃ-free/Roꢀꢄ-compliant package.
*Future product—contact factory for availability.
**EP = Exposed paddle.
Applications
Multivoltage ꢁidirectional Level Translation
ꢄPI™, MICROWIRE™, and I2C Level Translation
Open-Srain Rise-Time ꢄpeed-Up
Selector Guide appears at end of data sheet.
-in Configurations
TOP VIEW
(LEADS ON BOTTOM)
ꢀigh-ꢄpeed ꢁus Fan-Out Expansion
Cell Phones
8
6
7
5
4
*EP
Telecom, Networking, ꢄervers, RAIS/ꢄAN
MAX3394E
+
1
2
3
MICROWIRE is a trademark of National ꢄemiconductor Corp.
ꢄPI is a trademark of Motorola, Inc.
TDFN
*CONNECT EXPOSED PAD TO GROUND
UCꢄP is a trademark of Maxim Integrated Products, Inc.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
ABSOLUTE MAXIMUM RATINGS
ꢂAll voltages referenced to GNS.ꢃ
12-Pin TQFN ꢂderate 16.9mW/°C above +70°Cꢃ ........1349mW
12-ꢁump UCꢄP ꢂderate 6.5mW/°C above +70°Cꢃ ..... 519mW
20-Pin TQFN ꢂderate 20.8mW/°C above +70°Cꢃ ........1667mW
20-ꢁump UCꢄP ꢂderate 10.0mW/°C above +70°Cꢃ .....800mW
Operating Temperature Range ......................... -40°C to +85°C
ꢄtorage Temperature Range ........................... -65°C to +150°C
Junction Temperature .....................................................+150°C
ꢁump Temperature ꢂsolderingꢃ ...................................... +235°C
Lead Temperature ꢂsoldering, 10sꢃ ............................... +300°C
V
CC
......................................................................... -0.3V to +6V
V ............................................................................ -0.3V to +6V
L
I/O V
...................................................... -0.3V to V
+ 0.3V
CC_
CC
L
I/O V ........................................................... -0.3V to V + 0.3V
L_
EN ........................................................................... -0.3V to +6V
ꢄhort-Circuit Suration I/O V , I/O V to GNS ..... Continuous
L_
CC_
Maximum Continuous Current ........................................ 50mA
Continuous Power Sissipation ꢂT = +70°Cꢃ
A
8-Pin TSFN ꢂderate 18.2mW/°C above +70°Cꢃ ........ 1455mW
9-ꢁump UCꢄP ꢂderate 4.7mW/°C above +70°Cꢃ ........ 379mW
ꢄtresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
ꢂV
CC
= +1.65V to +5.5V, V = +1.2V to V ; C
≤ 15pF, C ≤ 15pF; T = -40°C to +85°C, unless otherwise noted. Typical val-
IOVCC A
L
CC IOVL
ues are at T = +25°C.ꢃ ꢂNote 1ꢃ
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
V ꢄupply Range
V
1.2
V
CC
V
V
L
L
V
ꢄupply Range
V
1.65
5.50
150
300
600
30
CC
CC
MAX3394E
MAX3395E
MAX3396E
MAX3394E
MAX3395E
MAX3396E
I/O lines internally
pulled up
ꢄupply Current from V
I
µA
µA
CC
L
CC
I/O lines internally
pulled up
ꢄupply Current from V
I
30
L
30
V
Tri-ꢄtate ꢄupply Current
I
EN = GNS, T = +25°C
3
6
µA
µA
CC
CC-3
A
45/MAX396E
V Tri-ꢄtate ꢄupply Current
L
I
EN = GNS, T = +25°C
0.7
2
L-3
A
LOGIC I/O
I/O V _ Input-Voltage ꢀigh
L
Threshold
0.7 x
V
L
V
V
IꢀL
I/O V _ Input-Voltage Low
L
Threshold
0.3 x
V
L
V
V
ILL
I/O V _ Internal Pullup SC
L
Resistance
R
EN = V
or V
L
5
10
15
10
20
kΩ
mA
mA
L
CC
I/O V _ ꢄource Current Suring
L
Low-to-ꢀigh Transition
I
V = +1.2V
L
IꢀL
I/O V _ ꢄink Current Suring ꢀigh-
L
to-Low Transition
I
V
= +1.65V
CC
ILL
2
_______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
ELECTRICAL CHARACTERISTICS (continued)
ꢂV
CC
= +1.65V to +5.5V, V = +1.2V to V ; C
≤ 15pF, C
≤ 15pF; T = -40°C to +85°C, unless otherwise noted. Typical val-
IOVCC A
L
CC IOVL
ues are at T = +25°C.ꢃ ꢂNote 1ꢃ
A
PARAMETER
SYMBOL
CONDITIONS
= +3.3V, V = +1.8V
MIN
TYP
MAX
UNITS
I/O V _ Low-to-ꢀigh Transition
L
Threshold
0.3 x
0.5 x
V
L
V
V
V
L-Tꢀ
CC
L
V
L
I/O V _ sink current = 5mA, V
= 0V
0.25
L
ILC
I/O V _ Output-Voltage Low
V
V
L
OLL
I/O V _ sink current = 10mA, V
≤ 0.4V or
V
+
ILC
L
ILC
0.2 x V
0.4V
L
I/O V _ Tri-ꢄtate Output Leakage
L
Current
EN = GNS, T = +25°C
A
-1
+1
µA
V
I/O V _ Input-Voltage ꢀigh
CC
Threshold
0.7 x
V
CC
V
ꢂNote 2ꢃ
ꢂNote 2ꢃ
IꢀC
I/O V _ Input-Voltage Low
CC
Threshold
0.3 x
V
V
ILC
V
CC
I/O V _ Internal Pullup SC
CC
Resistance
R
EN = V
or V
L
5
10
15
20
kΩ
mA
mA
V
CC
CC
I/O V _ ꢄource Current Suring
CC
Low-to-ꢀigh Transition
I
V
V
V
= +1.65V
= +1.65V
IꢀCC
CC
CC
CC
I/O V _ ꢄink Current Suring
CC
ꢀigh-to-Low Transition
I
10
ILCC
I/O V _ Low-to-ꢀigh Transition
CC
Threshold
0.3 x
CC
0.5 x
V
CC
V
= +3.3V, V = +1.8V
L
CC-Tꢀ
V
I/O V _ sink current = 5mA, V = 0V
0.25
CC
ILL
I/O V _ Output-Voltage Low
V
V
CC
OLC
I/O V _ sink current = 10mA, V ≤ 0.4V
V
+
ILL
CC
ILL
or 0.2 x V
0.4V
L
I/O V _ Tri-ꢄtate Output
CC
Leakage Current
EN = GNS, T = +25°C
-1
+1
µA
V
A
0.7 x
EN Input-Voltage ꢀigh Threshold
V
IꢀE
V
L
0.3 x
EN Input-Voltage Low Threshold
V
V
ILE
V
L
EN Pin Input Leakage Current
T
= +25°C
-1
+1
µA
A
ESD PROTECTION
I/O V _ EꢄS Protection
C
= 1µF, ꢀuman ꢁody Model
VCC
15
kV
CC
_______________________________________________________________________________________
3
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
TIMING CHARACTERISTICS
ꢂV
CC
= +1.65V to +5.5V, V = +1.2V to V ; C
≤ 15pF, C ≤ 15pF; T = -40°C to +85°C, unless otherwise noted. Typical val-
IOVCC A
L
CC IOVL
ues are at T = +25°C.ꢃ ꢂNote 1ꢃ
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
50
UNITS
Push-pull driver, Figure 1
I/O V _ Rise Time
t
ns
CC
RVCC
Open-drain driver, internal pullup, Figure 2
Push-pull driver, Figure 1
500
50
I/O V _ Fall Time
t
ns
ns
ns
CC
FVCC
Open-drain driver, internal pullup, Figure 2
Push-pull driver, Figure 3
50
50
I/O V _ Rise Time
t
RVL
L
Open-drain driver, internal pullup, Figure 4
Push-pull driver, Figure 3
500
50
I/O V _ Fall Time
L
t
FVL
Open-drain driver, internal pullup, Figure 4
Push-pull driver, Figure 1
50
50
t
t
I/OVL-VCC
I/OVCC-VL
Open-drain driver, internal pullup, Figure 2
Push-pull driver, Figure 3
600
50
Propagation Selay
ns
Open-drain driver, internal pullup, Figure 4
Push-pull or open-drain driver, Figure 5
Push-pull driver
600
5
Propagation Selay After EN
Channel-to-Channel ꢄkew
t
µs
ns
EN
5
t
ꢄKEW
Open-drain driver, internal pullup
Push-pull driver, Figures 1, 3
100
6
Maximum Sata Rate
Mbps
Open-drain driver, internal pullup,
Figures 2, 4
1
Note 1: All units are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design
A
and not production tested.
Note 2: Suring a low-to-high transition, the threshold at which the I/O changes state is the lower of V and V
since the two sides
ILC
ILL
are internally connected by an internal switch while the device is in the logic-low state.
45/MAX396E
4
_______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
Typical Operating Characteristics
ꢂV
CC
= +2.5V, V = +1.8V, C = 15pF, T = +25°C, unless otherwise noted.ꢃ
L
L
A
V
CC
SUPPLY CURRENT
vs. TEMPERATURE
V
SUPPLY CURRENT
V SUPPLY CURRENT
L
vs. SUPPLY VOLTAGE
CC
vs. SUPPLY VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
DRIVING I/O V
L_
V = +1.2V
DRIVING I/O V
V
= +5.0V
L
CC
DRIVING I/O V
L_
L_
2.5
2.0
1.5
1.0
0.5
0
6Mbps PUSH-PULL
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
6Mbps PUSH-PULL
1Mbps OPEN-DRAIN
1Mbps OPEN-DRAIN
-40
-15
10
35
60
85
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
V SUPPLY VOLTAGE (V)
L
V
CC
V
SUPPLY CURRENT
V SUPPLY CURRENT
L
vs. LOAD CAPACITANCE
V SUPPLY CURRENT
L
vs. TEMPERATURE
CC
vs. LOAD CAPACITANCE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
3.0
2.5
2.0
1.5
1.0
0.5
0
DRIVING I/O V
L_
DRIVING I/O V
DRIVING I/O V
L_
L_
6Mbps PUSH-PULL
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
1Mbps OPEN-DRAIN
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
-40
-15
10
35
60
85
TEMPERATURE (°C)
OPEN-DRAIN RISE TIME
vs. LOAD CAPACITANCE
OPEN-DRAIN FALL TIME
vs. LOAD CAPACITANCE
PUSH-PULL RISE TIME
vs. LOAD CAPACITANCE
500
450
400
350
300
250
200
150
100
50
30
25
20
15
10
5
30
25
20
15
10
5
DRIVING I/O V
CC_
DRIVING I/O V
L_
DRIVING I/O V
L_
DRIVING I/O V
DRIVING I/O V
CC_
CC_
DRIVING I/O V
L_
0
0
0
0
10 20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
_______________________________________________________________________________________
5
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
Typical Operating Characteristics (continued)
ꢂV
CC
= +2.5V, V = +1.8V, C = 15pF, T = +25°C, unless otherwise noted.ꢃ
L L A
PUSH-PULL FALL TIME
vs. LOAD CAPACITANCE
PROPAGATION DELAY
vs. LOAD CAPACITANCE
PROPAGATION DELAY
vs. LOAD CAPACITANCE
20
18
16
14
12
10
8
14
12
10
8
30
25
20
15
10
5
DRIVING I/O V
OPEN-DRAIN
DRIVING I/O V OPEN-DRAIN
CC_
L_
t
PDHL
DRIVING I/O V
CC_
6
6
4
DRIVING I/O V
L_
t
4
PDHL
2
t
t
2
PDLH
PDLH
0
0
0
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
(DRIVING I/O V , V = +2.5V, V = +1.8V,
L_ CC
L
PROPAGATION DELAY
vs. LOAD CAPACITANCE
PROPAGATION DELAY
vs. LOAD CAPACITANCE
C = 15pF, DATA RATE = 6Mbps)
L
MAX3394E-96E toc15
20
18
16
14
12
10
8
50
45
40
35
30
25
20
15
10
5
DRIVING I/O V PUSH-PULL
L_
DRIVING I/O V
SEE FIGURE 3
PUSH-PULL
CC_
I/O V
1V/div
L_
t
PDHL
t
PDHL
I/O V
1V/div
CC_
6
4
9
t
PDLH
2
0
0
40ns/div
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
(DRIVING I/O V , V = +5.0V, V = +3.3V,
L_ CC
L
(DRIVING I/O V , V = +5.0V, V = +3.3V,
C = 400pF, EXTERNAL 4.7kΩ
L_ CC
L
L
C = 100pF, DATA RATE = 1Mbps)
PULLUPS, DATA RATE = 1Mbps)
L
MAX3394E-96E toc16
MAX3394E-96E toc17
I/O V
L_
2V/div
I/O V
2V/div
L_
I/O V
2V/div
I/O V
2V/div
CC_
CC_
200ns/div
200ns/div
6
_______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
-in Description
PIN
NAME
FUNCTION
MAX3394E
MAX3395E
MAX3396E
TDFN
UCSP
TQFN
UCSP
TQFN
UCSP
V
V
ꢄupply Voltage +1.65V ≤ V
to GNS with a 0.1µF ceramic capacitor and a
≤ +5.5V. ꢁypass
CC
CC
CC
1
2
A1
11
6
ꢁ1
14
4
S3
V
CC
1µF or greater ceramic capacitor as close to the
device as possible.
Enable Input. Srive EN logic high for normal
operation. Srive EN logic low to force all I/O lines to
a high-impedance state and disconnect internal
pullup resistors.
ꢁ1
ꢁ3
A4
EN
3
4
5
6
7
A2
A3
ꢁ3
C3
C2
10
9
C1
C2
ꢁ4
A2
A1
18
16
13
20
19
C1
S1
S4
A1
ꢁ1
I/O V
1
2
I/O 1 Referred to V
I/O 2 Referred to V
Ground
CC
CC
I/O V
CC
CC
5
GNS
I/O V 2
2
I/O 2 Referred to V
I/O 1 Referred to V
L
L
L
1
I/O V 1
L
Logic ꢄupply Voltage +1.2V ≤ V ≤ V . ꢁypass V
L
L
CC
to GNS with a 0.1µF or greater ceramic capacitor
8
C1
12
ꢁ2
3
A3
V
L
as close to the device as possible.
—
—
—
—
—
—
—
—
—
—
—
—
EP
—
—
—
—
—
—
—
—
—
—
—
—
—
3
4
A3
A4
C4
C3
—
—
—
—
—
—
—
—
—
1
2
ꢁ2
A2
S2
C2
C3
S5
C4
C5
ꢁ3
A5
ꢁ4
ꢁ5
—
I/O V 3
I/O 3 Referred to V
I/O 4 Referred to V
I/O 4 Referred to V
I/O 3 Referred to V
I/O 5 Referred to V
I/O 6 Referred to V
I/O 7 Referred to V
I/O 8 Referred to V
I/O 5 Referred to V
I/O 6 Referred to V
I/O 7 Referred to V
I/O 8 Referred to V
L
L
I/O V 4
L
L
7
15
17
12
11
10
9
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
4
3
5
6
7
8
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
L
8
—
—
—
—
—
—
—
—
EP
5
I/O V 5
L
6
I/O V 6
L
L
7
I/O V 7
L
L
8
I/O V 8
L
L
EP
EP
Exposed Pad. Connect exposed pad to GNS.
pullup resistors and increased bus load capacitance.
Externally applied voltages, V and V , set the logic-
Detailed Description
CC
L
The MAX3394E/MAX3395E/MAX3396E bidirectional
level translators provide level shifting required for data
transfer in a multivoltage system. Internal slew-rate
enhancement circuitry features 10mA current-sink and
15mA current-source drivers to isolate capacitive loads
from lower current drivers. In open-drain systems, slew-
rate enhancement enables fast data rates with larger
high levels for the device. A logic-low signal on one I/O
side of the device appears as a logic-low signal on the
opposite I/O side and vice-versa. Each I/O line is pulled
up to V
or V by an internal pullup resistor, allowing
L
CC
the devices to be driven by either push-pull or open-
drain drivers.
_______________________________________________________________________________________
7
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
t
t
RVCC
FVCC
V
V
CC
L
90%
90%
V
EN
V
CC
L
MAX3394E
MAX3395E
MAX3396E
I/O V
L
50%
50%
V
V
L
CC
50%
50%
I/O V
L_
I/O V
CC_
10%
I/O V
10%
CC
50Ω
C
IOVCC
t
I/OVL-VCC
t
I/OVL-VCC
Figure 1. Push-Pull Sriving I/O V Test Circuit and Timing
L_
t
t
RVCC
FVCC
V
L
V
CC
I/O V
CC
90%
90%
EN
V
V
L
CC
MAX3394E
MAX3395E
MAX3396E
V
GATE
50%
50%
V
V
L
CC
50%
50%
I/O V
I/O V
CC_
L_
10%
10%
45/MAX396E
C
IOVCC
V
GATE
t
I/OVL-VCC
t
I/OVL-VCC
Figure 2. Open-Srain Sriving I/O V Test Circuit and Timing
L_
The MAX3394E/MAX3395E/MAX3396E feature a tri-
state output mode, thermal-shutdown protection, and
15kV ꢀuman ꢁody Model ꢂꢀꢁMꢃ EꢄS protection on
teed data rate of 6Mbps with push-pull drivers and
1Mbps with open-drain drivers.
Level Translation
The MAX3394E/MAX3395E/MAX3396E utilize a trans-
mission gate architecture to provide bidirectional level
the V
side for greater protection in applications that
CC
route signals externally.
The MAX3394E/MAX3395E/MAX3396E accept V
volt-
CC
translation between I/O V _ and I/O V _. The trans-
L
CC
ages from +1.65V to +5.5V, and V voltages from +1.2V
L
mission gate architecture is comprised of a pass-FET,
gate-control logic, and slew-rate enhancement circuit-
to V , making them ideal for data transfer between low-
CC
voltage AꢄIC/PLSs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396E operate at a guaran-
ry. When both I/O V _ and I/O V _ are logic high, the
L
CC
gate-control logic disables the pass-FET, providing
8
_______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
t
t
FVL
RVL
V
V
L
CC
I/O V
CC
EN
V
V
CC
L
MAX3394E
MAX3395E
MAX3396E
V
V
CC
L
90%
90%
50%
50%
50%
50%
I/O V
CC_
I/O V
L_
10%
50Ω
10%
t
I/O V
L
C
IOVL
t
I/OVCC-VL
I/OVCC-VL
Figure 3. Push-Pull Sriving I/O V
Test Circuit and Timing
CC_
t
t
RVL
V
L
V
FVL
CC
EN
V
V
L
CC
I/O V
L
MAX3394E
MAX3395E
MAX3396E
90%
90%
50%
50%
V
V
CC
L
50%
50%
I/O V
10%
10%
I/O V
CC_
L_
C
IOVL
V
GATE
t
t
I/OVCC-VL
I/OVCC-VL
Figure 4. Open-Srain Sriving I/O V
Test Circuit and Timing
CC_
capacitive isolation between I/O lines. When one or
both I/O lines are at a logic-low level, the gate-control
logic turns the pass-FET on. When the pass-FET is
active, I/O V _ and I/O V _ are connected, allowing
the logic-low signal to be expressed simultaneously on
both I/O lines.
Internal ꢁlewꢂRate Enhancement
Internal slew-rate enhancement circuitry accelerates
logic-state changes by turning on MOꢄFETs M and
P1
M
M
during low-to-high logic transitions, and MOꢄFETs
L
CC
P2
N3
and M
during high-to-low logic transitions ꢂsee
N4
the Functional Siagramꢃ. Suring logic-state changes,
speed-up MOꢄFETꢄ are triggered by I/O line voltage
thresholds. MOꢄFETꢄ M
high-to-low logic transitions. M and M source 15mA
The MAX3394E/MAX3395E/MAX3396E have internal
and M
sink 10mA during
N3
N4
10kΩ ꢂtypꢃ pullup resistors from I/O V _ and I/O V
_
L
CC
P1
P2
to the respective supply voltages, allowing operation
with open-drain drivers. Internal slew-rate enhancement
circuitry accelerates logic-state transitions, maintaining
a fast data rate with a higher bus load capacitance.
Additionally, the 10mA current sink drivers permit the
use of smaller external pullup resistors.
during low-to-high logic transitions. ꢄlew-rate enhance-
ment allows a fast data rate despite large capacitive bus
loads, and permits larger external pullup resistors.
_______________________________________________________________________________________
9
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
V
V
V
L
V
CC
L
CC
V
V
V
CC
V
CC
L
L
EN
EN
MAX3394E
MAX3395E
MAX3396E
MAX3394E
MAX3395E
MAX3396E
V
V
V
V
L
CC
L
CC
R
R
LOAD
LOAD
I/O V
I/O V
I/O V
CC_
I/O V
CC_
L_
L_
C
C
IOVCC
IOVL
50Ω
50Ω
t
EN
V
I/O V
CC_
EN
0.5V
TIME
V
t
EN
45/MAX396E
EN
I/O V
L_
0.2V (V < 2V)
L
0.5V (V ≥ 2V)
L
TIME
Figure 5. Enable Test Circuit and Timing
Tri-State Output Mode
for normal operation. Srive
CC
-owerꢂꢁupply ꢁequencing
The MAX3394E/MAX3395E/MAX3396E require two sup-
ply voltages. For proper operation, ensure that +1.65V ≤
Connect EN to V or V
L
EN low to force the MAX3394E/MAX3395E/MAX3396E
to a tri-state output mode. In tri-state output mode, all
I/O lines are driven to a high-impedance state, and the
pass-FET is disabled to prevent current flow between
I/O lines. Tri-state output mode disables the internal
pullup resistors on I/O V _ and I/O V _, and reduces
V
CC
≤ +5.5V, and +1.2V ≤ V ≤ V . There are no restric-
L CC
tions on power-supply sequencing. Suring power-up or
power-down, the MAX3394E/MAX3395E/MAX3396E can
withstand either the V or the V
supply floating while
L
CC
the other supply is applied. The device will not latch up in
this state.
L
CC
supply current to 3µA typ ꢂV ꢃ and 0.7µA typ ꢂV ꢃ.
CC
L
10 ______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
R
C
R
D
1MΩ
1500Ω
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
36.8%
DEVICE-
UNDER-
TEST
C
100pF
STORAGE
CAPACITOR
s
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 6b. ꢀꢁM Sischarge Current Waveform
Figure 6a. ꢀuman ꢁody EꢄS Test Model
To ensure full 15kV EꢄS protection, bypass V
ground with a 0.1µF ceramic capacitor and an additional
1µF ceramic capacitor as close to the device as possible.
to
CC
The high-impedance state of the I/O lines during tri-
state output mode facilitates use in multidrop networks.
In tri-state output mode, do not exceed ꢂV + 0.3Vꢃ on
L
I/O V _ or ꢂV
+ 0.3Vꢃ on I/O V _.
CC CC
L
EꢁD Test Conditions
EꢄS performance depends on a variety of conditions.
Contact Maxim for a reliability report documenting test
setup, methodology, and results.
Thermalꢂꢁhutdown -rotection
The MAX3394E/MAX3395E/MAX3396E are protected
from thermal damage resulting from short-circuit faults.
In the event of a short-circuit fault, when the junction
Applications Information
temperature ꢂT ꢃ reaches +125°C, a thermal sensor
J
forces the device into the tri-state output mode. When
-owerꢂꢁupply Decoupling
to ground with 0.1µF ceramic
CC
T drops below +115°C, normal operation resumes.
J
ꢁypass V and V
L
capacitors. To ensure full 15kV EꢄS protection,
bypass V to ground with an additional 1µF or greater
ceramic capacitor. Place all capacitors as close to the
device as possible.
±±5ꢀk EꢁD -rotection
As with all Maxim devices, EꢄS-protection structures are
incorporated on all pins to protect against EꢄS encoun-
CC
tered during handling and assembly. The I/O V _ lines
CC
are further protected by advanced EꢄS structures to
guard these pins from damage caused by EꢄS of up to
15kV. Protection structures prevent damage caused by
EꢄS events in normal operation, tri-state output mode,
and when the device is unpowered. After arresting an
EꢄS event, MAX3394E/MAX3395E/MAX3396E continue
to function without latching up, whereas competing
devices can enter a latched-up state and must be power
cycled to restore functionality.
OpenꢂDrain Mode vs. -ushꢂ-ull Mode
The MAX3394E/MAX3395E/MAX3396E are compatible
with push-pull ꢂactiveꢃ and open-drain drivers. For push-
pull operation, maximum data rate is guaranteed to
6Mbps. For open-drain applications, the MAX3394E/
MAX3395E/MAX3396E include internal pullup resistors
and slew-rate enhancement circuitry, providing a maxi-
mum data rate of 1Mbps. External pullup resistors can
be added to increase data rate when the bus is loaded
by high capacitance. ꢂꢄee the Use of External Pullup
Resistors section.ꢃ
ꢄeveral EꢄS testing standards exist for gauging the
robustness of EꢄS structures. The EꢄS protection of
the MAX3394E/MAX3395E/MAX3396E is characterized
for the human body model ꢂꢀꢁMꢃ. Figure 6a shows the
model used to simulate an EꢄS event resulting from
contact with the human body. The model consists of a
100pF storage capacitor that is charged to a high volt-
age then discharged through a 1.5kΩ resistor. Figure
6b shows the current waveform when the storage
capacitor is discharged into a low impedance.
Serial-Interface Level Translation
The MAX3395E provides level translation on four I/O
lines, making it an ideal device for multivoltage I2C,
MICROWIRE, and ꢄPI serial interfaces.
Use of External -ullup Resistors
The MAX3394E/MAX3395E/MAX3396E include internal
10kΩ pullup resistors. Suring a low-to-high logic transi-
tion, the internal pullup resistors charge the bus capac-
______________________________________________________________________________________ 11
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
Functional Diagram
V
CC
V
L
V
L
V
CC
M
P1
M
P2
GATE CONTROL
I/O V
I/O V
L_
CC_
N-CHANNEL
PASS-FET
SLEW-RATE
ENHANCEMENT
M
N3
M
N4
Typical Operating Circuit
+1.8V
+3.3V
0.1μF
1μF
0.1μF
V
V
L
CC
+1.8V
SYSTEM
CONTROLLER
+3.3V
SYSTEM
MAX3394E
EN
EN
I/O V
I/O V
1
I/O V 1
L
CLK
CLK
CC
I/O V 2
L
2
DATA
DATA
CC
45/MAX396E
GND
GND
GND
itance with a characteristic RC charging waveform.
When the low-to-high transition threshold ꢂV or V
upon restoration of the V
supply voltage. The
CC
MAX3395E provides bidirectional level translation on
four I/O lines, making it well suited for buffering and
translating 4-wire serial interfaces.
CC-Tꢀ
L-
ꢃ is reached, the rise time accelerators switch on,
Tꢀ
sourcing 15mA to fully charge the bus capacitance.
External pullup resistors reduce the time needed to
reach the low-to-high transition threshold, thereby
increasing the data rate. In the logic-low state however,
external pullup resistors increase the SC current
through the internal pass-FET, increasing the output
voltage of the device.
UCꢁ- Applications Information
For the latest application details on UCꢄP construction,
dimensions, tape carrier information, PCꢁ techniques,
bump-pad layout, and recommended reflow temperature
profiles, as well as the latest information on reliability test-
ing results, go to Maxim’s web site at www.maxim-
ic.com/ucsp to find the Application Note 1891:
Wafer-Level Packaging ꢂWLPꢃ and Its Applications.
ꢁmartꢂCard Interface
The MAX3395E provides level translation for Class A, ꢁ,
and C smart cards. When supply voltage V
is inter-
CC
rupted due to the disconnection of a smart card, the
device does not latch up. Normal operation resumes
12 ______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
-in Configurations (continued)
TOP VIEW
(BUMPS ON BOTTOM)
1
2
3
A
I/O V
1
I/O V 2
CC
V
CC
CC
B
MAX3394E
EN
GND
C
V
L
I/O V 1
L
I/O V 2
L
UCSP
TOP VIEW
TOP VIEW
(BUMPS ON BOTTOM)
(LEADS ON BOTTOM)
1
2
3
4
MAX3395E
9
8
7
A
*EP
I/O V
1
10
11
12
6
5
4
EN
CC
I/O V 1
L
I/O V 3
L
I/O V 2
L
I/O V 4
L
V
GND
CC
MAX3395E
B
V
CC
EN
V
L
V
L
GND
I/O V 4
L
+
C
1
2
3
I/O V
CC
1
I/O V 3
CC
I/O V
CC
2
I/O V 4
CC
TQFN
UCSP
*CONNECT EXPOSED PAD TO GROUND
TOP VIEW
(LEADS ON BOTTOM)
TOP VIEW
(BUMPS ON BOTTOM)
1
2
3
5
4
15
14
13
12
11
MAX3396E
I/O V
7
8
10
9
I/O V
I/O V
I/O V
2
3
1
16
17
18
CC
CC
CC
CC
CC
A
*EP
I/O V
I/O V 6
L
I/O V 2
L
V
L
I/O V 4
L
EN
8
I/O V 8
L
MAX3396E
B
I/O V 1 19
7
I/O V 7
L
L
I/O V 8
L
I/O V 1
L
I/O V 5
L
I/O V 3
I/O V 7
L
L
20
6
I/O V 6
L
I/O V 2
L
+
C
1
2
3
4
5
I/O V
I/O V
8
I/O V
CC
1
2
I/O V 5
CC
I/O V
I/O V
3
I/O V 7
CC
CC
CC
D
TQFN
*CONNECT EXPOSED PAD TO GROUND
6
I/O V
CC
V
CC
4
GND
CC
CC
UCSP
______________________________________________________________________________________ 13
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
ꢁelector Guide
Chip Information
PROCEꢄꢄ: ꢁiCMOꢄ
NUMBER OF
TOP
PART
CONNECT EXPOꢄES PAS TO GNS.
TRANSLATORS
MARK
MAX3394EETA+T
MAX3394EEꢁL+T
MAX3395EETC+
MAX3395EEꢁC+T
MAX3396EEꢁP+T
MAX3396EETP+
2
2
4
4
8
8
APE
AEZ
AAFZ
ACO
—
—
Note: All devices specified over the -40°C to +85°C operating
range.
+Senotes leadꢂPbꢃ-free/Roꢀꢄ-compliant package.
45/MAX396E
14 ______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
-acꢀage Information
ꢂThe package drawingꢂsꢃ in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.ꢃ
PACKAGE VARIATIONS
COMMON DIMENSIONS
SYMBOL MIN. MAX.
PKG. CODE
T633-2
N
6
8
8
D2
1.50 0.10 2.30 0.10 0.95 BSC
1.50 0.10 2.30 0.10
1.50 0.10 2.30 0.10 0.65 BSC
E2
e
b
JEDEC SPEC
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEED-3
[(N/2)-1] x e
0.40 0.05 1.90 REF
0.30 0.05 1.95 REF
0.30 0.05 1.95 REF
A
D
0.70
2.90
2.90
0.00
0.20
0.80
3.10
3.10
0.05
0.40
T833-2
0.65 BSC
E
T833-3
T1033-1
T1033MK-1
T1033-2
T1433-1
T1433-2
T1433-3F
10 1.50 0.10 2.30 0.10 0.50 BSC
0.25 0.05
2.00 REF
2.00 REF
2.00 REF
2.40 REF
2.40 REF
A1
L
10 1.50 0.10 2.30 0.10 0.50 BSC MO229 / WEED-3 0.25 0.05
10 1.50 0.10 2.30 0.10 0.50 BSC MO229 / WEED-3 0.25 0.05
k
0.25 MIN.
0.20 REF.
14 1.70 0.10 2.30 0.10 0.40 BSC
14 1.70 0.10 2.30 0.10 0.40 BSC
14 1.70 0.10 2.30 0.10 0.40 BSC
- - - -
- - - -
- - - -
0.20 0.05
0.20 0.05
A2
0.20 0.05 2.40 REF
______________________________________________________________________________________ 15
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
-acꢀage Information (continued)
ꢂThe package drawingꢂsꢃ in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.ꢃ
45/MAX396E
PACKAGE OUTLINE, 3x3 UCSP
1
21-0093
L
1
16 ______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
-acꢀage Information (continued)
ꢂThe package drawingꢂsꢃ in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.ꢃ
PACKAGE OUTLINE, 4x3 UCSP
1
21-0104
F
1
______________________________________________________________________________________ 17
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
-acꢀage Information (continued)
ꢂThe package drawingꢂsꢃ in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.ꢃ
45/MAX396E
18 ______________________________________________________________________________________
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
45/MAX396E
-acꢀage Information (continued)
ꢂThe package drawingꢂsꢃ in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.ꢃ
______________________________________________________________________________________ 19
±±5ꢀk EꢁDꢂ-rotected, HighꢂDrive Current, Dualꢂ/Quadꢂ/
OctalꢂLevel Translators with ꢁpeedꢂUp Circuitry
-acꢀage Information (continued)
ꢂThe package drawingꢂsꢃ in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.ꢃ
45/MAX396E
Revision History
Pages changed at Rev 2: 1–4, 9, 11, 12, 14, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated -roducts, ±20 ꢁan Gabriel Drive, ꢁunnyvale, CA 94086 408ꢂ737ꢂ7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
ꢁoblet
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±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry
MAXIM
MAX3396EETP+
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry
MAXIM
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