MAX34408 [MAXIM]
SMBus Dual/Quad Current Monitor;
| 型号： | MAX34408 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | SMBus Dual/Quad Current Monitor |
| 文件： | 总19页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
General Description
The MAX34408/MAX34409 are two- and four-channel
Benefits and Features
●ꢀ EnablesꢀAccurateꢀCurrentꢀConsumptionꢀMeasurementꢀ
onꢀUpꢀtoꢀFourꢀRailsꢀwithꢀDigitalꢀSerialꢀReadout
• Low 12.25mV Full-Scale Current-Sense Voltage
• AutomaticꢀRoundꢀRobinꢀSequencingꢀtoꢀSampleꢀ
Each Current-Sense Input
current monitors that are configured and monitored with a
2
standard I C/SMBus serial interface. Each unidirectional
current sensor offers precision high-side operation with a
low full-scale sense voltage. The devices automatically
sequence through two or four channels and collect the
current-sense samples and average them to reduce the
effect of impulse noise. The raw ADC samples are com-
pared to user-programmable digital thresholds to indicate
overcurrent conditions. Overcurrent conditions trigger a
hardware output to provide an immediate indication to
shut down any necessary external circuitry.
• Selectable Averaging to Improve Current-Sense
Accuracy
• Programmable Digital Overcurrent Thresholds with
Delay Function
2
• I C/SMBus Interface with Bus Timeout
• RegisterꢀAccessꢀtoꢀReal-TimeꢀCurrentꢀMeasurements
●ꢀ CompatibleꢀonꢀaꢀWideꢀRangeꢀofꢀVoltageꢀRailsꢀ
• Wideꢀ2.5Vꢀtoꢀ13.2VꢀCommon-ModeꢀRangeꢀ
Applications
●ꢀ NetworkꢀSwitchesꢀandꢀRouters
●ꢀ BaseꢀStations
●ꢀ Servers
●ꢀ AutomaticꢀSystemꢀShutdownꢀonꢀOvercurrentꢀCondition
• Shutdown Output Provides Immediate Hardware
Indication of Overcurrent
●ꢀ SmartꢀGridꢀNetworkꢀSystems
●ꢀ IndustrialꢀControls
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX34408.related.
Ordering Information appears at end of data sheet.
Typical Application Circuit and Block Diagram
2.7V TO
3.6V
V
DD
POWER
CONTROL
MAX34408/MAX34409
GND
LATCH AND DELAY RESET
RESET
ENA
AUTOMATIC
SEQUENCING
NOT PRESENT
ON MAX34408
OPTIONAL
FILTER
NETWORK
AMPLIFIER 4
SHTDN
CURRENT
FLOW
OR
AMPLIFIER 3
AMPLIFIER 2
SHUTDOWN
DELAY
SHUTDOWN
LATCH
AMPLIFIER 1
2 OR
4
SHUTDOWN DELAY RESET
100Ω
100Ω
IN+
IN-
OVER-
CURRENT
DETECTION
DELAY
MUX
1µF
1µF
DIGITAL
COMPARATOR
VREF
R
SENSE
REGISTERS
2 OR
4
CURRENT-
SENSE
AMPLIFIER
ADC
AVERAGING
SCL
SDA
SMBus
INTERFACE
ALERT
ADDR
R
EP (EXPOSED PAD)
ADDR
19-6792; Rev 1; 1/15
MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Absolute Maximum Ratings
VoltageꢀRangeꢀonꢀV ꢀRelativeꢀtoꢀGND ................-0.3V to +4V
Continuous Power Dissipation (T = +70°C)
A
DD
VoltageꢀRangeꢀonꢀIN+,ꢀIN-ꢀRelativeꢀtoꢀGND.........-0.3V to +16V
VoltageꢀRangeꢀonꢀAllꢀOtherꢀPins
16-PinꢀTQFNꢀ(derateꢀ25mW/°Cꢀaboveꢀ+70°C) .........2000mW
OperatingꢀTemperatureꢀRange........................... -40°C to +85°C
StorageꢀTemperatureꢀRange............................ -55°C to +125°C
Soldering Temperature (reflow).......................................+260°C
LeadꢀTemperatureꢀ(soldering,ꢀ10s) .................................+300°C
RelativeꢀtoꢀGND... -0.3V to (V
+ 0.3V) (not to exceed +4V)
DD
DifferentialꢀInputꢀVoltage,ꢀIN+ꢀtoꢀIN- ...................................±16V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-AmbientꢀThermalꢀResistanceꢀ(θ )...........40°C/W
JA
Junction-to-CaseꢀThermalꢀResistanceꢀ(θ )..................6°C/W
JC
Note 1:ꢀ PackageꢀthermalꢀresistancesꢀwereꢀobtainedꢀusingꢀtheꢀmethodꢀdescribedꢀinꢀJEDECꢀspecificationꢀJESD51-7,ꢀusingꢀaꢀfour-layerꢀ
board.ꢀForꢀdetailedꢀinformationꢀonꢀpackageꢀthermalꢀconsiderations,ꢀreferꢀto www.maximintegrated.com/thermal-tutorial.
Recommended DC Operating Conditions
(T ꢀ=ꢀ-40°Cꢀtoꢀ+85°C.)ꢀ(Notesꢀ2,ꢀ3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
ꢀOperatingꢀVoltageꢀRange
V
2.7
3.6
V
DD
DD
V
DD
0.7
x
V
DD
0.3
+
InputꢀLogicꢀ1:ꢀENAꢀPin
V
V
IH1
InputꢀLogicꢀ0:ꢀENAꢀPin
V
-0.3
2.1
+0.3 x V
V
V
V
IL1
DD
Input Logic 1: SCL/SDA Pins
Input Logic 0: SCL/SDA Pins
V
V
+ 0.3
+0.8
IH2
DD
V
-0.3
IL2
Electrical Characteristics
(V
= V ꢀ=ꢀ12V,ꢀV
ꢀ=ꢀ0V,ꢀV ꢀ=ꢀ2.7Vꢀtoꢀ3.6V,ꢀT ꢀ=ꢀ-40°Cꢀtoꢀ+85°C,ꢀunlessꢀotherwiseꢀnoted.ꢀTypicalꢀvaluesꢀareꢀatꢀV
= 3.3V
IN+
IN-
SENSE
DD
A
DD
and T ꢀ=ꢀ+25°C.)ꢀ(Notesꢀ2,ꢀ3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
SMBus idle
830
µA
DD
Current-Sense Common-Mode
InputꢀRange
2.5
13.2
V
Common-modeꢀvoltageꢀ=ꢀ13.2V,ꢀINꢀinputꢀ
differential = 12.25mV
InputꢀBiasꢀCurrentꢀ(IN+/IN-)
ADCꢀResolution
2
1
µA
Bits
ksps
8
Per-Channel Current
SampleꢀRate
INꢀInputꢀFullꢀScale
ADCꢀINL
12.00
12.25 12.50
mV
LSB
LSB
LSB
±0.5
±0.5
±0.5
±2
±2
±4
ADCꢀDNL
INꢀInputꢀOffset
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MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Electrical Characteristics (continued)
(V
= V ꢀ=ꢀ12V,ꢀV
ꢀ=ꢀ0V,ꢀV ꢀ=ꢀ2.7Vꢀtoꢀ3.6V,ꢀT ꢀ=ꢀ-40°Cꢀtoꢀ+85°C,ꢀunlessꢀotherwiseꢀnoted.ꢀTypicalꢀvaluesꢀareꢀatꢀV
= 3.3V
IN+
IN-
SENSE
DD
A
DD
and T ꢀ=ꢀ+25°C.)ꢀ(Notesꢀ2,ꢀ3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Logic Low
(SHTDN,ꢀALERT)
V
I
= 4mA
OL
0.4
V
OL
OutputꢀLeakage
(SHTDN,ꢀALERT)
±1
µA
SCL,ꢀSDAꢀLeakage
ENAꢀLeakage
V
ꢀ=ꢀ0Vꢀorꢀfloat
±5
±1
µA
µA
DD
DigitalꢀComparatorꢀResolution
8
Bits
Delay Time from VDD Applied
Until SMBus Active (Figure 1)
t
500
10
µs
SMBD
Delay Time from Common-Mode
Voltage Applied Until Current
Monitoring Active (Figure 1)
t
ms
CSAD
2
AC Electrical Characteristics: I C/SMBus Interface
(V ꢀ=ꢀ2.7Vꢀtoꢀ3.6V,ꢀT ꢀ=ꢀ-40°Cꢀtoꢀ+85°C,ꢀunlessꢀotherwiseꢀnoted.ꢀTypicalꢀvaluesꢀareꢀatꢀV ꢀ=ꢀ3.3V,ꢀT ꢀ=ꢀ+25°C.)ꢀ(Notesꢀ3,ꢀ4)
DD
A
DD
A
(Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLꢀClockꢀFrequency
f
10
400
kHz
SCL
Bus Free Time Between
STOPꢀandꢀSTARTꢀConditions
t
1.3
0.6
µs
µs
BUF
HoldꢀTimeꢀ(Repeated)
STARTꢀCondition
t
HD:STA
Low Period of SCL
High Period of SCL
t
1.3
0.6
0
µs
µs
LOW
t
HIGH
Receive
Data Hold Time
t
ns
HD:DAT
Transmit
300
100
0.6
Data Setup Time
t
ns
µs
ns
ns
µs
ms
SU:DAT
Start Setup Time
t
SU:STA
SDAꢀandꢀSCLꢀRiseꢀTime
SDA and SCL Fall Time
Stop Setup Time
t
300
300
R
t
F
t
0.6
25
SU:STO
ClockꢀLowꢀTimeout
t
35
TO
Note 2: All voltages are referenced to ground. Current entering the device are specified as positive and currents exiting the device
are negative.
Note 3: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range and
A
relevant supply voltage range are guaranteed by design and characterization.
Note 4: All timing specifications are guaranteed by design.
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MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Timing Diagrams
2.5V
V
DD
t
SMBD
NOT ACTIVE
ACTIVE
SMBus
2V
IN+
t
CSAD
CURRENT
MONITORING
NOT ACTIVE
ACTIVE
Figure 1. Delay Timing
SDA
SCL
t
BUF
t
F
t
t
SP
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
t
HD:STA
R
t
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IL(MAX)
IH(MIN)
2
Figure 2. I C/SMBus Timing
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MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Typical Operating Characteristics
(V
= 3.3V and T ꢀ=ꢀ+25°C,ꢀcommon-modeꢀvoltageꢀ=ꢀ12.0V,ꢀunlessꢀotherwiseꢀnoted.)
DD
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
IN INPUT FULL SCALE
vs. TEMPERATURE
toc01
toc02
toc03
0.80
0.75
0.70
0.65
0.60
0.80
0.75
0.70
0.65
0.60
14.0
13.5
13.0
12.5
12.0
11.5
11.0
2.6
2.8
3.0
3.2
3.4
3.6
3.8
-50
-30
-10
10
30
50
70
90
-50
-30
-10
10
30
50
70
90
VDD (V)
TEMPERATURE (ºC)
TEMPERATURE (ºC)
VOL
vs. IOL
SHTDN, ALERT#, SDA PINS
IN INPUT OFFSET
vs. COMMON-MODE VOLTAGE
IN INPUT OFFSET
vs. TEMPERATURE
toc04
toc05
toc06
3
2
1
0
3
2
1
0
700
600
500
400
300
200
100
0
SHTDN
ALERT#
SDA
0
5
10
15
IOL (mA)
20
25
-50
-30
-10
10
30
50
70
90
2
4
6
8
10
12
14
TEMPERATURE (ºC)
COMMON-MODE VOLTAGE (V)
PERCENT OF POPULATION
vs. IN INPUT OFFSET
PERCENT OF POPULATION
vs. IN FULL SCALE
toc07
toc08
35
30
25
20
15
10
5
30
COMMON-MODE
VOLTAGE = 2.5V
25
20
15
10
5
0
0
OFFSET (LSB)
IN FULL SCALE (mV)
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MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Pin Configurations
TOP VIEW
12
11
10
9
12
11
10
9
N.C.
IN3+
8
7
6
5
8
7
6
5
N.C. 13
IN4- 13
ADDR 14
GND
ADDR 14
GND
MAX34408
MAX34409
V
ALERT
IN2-
V
ALERT
IN2-
15
16
15
16
DD
DD
*EP
*EP
IN1+
IN1+
+
+
1
2
3
4
1
2
3
4
16 TQFN
(4mm x 4mm x 0.75mm)
*EXPOSED BACKSIDE PAD (EP)
Pin Description
PIN
NAME
FUNCTION
MAX34408
MAX34409
ExternalꢀSenseꢀResistorꢀLoad-SideꢀConnectionꢀforꢀAmplifierꢀ1.ꢀThisꢀpinꢀshouldꢀbe
left open circuit if not needed.
1
1
IN1-
2
2
3
2
3
SDA
SCL
I C/SMBus-Compatible Data Input/Output. Output is open drain.
2
I C/SMBus-CompatibleꢀClockꢀInput
ExternalꢀSenseꢀResistorꢀPower-SideꢀConnectionꢀforꢀAmplifierꢀ2.ꢀThisꢀpinꢀshouldꢀbeꢀ
left open circuit if not needed.
4
5
4
5
IN2+
IN2-
ExternalꢀSenseꢀResistorꢀLoad-SideꢀConnectionꢀforꢀAmplifierꢀ2.ꢀThisꢀpinꢀshouldꢀbeꢀ
left open circuit if not needed.
2
6
6
7
ALERT
GND
I C/SMBus Interrupt. Open-drain output.
7
GroundꢀConnection
8,ꢀ9,ꢀ12,ꢀ13
—
N.C.
NoꢀConnection.ꢀDoꢀnotꢀconnectꢀanyꢀsignalꢀtoꢀthisꢀpin.
Shutdown Output. Open-drain output. This output transitions to high impedance
whenꢀanyꢀofꢀtheꢀdigitalꢀcomparatorꢀthresholdsꢀareꢀexceededꢀasꢀlongꢀasꢀtheꢀENA
pin is high.
10
11
14
10
11
14
SHTDN
ENA
SHTDNꢀEnableꢀInput.ꢀCMOSꢀdigitalꢀinput.ꢀConnectꢀtoꢀGNDꢀtoꢀclearꢀtheꢀlatchꢀandꢀ
unconditionallyꢀdeassertꢀ(forceꢀlow)ꢀtheꢀSHTDNꢀoutputꢀandꢀresetꢀtheꢀshutdownꢀ
delay. Connect to V ꢀtoꢀenableꢀnormalꢀlatchꢀoperationꢀofꢀtheꢀSHTDNꢀoutput.
DD
2
I C/SMBusꢀAddressꢀSelect.ꢀOnꢀdeviceꢀpower-up,ꢀtheꢀdeviceꢀsamplesꢀaꢀresistorꢀtoꢀ
ADDR
ground to determine the 7-bit serial bus address. See the Addressing section for
details on which resistor values select which SMBus address.
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MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Pin Description (continued)
PIN
NAME
FUNCTION
MAX34408
MAX34409
Supply Voltage for Comparators and Logic. A +2.7V to +3.6V supply. This pin
shouldꢀbeꢀdecoupledꢀtoꢀGNDꢀwithꢀaꢀ100nFꢀceramicꢀcapacitor.
15
15
V
DD
ExternalꢀSenseꢀResistorꢀPower-SideꢀConnectionꢀforꢀAmplifierꢀ1.ꢀThisꢀpinꢀshouldꢀbeꢀ
left open circuit if not needed.
16
—
—
—
16
8
IN1+
IN3+
IN3-
IN4+
ExternalꢀSenseꢀResistorꢀPower-SideꢀConnectionꢀforꢀAmplifierꢀ3.ꢀThisꢀpinꢀshouldꢀbe
left open circuit if not needed.
ExternalꢀSenseꢀResistorꢀLoad-SideꢀConnectionꢀforꢀAmplifierꢀ3.ꢀThisꢀpinꢀshouldꢀbe
left open circuit if not needed.
9
ExternalꢀSenseꢀResistorꢀPower-SideꢀConnectionꢀforꢀAmplifierꢀ4.ꢀThisꢀpinꢀshouldꢀbeꢀ
left open circuit if not needed.
12
ExternalꢀSenseꢀResistorꢀLoad-SideꢀConnectionꢀforꢀAmplifierꢀ4.ꢀThisꢀpinꢀshouldꢀbeꢀ
left open circuit if not needed.
—
—
13
—
IN4-
EP
ExposedꢀPad.ꢀNoꢀinternalꢀelectricalꢀconnection.ꢀCanꢀbeꢀleftꢀopenꢀcircuit.
SMBus Operation
Detailed Description
The devices use the SMBus command/response for-
mat as described in the System Management Bus
Specification Version 2.0. The structure of the data flow
between the host and the slave is shown for several dif-
ferent types of transactions. Data is sent MSB first. The
fixed slave address of the MAX34408 or MAX34409 is
determined on device power-up by sampling the resistor
connectedꢀtoꢀtheꢀADDRꢀpin.ꢀSeeꢀtheꢀAddressing section
forꢀ details.ꢀ Onꢀ deviceꢀ power-up,ꢀ theꢀ deviceꢀ defaultsꢀ toꢀ
the STATUS command code (00h). If the host sends an
invalidꢀcommandꢀcode,ꢀtheꢀdeviceꢀNACKsꢀ(notꢀacknowl-
edge) the command code. If the host attempts to read the
deviceꢀwithꢀanꢀinvalidꢀcommandꢀcode,ꢀallꢀonesꢀ(FFh)ꢀareꢀ
returned in the data byte.
The MAX34408 and MAX34409 are two- and four-channel
current monitors that are configured and monitored with a
2
standard I C/SMBus serial interface. Each unidirectional
current sensor offers precision high-side operation with a
low full-scale sense voltage. The devices automatically
sequence through two or four channels and collect the
current-sense samples and average them to reduce the
effect of impulse noise. The raw ADC samples are com-
pared to user-programmable digital thresholds to indicate
overcurrent conditions. Overcurrent conditions trigger a
hardware output to provide an immediate indication to
shut down any necessary external circuitry.
The devices provide an ALERT output signal. Host com-
munications are conducted through a SMBus-compatible
communications port.
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MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Table 1. Read Byte Format
1
7
1
1
8
1
1
7
1
1
8
1
1
Slave
Address
Command
Code
Slave
Address
S
W
A
A
SR
R
A
Data Byte
NA
P
Table 2. Write Byte Format
Table 3. Receive Byte Format (reads data
from the last transacted command code)
1
7
1
1
8
1
8
1
1
1
7
1
1
8
1
1
Slave
Address
Command
Code
Data
Byte
S
W
A
A
A
P
Slave
Address
S
R
A
Data Byte
NA
P
Key:
S = Start
Table 4. SMBus Slave Address Select
SRꢀ=ꢀRepeatedꢀStart
P = Stop
R
(±1%)
SLAVE
ADDRESS
R
(±1%)
SLAVE
ADDRESS
ADDR
ADDR
Wꢀ=ꢀWriteꢀBitꢀ(0)
Rꢀ=ꢀReadꢀBitꢀ(1)
0011 110
(3Ch)
0010 110
(2Ch)
Open
3.01kΩ
0011 100
(38h)
0010 100
(28h)
Aꢀ=ꢀAcknowledgeꢀ(ACK)ꢀ(0)
9.31kΩ
6.81kΩ
4.75kΩ
1.69kΩ
750Ω
NAꢀ=ꢀNotꢀAcknowledgeꢀ(NACK)ꢀ(1)
ShadedꢀBlockꢀ=ꢀSlaveꢀTransaction
0011 010
(34h)
0010 010
(24h)
Addressing
0011 000
(30h)
0 (connect to
0010 000
(20h)
GND)
The devices respond to receiving the fixed slave address
byꢀassertingꢀanꢀACKꢀonꢀtheꢀbus.ꢀTheꢀfixedꢀslaveꢀaddressꢀ
of the MAX34408 or MAX34409 is determined on device
power-upꢀbyꢀsamplingꢀtheꢀresistorꢀconnectedꢀtoꢀtheꢀADDRꢀ
pin. See Table 4 for more details. The devices do not
respondꢀtoꢀaꢀGeneralꢀCallꢀaddress,ꢀonlyꢀwhenꢀitꢀreceivesꢀ
itsꢀ fixedꢀ slaveꢀ addressꢀ orꢀ theꢀ Alertꢀ Responseꢀ Addressꢀ
(ARA).ꢀSeeꢀtheꢀALERTꢀdescriptionꢀforꢀmoreꢀdetails.
Table 5. Alert Response Address (ARA)
Byte Format
1
7
1
1
8
1
1
ARA
0001100
Device Slave Address
with LSB = 1
S
R
A
NA
P
ALERT and Alert Response Address (ARA)
If the ALERTꢀ outputꢀ isꢀ enabledꢀ (ALERTꢀ bitꢀ =ꢀ 1ꢀ inꢀ
CONTROL),ꢀwhenꢀanꢀovercurrentꢀconditionꢀisꢀdetected,ꢀ
the devices assert the ALERT signal and then wait for the
hostꢀtoꢀsendꢀtheꢀAlertꢀResponseꢀAddressꢀ(ARA)ꢀasꢀshownꢀ
in Table 5.
address on the bus by arbitrating the bus since another
deviceꢀmayꢀalsoꢀtryꢀtoꢀrespondꢀtoꢀtheꢀARA.ꢀTheꢀrulesꢀofꢀ
arbitration state that the lowest address device wins. If the
devicesꢀwinꢀtheꢀarbitration,ꢀtheyꢀdeassertꢀALERT. If the
devicesꢀloseꢀarbitration,ꢀtheyꢀkeepꢀALERT asserted and
waitꢀforꢀtheꢀhostꢀtoꢀonceꢀagainꢀsendꢀtheꢀARA.
Whenꢀ theꢀARAꢀ isꢀ receivedꢀ andꢀ theꢀ devicesꢀ areꢀ assert-
ing ALERT,ꢀtheꢀdevicesꢀattemptꢀtoꢀplaceꢀtheꢀfixedꢀslaveꢀ
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MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
SMBus Commands
AꢀsummaryꢀofꢀtheꢀSMBusꢀcommandsꢀsupportedꢀbyꢀtheꢀdevicesꢀareꢀdescribedꢀinꢀtheꢀfollowingꢀsections,ꢀseeꢀTable 6.
Table 6. Command Codes
COMMAND
POR
(Noteꢀ1)
NAME
DETAILED DESCRIPTION
TYPE
CODE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
STATUS
CONTROL
OCDELAY
SDDELAY
ADC1
Overcurrent Alarm
R/WꢀByte
R/WꢀByte
R/WꢀByte
R/WꢀByte
ReadꢀByte
ReadꢀByte
ReadꢀByte
ReadꢀByte
R/WꢀByte
R/WꢀByte
R/WꢀByte
R/WꢀByte
ReadꢀByte
ReadꢀByte
ReadꢀByte
00h
DeviceꢀConfiguration
0Ch
OvercurrentꢀDetectionꢀDelayꢀConfiguration
SHTDNꢀPinꢀDelayꢀConfiguration
04h
14h
AveragedꢀADCꢀReadingꢀfromꢀCurrentꢀSensorꢀ1
AveragedꢀADCꢀReadingꢀfromꢀCurrentꢀSensorꢀ2
AveragedꢀADCꢀReadingꢀfromꢀCurrentꢀSensorꢀ3ꢀ(Noteꢀ2)
AveragedꢀADCꢀReadingꢀfromꢀCurrentꢀSensorꢀ4ꢀ(Noteꢀ2)
Overcurrent Threshold for Current Sensor 1
Overcurrent Threshold for Current Sensor 2
OvercurrentꢀThresholdꢀforꢀCurrentꢀSensorꢀ3ꢀ(Noteꢀ3)
OvercurrentꢀThresholdꢀforꢀCurrentꢀSensorꢀ4ꢀ(Noteꢀ3)
DeviceꢀIDꢀ&ꢀRevision
—
ADC2
—
ADC3
—
ADC4
—
OCT1
D1h
OCT2
D1h
OCT3
D1h
OCT4
D1h
DID
Factory Set
Factory Set
Factory Set
DCYY
Date Code Year
DCWW
DateꢀCodeꢀWorkꢀWeek
Note 1:ꢀ PORꢀ=ꢀPower-onꢀreset,ꢀandꢀthisꢀisꢀtheꢀdefaultꢀvalueꢀwhenꢀpowerꢀisꢀappliedꢀtoꢀtheꢀdevice.
Note 2:ꢀ InꢀtheꢀMAX34408,ꢀADC3ꢀandꢀADC4ꢀalwaysꢀreportꢀ00hꢀwhenꢀread.
Note 3:ꢀ InꢀtheꢀMAX34408,ꢀOCT3ꢀandꢀOCT4ꢀcanꢀbeꢀwrittenꢀtoꢀandꢀreadꢀfrom,ꢀbutꢀtheyꢀhaveꢀnoꢀaffectꢀonꢀtheꢀdevice.
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STATUS (00h)
The STATUS command returns 1 byte of information with a summary of the fault conditions along with the real-time status
ofꢀtheꢀENAꢀandꢀSHTDNꢀpins.ꢀTheꢀSTATUSꢀbyteꢀmessageꢀcontentꢀisꢀdescribedꢀinꢀTable 7. See Figure 3 for STATUS bits
3:0 organization.
Table 7. STATUS (00h)—R/W Byte
BIT
BIT 7
NA
0
BIT 6
NA
0
BIT 5
ENA
0
BIT 4
SHTDN
0
BIT 3
OC4
0
BIT 2
OC3
0
BIT 1
OC2
0
BIT 0
OC1
0
NAME
POR
Note:ꢀBitꢀpositionsꢀmarkedꢀasꢀNAꢀareꢀNotꢀAssignedꢀandꢀhaveꢀnoꢀmeaning.ꢀTheseꢀbitsꢀcanꢀbeꢀeitherꢀ0ꢀorꢀ1ꢀwhenꢀread.
BIT
NAME
DESCRIPTION
Thisꢀbitꢀreportsꢀtheꢀreal-timeꢀstatusꢀofꢀtheꢀENAꢀinputꢀpin.ꢀTheꢀENAꢀpinꢀisꢀsampledꢀwhenꢀSMBusꢀ
communication is initiated. This bit has no affect on the ALERT output.ꢀWritingꢀaꢀ0ꢀorꢀ1ꢀtoꢀthisꢀbitꢀ
position has no affect on the device.
5
ENA
Thisꢀbitꢀreportsꢀtheꢀreal-timeꢀstatusꢀofꢀtheꢀSHTDNꢀoutputꢀpin.ꢀTheꢀshutdownꢀlatchꢀisꢀsampledꢀwhenꢀ
SMBus communication is initiated. This bit has no affect on the ALERTꢀoutput.ꢀWritingꢀaꢀ0ꢀorꢀ1ꢀtoꢀthisꢀ
bit position has no affect on the device.
4
SHTDN
Theseꢀbitsꢀreflectꢀtheꢀlatchedꢀstatusꢀofꢀtheꢀovercurrentꢀthresholdsꢀforꢀeachꢀcurrentꢀsensor.ꢀTheꢀ
OCD0ꢀtoꢀOCD3ꢀbitsꢀconfiguredꢀwithꢀtheꢀOCDELAYꢀcommandꢀdetermineꢀtheꢀnumberꢀofꢀconsecutiveꢀ
overcurrentꢀthresholdꢀexcursionꢀsamplesꢀthatꢀareꢀrequiredꢀtoꢀsetꢀtheseꢀbits.ꢀOnceꢀset,ꢀtheseꢀbitsꢀ
remainꢀsetꢀuntilꢀwrittenꢀwithꢀaꢀ0.ꢀOnceꢀtheyꢀareꢀcleared,ꢀtheyꢀareꢀnotꢀsetꢀagainꢀuntilꢀtheꢀsensedꢀ
current has exceeded the threshold for the programmed delay time. The setting of any of these
bits asserts the ALERTꢀpinꢀifꢀtheꢀALERTꢀbitꢀinꢀtheꢀCONTROLꢀcommandꢀisꢀsetꢀtoꢀaꢀone.ꢀReadingꢀ
or writing the STATUS command deasserts the ALERTꢀpinꢀifꢀitꢀisꢀasserted.ꢀInꢀtheꢀMAX34408,ꢀbitꢀ
positions OC3 and OC4 are inactive.
OC4/OC3/
OC2/OC1
(MAX34409)
3:0
OC2/OC1
(MAX34408)
1:0
SET
STATUS
OC1
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
OVERCURRENT EVENT
OVERCURRENT DELAY
OVERCURRENT DELAY
OVERCURRENT DELAY
OVERCURRENT DELAY
LATCH
LATCH
LATCH
LATCH
OVERCURRENT EVENT
OVERCURRENT EVENT
OVERCURRENT EVENT
OC2
OC3
OC4
CLEAR
WRITE A 0 TO OCn BIT POSITION
IN STATUS COMMAND CODE
OR
SET
READ OR WRITE STATUS
CLEAR
OR
LATCH
ALERT RESPONSE ADDRESS (ARA)
RECEIVED AND ARBITRATION WON
ALERT
OUTPUT
AND
ALERT BIT IN CONTROL
Figure 3. OCn Status Bits Set/Clear Functionality and ALERT Assertion
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CONTROL (01h)
Theꢀ CONTROLꢀ commandꢀ configuresꢀ theꢀ digitalꢀ current-sensingꢀ averagingꢀ function.ꢀ Theꢀ CONTROLꢀ commandꢀ alsoꢀ
definesꢀifꢀtheꢀdevicesꢀrespondꢀtoꢀtheꢀAlertꢀResponseꢀAddress.ꢀTheꢀCONTROLꢀbyteꢀcommandꢀisꢀdescribedꢀinꢀTable 8.
Table 8. CONTROL (01h)—R/W Byte
BIT
BIT 7
NA
0
BIT 6
NA
0
BIT 5
NA
0
BIT 4
NA
0
BIT 3
ALERT
1
BIT 2
AVG2
1
BIT 1
AVG1
0
BIT 0
AVG0
0
NAME
POR
Note:ꢀBitꢀpositionsꢀmarkedꢀasꢀNAꢀareꢀNotꢀAssignedꢀandꢀhaveꢀnoꢀmeaning.ꢀTheseꢀbitsꢀcanꢀbeꢀeitherꢀ0ꢀorꢀ1ꢀwhenꢀread.
BIT
NAME
DESCRIPTION
Ifꢀthisꢀbitꢀisꢀcleared,ꢀtheꢀALERTꢀoutputꢀisꢀdisabledꢀandꢀtheꢀdevicesꢀdoꢀnotꢀrespondꢀtoꢀtheꢀAlertꢀResponseꢀ
Address.ꢀIfꢀthisꢀbitꢀisꢀset,ꢀtheꢀALERTꢀfunctionꢀisꢀenabledꢀandꢀtheꢀdevicesꢀrespondꢀtoꢀtheꢀAlertꢀResponseꢀ
Address.
3
ALERT
Theseꢀbitsꢀconfigureꢀtheꢀdigitalꢀcurrent-sensingꢀaveragingꢀfunctionꢀasꢀshownꢀbelow.
AVG2
AVG1
AVG0
SELECTED AVERAGING
1 Sample (no averaging)
2 Samples
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 Samples
AVG2/
AVG1/AVG0
2:0
8 Samples
16 Samples (default)
32 Samples
64 Samples
128 Samples
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OVER_CURRENT_DELAY (02h)
Theꢀ OVER_CURRENT_DELAYꢀcommandꢀconfiguresꢀandꢀresetsꢀtheꢀovercurrentꢀdelayꢀcounters.ꢀTheꢀOVER_CURRENT_DELAYꢀ
byte command is described in Table 9. See Figure 4 for delay counter timing.
Table 9. OVER_CURRENT_DELAY (02h)—R/W Byte
BIT
BIT 7
RESET
0
BIT 6
OCD6
0
BIT 5
OCD5
0
BIT 4
OCD4
0
BIT 3
OCD3
0
BIT 2
OCD2
1
BIT 1
OCD1
0
BIT 0
OCD0
0
NAME
POR
BIT
NAME
DESCRIPTION
Ifꢀthisꢀbitꢀisꢀcleared,ꢀtheꢀOCD0ꢀtoꢀOCD6ꢀbitsꢀareꢀusedꢀtoꢀsetꢀtheꢀovercurrentꢀdelayꢀforꢀallꢀchannels.ꢀ
Ifꢀthisꢀisꢀset,ꢀallꢀofꢀtheꢀovercurrentꢀdelayꢀcountersꢀareꢀresetꢀandꢀtheꢀdevicesꢀdoꢀnotꢀtriggerꢀanyꢀ
overcurrent events and the OC status bits are cleared.
7
RESET
Theseꢀbitsꢀconfigureꢀtheꢀovercurrentꢀdelayꢀasꢀshownꢀbelow.ꢀForꢀeachꢀchannel,ꢀtheꢀdigitalꢀovercurrentꢀ
threshold must be continuously breached in consecutive samples for the delay listed below before
the respective OC bit in the STATUS register is set and the ALERT output is asserted (if enabled
withꢀtheꢀALERTꢀbitꢀinꢀtheꢀCONTROLꢀcommand).ꢀForꢀexample,ꢀifꢀtheꢀdelayꢀisꢀsetꢀtoꢀ0ms,ꢀthenꢀtheꢀOCꢀ
bit and the ALERTꢀoutputꢀareꢀassertedꢀonꢀtheꢀfirstꢀsampleꢀthatꢀbreachesꢀtheꢀthreshold.ꢀIfꢀdelayꢀisꢀ
setꢀtoꢀ4ms,ꢀthenꢀtheꢀOCꢀbitꢀandꢀtheꢀALERT output are not asserted until the overcurrent threshold is
exceededꢀinꢀfiveꢀconsecutiveꢀsamples.
OCD[6:0]
00h
OVERCURRENT DELAY
0ms
1ms
1 Event
OCD6 to
OCD0
01h
2 Consecutive Events
3 Consecutive Events
4 Consecutive Events
5 Consecutive Events
21 Consecutive Events
22 Consecutive Events
127 Consecutive Events
128 Consecutive Events
6:0
02h
2ms
03h
3ms
04h
4ms (default)
20ms
14h
15h
21ms
7Eh
7Fh
126ms
127ms
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CURRENT
OVERCURRENT
THRESHOLD
3ms DELAY
OVERCURRENT
DELAY COUNTER
7ms DELAY
SHUTDOWN
DELAY COUNTER
OC STATUS BIT
ALERT
SHTDN
ARA BUS
TRANSACTION
STATUS BYTE WRITE
(0 TO OCn BIT POSITION)
Figure 4. Delay Timing
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SHUTDOWN_DELAY (03h)
TheꢀSHUTDOWN_DELAYꢀcommandꢀconfiguresꢀandꢀresetsꢀtheꢀshutdownꢀdelayꢀcounters.ꢀTheꢀSHUTDOWN_DELAYꢀbyteꢀ
command is described in Table 10.
Table 10. SHUTDOWN_DELAY (03h)—R/W Byte
BIT
BIT 7
RESET
0
BIT 6
SHD6
0
BIT 5
SHD5
0
BIT 4
SHD4
1
BIT 3
SHD3
0
BIT 2
SHD2
1
BIT 1
SHD1
0
BIT 0
SHD0
0
NAME
POR
BIT
NAME
DESCRIPTION
Ifꢀthisꢀbitꢀisꢀcleared,ꢀtheꢀSHD0ꢀtoꢀSHD6ꢀbitsꢀareꢀusedꢀtoꢀsetꢀtheꢀshutdownꢀdelayꢀthatꢀisꢀusedꢀtoꢀcontrolꢀ
theꢀSHTDNꢀpin.ꢀIfꢀthisꢀisꢀset,ꢀtheꢀshutdownꢀdelayꢀcounterꢀisꢀresetꢀandꢀtheꢀSHTDNꢀpinꢀisꢀforcedꢀ
inactive (low).
7
RESET
Theseꢀbitsꢀconfigureꢀtheꢀshutdownꢀlatchꢀdelayꢀasꢀshownꢀbelow.ꢀForꢀeachꢀchannel,ꢀtheꢀdigitalꢀ
overcurrent threshold must be continuously breached in consecutive samples for the delay listed
belowꢀbeforeꢀtheꢀshutdownꢀlatchꢀ(andꢀhenceꢀtheꢀSHTDNꢀpin)ꢀisꢀasserted.ꢀForꢀexample,ꢀifꢀtheꢀdelayꢀ
isꢀsetꢀtoꢀ0ms,ꢀthenꢀtheꢀSHTDNꢀoutputꢀisꢀassertedꢀonꢀtheꢀfirstꢀsampleꢀthatꢀbreachesꢀtheꢀthreshold.ꢀ
Ifꢀdelayꢀisꢀsetꢀtoꢀ20ms,ꢀthenꢀtheꢀSHTDNꢀoutputꢀisꢀnotꢀassertedꢀuntilꢀtheꢀovercurrentꢀthresholdꢀisꢀ
exceeded in 21 consecutive samples.
SHD[6:0]
00h
SHUTDOWN DELAY
0ms
1ms
1 Event
SHD6 to
SHD0
6:0
01h
2 Consecutive Events
3 Consecutive Events
4 Consecutive Events
20 Consecutive Events
21 Consecutive Events
22 Consecutive Events
127 Consecutive Events
128 Consecutive Events
02h
2ms
03h
3ms
13h
19ms
14h
20ms (default)
21ms
15h
7Eh
7Fh
126ms
127ms
ADC1/2/3/4 (04h/05h/06h/07h)
The ADC1/2/3/4 command returns the associated latest measured current reading. The ADC1/2/3/4 byte command is
described in Table 11.
Table 11. ADC1/2/3/4 (04h/05h/06h/07h)—Read Byte
BIT
BIT 7
C7
BIT 6
C6
BIT 5
C5
BIT 4
C4
BIT 3
C3
BIT 2
C2
BIT 1
C1
BIT 0
C0
NAME
POR
X
X
X
X
X
X
X
X
BIT
NAME
DESCRIPTION
These bits report the latest current reading from the ADC. The reported results are averaged
accordingꢀtoꢀtheꢀaveragingꢀfunctionꢀasꢀconfiguredꢀwithꢀtheꢀAVG0ꢀtoꢀAVG2ꢀbitsꢀinꢀtheꢀCONTROLꢀ
command.ꢀReadingꢀtheꢀADCꢀresultsꢀfasterꢀthanꢀtheyꢀareꢀsampledꢀandꢀaveragedꢀresultsꢀinꢀtheꢀ
previousꢀvaluesꢀbeingꢀreported.ꢀInꢀtheꢀMAX34408,ꢀADC3ꢀandꢀADC4ꢀalwaysꢀreportꢀ00hꢀwhenꢀread.
7:0
C7 to C0
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OVER_CURRENT_THRESHOLD_1/2/3/4 (08h/09h/0Ah/0Bh)
Theꢀ OVER_CURRENT_THRESHOLD_1/2/3/4ꢀ commandꢀ setsꢀ theꢀ overcurrentꢀ thresholdꢀ forꢀ eachꢀ channel.ꢀ Theꢀ
OVER_CURRENT_THRESHOLD_1/2/3/4ꢀbyteꢀcommandꢀisꢀdescribedꢀinꢀTable 12. See Table 13 for the configura-
tion formula and Table 14 for an example.
Table 12. OVER_CURRENT_THRESHOLD_1/2/3/4 (08h/09h/0Ah/0Bh)—R/W Byte
BIT
BIT 7
OCT7
1
BIT 6
OCT6
1
BIT 5
OCT5
0
BIT 4
OCT4
1
BIT 3
OCT3
0
BIT 2
OCT2
0
BIT 1
OCT1
0
BIT 0
OCT0
1
NAME
POR
Note: InꢀtheꢀMAX34408,ꢀOCT3ꢀandꢀOCT4ꢀcanꢀbeꢀwrittenꢀtoꢀandꢀreadꢀfromꢀbutꢀtheyꢀhaveꢀnoꢀaffectꢀonꢀtheꢀdevice.
BIT
NAME
DESCRIPTION
These bits select the digital overcurrent threshold for each channel. The formula for selecting the
thresholdꢀisꢀasꢀshownꢀinꢀTableꢀ13.ꢀIfꢀtheꢀthresholdꢀisꢀsetꢀtoꢀFFh,ꢀtheꢀdigitalꢀcomparatorꢀisꢀdisabledꢀandꢀ
the output of the comparator is unconditionally deasserted.
OCT7 to
OCT0
7:0
Table 13. Overcurrent Threshold Register Configuration Formula
Overcurrent Threshold
Analog Voltage at the
IN+/IN-ꢀPins
Roundedꢀ
Decimal
Value
RatioꢀtoꢀFullꢀ
Overcurrent Threshold
÷
0.01225
=
x
256
=
=
=
Scale
RegisterꢀSetting
Table 14. Overcurrent Threshold Register Example
10mV
÷
0.01225
=
0.816
x
256
=
209
D1h
DEVICE_ID_&_REVISION (0Ch)
Theꢀ DEVICE_ID_&_REVISIONꢀ commandꢀ returnsꢀ aꢀ fixedꢀ deviceꢀ IDꢀ andꢀ aꢀ factoryꢀ programmedꢀ revision.ꢀ Theꢀ
DEVICE_ID_&_REVISIONꢀbyteꢀcommandꢀisꢀdescribedꢀinꢀTable 15.
Table 15. DEVICE_ID_&_REVISION (0Ch)—Read Byte
BIT
BIT 7
ID4
0
BIT 6
ID3
0
BIT 5
ID2
0
BIT 4
ID1
0
BIT 3
ID0
1
BIT 2
BIT 1
REV1
BIT 0
NAME
POR
REV2
REV0
Factory set
BIT
NAME
DESCRIPTION
7:3
2:0
ID4 to ID0
Theseꢀbitsꢀreportꢀtheꢀdeviceꢀidentificationꢀ(ID).ꢀTheꢀIDꢀisꢀfixedꢀatꢀ01h.
REV2ꢀtoꢀREV0
These bits report the device revision. The device revision is factory set.
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DATE_CODE_YEAR (0Dh)
TheꢀDATE_CODE_YEARꢀcommandꢀreturnsꢀaꢀfactoryꢀprogrammedꢀdateꢀcode.ꢀTheꢀDATE_CODE_YEARꢀbyteꢀcommandꢀ
is described in Table 16.
Table 16. DATE_CODE_YEAR (0Dh)—Read Byte
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME
POR
0
0
YY5
YY4
YY3
YY2
YY1
YY0
Factory Set
BIT
NAME
DESCRIPTION
These bits report the last two decimal digits of the calendar year in which the device was tested.
The year is reported as a binary decimal. Some examples are listed below. The range is valid until
the year 2063.
YY[5:0]
0Ch
YEAR
2012
2013
2020
5:0
YY5 to YY0
0Dh
14h
DATE_CODE_WORK_WEEK (0Eh)
TheꢀDATE_CODE_WORK_WEEKꢀcommandꢀreturnsꢀaꢀfactory-programmedꢀdateꢀcode.ꢀTheꢀDATE_CODE_WORK_WEEKꢀ
byte command is described in Table 17.
Table 17. DATE_CODE_WORK_WEEK (0Eh)—Read Byte
BIT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME
POR
0
0
WW5
WW4
WW3
WW2
WW1
WW0
Factory Set
BIT
NAME
DESCRIPTION
Theseꢀbitsꢀreportꢀtheꢀcalendarꢀworkꢀweekꢀinꢀwhichꢀtheꢀdeviceꢀwasꢀtested.ꢀTheꢀworkꢀweekꢀisꢀreportedꢀ
as a binary decimal. Some examples are listed below. 00h (0 decimal) and 36h (54 decimal) through
3Fh (63) are not valid.
WW5ꢀtoꢀ
WW0
5:0
WW[5:0]
06h
WORK WEEK
6
0Dh
13
43
2Bh
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Kelvin Connections
BecauseꢀofꢀtheꢀhighꢀcurrentsꢀthatꢀflowꢀthroughꢀR
takeꢀ careꢀ toꢀ eliminateꢀ parasiticꢀ traceꢀ resistanceꢀ fromꢀ
causingꢀ errorsꢀ inꢀ theꢀ senseꢀ voltage.ꢀ Useꢀ Kelvinꢀ (forceꢀ
and sense) PCB layout techniques as shown in Figure 6.
Applications Information
SENSE,
Sense Resistor, R
SENSE
value to monitor higher or lower cur-
AdjustꢀtheꢀR
SENSE
rentꢀlevels.ꢀSelectꢀR
based on the following criteria:
SENSE
Resistor Value:ꢀSelectꢀanꢀR
resistor value in which
SENSE
the largest expected current results in a 10mV full-scale
current-senseꢀvoltage.ꢀSelectꢀR in accordance to
the following equation and see Table 18 for examples:
SENSE
ERROR CONTRIBUTED BY
INPUT OFFSET vs. READING
PERCENTAGE OF FULL SCALE
20
R
= 10mV/(Max Current)
SENSE
Power Dissipation: Select a sense resistor that is rated
for the max expected current and power dissipation (watt-
age). The sense resistor’s value might drift if it is allowed
to heat up excessively.
WORST-CASE
OFFSET (±4LSB)
Accuracy
10
Current measurement accuracy increases the closer the
measured current readings are to the 12.25mV full-scale
current-sense voltage. This is because offsets become
less significant when the sense voltage is larger. For best
TYPICAL
OFFSET (±0.5LSB)
performance,ꢀ selectꢀ R
to provide approximately
SENSE
0
10mV of sense voltage for the full-scale current in each
application. Figure 5 shows the error contributed by the
input offset vs. reading percentage of full scale.
0
25
50
75
100
READING PERCENTAGE OF FULL SCALE (%)
Figure 5. Input Offset Error
Table 18. R
Example Values
SENSE
R
(mΩ)
MAX CURRENT (A)
SENSE
HIGH CURRENT PATH
0.25
0.5
1
40
20
RSENSE
10
5
2
10
1
INX+ KELVIN
INX- KELVIN
50
0.2
0.1
0.05
0.02
CONNECTION
CONNECTION
100
200
500
Figure 6. Kelvin Connection Layout Example
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Optional Filter Network
Ordering Information
Forꢀ noisyꢀ environments,ꢀ aꢀ simpleꢀ lowpassꢀ filterꢀ canꢀ
be placed at the devices’ amplifier inputs as shown in
Figure 7.ꢀ Theꢀ 100Ωꢀ resistorꢀ andꢀ 1µFꢀ capacitorꢀ provideꢀ
aꢀ 1.6kHzꢀ rolloffꢀ frequency.ꢀToꢀ achieveꢀ theꢀ mostꢀ effectiveꢀ
results,ꢀuseꢀtheꢀfilterꢀinꢀconjunctionꢀwithꢀtheꢀdevice’sꢀdigitalꢀ
averaging as described in the CONTROL (01h) section.
PART
CONFIGURATION
PIN-PACKAGE
16ꢀTQFN-EP*
16ꢀTQFN-EP*
MAX34408ETE+
MAX34409ETE+
Dual
Quad
+Denotes a lead (Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Layout Considerations
Forꢀnoisyꢀdigitalꢀenvironments,ꢀtheꢀuseꢀofꢀaꢀmultilayerꢀPCBꢀ
with separate ground and power-supply planes is recom-
mended.ꢀKeepꢀdigitalꢀsignalsꢀfarꢀawayꢀfromꢀtheꢀsensitiveꢀ
analog inputs. Unshielded long traces at the input termi-
nals of the amplifier can degrade performance due to noise
pickup.ꢀTheꢀanalogꢀdifferentialꢀcurrent-senseꢀtracesꢀshouldꢀ
be routed close together to maximize common-mode rejec-
tion.
Package Information
Forꢀtheꢀlatestꢀpackageꢀoutlineꢀinformationꢀandꢀlandꢀpatternsꢀ(foot-
prints),ꢀ goꢀ toꢀ www.maximintegrated.com/packages.ꢀ Noteꢀ thatꢀ
aꢀ“+”,ꢀ“#”,ꢀorꢀ“-”ꢀinꢀtheꢀpackageꢀcodeꢀindicatesꢀRoHSꢀstatusꢀonly.ꢀ
Packageꢀdrawingsꢀmayꢀshowꢀaꢀdifferentꢀsuffixꢀcharacter,ꢀbutꢀtheꢀ
drawingꢀpertainsꢀtoꢀtheꢀpackageꢀregardlessꢀofꢀRoHSꢀstatus.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Power-Supply Decoupling
Toꢀ achieveꢀ theꢀ bestꢀ resultsꢀ whenꢀ usingꢀ theseꢀ devices,ꢀ
16ꢀTQFN-EP
T1644+4
21-0139
90-0070
decouple the V
power supply with a 0.1µF capacitor.
DD
Useꢀ aꢀ high-quality,ꢀ ceramic,ꢀ surface-mountꢀ capacitorꢀ ifꢀ
possible. Surface-mount components minimize lead induc-
tance,ꢀwhichꢀimprovesꢀperformance,ꢀandꢀceramicꢀcapaci-
tors tend to have adequate high-frequency response for
decoupling applications.
OPTION
FILTER
NETWORK
CURRENT
100Ω
IN+
IN-
FLOW
1µF
1µF
R
ESENSE
100Ω
Figure 7. Filter Network
Maxim Integrated
│ 18
www.maximintegrated.com
MAX34408/MAX34409
SMBus Dual/Quad Current Monitor
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
9/13
1/15
Initial release
—
1
Updated Benefits and Features section
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 MaximꢀIntegratedꢀProducts,ꢀInc.ꢀꢀ
│ 19
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