MAX35104ETL+T_技术文档

EVALUATION KIT AVAILABLE

MAX35104

Gas Flow Meter SoC

General Description

Beneﬁts and Features

● High Accuracy Flow Measurement for Billing and

The MAX35104 is a gas flow meter system-on-chip (SoC)

targeted as an analog front-end solution for the ultrasonic

gas meter and medical ventilator markets. With a time

measurement accuracy of 700ps and automatic differen-

tial time of flight (TOF), the device makes for simplified

computation of gaseous flow.

Leak Detection

• Time-to-Digital Accuracy Down to 700ps

Measurement Range Up to 8ms

• 2 Channels: Single-Stop Channel

● High Accuracy Temperature Measurement for Precise

Flow Calculations

Power consumption is the lowest available with ultra-low

62µA time-of-flight measurement and 125nA duty-cycled

temperature measurement. Multi-hit (up to six per wave)

capability with stop-enable windowing allows the device to

be fine-tuned for the application. Internal analog switches,

a configurable three-stage integrated operational ampli-

fier chain amplifier, and an ultra-low input offset compara-

tor provide the analog interface and control for a minimal

electrical bill of material solution. A programmable high-

voltage (up to 30V) pulse launcher provides up to 19dB of

transducer launch amplitude adjustment to compensate

for transducer aging and temperature, pressure, humidity

affects. Early edge detection ensures measurements are

made with consistent wave patterns to greatly improve

accuracy and eliminate erroneous measurements. Built-in

arithmetic logic unit provides TOF difference measure-

ments and programmable receiver hit accumulators to

minimize the host microprocessor access. For tempera-

ture measurement, the device supports a single 2-wire

PT1000 platinum resistive temperature detector (RTD) or

NTC thermistor. A simple 4-wire SPI interface allows any

microcontroller to effectively configure the device for its

intended measurement.

• One 2-Wire Sensor: PT1000, PT500 RTD, and

Thermistor Support

● Maximizes Battery Life with Low Device and Overall

System Power

• Ultra-Low 62µA TOF Measurement and 125nA

Duty-Cycled Temperature Measurement

• Event Timing Mode with Randomizer Reduces

Host μC Overhead to Minimize System Power

Consumption

• 2.3V to 3.6V Single-Supply Operation

● High Integration Solution Minimizes Parts Count and

Reduces BOM Cost

• Built-In Real-Time Clock

• Small, 5mm x 5mm, 40-Pin TQFN Package

• -40°C to +85°C Operation

Ordering Information appears at end of data sheet.

Applications

● Ultrasonic Gas Meters

● Medical Ventilators

19-8501; Rev 3; 12/17

MAX35104

Gas Flow Meter SoC

TABLE OF CONTENTS

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended External Crystal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Time-of-Flight (TOF) Measurement Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Pulse Echo TOF Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Early Edge Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TOF Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Step-Up DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Control and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Compensation Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

RSENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Kelvin Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Inductor (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Output Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Piezo Driver Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Transducer Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Analog Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Temperature Measurement Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Temperature Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Event Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Continuous Event Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Continuous Interrupt Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

TOF Sample Randomizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Event Timing Mode 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Event Timing Mode 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Event Timing Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

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MAX35104

Gas Flow Meter SoC

(

)

TABLE OF CONTENTS continued

Calibration Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Error Handling during Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

RTC, Alarm, Watchdog, and Tamper Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

RTC Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Alarm Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Tamper Detect Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Device Interrupt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

INT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Serial Peripheral Interface Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Opcode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Execution Opcode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TOF_UP Command (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

TOF_Down Command (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

TOF_DIFF Command (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Temperature Command (03h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Reset Command (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Initialize Command (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Bandpass Calibrate Command (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

EVTMG1 Command (07h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

EVTMG2 Command (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

EVTMG3 Command (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

HALT Command (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Calibrate Command (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Register Opcode Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Read Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Write Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

RTC and Watchdog Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Configuration Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Conversion Results Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

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MAX35104

Gas Flow Meter SoC

LIST OF FIGURES

Figure 1. SPI Timing Diagram Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 2. SPI Timing Diagram Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3. Time-of-Flight Up Measurement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. Start/Stop for Time-to-Digital Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5A. Pulse Echo Measurement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5B. Early Edge Detect Received Wave Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6. Boost Circuits Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. Kelvin Sense Connection Layout Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8. Piezo Driver Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9. Analog Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 10. Temperature Command Execution Cycle Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11. EVTMG2 Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12. EVTMG2 Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13. EVTMG3 Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 14. EVTMG3 Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 15. EVTMG1 Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 16. EVTMG1 Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17. Execution Opcode Command Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18. Read Register Opcode Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 19. Continuous Read Register Opcode Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 20. Write Register Opcode Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 21. Continuous Write Register Opcode Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

LIST OF TABLES

Table 1. Two’s Complement TOF_DIFF Conversion Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2. RSENSE Example Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 3. Example Gain Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4. Randomizer Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 5. Opcode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 6. Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 7. RTC Seconds Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 8. RTC Mins_Hrs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 9. RTC Day_Date Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 10. RTC Month_Year Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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MAX35104

Gas Flow Meter SoC

(

)

LIST OF TABLES continued

Table 11. Watchdog Alarm Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 12. Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 13. Switcher 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 14. Switcher 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 15. AFE 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 16. AFE 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 17. TOF1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 18. TOF2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 19. TOF3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 20. TOF4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 21. TOF5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 22. TOF6 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 23. TOF7 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 24. Event Timing 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 25. Event Timing 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 26. TOF Measurement Delay Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 27. Calibration and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 28. Real-Time Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 29. Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 30. Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 31. Conversion Results Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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MAX35104

Gas Flow Meter SoC

Absolute Maximum Ratings

(Voltage relative to ground.)

Operating Temperature Range............................-40ºC to +85ºC

Junction Temperature......................................................+150ºC

Storage Temperature Range.............................-55ºC to +125ºC

Soldering Temperature (reflow).......................................+260ºC

Lead Temperature (soldering, 10s) .................................+300ºC

ESD Protection (All Pins, Human Body Model) ................±500V

Voltage Range on V

Pins.................................-0.5V to +4.0V

CC

Voltage Range on All Other

Pins (not to exceed 4.0V)..................... -0.5V to (V

Voltage Range on High Voltage Pins....................................32V

+ 0.3V)

CC

Continuous Power Dissipation (T = +70ºC)

A

TQFN (derate 35.70mW/ºC above +70ºC)...........2857.10mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

(Note 1)

Package Thermal Characteristics

TQFN

Junction-to-Ambient Thermal Resistance (θ ) ..........28°C/W

Junction-to-Case Thermal Resistance (θ ).................2°C/W

JC

JA

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Recommended Operating Conditions

(T = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3)

A

PARAMETER

Supply Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

2.3

3.3

3.6

V

CC

Input Logic 1 (RST, CSW, SCK,

DIN, CE)

V

x 0.7

V + 0.3

CC

V

IH

CC

Input Logic 0 (RST, CSW, SCK,

DIN, CE)

V

-0.3

x 0.85

V

x 0.3

+ 0.3

IL

CC

Input Logic 1 (32KX1)

Input Logic 0 (32KX1)

V

IH32KX1

CC

V

-0.3

V

x 0.15

CC

IL32KX1

Electrical Characteristics

(V

= +2.3V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V

= 3.3V and T = +25°C.) (Notes 2, 3)

CC A

CC

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Leakage (CSW, RST,

SCK, DIN, CE, CIP, CIN)

I

-0.1

+0.1

µA

L

Output Leakage (INT, WDO,

T1,T2)

O

-0.1

+0.1

µA

L

Output Voltage Low (32KOUT)

Output Voltage High (32KOUT)

V

2mA

0.2 x V

V

OL32K

CC

V

-1mA

0.8 x V

3.4

OH32K

CC

Output Voltage High

(DOUT, CMP_OUT/UP_DN)

V

-4mA

V

Ω

OH

CC

Output Voltage High (TC)

V

= 3.6V, I

= -4mA

OHTC

CC

OUT

Output Voltage Low (WDO,

INT, DOUT, MP_OUT/UP_DN)

V

4mA

ITC

0.2 x V

1750

OL

TC

CC

Pulldown Resistance (TC)

R

650

1000

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MAX35104

Gas Flow Meter SoC

Electrical Characteristics (continued)

(V

= +2.3V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V

= 3.3V and T = +25°C.) (Notes 2, 3)

CC A

CC

A

PARAMETER

SYMBOL

V

CONDITIONS

MIN

TYP

MAX

UNITS

Input Voltage Low (TC)

Pulldown (RXP, RXN)

Resistance (T1, T2)

0.36 x V

V

ILTC

CC

AFE_BP = 0, pins disabled

80

1.5

7

µA

Ω

R

ON

Input Capacitance (CE, SCK,

DIN, RST, CSW)

C

Not tested

pF

ns

IN

RST Low Time

t

100

RST

CURRENT

Standby Current

32kHz OSC Current

4MHz OSC Current

I

No oscillators running

10

1

µA

DDQ

I

32kHz oscillator only, V

= 3.6V

0.42

82

32KHZ

CC

I

4MHz oscillator only, V

135

4MHZ

CC

Time Measurement Unit

Current

I

V

= 3.3V

4.3

1.2

62

8

3

mA

CCTMU

CC

Calculator Current

I

CCCPU

V

= 3.3V, TOF_DIFF = 2 per second,

CC

Device Current Drain

I

CC

µA

temperature = 1 per 30 seconds

TRANSMITTER: BOOST SWITCH

Output Voltage Range

ER

9

30

V

Programmable Output Voltage

Step Size

1.7

Output Switching Frequency

Current-Limit Trip Level

100

200

kHz

mV

V

150

CS-SW

TRANSMITTER: FET GATE DRIVER

External FET Gate Charge

Rise Time

Q

2

nC

ns

G

t

C = 1nF (Figure 2, Note 3)

100

R

L

Fall Time

t

C = 1nF (Figure 2, Note 3)

L

F

TRANSMITTER: HIGH-VOLTAGE REGULATOR

Output Voltage Range

Low

5.4

V

Output Voltage Range

High

26.4

Programmable Output Voltage

Step Size

1.7

V

Output Voltage Accuracy

5

%

Load Regulation

I

= 15mA

150

mV

LOAD

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MAX35104

Gas Flow Meter SoC

Electrical Characteristics (continued)

(V

= +2.3V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V

= 3.3V and T = +25°C.) (Notes 2, 3)

CC A

CC

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TRANSMITTER: PIEZO DRIVER

Driver Output Resistance

Pulling Down (n-Channel)

R

V

= 10V, I =10mA

50

Ω

ON-N-PD

IN

LD

Driver Output Resistance

Pulling Up (p-Channel)

= 10V, I =10mA

ON-P-PU

IN

LD

Output Leakage Current

Rise Time

I

0.05

100

µA

ns

LK-PD

t

C = 1nF

L

R-PD

Fall Time

t

C = 1nF

L

F-PD

FILTER SPECIFICATION

Input Amplitude

1

10

mV

kΩ

dB

Diﬀerential Input Impedance

Programmable Gain Resolution

COMPARATOR SPECIFICATION

4

Per bit

1.5

C_OFFSETUP or C_OFFSETDN

register programmed to 00h

Input Oﬀset Voltage

V

2

1

mV

OFFSET

Input Oﬀset Step Size

V

STEP

Receiver Sensitivity

V

Stop hit detect level

f = 200kHz

10

mV

P-P

SENS

ANALOG RECEIVER: BANDPASS FILTER

Center Frequency Accuracy

f

6

4

%

0A

Q Range

Hz/Hz

%

12

20

Q Accuracy

200kHz PERFORMANCE

A1 Diﬀerential Gain

200kHz, V = 6mV

10

±1

V/V

%

IN

P-P

UP/DN Gain Match

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MAX35104

Gas Flow Meter SoC

Electrical Characteristics (continued)

(V

= +2.3V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V

= 3.3V and T = +25°C.) (Notes 2, 3)

CC A

CC

A

PARAMETER

PGA[3:0] = 0000b

SYMBOL

CONDITIONS

MIN

TYP

3.16

3.69

4.30

5.01

5.84

6.81

7.94

9.26

10.8

12.6

14.7

17.1

20.0

23.3

27.1

31.6

MAX

UNITS

V

= 19.0mV

= 16.3mV

= 14.0mV

= 12.0mV

= 10.3mV

= 8.80mV

= 7.55mV

= 6.48mV

= 5.56mV

= 4.76mV

= 4.09mV

= 3.51mV

= 3.02mV

= 2.58mV

= 2.21mV

= 1.90mV

IN

P-P

PGA[3:0]= 0001b

PGA[3:0]= 0010b

PGA[3:0]= 0011b

PGA[3:0]= 0100b

PGA[3:0]= 0101b

PGA[3:0]= 0110b

PGA[3:0]= 0111b

PGA[3:0]= 1000b

PGA[3:0]= 1001b

PGA[3:0]= 1010b

PGA[3:0]= 1011b

PGA[3:0]= 1100b

PGA[3:0]= 1101b

PGA[3:0]= 1110b

PGA[3:0]= 1111b

PGA Gain

V

= 600mV

V/V

OUT

P-P

V

= 19mV

IN

P-P

Filter Gain at 200kHz Trim

1.0

V/V

Filter Gain with Bypass

= 19mV

0.01

IN

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MAX35104

Gas Flow Meter SoC

Electrical Characteristics (continued)

(V

= +2.3V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V

= 3.3V and T = +25°C.) (Notes 2, 3)

CC A

CC

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIME MEASUREMENT UNIT

Measurement Range

t

Time of ﬂight

Diﬀerential time measurement

4

8000

µs

ps

MEAS

Time Measurement Accuracy

Time Measurement Resolution

EXECUTION TIMES

t

700

3.8

ACC

t

RES

Power-On-Reset Time

Case Switch Time

V

MIN to POR bit set

275

20

µs

ns

CC

CSW pin logic-high until CSWI bit set

Command received until CAL bit set

CAL Command Time

1.25

ms

SERIAL PERIPHERAL INTERFACE (Figure 1 and Figure 2)

DIN to SCK Setup

SCK to DIN Hold

SCK to DOUT Delay

t

20

ns

DC

t

2

5

CDH

CDD

V_CC≥ 3.0V

25

50

25

4

SCK Low Time

t

ns

CL

V_CC= 2.3V

30

4

SCK High Time

t

ns

MHz

ns

CH

SCK Frequency

t

20

10

40

20

40

SCK

SCK Rise and Fall

CE to SCK Setup

SCK to CE Hold

t , t

R

F

t

5

ns

CC

t

ns

CCH

CE Inactive Time

CE to DOUT High Impedance

t

2

5

ns

CWH

t

ns

CCZ

Note 2: All voltages are referenced to ground. Current entering the device are specified as positive and currents exiting the device

are negative.

Note 3: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage

A

range are guaranteed by design and characterization.

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MAX35104

Gas Flow Meter SoC

Recommended External Crystal Characteristics

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

32kHz Nominal Frequency

f

32.768

kHz

32K

32kHz Frequency Tolerance

32kHz Load Capacitance

32kHz Series Resistance

∆f

/f

25°C

-20

+20

70

ppm

pF

32K 32K

C

12.5

L32K

S32K

R

kΩ

4MHz Crystal Nominal Frequency

4MHz Crystal Frequency Tolerance

4MHz Crystal Loadapacitance

f

4.000

12.0

4.000

30

MHz

ppm

pF

4M

Δf /f

25°C

-30

+30

120

+0.5

4M 4M

C

L4M

4MHz Crystal Series Resistance

4MHz Ceramic Nominal Frequency

4MHz Ceramic Frequency Tolerance

4MHz Ceramic Load Capacitance

R

Ω

S4M

MHz

%

-0.5

pF

Timing Diagrams

t

CC

CE

t

CWH

t

CDH

SCK

DIN

t

DC

MSB

LSB

t

CCZ

CDD

DOUT

HIGH IMPEDANCE

MSB

LSB

Figure 1. SPI Timing Diagram Read

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MAX35104

Gas Flow Meter SoC

Timing Diagrams (continued)

t

CC

t

CWH

CE

t

CLK

t

R

t

CCH

F

t

CH

CDH

V

IH

t

CL

SCK

DIN

V

IL

t

DC

MSB

LSB

DOUT

HIGH IMPEDANCE

Figure 2. SPI Timing Diagram Write

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MAX35104

Gas Flow Meter SoC

Pin Conﬁguration

TOP VIEW

30 29 28 27 26 25 24 23 22 21

31

32

33

34

35

36

37

38

39

40

20

19

18

17

16

15

14

13

12

11

AVDD

RXP

RXN

CIN

V

2X

FETG

V_DD

CPH

CPL

WDO

INT

CIP

MAX35104

AVSS

32KOUT

T1

DOUT

DIN

EP = V

SSIO

+

T2

SCK

TC

1

2

3

4

5

6

7

8

9

10

TQFN

(5mm x 5mm)

Pin Description

NAME

FUNCTION

Connections for 32.768kHz Quartz Crystal, Connect a 12pF ceramic capacitor from each pin to

ground. An external CMOS 32.768kHz signal can also drive the device. In this conﬁguration, the

32KX1 pin is connected to the external signal and the 32KX2 pin is left unconnected.

1

32KX1

2

3

32KX2

LDO Supply Voltage. This pin should be decoupled to V

(Note 1).

with a 100nF ceramic capacitor

SSISO

V

DDISO

Connections for 4MHz Quartz Crystal, connect a 12pF ceramic capacitor from each pin to

ground. A ceramic resonator can also be used. An external CMOS 4MHz signal can also drive

the device. In this conﬁguration, the 4MX1 pin is connected to the external signal and the 4MX2

pin is left unconnected.

4

4MX1

5

6

7

4MX2

CSW

CMOS Digital Input Case Switch. Active high tamper detect input.

CMOS output that indicates the direction (upstream or downstream) of which the pulse launcher

is currently launching pulses OR the comparator output (Note 2).

CMP_OUT/UP_DN

Connect this pin to ground with a 100nF ceramic capacitor to provide stability for the on-board

low-dropout regulator. The eﬀective series resistance of this capacitor needs to be in the range of

1Ω to 2Ω (Note 3).

8

BYPASS

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MAX35104

Gas Flow Meter SoC

Pin Description (continued)

9

NAME

RST

CE

FUNCTION

Active-Low Reset (CMOS Digital Input). Performs the same function as a power-on reset (POR).

Active-Low Serial Peripheral Interface Chip Enable Input (CMOS Digital Input)

Serial Peripheral Interface Clock Input (CMOS Digital Input)

10

11

12

13

SCK

DIN

Serial Peripheral Interface Data Input (CMOS Digital Input)

DOUT

Serial Peripheral Interface Data Output (CMOS Output)

Active-Low, Open-Drain Interrupt Output. The pin is driven low when the device requires service

from the host microprocessor.

14

15

16

17

18

19

20

21

22

23

INT

WDO

CPL

CPH

Active-Low, Open-Drain Watchdog Output. The pin is driven low when the watchdog counter

reaches zero (if enabled).

Negative terminal of the ﬂying capacitor for the voltage doubler. Connect this pin to CPH with a

100nF ceramic capacitor. (Note 4)

Positive terminal of the ﬂying capacitor for the voltage doubler. Connect this pin to CPL with a

100nF ceramic capacitor. (Note 4,5)

Supply Voltage. This pin should be decoupled to V with a 100nF and a 22µF ceramic capacitor

SS

(Note 1).

V

DD

PWM Modulated CMOS Gate Driver Output for External n-Channel Power Transistor used in the

Boost Switcher. Place a 25Ω series resistor between this pin and the transistor gate.

FETG

Connect this pin to ground with a 100nF ceramic capacitor to provide stability for the on-board

voltage doubler (Notes 3, 4).

V

2X

Error-Ampliﬁer Output of Boost Converter. Connect the frequency-compensation network

between COMP and AVSS. See Figure 6 (Notes 3, 4).

COMP

High-Current Ground Return for the Boost Switcher. Connect the current-sense resistor between

this pin and CSIN+ (Note 4).

V

SS_SW

Positive Analog Input to the Current-Sense Ampliﬁer for the Boost Switcher. Connect the current-

sense resistor between this pin and CSIN (Note 4).

CSIN

Connect to the negative terminal of the piezo transducer located downstream of the gas ﬂow.

Performs the launching and receiving functions required for a time-of-ﬂight measurement. In the

launch case, it is the negative output of the bridged diﬀerential output driver pair. In the receive

case, it is the negative input of the analog diﬀerential return signal from the piezo transducer

(Notes 2, 4).

24

25

TX_DNN

TX_DNP

Connect to the positive terminal of the piezo transducer located downstream of the gas ﬂow.

Performs the launching and receiving functions required for a time-of-ﬂight measurement. In the

launch case, it is the positive output of the bridged diﬀerential output driver pair. In the receive

case, it is the positive input of the analog diﬀerential return signal from the piezo transducer

(Notes 2, 4).

26

27

V

Ground Connection

SS

Resulting High-Voltage Bias Generated by the Boost Switcher Circuit. Used as the supply for the

high-voltage regulator and to generate the feedback voltage fed into the error-ampliﬁer for closed

loop control. (Notes 3, 4).

V

P

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MAX35104

Gas Flow Meter SoC

Pin Description (continued)

NAME

FUNCTION

Connect this pin to ground with a 1µF ceramic capacitor to provide stability for the on-board high-

voltage regulator. When the high-voltage regulator is not used and constantly disabled, short this

pin to VP (Notes 3, 4).

28

V

PR

Connected to the negative terminal of the piezo transducer located upstream of the gas ﬂow.

Performs the launching and receiving functions required for a time-of-ﬂight measurement. In the

launch case, it is the negative output of the bridged diﬀerential output driver pair. In the receive

case, it is the negative input of the analog diﬀerential return signal from the piezo transducer

(Notes 2, 4).

29

30

TX_UPN

TX_UPP

Connected to the positive terminal of the piezo transducer located upstream of the gas ﬂow.

Performs the launching and receiving functions required for a time-of-ﬂight measurement. In the

launch case, it is the positive output of the bridged diﬀerential output driver pair. In the receive

case, it is the positive input of the analog diﬀerential return signal from the piezo transducer

(Notes 2, 4).

Analog Supply Voltage. This pin should be decoupled to AVSS with a 100nF ceramic capacitor

(Note 1).

31

32

AVDD

RXP

Do Not Connect (DNC) When Utilizing the Internal Analog Front-End. Positive analog output from

the selected transducer’s diﬀerential return signal. When used with the CIP pin provides a way to

construct an external analog front-end (Note 5).

Do Not Connect (DNC) When Utilizing the Internal Analog Front-End. Negative analog output

from the selected transducer’s diﬀerential return signal. When used with the CIN pin provides a

way to construct an external analog front-end (Note 5).

33

34

35

RXN

CIN

CIP

Do Not Connect (DNC) When Utilizing the Internal Analog Front-End. Negative analog input to

the diﬀerential receive comparator. When used with the RXN pin provides a way to construct an

external analog front-end (Note 5). OR negative analog output of selectable AFE stages (Note 2).

Do Not Connect (DNC) When Utilizing the Internal Analog Front-End. Positive analog input to

the diﬀerential receive comparator. When used with the RXP pin provides a way to construct an

external analog front-end (Note 5). OR positive analog output of selectable AFE stages (Note 2).

36

37

38

39

40

EP

AVSS

32KOUT

T1

Ground Connection

CMOS Output That Repeats the 32kHz Crystal Oscillator Frequency

Open-Drain Probe 1 Temperature Measurement (Note 5)

Open-Drain Probe 2 Temperature Measurement (Note 5)

Input/Output Temperature Measurement Capacitor Connection (Note 5)

Exposed Pad, Ground Connection

T2

TC

V

SSISO

Note 1: A +2.7V to +3.6V supply. Typically sourced from a single lithium cell.

Note 2: Dual functionality pin.

Note 3: Do not connect to additional non-recommended external circuitry.

Note 4: High-voltage tolerant.

Note 5: This pin can be left open circuit if not needed.

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MAX35104

Gas Flow Meter SoC

Block Diagram

CIP CIN

CMP_OUT/UP_DN

T1

T2

V

BAT

10kΩ (50ppm)

METAL FILM

TUNABLE BPF

125kHz TO

500kHz

3.6V LTC CELL

PGM OFFSET

COMPARATOR

TIME-TO-DIGITAL

CONVERTER

10DB TO

30dB

FIXED

20dB

10 nF COG (NP0)

(30ppm/°C)

TC

TEMPERATURE

RXP

RXN

MAX35104

SCK

DOUT

DIN

DATA AND STATUS

REGISTER

SPI

PROGRAMMABLE ALU

4-WIRE SPI

I /

TX_UPN

HIGH-VOLTAGE

PULSE

TX_UPP

CE

PIEZOELECTRIC

TRANSDUCERS

LAUNCHER UP

TX_DNN

TX_DNP

MICRO

TO 30 V

DIGITAL

CONTROL

INTERFACE

WDO

INT

HV REGULATOR

V

PR

STATE MACHINE

CONTROLLER

INTERRUPT

CONFIG

REGISTERS

V

P

V

DD

RST

COMP

CSW

F/F

Q

ERROR

AMP

R

COMP

V

DD

SWITCHER

N

S

INTERNAL LDO

BYPASS

GAIN

(4x)

BG

CSIN

HIGH-SPEED

OSCILLATOR

REAL-TIME

CLOCK

EVENT TIMER W/

RANDOMIZER

32kHz OSCILLATOR

GATE DRIVER

FETG

VOLTAGE DOUBLER

V

SS_SW

AVDD

V

DD

DDISO

CPL

CPH

4MX1

4MX2

32KOUT

32KX1

32KX2

V

2X

AVSS

V

SS

SSISO

solution. A programmable high-voltage (up to 30V) pulse

launcher provides up to 19dB of transducer launch ampli-

tude adjustment to compensate for transducer aging and

temperature, pressure, humidity affects.

Detailed Description

The MAX35104 is a gas flow meter SoC targeted as an

analog front-end solution for the ultrasonic gas meter

and medical ventilator markets. With a time measure-

ment accuracy of 700ps and automatic differential Time-

of-Flight measurement, the device makes for simplified

computation of gaseous flow. Power consumption is the

lowest available with ultra-low 62µA TOF measurement

and 125nA duty-cycled temperature measurement.

Early edge detection ensures measurements are made

with consistent wave patterns to greatly improve accuracy

and eliminate erroneous measurements. A built-in arith-

metic logic unit provides TOF difference measurements

and programmable receiver hit accumulators to minimize

the host microprocessor access. For temperature mea-

surement, the device supports a single 2-wire PT1000

platinum resistive temperature detector (RTD) or NTC

thermistor. A simple 4-wire SPI interface allows any micro-

controller to effectively configure the device for its intended

measurement.

Multihit (up to 6 per wave) capability with stop-enable

windowing allows the device to be fine-tuned for the appli-

cation. Internal analog switches, a configurable 3-stage

integrated operational amplifier chain amplifier, and an

ultra-low input offset comparator provide the analog inter-

face and control for a minimal electrical bill of material

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MAX35104

Gas Flow Meter SoC

TOF START

V

HV-REGULATOR

1

0

1

0

TX_UPN

TX_UPP

TRANSDUCER

RING DOWN

~0.7V

TX_DNN

TX_DNP

AMPLIFIED AND FILTERED OUTPUT TO

PROGRAMMABLE OFFSET

COMPARATOR (INTERNAL TO THE

DEVICE)

POWER

DOWN

STATE

TOF STOP

AVG =

∑(HIT[1:6]) ÷ 6

COMPARATOR OFFSET

WAVE NUMBER

COMPARATOR

OFFSET

RETURN

POWER DOWN STATE

POWER

DOWN

STATE

PROGRAMMABLE OFFSET COMPARATOR

INPUTS (INTERNAL TO THE DEVICE)

0

1

2

3

4

5

6

7

8

9

10 11

INT PIN

(2)

(1)

4 MHZ

STARTUP

(4)

TOF

ENABLE BOOST

CIRCUIT & WAIT

STABILIZATION

TIME

MEASUREMENT

DELAY

(3)

LAUNCH

PULSES

~10us

CONFIGURE

(6)

(8)

ENABLE

COMPARATOR

TOF COMMAND

(5)

INTERNAL ANALOG

RECEIVED

BIAS APPLIED TO

INTERNAL

DISABLE BOOST

CIRCUIT

SWICTHES

COMPARATOR CAPS

(13)

CALCULATIO

NS

(9)

(11)

(10)

COMPARE

RETURN

(12)

STOP

HITS

(14)

INT

ASSERTED

t

WAVE

t WAVE

2

1

SELECTED WAVES FOR HITS:

= 4 HIT1 = 6 HIT2 = 7 HIT3 = 8 HIT4 = 9 HIT5 = 10 HIT6 = 11

STOP HITS SELECTED = 6, STOP POLARITY = POSITIVE EDGE

t

2

Figure 3. Time-of-Flight Up Measurement Sequence

1) The 4MHz oscillator and LDO is enabled with a pro-

grammable settling delay time set by the CLK_S[2:0]

bits in Calibration and Control register.

Time-of-Flight (TOF) Measurement Operations

TOF is measured by launching pulses from one piezo-

electric transducer and receiving the pulses at a second

transducer. The time between when the pulses are

launched and received is defined as the time of flight. The

device contains the functionality required to create a string

of pulses, sense the receiving pulse string, and measure

the time of flight. The device can measure two separate

TOFs, which are defined as TOF Up and TOF Down.

2) The boost circuit is enabled and attempts to reach

the targeted set output voltage. Once at the target

voltage, the stabilization time to wait before mov-

ing to the next step is set by the ST[3:0] bits in the

Switcher 2 register.

3) The pulse launcher drives the appropriate TX pins

with a programmable sequence of pulses. The num-

ber of pulses launched is set by the PL[7:0] bits in

the TOF1 register. The frequency of these 50% duty-

cycle pulses is set by the DPL[3:0] bits, also in the

TOF1 register. The start of these launch pulses gen-

erates a start signal for the Time-to-Digital Converter

(TDC) and is considered to be time zero for the TOF

measurement. This is denoted in Figure 4.

A TOF Up measurement has pulses launched from the

TX_UPN and TX_UPP pins, which is connected to the

downstream transducer. The ultrasonic pulse is received

at the upstream transducer, which is connected to the

TX_DNN and TX_DNP pins. A TOF Down measurement

has pulses launched from the TX_DNN and TX_DNP

pins, which is connected to the upstream transducer. The

ultrasonic pulse is received at the downstream transduc-

er, which is connected to the TX_UPN and TX_UPP pins.

4) After a programmable delay time set in TOF Mea-

surement Delay register, the comparator and hit

detector at the appropriate pins are enabled. This

delay allows the receiver to start recording hits when

the received wave is expected, eliminating possible

false hits from noise in the system.

TOF measurements can be initiated by sending either the

TOF_UP, TOF_DN, or TOF_DIFF commands. TOF_DIFF

measurements can also be automatically executed using

Event Timing Mode commands EVTMG1 or EVTMG2.

The steps involved in a single TOF measurement are

described below and labeled in Figure 3.

5) Once the pulse launcher has completed transmitting

the sequence of pulses, the boost circuit is disabled.

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MAX35104

Gas Flow Meter SoC

6) A common mode bias is enabled on the internal

capacitor connecting the output of the bandpass ﬁlter

to the input of the programmable oﬀset comparator.

This bias charge time is ﬁxed at approximately 10µs.

AVGDNInt and AVGDNFrac. The ratio of t /t and t /

1 2 2

t

are calculated and stored in the WVRUP or

IDEAL

WVRDN register.

13) Once all the hit data, wave ratios, and averages

become available in the Results registers, the TOF

7) The comparator is enabled.

bit in the Interrupt Status register is set and the INT

pin is asserted (if enabled) and remains asserted

until the Interrupt Status register is accessed by the

microprocessor with a Read register command.

8) Stop hits are detected according to the programmed

preferred edge of the acoustic signal sequence

received at the appropriate pins according to the

setting of the STOP_POL bit in the TOF1 register.

When a wave received at the receiving pins exceeds

the Comparator Oﬀset Voltage, which is set in the

TOF6 and TOF7 registers, this wave is detected and

identiﬁed as wave number 0. The width of the wave’s

pulse that exceeds the Comparator Oﬀset Voltage is

The computation of the total time of flight is performed

by counting the number of full and fractional 4MHz clock

cycles that elapsed between the launch start and a hit

stop as shown in Figure 4.

Table 1. Two’s Complement TOF_DIFF

Conversion Example

measured and stored as the t time.

1

9) The oﬀset of the comparator then automatically and

immediately switches to the Comparator Return Oﬀ-

set, which is set in the TOF6 and TOF7 registers.

REGISTER VALUE

CONVERTER VALUE

TOF_DIFFInt

TOF_DIFFFrac

(hex)

TOF DIFF Value

10) The t wave is detected and the width of the t pulse

(hex)

7FFF

001C

0001

0000

FFFF

FFFE

FF1C

8000

(ns)

2

is measured and stored as the t time. The wave

2

FFFF

0403

00A1

0089

0001

0000

FFFF

FFC0

1432

8001

0000

8,191,999.9962

7,003.9177

250.6142

0.5226

number for the measurement of the t wave width is

set by the T2WV[5:0] bits in the TOF2 register.

2

11) The preferred number of stop hits are then detected.

For each hit, the measured TOF is stored in the

appropriate HITxUPINT and HITxUPFrac or HITx-

DNINT and HITxDNFRAC registers. The number

of hits to detect is set by the STOP[2:0] bits in the

TOF2 register. The wave number to measure for

each stop hit is set by the Hitx Wave Select bits in

the TOF3, TOF4, and TOF5 registers.

0.0038

0.0000

-0.0038

-0.2441

-480.2780

-56,874.9962

-8,192,000.0000

12) After receiving all the programmed hits, the de-

vice calculates the average of the recorded hits

and stores this to AVGUPINT and AVGUPFrac or

FRACTIONAL TOF RESULTS PORTION

1 LSB = T_4MHz/(2^16)

INTEGER TOF RESULTS PORTION

1 LSB = T_4MHZ

2

3

4

N

1

4 MHz CLOCK

START SIGNAL

STOP SIGNAL

(INTERNALLY GENERATED

WHEN ACOUSTIC SIGNAL

IS TRANSMITTED)

(GENERATED UPON

ACOUSTIC SIGNAL

RECEPTION)

TOTAL TIME OF FLIGHT = INTEGER + FRACTIONAL

Figure 4. Start/Stop for Time-to-Digital Timing

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MAX35104

Gas Flow Meter SoC

Each TOF measurement result is comprised of an integer

portion and a fractional portion. The integer portion is a

if triggering on a negative edge, with 1 LSB = V /3072.

CC

Separate input offset settings are available for the

Upstream received signal and the Downstream received

signal. The input offset for the Upstream received signal is

programmedusingtheC_OFFSETUP[6:0]bitsintheTOF6

register,. The input offset for the Downstream received

signal is programmed using the C_OFFSETDN[6:0] bits in

binary representation of the number of t

periods that

4MHz

contribute to the time results. The fractional portion is a

binary representation of one t period quantized to

4MHz

a 16-bit resolution. The maximum size of the integer is

15

7FFFh or (2 - 1) x t

or ~ 8.19ms. The maximum

4MHz

16

size of the fraction is FFFFh or (2 - 1)/2 x t

. or

the TOF7 register. Once the first hit is detected, the time t

4MHz

1

~ 249.9961 ns.

equal to the width of the earliest detectable edge is mea-

sured. The input offset voltage is then automatically and

immediately returned to a preprogrammed comparator

offset value. This return offset value has a range of +127

LSB’s to -128 LSB’s in 1 LSB steps and is programmed

into the C_OFFSETUPR[7:0] bits in the TOF6 register for

the Upstream received signal and programmed into the

C_OFFSETDNR[7:0] bits in the TOF7 register. This pre-

programmed comparator offset return value is provided to

allow for common-mode shifts that can be present in the

received acoustic wave.

Pulse Echo TOF Mode

The device also has a pulse echo mode of operation.

This mode allows time-of-flight measurements to be taken

when only one transducer is used. The sole transducer

transmits the high-voltage pulses and then receives the

return signal. The time-of-flight measurement operation

acts exactly as described in steps 1–13 except that the

common mode of the AFE is applied to the same pins that

transmitted the high-voltage pulses (Figure 5A).

The resulting data from the measurement is reported in

the same manner as described in the TOF_UP, TOF_

DOWN, or TOF_DIFF sections depending upon which

command was executed.

The device is now ready to measure the successive hits.

The next selected wave that is measured is the t wave.

2

In the example in Figure 5B, this is the 7th wave after the

Early Edge Detect wave. The selection of the t wave is

2

made with the T2WV[5:0] bits in the TOF2 register.

The pulse echo mode is enabled by setting the PECHO

bit in the Switcher 2 Register.

With reference to Figure 5B, the ratio t /t is calculated

1 2

and registered for the user. This ratio allows determination

of abrupt changes in flow rate, received signal strength,

partially filled tube detection, and empty tube. It also pro-

vides noise suppression to prevent erroneous edge detec-

Early Edge Detect

The Early Edge Detect method of measuring the TOF of

acoustic waves is used for all the TOF commands includ-

ing TOF_UP, TOF_DN, and TOF_DIFF. This method

allows the device to automatically control the input offset

voltage of the receiver comparator so that it can provide

advanced measurement accuracy. The input offset of the

receiver comparator can be programmed with a range

+127 LSBs if triggering on a positive edge and -127 LSBs

tion. Also, the ratio t /t

is calculated and registered

2 iDEAL

for the user. For this calculation, t

is one-half the

IDEAL

period of launched pulse. This ratio adds confirmation that

the t wave is a strong signal, which provides insight into

2

the common mode offset of the received acoustic wave.

DIFFERENTIAL DRIVE, SD_EN = 0B

PULSE ECHO MODE, PECHO = 1b

V

HV-REGULATOR

1

0

TRANSDUCER

RING DOWN

TX_UPN

TX_UPP

~0.7V

TX_DNN

TX_DNP

Figure 5A. Pulse Echo Measurement Mode

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MAX35104

Gas Flow Meter SoC

OFFSET RESETS AUTOMATICALLY TO A PRE-

PROGRAMMED VALUE (± 127mV IN 1mV STEPS) TO

DETECT SUBSEQUENT ZERO-CROSSINGS

WAVE NUMBER

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

PROGRAMMABLE OFFSET DETECT: ± 127mV IN

1mV STEPS

Programmable Offset

Comparator Inputs (Internal

to the Device)

HIT #:

1

2

3

4

5

6

t

2

t

1

EXAMPLE: MEASURE WIDTH OF

7^THWAVE AFTER EARLY EDGE

DETECT

Figure 5B. Early Edge Detect Received Wave Example

The integrated boost controller in enabled and disabled

automatically by the device. The logic enables the boost

before executing a time of flight command and disables

the boost once the transmit pulse train is complete, see

example timing in the Figure 3. The boost is disabled

upon completion of the transmit pulses in order to reduce

overall system power consumption as well as to eliminate

any controller switching noise that would be introduced

during the return signal’s timing measurements.

TOF Error Handling

Any of the TOF measurements can result in an error.

If an error occurs during the measurement, all the

associated registers report FFFFh. If a TOF_DIFF is

being performed, the TOF_DIFFInt and TOF_DIF_Frac

registers report 7FFFh and FFFFh, respectively. The

TOF_DIFF_AVG Results registers do not include the error

measurement. If the measurement error is caused by

the time measurement exceeding the timeout set by the

TIMOUT[2:0] bits in the TOF2 register, then the TO bit in

the Interrupt Status register is set and the INT device pin

is asserted (if enabled).

Control and Operation

The switching frequency of the controller is programmable

from 100kHz to 200kHz in 4 steps set by the SFREQ[1:0]

bits in the Switcher 1 register. In order to set the output

voltage the controller uses an outer loop feedback topol-

ogy along with a peak current mode inner loop control.

Step-Up DC-DC Controller

In order to increase the power transferred to the trans-

ducers during a launch sequence which is required to

counteract the high attenuation factors for ultrasonic

waves in gaseous mediums the device contains an inte-

grated DC-DC Step-Up controller designed to operate

in discontinuous-conduction mode (DCM boost). The

controller provides adjustable-output voltage operation

including programmable stabilization times with built in

under voltage monitoring. The MAX35104’s integrated

gate driver utilizes the onboard voltage double in order to

drive an external N-channel MOSFET’s gate from ground

The controller’s outer loop targets an output voltage from

9V to 30V based on the programmed value set by the

VS[3:0] bits in the Switcher 1 register. An internal error

amplifier creates a control voltage, which generates a

duty-modulated signal to control the operation of the

internal gate driver used to switch the external MOSFET.

Additionally, the MOSFET’s source needs an external

current sense resistor, which feeds back the inductor’s

current per cycle as a voltage and compares with the error

amplifier’s output to further adjust the duty-modulated

signal, thus forming an inner loop.

to 2 x V . The controller uses an external sense resis-

DD

tor to control the peak inductor current and operates at

adjustable switching frequencies.

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MAX35104

Gas Flow Meter SoC

The controller has an undervoltage comparator that deter-

mines if the target output voltage is at target voltage, con-

sidered power good, or undervoltage. If the output voltage

is below target, the switcher operates in startup limit mode

that is determined by user selectable peak current limit

set by the LT_S[3:0] bits in the Switcher 2 register. This

is essentially a slew rate control on how fast the boost

powers up and can be used to control the current signa-

tures seen by the supply battery. After the output voltage

crosses the undervoltage threshold, the switcher runs in

normal duty mode. There is an additional optional peak

current limit setting for the normal duty mode that is set by

the LT_N[3:0] bits in the Switcher 2 register. Once in nor-

mal duty mode the device waits a programmable switcher

stabilization time before a launch sequence begins. The

stabilization time ensure that the controller has reaches a

stable and repeatable output voltage each time it is pow-

ered. This time is set by the ST[3:0] bits in the Switcher 2

register. See Figure 6.

frequency of the open-loop gain-transfer function of the

converter. The error amplifier included in the devices is a

transconductance amplifier. Figure 6 shows the compen-

sation network used to apply the necessary loop com-

pensation for the example inductor and output capacitor

values provided, where:

RZ = 22kΩ

CP = 470pF

CZ = 10nF

RSENSE

The external sense resistor value determines the peak

allowable inductor current. For a given limit trim setting,

LT_N[3:0] and LT_S[3:0] in the Switcher 2 register. Adjust

the RSENSE value to adjust the peak allowable current.

Select RSENSE based on the following criteria:

Resistor Value: Select an RSENSE resistor value in which

the largest desired current would result in a 200mV full-

scale current sense voltage. Assuming an LT_x setting of

0h, select RSENSE in accordance to the following equa-

tion and see Table 2 for examples:

Compensation Component Values

In order to achieve standard operations the boost control-

ler requires that proper loop compensation be applied to

the error-amplifier output (COMP pin). The goal of the

compensator design is to achieve the desired closed-loop

bandwidth and sufficient phase margin at the crossover

RSENSE = 200mV/(Max Current)

Power Dissipation: Select a sense resistor that is rated

for the max expected current and power dissipation (watt-

age). The sense resistor’s value might drift if it is allowed

to heat up excessively.

V

DD

Kelvin Sense

For best performance, a Kelvin Sense arrangement is

recommended for sense resistor as shown in Figure 7. In

a Kelvin Sense arrangement, the voltage-sensing nodes

across the sense element are placed such that they mea-

sure the true voltage drop across the sense element and

not any additional excess voltage drop that can occur in

the copper PCB traces or the solder mounting of the sense

element. Routing the differential sense lines along the

same path to the device and keeping the path short also

improves the system performance. The analog differential

current-sense traces should be routed close together to

maximize common-mode rejection.

5µH

B340A-13-F

0Ω

N

FETG

IRLM10060TRPBF

CSIN+

1µF

100mΩ

MAX35104

CSIN

V

P

R

22kΩ

=

Z

Power Transistor

COMP

C

10nF

=

Z

C

470pF

=

P

Use an n-channel MOSFET power transistor with the

MAX35104. To ensure the external n-channel MOSFET

(nFET) is turned on hard, use logic-level or low-threshold

nFETs such that the MAX35104’s internal gate driver’s 2 x

V

supply voltage is sufficient for proper switching oper-

DD

ation. nFETs provide the highest efficiency because they

do not draw any DC gate-drive current. When selecting

Figure 6. Boost Circuits Components

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MAX35104

Gas Flow Meter SoC

an nFET, three important parameters are the total gate

Table 2. RSENSE Example Values

charge (Qg), on-resistance (R

fer capacitance (CRSS).

), and reverse trans-

DS(ON)

LIMIT TRIM

SETTING

(STARTUP

CSIN TRIP

VOLTAGE

(V)

MAX

CURRENT

(A)

RLIM

(Ω)

Qg takes into account all capacitances associated with

charging the gate. Use the typical Qg value for best

results; the maximum value is usually grossly over speci-

fied since it is a guaranteed limit and not the measured

value. The typical total gate charge should be 50nC or

less. With larger numbers, the FETG pins may not be able

to adequately drive the gate.

AND NORMAL)

0

1

2

4

0

1

2

4

0

1

2

4

0

1

2

4

0

1

2

4

0.2

0.4

0.8

1.6

0.2

0.4

0.8

1.6

0.2

0.4

0.8

1.6

0.2

0.4

0.8

1.6

0.2

0.4

0.8

1.6

2

4

0.1

0.25

0.5

1

8

16

0.8

1.6

3.2

6.4

0.4

0.8

1.6

3.2

0.2

0.4

0.8

1.6

0.1

0.2

0.4

0.8

The two most significant losses contributing to the nFET’s

2

power dissipation are I R losses and switching losses.

Select a transistor with low r

minimize these losses.

and low CRSS to

DS(ON)

Determine the maximum required gate-drive current

from the Qg specification in the nFET data sheet. The

MAX35104’s maximum allowed switching frequency is

200kHz, so the maximum current required to charge

the nFET’s gate is f(max) x Qg(typ). Use the typical Qg

number from the transistor data sheet. For example, the

Si9410DY has a Qg(typ) of 17nC (at V

= 5V), there-

GS

fore, the current required to charge the gate is:

IGATE (max) = (300kHz) (17nC) = 5.1mA

The bypass capacitor (C1) on the voltage double pin V2X

must instantaneously furnish the gate charge without

excessive droop (e.g., less than 200mV):

2

∆V2X = Qg/C1

Note: The current must be large enough such that the switcher

can reach its target output voltage (< 1s).

Continuing with the example, ∆V+ = 17nC/0.1μF = 170mV.

Figure 6 uses an IRLM10060TRPBF logic-level nFET with

a guaranteed threshold voltage (V ) of 2.5V.

TH

CURRENT PATH

KELVIN CONNECTIONS

COPPER

TRACE

COPPER

TRACE

SENSE RESISTOR OUTLINE

ROUTE SENSE LINES ALONG

THE SAME PATH

IN+ IN-

Figure 7. Kelvin Sense Connection Layout Example

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MAX35104

Gas Flow Meter SoC

high voltage transducer drivers. The regulator is used

to provide a more stable higher bandwidth source from

which the transducers can be driven. This helps mitigate

any loading mismatches between the two transduc-

ers and provides a more repeatable launch signature

between upstream and downstream measurements, ulti-

mately reducing overall system error.

Inductor (L)

Practical inductor values range from 5μH to 150μH. 56μH

is a good choice for most applications. Larger inductance

values tend to increase the startup time slightly, while

smaller inductance values allow the coil current to ramp

up to higher levels before the over current switch halts

switching, increasing the ripple at light loads. Inductors

with a ferrite core or equivalent are recommended; pow-

der iron cores are not recommended for use with high

switching frequencies. Make sure the inductor’s satura-

tion current rating (the current at which the core begins

to saturate and the inductance starts to fall) exceeds the

The high-voltage linear regulator operates from 5.4V to

27V in programmable 1.7V steps set by the VS[3:0] bits in

the Switcher 1 register. There is an option to not use the

high voltage regulator in the case where it is not desired

and the switcher voltage is deem sufficient to drive the

transducers. Disable the regulator with the HREG_EN bit

in the Switcher 1 register. When disabled the VPR and VP

pins must be externally shorted together.

peak current rating set by R

. For highest efficiency,

SENSE

use a coil with low DC resistance, preferably under 20mΩ.

To minimize radiated noise, use a toroid, a pot core, or a

shielded coil.

When the regulator is enabled, its output is cycled off and

on automatically by the device at the same time as the

boost switcher, see example timing Figure 3.

Diode

The device high switching frequency demands a high-

speed rectifier. Schottky diodes such as the B340A-13-F

are recommended. Make sure the Schottky diode’s aver-

age current rating exceeds the peak current limit set by

Output Capacitor Selection

For stable operation over the full temperature range, use

a low-ESR 1µF (min) 0805 ceramic output capacitor on

the VPR pin. Ceramic capacitors exhibit capacitance

and ESR variations over temperature. Ensure that the

minimum capacitance under worst-case conditions does

not drop below 1µF to ensure output stability. With a 1µF

X7R dielectric, is sufficient at all operation temperatures.

R

, and that its breakdown voltage exceeds V

.

SENSE

OUT

Output Filter Capacitor

The primary criterion for selecting the output filter capaci-

tor is low effective series resistance (ESR). The product of

the peak inductor current and the output filter capacitor’s

ESR determines the amplitude of the ripple seen on the

output voltage. Smaller-value and/or higher- ESR capaci-

tors are acceptable for light loads or in applications that

can tolerate higher output ripple. Since the output filter

capacitor’s ESR affects efficiency, use low-ESR capaci-

tors for best performance.

Transducer Driver

The device has two integrated high voltage full-bridge

transducer drivers, one for the upstream and one for the

downstream transducer as shown in Figure 8. The drivers

direct connect to the transducers without any external

components required. The drivers can also be configured

to drive the transducer in a single-ended manner. Set

the single-ended drive enable bit, SD_EN, in the AFE

1 register. In this configuration, the negative terminal of

the drivers are held at ground and the positive terminal

is modulated between the high-voltage node and ground.

Piezo Driver Regulator

The MAX35104 provides an internal high voltage low

dropout linear regulator. The input to this regulator is the

boost switcher’s output and the output of the regulator

supplies the high side bias used for the CMOS push pull

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MAX35104

Gas Flow Meter SoC

V

HV_REGULATOR

TX_UPP

DOWNSTREAM

TRANSDUCER

DRIVER

V

HV_REGULATOR

TX_UPN

MAX35104

V

HV_REGULATOR

TX_DNP

UPSTREAM

TRANSDUCER

DRIVER

V

HV_REGULATOR

TX_DNN

Figure 8. Piezo Driver Connection

applied to the common mode, providing an additional

level of system accuracy and robustness.

Analog Front-End

The device has a programmable analog front-end used

to condition the return signal before the signal is used

to determine when the stop-hit timing should occur. This

analog front-end consists of two amplifications stages, fol-

lowed by a band pass filter, which feeds into the final com-

parator. The return signal is sampled differentially from

the transducer. The entire AFE operates differentially all

the way to the final comparator. By operating differently,

the receive chain is less susceptible to noise injections

The first stage is a fixed 20dB gain amplifier. An internal

analog switch automatically connects the input of this

amplifier to the appropriate receiving transducer. When

enabled, the input is pulled to VBIAS ~0.7V through 2kΩ

input resistance. The valid input range for the first amplifi-

cation stage, and, therefore, the targeted return amplitude

from the receiving transducer is 1mV to 10mV.

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MAX35104

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The second amplification stage is a programmable gain

amplifier (PGA). The PGA is has a programmable range

from 10 dB to 30dB in 1.33dB steps set by the PGA[3:0]

bits in the AFE 1 register. Figure 9 shows the possible

gain settings and input voltage amplitude combinations.

The ideal input amplitude for the differential stop com-

parator is 350mV and therefore this should be the target

for the output of the AFE. Table 3 shows ideals settings

highlighted in green for all return signal amplitudes.

routine that can be used to select and set the appropriate

center frequency. To use this feature send the BYPASS_

CALIBRATE command and wait until the complete bit is

set. This routine performs the required calibration and

automatically sets the F0 Adjust settings, bits F0[6:0] in

the AFE 2 register to the correct value.

The bandpass filter can be bypassed as shown in

Figure 9 by enabling the BP_BP bit in the AFE1 register.

If the internal analog front-end is not required it can be

completely bypassed by externally shorting the RNX/RXP

pins to the CIN/CIP pins as shown in Figure 9 and setting

the AFE_BYPASS bit in the AFE1 register. This allows for

an external AFE to be constructed with external compo-

nents. The CIN/CIP pins can also be used to output each

stage of the AFE by setting the AFEOUT[1:0] bits in the

AFE 2 register.

The bandpass filter is a 2-pole bandpass filter with pro-

grammable Q and center frequency. The Q of the filter

can be adjusted with four programmable options in the

range for 4.2 to 12 (Hz/Hz) set by the LOWQ[1:0] bits in

the AFE 1 register. The center frequency is programmable

from 125kHz to 500kHz in 3kHz steps set by the F0[6:0]

bits in the AFE 2 register. The MAX35104 provides an

integrated and automated center-frequency calibration

HARDWIRE

AFE BYPASS*

CIN CIP

RXN RXP

CMP_OUT/UP_DN

AFE OUTPUT SELECT BITS

MAX35104

AFE_BYPASS

BIT

BP BYPASS

SELECT BIT

TUNABLE BPF

125kHz TO

500kHz

TIME-TO-

DIGITAL

CONVERTER

TX_UPN

TX_UPP

10 dB

TO 30

dB

PGM OFFSET

COMPARATOR

FIXED

20 dB

TX_DNN

TX_DNP

TUNABLE Q

* USED TO BYPASS INTERNAL AFE

OR

4 TO 12 (Hz/Hz)

RECEIVE

TRANSDUCER SELECT

TO IMPLEMENT A DIFFERENT

FILTERING ARCHITECTURE

BP BYPASS

Figure 9. Analog Front-End

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Table 3. Example Gain Settings

TRANSDUCER RECEIVE SIGNAL (V)

0.001

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.11

0.13

0.15

0.17

0.20

0.23

0.27

0.31

0.002

0.06

0.07

0.09

0.10

0.12

0.14

0.16

0.18

0.22

0.25

0.29

0.34

0.40

0.46

0.54

0.63

0.003

0.09

0.11

0.13

0.15

0.17

0.20

0.24

0.28

0.32

0.38

0.44

0.51

0.60

0.69

0.81

0.94

0.004

0.13

0.15

0.17

0.20

0.23

0.27

0.32

0.37

0.43

0.50

0.58

0.68

0.79

0.93

1.08

1.26

0.005

0.16

0.18

0.22

0.25

0.29

0.34

0.40

0.46

0.54

0.63

0.73

0.85

0.99

1.16

1.35

1.57

0.006

0.19

0.22

0.26

0.30

0.35

0.41

0.48

0.55

0.65

0.75

0.88

1.02

1.19

1.39

1.62

1.89

0.007

0.22

0.26

0.30

0.35

0.41

0.48

0.56

0.65

0.75

0.88

1.02

1.19

1.39

1.62

1.89

2.20

0.008

0.25

0.30

0.34

0.40

0.47

0.54

0.63

0.74

0.86

1.00

1.17

1.36

1.59

1.85

2.16

2.52

0.009

0.28

0.33

0.39

0.45

0.52

0.61

0.71

0.83

0.97

1.13

1.32

1.53

1.79

2.08

2.43

2.83

0.01

0.32

0.37

0.43

0.50

0.58

0.68

0.79

0.92

1.08

1.26

1.46

1.70

1.99

2.32

2.70

3.14

3.16

3.69

4.3

5.01

5.83

6.8

7.93

9.24

10.76

12.55

14.62

17.04

19.86

23.15

26.98

31.44

an approximation to the TDC converter. During the real

measurement, the TDC can then optimize its measure-

ment parameters to use power efficiently. These evalu-

ate cycles are automatically inserted. The time from the

start of one port’s temperature measurement to the next

port’s temperature measurement is set using with the

PORTCYC[1:0] bits in the Event Timing 2 register.

Temperature Measurement Operations

A temperature measurement is a time measurement of

the RC circuit connected to the temperature port device

pins T1, T2, and TC. The TC device pin has a driver to

charge the timing capacitor.

Figure 6 depicts a 10kΩ NTC thermistor with a 10nF NPO

COG 30ppm/°C capacitor. It shows two dummy cycles

with two temperature port-evaluation measurements and

two real temperature port measurements.

Once all the temperature measurements are completed,

the times measured for each port are reported in the cor-

responding TxInt and TxFrac Results registers. The TE bit

in the Interrupt Status register is also set and the INT pin

is asserted (if enabled).

The Dummy 1 and Dummy 2 cycles represent preamble

measurements that are intended to eliminate the dielectric

absorption of the temperature measurement capacitor.

These Dummy cycles are executed using a thermistor

Emulation resistor of 1000 Ohms internal to the device.

This Dummy path allows the dielectric absorption effects

of the capacitor to be eliminated without causing the

thermistor to be unduly self-heated. The number of

Dummy measurements to be taken ranges from 0 to 7.

This parameter is configured by setting the PRECYC[2:0]

bits in the Event Timing 2 register.

Actual temperature is determined by a ratio-metric calcu-

lation. If T2 is connected to a thermistor and T1 is con-

nected to the reference resistor (as shown in the System

Diagram), then the ratio of T2/T1 = R

/R

..

THERMISTOR REF

The ratio R

/R

. can be determined by the

THERMISTOR REF

host microprocessor and the temperature can be derived

from a lookup table of Temperature vs. Resistance for the

thermistor utilizing interpolation of table entries if required.

Temperature Error Handling

Following the dummy cycles, an evaluation, TXevaluate,

is performed. This measurement allows the device to

maximize power efficiency by evaluating the temperature

of the thermistor with a coarse measurement prior to a

real measurement. The coarse measurement provides

The temperature measurement unit can detect open and/

or short circuit temperature probes. If the resultant tem-

perature reading in less than 8µs, then the device writes

a value of 0000h to the corresponding Results registers to

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MAX35104

Gas Flow Meter SoC

●

EVTMG2: Performs automatic TOF_DIFF measure-

ments. The parameters and operation of the TOF

measurement are described in the Time-of-Flight

Measurement section.

Table 4. Randomizer Sampling

TDF

MINIMUM

MAXIMUM

LSB

FREQUENCY NEXT SAMPLE NEXT SAMPLE WEIGHT

(Hz)

PERIOD (S)

(S)

EVTMG3: Performs automatic Temperature

measurements. The parameters and operation of the

Temperature measurements are described in

the Temperature Measurement section.

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

5.50

6.00

6.50

7.00

7.50

8.00

0.082

0.084

0.086

0.088

0.090

0.092

0.094

0.096

0.098

0.100

0.101

0.103

0.105

0.107

0.109

0.111

1.00

2.00

2.0E-3

3.9E-3

2.99

5.9E-3

EVTMG1: Performs automatic TOF_DIFF and

Temperature measurements.

3.99

7.8E-3

4.99

9.8E-3

Continuous Event Timing Operation

5.99

11.7E-3

13.7E-3

15.6E-3

17.6E-3

19.5E-3

21.5E-3

23.4E-3

25.4E-3

27.3E-3

29.3E-3

31.3E-3

The device can be configured to continue running Event

Timing sequences at the completion of any sequence. If

the ET_CONT bit in the Calibration and Control register

is set, the currently executing EVTMGx command con-

tinues to execute until a HALT command is received by

the device. If the ET_CONT bit is clear, automatic execu-

tion of Event Timing stops after the completion of a full

sequence of measurements.

6.99

7.98

8.98

9.98

10.98

11.98

12.97

13.97

14.97

15.97

Continuous Interrupt Timing Operation

When operating in Event Timing Mode, the INT pin

can be asserted (if enabled) either after each TOF or

Temperature measurement, or at the completion of the

sequence of measurements. If the CONT_INT bit in the

Calibration and Control register is set to a 1, then the INT

pin is asserted (if enabled) at the completion of each TOF

or Temperature command. This allows the host micro-

controller to interrogate the current Event for accuracy of

measurement. If the CONT_INT bit is set to a 0, then the

INT pin is only asserted (if enabled) at the completion of

a sequence of measurements. This allows the host micro-

controller to remain in a low-power sleep mode and only

wake-up upon the assertion of the INT pin.

indicate a short circuit temperature probe. If the measure-

ment process does not discharge the TC pin below the

threshold of the internal temperature comparator within

2µs of the time set by the PORTCYC[1:0] bits in the Event

Timing 2 register, then an open circuit temperature probe

error is declared. The MAX35104 writes a value of FFFFh

to the corresponding results registers to indicate an open

circuit temperature probe, the TO bit in the Interrupt Status

register is set, and the INT pin is asserted (if enabled). If

the temperature measurement error is caused by any

other problems, then the device writes a value of FFFFh

to each of the temperature port results registers indicating

that all the temperature port measurements are invalid.

TOF Sample Randomizer

The device has the ability to randomize the TOF samples

when operating in event timing mode, given a sample fre-

quency as selected by the TDF[3:0] bits, the subsequent

samples in the sequence occur at a period ±(1/F) from the

previous sample.

Event Timing Operation

The Event Timing mode of operation is an advanced

feature that allows the user to configure the device to

perform automatic measurement cycles. This allows

the host microcontroller to enter low power mode and

only awaken upon assertion of the INT pin (if enabled)

when new measurement data is available. By using the

TOF_DIFF and Temperature commands and configur-

ing the appropriate TOFx registers and the Event Timing

registers, the Event Timing Modes directs the device to

provide complete data for a sequence of measurements

captured on a cyclical basis. There are three versions of

the EVTMG commands.

This is accomplished using a 9-bit linear feedback shift

register (LFSR) to randomize the internals between suc-

cessive samples. The feedback polynomial implemented

9

5

for the LFSR is x + X + 1.

For example, if TDF[3:0] is set to 0, which is a sample fre-

quency of 0.5s and an event timing mode is initiated, the

first sample occurs 0.5s after that start. The subsequent

samples occur at a time between 0.082s and 1s after the

start of the previous sample, and so on. The times are

start-to-start times.

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MAX35104

Gas Flow Meter SoC

COUNT BEGINS

DRIVER TO CHARGE TC-

CONNECTED CAPACITOR

COUNT ENDS

VDD

3.0

2.0

1.2

1.0

T2

DUMMY 1

DUMMY 2

T1 EVALUATE

T2 EVALUATE

T1

0

256

128

384

512

640

768

SCHMITT

TRIGGER

THRESHOLD

PORTCYCLE TIME SET TO 128µs

DUMMY MEASUREMENTS SET TO 2

TIME (µs)

Figure 10. Temperature Command Execution Cycle Example

measurements. In addition, the Temperature Average

Results registers, TxAVG, are not updated with the error

measurement if a temperature error occurs during Event

Timing Operation.

Error Handling During Event Timing Operation

During execution of Event Timing modes, any error that

occurs during a TOF_DIFF or Temperature measurement

are handled as described in the corresponding error

handling sections. Calibration can also be executed dur-

ing Event Timing operation, if programmed to do so with

the Calibration Configuration bits in the Calibration and

Control register. If a Calibration error occurs, this is han-

dled as described in the Error Handling during Calibration

section. If any of these errors occur, the Event Timing

operation does not terminate, but continues operation.

Event Timing Mode 2

The EVTMG2 command execution causes the TOF_DIFF

command to be executed automatically with program-

mable repetition rates and programmable total counts as

shown in Figure 11.

During execution of the EVTMG2 command, each TOF_

DIFF command execution cycle causes the device to

compute a TOF_DIFF measurement (AVGUP register

minus AVGDN register) as well as the running average of

TOF_DIFF measurements (TOFF_DIFF_AVG register).

The setting of the TDF[3:0] bits in the Event Timing 1 reg-

ister selects the rate at which TOF_DIFF commands are

executed. The setting of the TDM[4:0] bits in the Event

Timing 1 register determines the number of TOF_DIFF

measurements to be taken during the sequence.

When making TOF measurements in Event Timing Mode,

the device provides additional data in the TOF_Cycle_

Count/TOF_Range register that can be used to check

the validity of all the TOF measurements. The TOF_

Cycle_Count is the number of valid error-free TOF mea-

surements that were recorded during an Event Timing

Sequence. If a TOF error occurs, the TOF_Cycle_Count

register is not incremented. The TOF_Range is the range

of all valid TOF measurements that were captured during

a sequence.

Once all the TOF_DIFF measurements in the sequence

are captured, the TOF_DIFF_AVG register contains the

average of the differences of the resultant AVGDN and

AVGUP Results register content of each TOF_DIFF

measurement. After the TOF_DIFF_AVG registers are

updated, the TOF_EVTMG bit is set in the Interrupt Status

register and the INT pin is asserted (if enabled).

When making temperature measurements in Event

Timing Mode, the device provides additional data in the

Temp_Cycle_Count register. This count increments after

every valid error-free temperature measurement and

can be used to check the validity of all the temperature

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MAX35104

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EVTMG2

COMMAND

TIME OF FLIGHT EVENT

HOST MICROCONTROLLER USE OF EVTMG2

TIME OF FLIGHT EVENT

START

PROGRAM TOF

DIFFERENCE

MEASUREMENT

GET CONFIGURATION

REGISTER DATA

PROGRAMMABLE IN

0.5 SECOND STEPS

UP TO 8 SECONDS

FREQUENCY

(8XS/TDF3-TDF0)

(EG. EVERY 2 SECONDS)

START TIMER

PROGRAM NUMBER OF TOF

DIFFERENCE

MEASUREMENTS

(TDM4-TDM0) TO BE TAKEN

(EG. 15)

NO

IS TIMER > = NEXT

8XS/TDF3-TDF0

INCREMENT?

UP TO 32

MEASUREMENTS CAN

BE TAKEN

ASSERT THE INT

DEVICE PIN

YES

PERFORM TOF_DIFF

COMMAND

CONFIGURE REMAINING

MAX35104 REGISTERS

INCLUDING THE CONT_INT

AND ET_CONT BITS

YES

IS TIMER > = NEXT

8XS/TDF3-TDF0

INCREMENT?

NO

SEND THE EVTMG2

COMMAND

COMPUTE RUNNING

AVG FOR TOF_DIFF

MEASUREMENTS AND

STORE AT

SEE ERROR

HANDLING

DESCRIPTION

TOF_DIFF_AVG

WAIT FOR ASSERTION OF

INT DEVICE PIN

INCREMENT

TOF_CYCLE_COUNT

SETTING CONT_INT

ALLOWS HOST

READ INTERRUPT STATUS

REGISTER

MICROCONTROLLER

TO INTERROGATE

MAX35104 AFTER

EACH MEASUREMENT

CYCLE

INCREMENT

SEQUENCE CYCLE

COUNTER

NO

IS TOF_EVTMG

BIT SET?

NO

SEQUENCE CYCLE

COUNTER = TDM4-

TDM0 ?

NO

YES

IS THE CONT_INT

BIT SET?

YES

AVERAGE OF 15 TOF

DIFFERENCE

MEASUREMENTS ARE

READY FOR THE

HOST

SET THE

TOF_EVTMG BIT IN

THE INTERRUPT

STATUS REGISTER

READ TOF_DIFF_AVG,

TOF_DIFF, AVGUP,

AVGDN, HITX REGISTERS

FOR TOF DATA

YES

ASSERT THE INT

DEVICE PIN

MICROCONTROLLER

ASSERT THE INT

DEVICE PIN

ASSERT THE INT

DEVICE PIN

SETTING ET_CONT BIT

CAUSES THE

SEQUENCE TO BE

CONTINUOUS

NO

OTHER

PROCESS

IS THE ET_CONT

BIT SET?

YES

IS THE ET_CONT BIT

SET?

NO

YES

END

Figure 11. EVTMG2 Command

Figure 12. EVTMG2 Pseudo Code

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Event Timing Mode 3

Calibration Operation

The EVTMG3 command execution causes the

Temperature command to be executed automatically with

programmable repetition rates and programmable total

counts as shown in Figure 13.

For more accurate results, calibration of the TDC can be

performed. Calibration allows the device to perform a cali-

bration measurement that is based upon the 32.768kHz

crystal, which is the most accurate clock in the system.

This calibration is used when a ceramic oscillator is

used in place of an AT-cut crystal for the 4MHz refer-

ence. The device automatically generates start and stop

signals based upon edges of the 32.768kHz clock. The

number of 32.768kHz clock periods that are used and

then averaged are selected with the CAL_PERIOD[3:0]

bits in the Calibration and Control register. The TDC

measures the number of 4MHz clock pulses that occur

during the 32.768kHz pulses. The measured time of a

32.768kHz clock pulse is reported in the CalibrationInt

and CalibrationFrac Results registers. These results can

then be used as a gain factor for calculating actual Time-

to-Digital converter measurement if the CAL_USE bit in

the Event Timing 2 register is set.

During execution of the EVTMG3 command, each

Temperature command execution cycle computes the

running average of the measurement of each tempera-

ture port. The results are provided in the Tx_AVGInt and

TxAVGFrac Results registers.

The setting of the TMF[5:0] bits in the Event Timing 1

register selects the rate at which Temperature commands

are executed. The setting of the TMM[4:0] bits in the Event

Timing 2 register determines the number of temperature

measurements to be taken during the sequence.

Once all the Temperature measurements in the sequence

are captured, the Tx_AVGInt and TxAVGFrac Results reg-

isters contain the average of all the temperature measure-

ments in the sequence. After these registers are updated,

the Temp_EVTMG bit is set in the Interrupt Status register

and the INT pin is asserted (if enabled).

Following is a description of an example calibration. Each

TDC measurement is a 15-bit fixed-point integer value

concatenated with a 16-bit fractional value binary repre-

sentation of the number of t_4MHz periods that contribute

to the time result, the actual period of t_4MHz needs to

be known. If the CAL_PERIOD[3:0] bits in the Calibration

and Control register are set to 6, then six measurements

of 32.768kHz periods are measured by the TDC and

then averaged. The expected measured value would be

30.5176µs/250ns = 122.0703125 t_4MHz periods. Let

us assume that the 4MHz ceramic resonator is actually

running at 4.02MHz. The TDC measurement unit would

then measure 30.5176µs/248.7562ns = 122.6806641

t_4MHz periods and this result would be returned in the

Calibration Results register. For all TDC measurements, a

gain value of 122.0703125/122.6806641 = 0.995024876

would then be applied.

Event Timing Mode 1

The EVTMG1 command execution causes the TOF_DIFF

command and the Temperature Command to be executed

automatically with programmable repetition rates and pro-

grammable total counts. In essence, both the EVTMG2

and EVTMG3 commands are simultaneously executed in

a synchronous manner.

Setting up the TOF measurements for automatic execu-

tion in Event Timing Mode 1 is identical to setting these up

for execution with Event Timing Mode 2. Likewise, setting

up the Temperature Measurements is identical to setting

these up for execution using Event Timing Mode 3.

If the TOF_DIF command repetition rate and the

Temperature command repetition rate cause both mea-

surements to be required at the same time, the TOFF_DIF

command takes precedent. Upon completion of the

TOFF_DIFF command, the pending Temperature com-

mand is executed, as shown in Figure 15.

Calibration is performed at the following events:

●

When the Calibration command is sent to the

MAX35104. At the completion of this calibration, the

CAL bit in the Interrupt Status register and the INT

pin is asserted (if enabled).

Once all the TOF_DIFF measurements in the sequence

are complete, the TOF_EVTMG bit in the Interrupt

Status register is set and the INT pin asserts (if enabled).

Likewise, when all the Temperature measurements in the

sequence are completed, the Temp_EVTMG bit in the

Interrupt Status register is set and the INT pin is asserted

(if enabled). It should be noted that depending upon the

selected rates and number of cycles, the TOF_DIFF and

Temperature measurements can complete their sequenc-

es at different times. This causes the INT pin to be assert-

ed (if enabled) before both sequences are complete.

●

During Event Timing Operation, automatic calibra-

tions can be performed before executing TOF or

Temperature measurements. This is selectable with

the CAL_CFG[2:0] bits in the Event Timing 2 register.

Upon completion of an automatic calibration during

Event Timing, the result is updated in the Calibration

Results register, but the CAL bit in the Interrupt Sta-

tus register is not set and the INT pin is not asserted.

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EVTMG3

COMMAND

TEMPERATURE EVENT

HOST MICROCONTROLLER USE OF EVTMG3

TEMPERATURE EVENT

START

PROGRAM TEMPERATURE

GET CONFIGURATION

REGISTER DATA

DIFFERENCE

MEASUREMENT

PROGRAMMABLE IN

1 SECOND STEPS

UP TO 64 SECONDS

FREQUENCY

(8XS/TDF5-TDF0)

(EG. EVERY 15 SECONDS)

START TIMER

TEMPERATURE

MEASUREMENT

REPETITION RATE

PROGRAM NUMBER OF

TEMPERATURE

NO

IS TIMER > = NEXT

8XS/TDF5-TDF0

INCREMENT?

UP TO 32

MEASUREMENTS CAN

BE TAKEN

DIFFERENCE

MEASUREMENTS

(TDM4-TDM0) TO BE TAKEN

(EG. 2)

YES

PERFORM

TEMPERATURE

COMMAND

CONFIGURE REMAINING

MAX35104 REGISTERS

INCLUDING THE CONT_INT

AND ET_CONT BITS

YES

TEMPERATURE

COMMAND ERROR ?

NO

COMPUTE RUNNING

AVG FOR EACH

MEASURED PORT

AND STORE AT

T1_AVG, T2_AVG,

T3_AVG, T4_AVG

REGISERS

SEND THE EVTMG3

COMMAND

SEE ERROR

HANDLING

DESCRIPTION

WAIT FOR ASSERTION OF

INT DEVICE PIN

SETTING CONT_INT

ALLOWS HOST

INCREMENT

TEMP_CYCLE_COUNT

RESULTS REGISTER

MICROCONTROLLER

TO INTERROGATE

MAX35104 AFTER

EACH MEASUREMENT

CYCLE

READ INTERRUPT STATUS

REGISTER

INCREMENT

SEQUENCE CYCLE

COUNTER

NO

IS TEMP_EVTMG

BIT SET?

NO

SEQUENCE CYCLE

COUNTER = TDM4-

TDM0 ?

IS THE CONT_INT

BIT SET?

YES

ACCUMULATION OF

TWO TEMPERATURE

MEASUREMENTS ARE

READY FOR THE

HOST

SET THE

TE BIT IN THE

INTERRUPT STATUS

REGISTER

TOF_EVTMG BIT IN

THE INTERRUPT

STATUS REGISTER

READ THE TXINT, TXFRAC,

TX_AVGINT, TX_AVGFRAC

REGISTERS FOR

TEMPERATURE DATA

MICROCONTROLLER

ASSERT THE INT

DEVICE PIN

ASSERT THE INT

DEVICE PIN

SETTING ET_CONT BIT

CAUSES THE

SEQUENCE TO BE

CONTINUOUS

NO

OTHER

PROCESS

IS THE ET_CONT

BIT SET?

YES

IS THE ET_CONT BIT

SET?

NO

YES

END

Figure 13. EVTMG3 Command

Figure 14. EVTMG3 Pseudo Code

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Error Handling during Calibration

HOST MICROCONTROLLER USE OF EVTMG1

TIME OF FLIGHT / TEMPERATURE EVENT

Since calibration can be set to be automatic by configur-

ing the CAL_CFG[2:0] bits in the Event Timing 2 register,

any errors that occur during the Calibrate command stop

the CalibrationInt and the CalibrationFrac Results regis-

ters from being updated with new calibration coefficients.

The results for the previous Calibration data remain in

these two registers and be used for scaling measured

results. If the calibration error is caused by the internal

calibration time measurement exceeding the time set

by the TIMOUT[2:0] bits in the TOF2 register, the TO bit

in the Interrupt Status register is set and the INT pin is

asserted (if enabled).

PROGRAM TOF

DIFFERENCE

MEASUREMENT

FREQUENCY

(8XS/TDF3-TDF0)

(EG. EVERY 2 SECONDS)

PROGRAMMABLE IN

0.5 SECOND STEPS

UP TO 8 SECONDS

PROGRAM NUMBER OF TOF

DIFFERENCE

MEASUREMENTS

(TDM4-TDM0) TO BE TAKEN

(EG. 2)

UP TO 32

MEASUREMENTS CAN

BE TAKEN

PROGRAM TEMPERATURE

MEASUREMENT FREQUENCY

(8XS/TMF5-TMF0)

PROGRAMMABLE IN

1 SECOND STEPS

UP TO 64 SECONDS

(EG. EVERY 15 SECONDS)

RTC, Alarm, Watchdog, and Tamper Operation

RTC Operation

PROGRAM # OF

TEMPERATURE

MEASUREMENTS

(TMM4-TMM0) TO BE TAKEN

(EG. 2)

UP TO 32

MEASUREMENTS CAN

BE TAKEN

The device contains a real-time clock (RTC) that is driven

by the 32kHz oscillator. The time and calendar informa-

tion is obtained by reading the appropriate register words.

The time and calendar are set or initialized by writing the

appropriate register words. The contents of the time and

calendar registers are in the binary-coded decimal (BCD)

format. The clock/calendar provides hundredths of sec-

onds, tenths of seconds, seconds, minutes, hours, day,

date, month, and year information. The date at the end

of the month is automatically adjusted for months with

fewer than 31 days, including corrections for leap year

valid up to 2100. The clock operates in either the 24-hour

or the 12-hour format with AM/PM indicator. The device’s

RTC can be programmed for either 12-hour or 24-hour

formats. If using the 24-hour format, Bit6 (12 HR MODE)

of the Mins_Hrs register should be cleared to 0 and then

Bit5 represents the 20-hour indicator. If using the 12-hour

format, Bit6 should be set to 1 and Bit5 represents AM

(if 0) or PM (if 1). The day-of-week register increments

at midnight. Values that correspond to the day of week

are user defined but must be sequential (i.e., if 0 equals

Sunday, then 1 equals Monday, and so on). Illogical time

and date entries result in undefined operation.

CONFIGURE REMAINING

MAX35104 REGISTERS

INCLUDING THE CONT_INT

AND ET_CONT BITS

SEND THE EVTMG3

COMMAND

WAIT FOR ASSERTION OF

INT DEVICE PIN

AVERAGE OF 15 TOF

DIFFERENCE

MEASUREMENTS ARE

READY FOR THE HOST

MICROCONTROLLER

READ INTERRUPT STATUS

REGISTER

READ TOF_DIFF_AVG,

TOF_DIFF, AVGUP,

AVGDN, HITX REGISTERS

FOR TOF DATA

IS TEMP_EVTMG

BIT SET?

NO

IS TEMP_EVTMG

BIT SET?

Alarm Operation

YES

AVERAGE OF TWO

TEMPERATURE

MEASUREMENTS ARE

READY FOR THE

HOST

The device’s RTC provides one programmable alarm.

The alarm is activated when either the AM1 or AM2 bits in

the Real-Time Clock register are set. Based upon these

bits, an alarm can occur when either the minutes and/or

hours programmed in the Alarm register match the current

value in the Mins_Hrs register. When an Alarm occurs, the

AF bit in the Interrupt Status register is set and the INT

device pin is asserted (if enabled).

READ THE TXINT, TXFRAC,

TX_AVGINT, TX_AVGFRAC

REGISTERS FOR

TEMPERATURE DATA

MICROCONTROLLER

NO

OTHER

PROCESS

IS THE ET_CONT

BIT SET?

YES

Figure 15. EVTMG1 Pseudo Code

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EVTMG1

TIME OF FLIGHT / TEMPERATURE COMMAND

START

START TIMER

GET CONFIGURATION REGISTER DATA

TOF_DIFF

MEASUREMENT

REPETITION

RATE

YES

IS TIMER > = NEXT

8XS/TDF3-TDF0

INCREMENT?

SET

TOF_PENDING

NO

TEMPERATURE

MEASUREMENT

REPETITION RATE

SET

IS TIMER > = NEXT

8XS/TMF5–TMF0

INCREMENT?

TEMPERATURE_

PENDING

NO

IS TOF_PENDING SET?

NO

IS

NO

PERFORM TOF_DIFF

COMMAND

TEMPERATURE_

PENDING SET?

YES

TOF_DIFF

COMMAND ERROR?

CLEAR

TEMPERATURE_

PENDING

PERFORM

TEMPERATURE

COMMAND

CLEAR

TOF_PENDING

NO

COMPUTE RUNNING

AVG FOR TOF_DIFF

MEASUREMENTS AND

STORE AT

YES

SEE ERROR

HANDLING

DESCRIPTION

TEMPERATURE

COMMAND ERROR?

SETTING CONT_INT

ALLOWS HOST

TOF_DIFF_AVG

MICROCONTROLLER

TO INTERROGATE

MAX35104 AFTER

EACH MEASUREMENT

CYCLE

NO

INCREMENT

TOF_CYCLE_COUNT

COMPUTE RUNNING

AVG FOR EACH

MEASURED PORT

AND STORE AT

T1_AVG, T2_AVG,

T3_AVG, T4_AVG

REGISERS

SEE ERROR HANDLING

DESCRIPTION

INCREMENT

SEQUENCE CYCLE

COUNTER

SETTING

CONT_INT

ALLOWS HOST

MICROCONTROLL

ER TO

INCREMENT

TEMPERATURE

CYCLE COUNTER

NO

SEQUENCE CYCLE

COUNTER = TDM4–

TDM0?

IS THE CONT_INT

BIT SET?

INTERROGATE

MAX35104 AFTER

EACH

MEASUREMENT

CYCLE

INCREMENT

SEQUENCE CYCLE

COUNTER

YES

SET THE

TOF BIT IN THE

INTERRUPT STATUS

REGISTER

TOF_EVTMG BIT IN

THE INTERRUPT

STATUS REGISTER

NO

SEQUENCE CYCLE

COUNTER = TMM4-

TMM0?

IS THE CONT_INT

BIT SET?

IS

YES

TEMPERATURE_PEND

ING SET?

TEMPERATURE_

PENDING SET?

SET THE

BIT IN THE INTERRUPT

STATUS REGISTER

TEMP_EVTMG BIT IN

THE INTERRUPT

STATUS REGISTER

NO

SETTING ET_CONT BIT

CAUSES THE

SEQUENCE TO BE

CONTINUOUS

ASSERT THE INT

DEVICE PIN

ASSERT THE INT

DEVICE PIN

ASSERT THE INT

DEVICE PIN

ASSERT THE INT

DEVICE PIN

YES

IS THE ET_CONT BIT

SET?

IS THE ET_CONT BIT

SET?

NO

END

Figure 16. EVTMG1 Command

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For proper alarm function, programming of the ALARM

register HOURS bits must match the format (12- or

24-hour modes) used in the Mins_Hrs register.

real-time events being performed by the MAX35104.

Upon completion of any command, the device alerts the

host microprocessor using the INT pin. The assertion of

the INT pin can be used to awaken the host microproces-

sor from its low-power mode. Upon receiving an interrupt

on the INT pin, the host microprocessor should read the

Interrupt Status register to determine which tasks were

completed.

Watchdog Operation

The device also contains a watchdog alarm. The Watchdog

Alarm Counter register is a 16-bit BCD counter that is pro-

grammable in 10ms intervals from 0.01 to 99.99 seconds.

A seed value can be written to this register representing

the start value for the countdown. The watchdog counter

begins decrementing when the WD_EN bit in the RTC

register is set.

Interrupt Status Register

The interrupt status register contains flags for all for all

commands and events that occur within the MAX35104.

These flags are set when the event occurs or at the

completion of the executing command. When the Interrupt

Status Register is read, all asserted bits are cleared. If

another interrupt source has generated an interrupt during

the read, these new flags are asserted following the read.

An immediate read of Watchdog Alarm Counter returns

the value just written. A read after a “wait” duration causes

a value “seed” minus “wait” to be returned. For example

if the seed value was 28.01 seconds, an immediate read

returns 28.01. A read after a 4 seconds returns 24.01 sec-

onds. The value read out for any read operation is a snap-

shot obtained at the instant of a serial read operation.

INT Pin

The device’s INT pin is asserted when any of the bits in

the Interrupt Status register are set. The INT pin remains

asserted until the Interrupt Status register is read by the

user and all bits in this register are clear. For the INT pin

to operate, it must first be enabled by setting the INT_EN

bit in the Calibration and Control register.

A write operation to the Watchdog Alarm Counter causes a

re-load with the newly written seed. When the Watchdog is

enabled and a non-zero value is written into the Watchdog

Alarm Counter, the Watchdog Alarm Counter decrements

every 1/100 second, until it reaches zero. At this point, the

WF bit in the Real Time Clock register is set and the WDO

pin is asserted low for a minimum of 150ms. At the end of

the pulse, the WDO pin becomes high impedance.

Serial Peripheral Interface Operation

Four pins are used for SPI-compatible communications:

DOUT (serial-data out), DIN (serial-data in), CE (chip

enable), and SCK (serial clock). DIN and DOUT are

the serial data input and output pins for the devices,

respectively. The CE input initiates and terminates a data

transfer. SCK synchronizes data movement between the

master (microcontroller) and the slave (MAX35104). The

SCK, which is generated by the microcontroller, is active

only when CE is low and during opcode and data transfer

to any device on the SPI bus. The inactive clock polarity

is logic-low. DIN is latched on the falling edge of SCK.

There is one clock for each bit transferred. Opcode bits

are transferred in groups of eight, MSB first. Data bits are

transferred in groups of 16, MSB first.

The WF flag remains set until cleared by writing WF to

a logic 0 in the Real-Time Clock register. If the WF bit is

cleared while the WDO device pin is being held low, the

WDO device pin is immediately released to its high-imped-

ance state. Writing a seed value of 0 does not cause the

WF bit to be asserted.

Tamper Detect Operation

The device provides a single input that can be connected

to a device case switch and used for tamper detection.

Upon detection of a case switch event the CSWA in

the Control Register and the CSWI bit in the Interrupt

Status register is set and the INT device pin is asserted

(if enabled).

The SPI is used to access the features and memory of the

MAX35104 using an opcode/command structure.

Device Interrupt Operations

The device is designed to optimize the power efficiency

of a flow metering application by allowing the host micro-

processor to remain in a low power sleep mode, instead

of requiring the microprocessor to keep track of complex

Opcode Commands

The MAX35104 supports the opcode/commands shown

in Table 5.

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Table 5. Opcode Commands

GROUP

COMMAND

OPCODE FIELD (HEX)

EXECUTION OPCODE COMMANDS

TOF_Up

00h

01h

02h

03h

04h

06h

07h

08h

09h

0Ah

0Eh

CE

TOF_Down

TOF_Diﬀ

0

1

2

3

4

5

6

7

Temperature

Reset

SCK

DIN

Execution

Opcode

Bandpass_Calibrate

EVTMG1

Commands

O

EVTMG2

LSB

MSB

8 BITS

EVTMG3

HALT

OPCODE

HIGH IMPEDANCE

Calibrate

DOUT

94h–97h, B0h–FFh

Each hex value

represents the location

of a single 16-bit

register.

Figure 17. Execution Opcode Command Protocol

Read Register

Write Register

Register

Opcode

Commands

Note: The TOF_UP command yields absolute time of

flight results that include circuit delays.

14h–17h, 30h–43h Each

hex value

represents the location

of a single 16-bit

register.

TOF_Down Command (01h)

The TOF_DOWN command generates a single TOF

measurement in the downstream direction. Pulses are

launched from the TX_DNP and TX_DNN pins and

received by TX_UPP and TX_UPN pins. The measured

hit results are reported in the HITxDnInt and HITxDnFrac

registers, with the calculated average of all the measured

hits being reported in the AVGDNInt and AVGDNFrac

Execution Opcode Commands

The device supports several single byte opcode com-

mands, which cause the MAX35104 to execute various

routines. All commands have the same SPI protocol

sequence as shown in Figure 17. Once all 8 bits of the

opcode are received by the MAX35104 and the CE

device pin is deasserted, the device begins execution of

the specified command as described in that Command’s

description.

register. The t /t and t /t

wave ratios are reported

1 2

2 IDEAL

in the WVRDN register. Once all these results are stored,

the TOF bit in the Interrupt Status register is set and the

INT pin is asserted (if enabled).

Note: The TOF_Down command yields absolute time of

flight results that include circuit delays.

TOF_DIFF Command (02h)

TOF_UP Command (00h)

The TOF_DIFF command performs back-to-back TOF_

UP and TOF_DN measurements as required for a meter-

ing application. The TOF_UP sequence is followed by the

TOF_DN sequence. The time between the start of the

TOF_UP measurement and the start of the TOF_DN mea-

surement is set by the TOF_CYC[2:0] bits in the TOF2

register. Upon completion of the TOF_DN measurement,

the results of AVGUP minus AVGDN is computed and

stored at the TOF_DIFFInt and TOF_DIFFFrac Results

register locations. Once these results are stored, then the

The TOF_UP command generates a single TOF mea-

surement in the upstream direction. Pulses are launched

from the TX_UPP and TX_UPN pins and received by the

TX_DNP and TX_DNN pins. The measured hit results

are reported in the HITxUPInt and HITxUPFrac regis-

ters, with the calculated average of all the measured hits

being reported in the AVGUPInt and AVGUPFrac register.

The t /t and t2/t

wave ratios are reported in the

1 2

IDEAL

WVRUP register. Once all these results are stored, then

the TOF bit in the Interrupt Status register is set and the

INT pin is asserted (if enabled).

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TOF bit in the Interrupt Status register is set and the INT

EVTMG2 Command (08h)

pin is asserted (if enabled).

The EVTMG2 command initiates the event timing mode

2 advanced automatic measurement feature. This timing

mode performs automatic TOF_DIFF measurements as

described in the Event Timing Operations section. The

duration of the automatic measurements depends upon

the settings in the Event Timing 1 register, CONT_INT

and ET_CONT bits in the Calibration and Control register.

Temperature Command (03h)

The Temperature command initiates a temperature mea-

surement sequence as described in the Temperature

Measurement Operations section. The characteristics the

temperature measurement sequence depends upon the

settings in the Event Timing 1 Register, and Event Timing

2 register. Once all the measurements are completed, the

times measured for each port are reported in the corre-

sponding TxInt and TxFrac Results Registers. The TE bit

in the Interrupt Status register is also set and the INT pin

is asserted (if enabled).

EVTMG3 Command (09h)

The EVTMG3 command initiates the event timing mode

3 advanced automatic measurement feature. This timing

mode performs automatic Temperature measurements as

described in the Event Timing Operations section. The

duration of the automatic measurements depends upon

the settings in the Event Timing 1 register, Event timing 2

register, CONT_INT and ET_CONT bits in the Calibration

and Control register.

Reset Command (04h)

The Reset command essentially performs the same func-

tion as a POR and causes all the Configuration registers to

be set to their POR values and all the Results registers and

the Interrupt Status register to be cleared and set to zero.

HALT Command (0Ah)

The HALT command is sent to the device to stop any

of the three EVTMG1/2/3 commands. All register data

content is frozen and the SPI is then made available for

access by the host microcontroller for commands, mem-

ory access, and register access. The HALT command

takes time to execute. Because the EVTMGx commands

are composed of multiple TOF_DIFF and Temperature

commands, the HALT command causes the device to

evaluate its own state and complete the currently execut-

ing TOF_DIFF or Temperature command. Once the HALT

command has completed, all registers are updated and

the device sets the Halt bit in the Interrupt Status regis-

ter and then asserts the INT device pin (if enabled). The

host microprocessor reads the Interrupt Status register to

determine the interrupt source.

Initialize Command (05h)

The Initialize command recalls POR values for registers

14h–17h.

Bandpass Calibrate Command (06h)

The Bandpass Calibrate command is used to automati-

cally program the bandpass filter’s center frequent. This

command should be run before any TOF commands are

executed (if the bandpass is enabled). To execute this

command, first select the desired launch frequency by

setting the DPL[3:0] bits in the TOF1 register. Upon exe-

cution of this command, the device uses internally gener-

ated signals at the set launch frequency to stimulate the

bandpass filter and selects the correct center frequency

values for the F0 Adjust bits, F0[6:0] in the AFE 2 register.

Calibrate Command (0Eh)

EVTMG1 Command (07h)

The Calibrate command performs the calibration routine

as described in the Calibration Operation section. When

the Calibrate command has completed the measurement,

the Calibration Results register contains the measured

32kHz period measurement value, the device sets the Cal

bit in the Interrupt Status register and then asserts the INT

device pin (if enabled). The host microprocessor reads

the Interrupt Status register to determine the interrupt

source and then reads the Calibration Results register to

calculate the 4MHz ceramic oscillator gain factor.

After issuing the Bandpass Calibrate command, an addi-

tional 5mA ICC current is active until the CE pin is toggled.

Note: The Bandpass Calibrate command is not available

for 1MHz pulse lauch divider setting, DPL[3:0] = 1.

The EVTMG1 command initiates the event timing mode

1 advanced automatic measurement feature. This timing

mode performs automatic TOF_DIFF and Temperature

measurements as described in the Event Timing

Operations section. The duration of the automatic mea-

surements depends upon the settings in the Event Timing

1 Register, Event timing 2 register, CONT_INT and ET_

CONT bits in the Calibration and Control register.

Register Opcode Commands

To manipulate the register memory, there are two com-

mands supported by the device: Read register and Write

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register. Each register accessed with these commands is

16 bits in length. These commands are used to access

all sections of the memory map including the RTC and

Watchdog registers, Configuration registers, Conversion

Results registers, and Status registers. The Conversion

Results registers and the Interrupt Status register of the

Status registers are all read only.

pin is deasserted as shown in Figure 19. The address

counter is automatically incremented.

Write Register Command

This command applies to all writable registers. See the

Register Memory Map for more detail. Figure 20 shows

the SPI protocol sequence.

The Write Register command can also be used to write

consecutive addresses. In this case, the data bits are

continuously received on the DIN device pin and bound

for the initial starting address register that is addressed in

the opcode. The address counter is automatically incre-

mented after each 16 bits of data and wraps around to the

beginning of the Configuration/Results register memory

map if the SCK device pin is continually clocked and the

CE device pin remains asserted as shown in Figure 21.

Read Register Command

The opcode must be clocked into the DIN device pin

before the DOUT device pin produces the register data.

Figure 18 shows the SPI protocol sequence.

The Read Register command can also be used to read

consecutive addresses. In this case, the data bits are

continuously delivered in sequence starting with the MSB

of the data register that is addressed in the opcode, and

continues with each SCK rising edge until the CE device

READ REGISTER COMMAND

CE

0

1

2

3

4

5

6

7

8

9

10

19 20 21 22 23

SCK

DIN

O

MSB

LSB

8 BITS

DATA 16 BITS

OPCODE

D

HIGH IMPEDANCE

DOUT

HIGH IMPEDANCE

MSB

LSB

Figure 18. Read Register Opcode Command Protocol

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CONTINUOUS READ REGISTER COMMAND

CE

SCK

DIN

0

1

2

3

4

5

6

7

8

9

10

19 20 21 22 23

24 25 26 27

39 40 41 42 43

O

MSB

LSB

8 BITS

DATA 16 BITS

OPCODE

DOUT

D

HIGH IMPEDANCE

MSB

LSB MSB

LSB

Figure 19. Continuous Read Register Opcode Command Protocol

WRITE REGISTER COMMAND

CE

0

1

2

3

4

5

6

7

8

9

10

19 20 21 22 23

SCK

O

D

DIN

LSB MSB

LSB

MSB

8 BITS

DATA 16 BITS

OPCODE

DOUT

HIGH IMPEDANCE

Figure 20. Write Register Opcode Command Protocol

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CONTINUOUS WRITE REGISTER COMMAND

CE

0

1

2

3

4

5

6

7

8

9

10

19 20 21 22 23 24 25 26 27

39

SCK

O

D

DIN

LSB MSB

LSB

MSB

8 BITS

DATA 16 BITS

OPCODE

DOUT

HIGH IMPEDANCE

Figure 21. Continuous Write Register Opcode Command Protocol

figuration variables are set to their POR default value. The

RTC, Results, Interrupt Status, and Control registers are

all 0000h following a reset.

Register Memory Map

Table 6 shows the registers that are accessed by the

Read register command and the Write register command.

“X” represents a reserved bit. Following a reset, all con-

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RTC and Watchdog Register Descriptions

Table 7. RTC Seconds Register

RTC SECONDS REGISTER

WRITE OPCODE

30h

READ OPCODE

POR DEFAULT VALUE

0000h

B0h

Bit

15

14

13

12

4

11

3

10

9

8

0

Name

Tenths of Seconds

Hundredths of Seconds

Bit

7

0

6

5

2

1

Name

10 Seconds

Seconds

BIT

NAME

DESCRIPTION

15:12

11:8

7

Tenths of Seconds

Hundredths of Seconds

0

Range 0 to 9

This bit always returns 0

Range 0 to 5

6:4

10 Second

3:0

Seconds

Range 0 to 9

Table 8. RTC Mins_Hrs Register

RTC MINS_HRS REGISTER

WRITE OPCODE

31h

READ OPCODE

POR DEFAULT VALUE

0000h

B1h

Bit

15

0

14

13

12

11

10

2

9

8

0

Name

10 Minutes

Minutes

Hours

Bit

7

0

6

5

4

3

1

Name

12/24

20HR/AM/PM

10HR

BIT

NAME

DESCRIPTION

15

0

This bit always returns 0

Range 0 to 5

14:12

11:8

7

10 Minutes

Minutes

0

Range 0 to 9

This bit always returns 0

1 = 12-Hour Mode

0 = 24-Hour Mode

This bit is write only

6

12/24

In 12-Hour Mode

1 = PM

0 = AM

5

20HR/AM/PM

In 24-Hour Mode: 20 Hour Digit

4

10HR

Hours

3:0

Range 0 to 9

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Table 9. RTC Day_Date Register

RTC DAY_DATE REGISTER

WRITE OPCODE

32h

READ OPCODE

POR DEFAULT VALUE

B2h

0000h

Bit

15

0

14

0

13

0

12

0

11

0

10

9

8

0

Name

Day

Bit

7

0

6

0

5

4

3

2

1

Name

10 Date

Date

BIT

NAME

DESCRIPTION

15:11

10:8

7:6

0

Day

These bits always return 0

Range 0 to 7

0

These bits always return 0

Range 0 to 3

5:4

10 Date

Date

3:0

Range 0 to 9

Table 10. RTC Month_Year Register

RTC MONTH_YEAR REGISTER

WRITE OPCODE

33h

READ OPCODE

POR DEFAULT VALUE

0000h

B3h

Bit

15

0

14

0

13

0

12

11

3

10

9

1

8

0

Name

10 Month

Month

Bit

7

6

5

4

2

Name

10 Year

Year

BIT

NAME

DESCRIPTION

15:13

12

0

These bits always return 0.

10 Month Range 0 to 1

11:8

7:4

Month

10 Year

Year

Range 0 to 9

3:0

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Table 11. Watchdog Alarm Counter Register

WATCHDOG ALARM COUNTER REGISTER

WRITE OPCODE

34h

READ OPCODE

POR DEFAULT VALUE

0000h

B4h

15

14

13

12

4

11

3

10

9

8

0

Bit

Tenths of Seconds

Hundredths of Seconds

Name

7

6

5

2

1

Bit

10 Seconds

Seconds

Name

BIT

NAME

Tenths of Seconds

Hundredths of Seconds

10 Second

DESCRIPTION

15:12

11:8

7:4

Range 0 to 9

3:0

Seconds

Table 12. Alarm Register

ALARM REGISTER

WRITE OPCODE

35h

READ OPCODE

B5h

POR DEFAULT VALUE

0000h

Bit

15

X

14

13

12

11

3

10

9

8

0

Name

10 Minutes

Minutes

Bit

7

6

5

4

2

1

Name

X

12/24

20HR/AM/PM

10HR

Hours

BIT

15

NAME

DESCRIPTION

X

Reserved

14:12

11:8

7

10 Minutes

Minutes

X

Range 0 to 5

Range 0 to 9

Reserved

1 = 12-Hour Mode

0 = 24-Hour Mode

This bit is write only

6

12/24

In 12-Hour Mode

1 = PM

0 = AM

5

20HR/AM/PM

In 24-Hour Mode: 20 Hour Digit

4

10HR

Hours

3:0

Range 0 to 9

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Conﬁguration Register Descriptions

Table 13. Switcher 1 Register

SWITCHER 1 REGISTER

WRITE OPCODE

14h

READ OPCODE

94h

POR VALUE

0030h

Bit

15

14

13

12

11

X

10

X

9

8

Name

SFREQ1

SFREQ0

HREG_D

0

X

Bit

7

6

5

1

4

1

3

2

1

0

Name

DFREQ1

DFREQ0

VS3

VS2

VS1

VS0

BIT

NAME

DESCRIPTION

Switcher Control Frequency: These 2 bits are used to control the switching frequency of the switcher

boost circuit.

SFREQ1

SFREQ0

SWITCHING FREQUENCY (kHz)

SFREQ

[1:0]

0

1

0

1

0

1

100

125

166

200

15:14

High Voltage Regulator Disable: This bit powers down the high voltage regulator in the case where it

is not desired and the switcher voltage is deem suﬃcient to drive the piezos. In such a case, the VPR

and VP pins must be externally shorted together.

13

HREG_D

When set to 0 the high voltage regulator is enabled. When set to 1 it is disabled.

Zero: This bit must always be written to 0b when accessing this register.

WARNING: Writing this bit to a non-zero value causes undesired device operation.

12

0

11:8

X

Reserved

Doubler Control Frequency: These 2 bits are used to control the switching frequency of the doubler

circuit.

DREQ1

DREQ0

SWITCHING FREQUENCY (kHz)

0

1

0

1

0

1

100

125

166

200

7:6

DREQ[1:0]

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Table 13. Switcher 1 Register (continued)

One: These bits must always be written to 11b when accessing this register.

WARNING: Writing these bits to a non-one value causes undesired device operation.

5:4

11

BIT

NAME

DESCRIPTION

Voltage Select: This is a hex value that controls the switcher and high voltage regulator output target

voltage:

DESCRIPTION

VS0[3:0]

MAX FET DUTY CYCLE (%)

REGULATOR

TARGET (V)

SWITCHER

TARGET (V)

LT_50D = 0b

LT_50D = 1b

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

5.4

9

50

60

63

65

68

70

73

78

80

83

85

90

9

5.4

9

5.4

9

5.4

9

7.2

10.8

12.6

15

3:0

VS[3:0]

9

11.4

13.2

15.6

17.4

19.2

21.6

23.4

25.2

27

16.8

19.2

21

22.8

25.2

27

28.8

30.6

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Table 14. Switcher 2 Register

SWITCHER 2 REGISTER

WRITE OPCODE

15h

READ OPCODE

95h

POR VALUE

44E0h

Bit

15

14

13

12

11

10

9

8

Name

LT_N3

LT_N2

LT_N1

LT_N0

LT_S3

LT_S2

LT_S1

LT_S0

Bit

7

6

5

4

3

2

0

1

0

Name

ST3

ST2

ST1

ST0

LD_50D

PECHO

BIT

NAME

DESCRIPTION

Limit trim Normal Operation: After the output voltage crosses the undervoltage good threshold,

which is the programmed voltage select output, the switcher runs in normal duty mode. Four bits

control the max inductor current in normal duty mode. The bits must be set in the one-hot pattern

shown below.

0000b = Loop conditions determine max

0001b = 0.2V/RSENSE = MAX CURRENT

15:12

LT_N[3:0]

0010b = 0.4V/RSENSE = MAX CURRENT

0100b = 0.8V/RSENSE = MAX CURRENT

1000b = 1.6V/RSENSE = MAX CURRENT

Limit trim Startup: During power up, a soft-start must be initiated as the inductor can saturate from

a maxed out duty cycle arising from the large error between target and the output voltage. Four bits

control the max inductor current. The bits must be set in the one-hot pattern shown below.

0000b = No limit

11:8

LT_S[3:0]

0001b = 0.2V/RSENSE = MAX CURRENT

LT_S[3:0]

0010b = 0.4V/RSENSE = MAX CURRENT

0100b = 0.8V/RSENSE = MAX CURRENT

1000b = 1.6V/RSENSE = MAX CURRENT

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Table 14. Switcher 2 Register (continued)

BIT

NAME

DESCRIPTION

Switcher Stabilization Time: This is a hex number that selects the time allotted for the stabilization

of the output voltage of the switcher. This count begins once the under voltage comparator

determines the target output voltage is within the deﬁned speciﬁcations. After the stabilization time

expires the launch pulses are then transmitted.

The time is based upon the 32.768 KHz crystal.

ST[3:0]

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

STABILIZATION TIME

64µs

128µs

192µs

256µs

320µs

7:4

ST[3:0]

384µs

473µs

512µs

768µs

1.02ms

1.25ms

1.50ms

2.05ms

4.10ms

8.19ms

16.4ms

LIMIT TRIM 50% Disable: This bit disables the 50% MAX duty cycle applied to the switcher FET.

When set to 0 the switcher FET’s applied MAX duty cycle will never exceed a 50%

When set to a 1 the switcher FET’s applied MAX duty cycle will dependent upon the settings in the

Launch Voltage Select, VS[3:0], bit ﬁeld in the Switcher 1 Register.

3

2:1

0

LT_50D

0

Zero: These bits must always be written to 00b when accessing this register.

WARNING: Writing these bits to a non-zero value will cause undesired device operation

Pulse Echo enable: This bit enables the pulse echo mode of the device. In pulse echo mode the

launch transducer is also the receive transducer.

When set to 1 the device operates in pulse echo mode.

PECHO

When set to 0 the device operates in normal time of ﬂight mode.

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Table 15. AFE 1 Register

AFE 1 REGISTER

WRITE OPCODE

16h

READ OPCODE

96h

POR VALUE

04Xxh

Bit

15

14

13

0

12

0

11

0

10

9

8

Name

AFE_BP

0

SD_EN

AFEOUT1

AFEOUT0

Bit

7

0

6

5

4

3

2

1

0

Name

WRITE BACK READ VALUES

BIT

NAME

DESCRIPTION

Analog Front-End Bypass: This bit is used to remove the entire analog front-end signal chain,

including both gain stages and the bandpass ﬁlter, from the return signal-chain path.

When set to 1, externally connecting the RXN/RXP pins to the CIN/CIP pins is required.

15

AFE_BP

When set to 0 the return signals are routed to the ﬁrst gain stage of the analog front-end.

Zero: These bits must always be written to 0000b when accessing this register.

WARNING: Writing these bits to a non-zero value will cause undesired device operation

14:11

10

0

Single Ended Drive Enable: This bit enables the transmitted square wave to be driven in a single

ended manner. When set to 0, the transmitted square wave will be driven diﬀerentially.

SD_EN

Analog Front End Output: These bits enable the AFE signals to be output on the CIP/CIN pins

according to the following stage output

AFEOUT1

AFEOUT0

DESCRIPTION

CIP/CIN output disabled

0

1

0

1

0

1

9:8

AFEOUT[1:0]

Route bandpass ﬁlter out

Route programmable gain ampliﬁer out

Route ﬁxed gain ampliﬁer out

Zero: This bit must always be written to 0b when accessing this register.

WARNING: Writing this b it to a non-zero value will cause undesired device operation

7

0

Write Back: This bit ﬁeld must be written back to the initial value that is read from the device after a

POR, before it is modiﬁed. When writing this register a POR read must occur ﬁrst and the value of

these 7 bits must be stored in the host microcontroller. Any future writes to this register must write this

7-bit bit-ﬁeld to the value that was initially read.

6:0

WB

WARNING :Writing these bits to a value that does not match the initial POR read value will cause

undesired device operation

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Table 16. AFE 2 Register

AFE 2 REGISTER

WRITE OPCODE

17h

READ OPCODE

97h

POR VALUE

0000h

15

14

13

12

11

10

9

8

Bit

4M_BP

F06

F05

F04

F03

F02

F01

F00

Name

7

6

5

4

3

2

1

0

Bit

PGA3

NAME

PGA2

PGA1

PGA0

LOWQ1

LOWQ0

BP_BP

Name

BIT

DESCRIPTION

4MHz Bypass: This bit, when set, allows an external CMOS-level 4.0 MHz signal to be applied to the

4MX1 device pin. The internal 4MHz oscillator is bypassed and the external signal is driven into the

device’s core.

15

4M_BP

F0 Adjust: This is a hex value that adjusts the center frequency of the bandpass ﬁlter.

Use the Bandpass Calibrate Command (06h) and the device will automatically select

the best center frequency based upon the selected launch frequency. These bits will

be set automatically by the device.

14:8

F0[6:0]

Gain Select: This is a hex value that selects the gain for the programmable gain ampliﬁer:

AMPLIFIER GAIN

PGA[3:0]

dB

V/V

3.16

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

10

11.33

12.66

13.99

15.32

16.65

17.98

19.31

20.64

21.97

23.30

24.63

25.96

27.29

28.62

29.95

3.69

4.30

5.01

5.83

6.80

7:4

PGA[3:0]

7.93

9.24

10.76

12.55

14.62

17.04

19.86

23.15

26.98

31.44

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Table 16. AFE 2 Register (continued)

BIT

NAME

DESCRIPTION

BPF Q Select: These 2 bits are used to lower the Q factor of the ﬁlter

LOWQ1

LOWQ2

FILTER Q (Hz/Hz)

0

1

0

1

0

1

12

7.4

5.3

4.2

3:2

LOWQ[1:0]

Zero: This bit must always be written to 0b when accessing this register.

WARNING :Writing this bit to a non-zero value will cause undesired device operation

1

0

Bandpass Filter Bypass: This bit is used to remove the tunable bandpass ﬁlter from the return

signal-chain path. When the bandpass ﬁlter is bypassed, the return signals present at the input of the

tunable bandpass ﬁlter are routed directly to programmable oﬀset comparator.

BP_BP

When set to 0 the BPF is used to condition the return signal. When set to 1 the BPF is bypassed.

Table 17. TOF1 Register

TOF1 REGISTER

WRITE OPCODE

38h

READ OPCODE

B8h

POR DEFAULT VALUE

0000h

15

14

13

12

11

10

9

8

Bit

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

Name

7

6

5

4

3

2

1

0

Bit

DPL3

DPL2

DPL1

DPL0

STOP_POL

X

Name

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Table 17. TOF1 Register (continued)

BIT

NAME

DESCRIPTION

Pulse Launcher Size: This is a hex value that deﬁnes the number of pulses that are launched

from the pulse launcher during transmission. The range of this hex value is 00h–FFh. When

PL[7:0] is set to 00h, the Pulse Launcher is disabled. Up to 127 pulses can be launched. When

PL7 is set, the pulse count is clamped at 127.

15:8

PL[7:0]

Pulse Launch Divider: This is a hex value that deﬁnes the divider ratio of the internal clock

signal used to drive the Pulse Launch signal. The 4 MHz external reference oscillator is used

as the source for the internal clock reference. The internal reference clock is ﬁrst divided by

2 to produce a 2MHz clock. The range of this hex value is 1h to Fh, resulting in a range of

division from ÷2 to ÷16 of the 2 MHz clock. A value of 0h is not supported and should not be

programmed.

Pulse Launch Frequency = 2MHz / (1+DPL[3:0])

7:4

DPL[3:0]

0000b

0001b

0002b

. . .

PULSE LAUNCH FREQUENCY

RESERVED

1MHz

666kHz

. . .

1110b

1111b

133.33kHz

125kHz

Stop Polarity: This bit deﬁnes the edge sensitivity of the internal programmable stop

comparator. The comparator generates a stop condition for the internal TDC time count on

the rising slope of the received signal if this bit is set to 0. The comparator generates a stop

condition for the internal TDC time count on the falling slope of the received signal if this bit is

set to 1.

3

STOP_POL

X

2:0

Reserved

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Table 18. TOF2 Register

TOF2 REGISTER

WRITE OPCODE

39h

READ OPCODE

B9h

POR DEFAULT VALUE

0000h

Bit

15

14

13

12

11

10

9

8

Name

STOP2

STOP1

STOP0

T2WV5

T2WV4

T2WV3

T2WV2

T2WV1

Bit

7

6

5

4

3

2

1

0

Name

T2WV0

TOF_CYC2

TOF_CYC1

TOF_CYC0

X

TIMOUT2

TIMOUT1

TIMOUT0

BIT

NAME

DESCRIPTION

Stop Hits: These bits set the number of stop hits to be expected and measured.

STOP2

STOP1

STOP0

DESCRIPTION

1 Hit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2 Hits

3 Hits

15:13

STOP[2:0]

4 Hits

5 Hits

6 Hits

Wave Selector for t :These bits determine the wave number for which t is measured. To ensure

2

measurement accuracy, the ﬁrst wave measurable after the Early Edge Detect is Wave 2. Waves are

numbered as depicted in Figure 5B.

T2WV[5:0] (decimal)

DESCRIPTION

Wave 2

12:7

T2WV[5:0]

0 through 2

3

Wave 3

4

Wave 4

5 through 63

Wave 5 through 63

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Table 18. TOF2 Register (continued)

BIT

NAME

DESCRIPTION

TOF Duty Cycle: These bits determine the time delay between successive executions of TOF

measurements. It is the Start-to-Start time of automatic execution of the TOF_UP and the TOF_DN and

is applicable only for the TOF_DIFF command. It is based upon the 32.768kHz crystal. If the actual TOF

of the acoustic path exceeds the programmed Start-to-Start time in this setting, then the TOF Duty Cycle

performs as if the bit setting is 000b.

DESCRIPTION

TOF_CYC[2:0]

32kHz CLOCK

CYCLES(decimal)

TYPICAL

TIME

4MHz ON BETWEEN TOF_UP

AND TOF_DOWN

TOF_CYC

[2:0]

6:4

000b

001b

010b

011b

100b

101b

110b

111b

0

4

0µs

Yes

No

122µs

244µs

488µs

732µs

976µs

16.65ms

19.97ms

8

16

24

32

546

655

No

3

X

Reserved

Timeout: These bits force a timeout in the Time-To-Digital measurement block. If the hit required

to measure t or Hit1 thru Hit6of the received signal does not occur in this time, the TO bit in the

t

1_,2_,

Interrupt Status register is set and the INT pin is asserted (if enabled). Additionally, any of the Conversion

Results registers read FFFFh if the data for that register is invalid. In addition, if resultant temperature

readings exceed the timeout value set by these bits, then the device writes a value of FFFFh to the

corresponding T1, T2, T3, T4 Results register to indicate an open circuit temperature probe.

TIMOUT2

TIMOUT1

TIMOUT0

DESCRIPTION

128µs

TIMOUT

[2:0]

2:0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

256µs

512µs

1024µs

2048µs

4096µs

8192µs

16384µs

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Table 19. TOF3 Register

TOF3 REGISTER

WRITE OPCODE

3Ah

READ OPCODE

BAh

POR DEFAULT VALUE

0000h

15

X

14

X

13

12

11

10

9

8

Bit

Hit1WV5

Hit1WV4

Hit1WV3

Hit1WV2

Hit1WV1

Hit1WV0

Name

7

6

5

4

3

2

1

0

Bit

X

Hit2WV5

Hit2WV4

Hit2WV3

Hit2WV2

Hit2WV1

Hit2WV0

Name

BIT

15:14

NAME

DESCRIPTION

X

Reserved

Hit1 Wave Select: These bits select the wave number for which the Hit1 stop time is

measured. Wave Numbers are depicted in Figure 5B. The Hit1 Wave Select value must be

at least 1 greater than the Wave Selected for t , which is conﬁgured in the TOF2 register.

2

For example, if the Wave Selector for t is set to wave number 7, then the Hit1 Wave Select

2

must be set to deselect wave number 8 or greater. The earliest wave for which Hit1 can be

measured is Wave 3.

13:8

HIT1WV[5:0]

HIT1WV[5:0] (decimal)

DESCRIPTION

Wave 3

0 to 3

4

5

Wave 4

Wave 5

6 to 63

Wave 6 to 63

7:6

5:0

X

Reserved

Hit2 Wave Select: These bits select the wave number for which the Hit2 stop time is

measured. Wave numbers are depicted in Figure 5B. The Hit2 Wave Select value must be at

least 1 greater than the Hit1 Wave Select value. For example, if Hit1 Wave Select value is set

to measure wave number 9, then the Hit2 Wave Select must be set to detect wave number 10

or greater. The earliest wave for which Hit2 can be measured is Wave 4.

HIT2WV[5:0]

HIT2WV[5:0] (decimal)

DESCRIPTION

Wave 4

0 to 4

5

6

Wave 5

Wave 6

7 to 63

Wave 7 to 63

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Table 20. TOF4 Register

TOF4 REGISTER

WRITE OPCODE

3Bh

READ OPCODE

BBh

POR DEFAULT VALUE

0000h

15

X

14

X

13

12

11

10

9

8

Bit

Hit3WV5

Hit3WV4

Hit3WV3

Hit3WV2

Hit3WV1

Hit3WV0

Name

7

6

5

4

3

2

1

0

Bit

X

Hit4WV5

Hit4WV4

Hit4WV3

Hit4WV2

Hit4WV1

Hit4WV0

Name

BIT

NAME

DESCRIPTION

15:14

13:8

7:6

X

Reserved

Hit3 Wave Select: These bits select the wave number for which the Hit3 stop time is measured.

Wave numbers are depicted in Figure 5B. The Hit3 Wave Select value must be at least 1 greater

than the Hit2 Wave Select value. For example, if the Hit2 Wave Select value is set to measure wave

number 10, then the Hit3 Wave Select must be set to detect wave number 11 or greater. The earliest

wave for which Hit3 can be measured is Wave 5.

HIT3WV

[5:0]

HIT3WV[5:0] (decimal)

DESCRIPTION

Wave 5

0 to 5

6

7

Wave 6

Wave 7

8 to 63

Wave 8 to 63

X

Reserved

Hit4 Wave Select: These bits select the wave number for which the Hit4 stop time is measured.

Wave numbers are depicted in Figure 5B. The Hit4 Wave Select value must be at least 1 greater

than the Hit3 Wave Select value. For example, if the Hit3 Wave Select value is set to measure wave

number 11, then the Hit4 Wave Select must be set to detect wave number 12 or greater. The earliest

wave for which Hit4 can be measured is Wave 6.

HIT4WV

[5:0]

5:0

HIT4WV[5:0] (decimal)

DESCRIPTION

Wave 6

0 to 6

7

8

Wave 7

Wave 8

9 to 63

Wave 9 to 63

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Table 21. TOF5 Register

TOF5 REGISTER

WRITE OPCODE

3Ch

READ OPCODE

BCh

POR DEFAULT VALUE

0000h

Bit

15

X

14

X

13

12

11

10

9

8

Name

Hit5WV5

Hit5WV4

Hit5WV3

Hit5WV2

Hit5WV1

Hit5WV0

Bit

7

6

5

4

3

2

1

0

Name

X

Hit6WV5

Hit6WV4

Hit6WV3

Hit6WV2

Hit6WV1

Hit6WV0

BIT

NAME

DESCRIPTION

15:14

13:8

7:6

X

Reserved

Hit5 Wave Select: These bits select the wave number for which the Hit5 stop time is measured.

Wave numbers are depicted in Figure 5B. The Hit5 Wave Select value must be at least 1 greater

than the Hit4 Wave Select value. For example, if the Hit4 Wave Select value is set to measure wave

number 12, then the Hit5 Wave Select must be set to detect wave number 13 or greater. The earliest

wave for which Hit5 can be measured is Wave 7.

HIT5WV

[5:0]

HIT5WV[5:0] (decimal)

DESCRIPTION

Wave 7

0 to 7

8

9

Wave 8

Wave 9

10 to 63

Wave 10 to 63

X

Reserved

Hit6 Wave Select: These bits select the wave number for which the Hit6 stop time is measured.

Wave numbers are depicted in Figure 5B. Hit6 Wave Select value must at least 1 greater than the

Hit5 Wave Select value. For example, if Hit5 Wave Select value is set to measure wave number 13,

then the Hit6 Wave Select must be set to detect wave number 14 or greater. The earliest wave for

which Hit6 can be measured is Wave 8.

HIT5WV

[5:0]

5:0

HIT4WV[5:0] (decimal)

DESCRIPTION

Wave 8

0 to 8

9

Wave 9

10

Wave 10

11 to 63

Wave 11 to 63

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Table 22. TOF6 Register

TOF6 REGISTER

WRITE OPCODE

3Dh

READ OPCODE

BDh

POR DEFAULT VALUE

0000h

Bit

15

14

13

12

11

10

9

8

C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET

Name

UPR7

UPR6

UPR5

UPR4

UPR3

UPR2

UPR1

UPR0

Bit

7

6

5

4

3

2

1

0

C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET

Name

X

UP6

UP5

UP4

UP3

UP2

UP1

UP0

BIT

NAME

DESCRIPTION

Comparator Return Oﬀset Upstream: When the device is measuring the t wave, the

2

programmed receive comparator oﬀset is returned to a common mode voltage automatically after

the Early Edge, t , is detected. The actual oﬀset return voltage is dependent upon and scales

1

with the voltage present at the V

pins. The following formula deﬁnes the Comparator Return

CC

Oﬀset voltage setting, where C_OFFSETUPR is a two’s-complement number:

1152 + C_OFFSETUPR

Comparator Return Offset Voltage = V

×

CC

C_OFFSETUP

R[7:0]

3072

15:8

V

CC

where 1 LSB =

3072

C_OFFSETUPR[6:0]

7Fh to 01h

00h

OFFSET (LSBs)

127 to 1

0

80h to FFh

-128 to -1

7

X

Reserved

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Table 22. TOF6 Register (continued)

BIT

NAME

DESCRIPTION

Comparator Oﬀset Upstream: These bits deﬁne an initial selected receive comparator oﬀset

voltage for the analog receiver comparator front-end. This comparator oﬀset is used to detect the

Early Edge wave, t . The actual common mode voltage is dependent upon and scales with the

1

voltage present at the V

pins.

CC

When the STOP_POL bit in the TOF1 register is set to zero indicating a rising edge detection of

the zero crossing of the received acoustic wave, then the Comparator Oﬀset is a positive value.

When the STOP_POL bit in the TOF1 register is set to one indicating a falling edge detection of

the zero crossing of the received acoustic wave, then the Comparator Oﬀset is a negative value.

The following formulas deﬁne the Comparator Oﬀset voltage setting

C_OFFSETUP

[6:0]

6:0

1152 + C_OFFSETUP

STOP_POL = 0 Comparator Offset Voltage = V

×

CC

3072

1151− C_OFFSETUP

STOP_POL = 1 Comparator Offset Voltage = V

×

CC

3072

V

CC

where 1 LSB =

3072

C_OFFSETUP[6:0]

OFFSET (LSBs)

00h to 7Fh

0 to 127

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Table 23. TOF7 Register

TOF7 REGISTER

WRITE OPCODE

3Eh

READ OPCODE

BEh

POR DEFAULT VALUE

0000h

Bit

15

14

13

12

11

10

9

8

C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET

Name

DNR7

DNR6

DNR5

DNR4

DNR3

DNR2

DNR1

DNR0

Bit

7

6

5

4

3

2

1

0

C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET C_OFFSET

Name

X

DN6

DN5

DN4

DN3

DN2

DN1

DN0

BIT

NAME

DESCRIPTION

Comparator Return Oﬀset Downstream: When the device is measuring the t2 wave, the

programmed receive comparator oﬀset is returned to a common mode voltage automatically

after the Early Edge, t , is detected. The actual oﬀset return voltage is dependent upon and

1

scales with the voltage present at the V

pins. The following formula deﬁnes the Comparator

CC

Return Oﬀset voltage setting, where C_OFFSETDNR is a two’s-complement number:

1152 + C_OFFSETDNR

Comparator Return Offset Voltage = V

×

CC

C_OFFSETDNR

[7:0]

3072

15:8

V

CC

where 1 LSB =

3072

C_OFFSETDNR[6:0]

7Fh to 01h

00h

OFFSET (LSBs)

127 to 1

0

80h to FFh

-128 to -1

7

X

Reserved

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Table 23. TOF7 Register (continued)

BIT

NAME

DESCRIPTION

Comparator Oﬀset Downstream: These bits deﬁne an initial selected receive comparator

oﬀset voltage for the analog receiver comparator front-end. This comparator oﬀset is used

to detect the Early Edge wave, t . The actual common mode voltage is dependent upon and

1

scales with the voltage present at the V

pins.

CC

When the STOP_POL bit in the TOF1 register is set to zero indicating a rising edge detection of

the zero crossing of the received acoustic wave, then the Comparator Oﬀset is a positive value.

When the STOP_POL bit in the TOF1 register is set to one indicating a falling edge detection

of the zero crossing of the received acoustic wave, then the Comparator Oﬀset is a negative

value.

The following formulas deﬁne the Comparator Oﬀset voltage setting:

C_OFFSETDN

[6:0]

6:0

1152 + C

OFFSETUP

3072

STOP_POL = 0 Comparator Offset Voltage = V

×

CC

1151− C

OFFSETUP

STOP_POL = 1 Comparator Offset Voltage = V

×

3072

V

CC

3072

where 1 LSB =

C_OFFSETDN[6:0]

OFFSET (LSBs)

00h to 7Fh

0 to 127

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Table 24. Event Timing 1 Register

EVENT TIMING 1 REGISTER

WRITE OPCODE

3Fh

READ OPCODE

BFh

POR DEFAULT VALUE

0000h

Bit

15

14

13

12

11

10

9

8

Name

TDF3

TDF2

TDF1

TDF0

TDM4

TDM3

TDM2

TDM1

Bit

7

6

5

4

3

2

1

0

Name

TDM0

TMF5

TMF4

TMF3

TMF2

TMF1

TMF0

X

BIT

NAME

DESCRIPTION

TOF Diﬀerence Measurement Frequency: These bits deﬁne the rate at which TOF_DIFF

measurements are executed when the EVTMG1 or EVTMG2 command is executed.

Rate = 0.5s + (TDF[3:0] x 0.5s) + randomizer value

TDF[3:0] (decimal)

RATE (s)

0.5

15:12

TDF[3:0]

0

1

1.0

. . .

14

. . .

7.5

TOF Diﬀerence Measurements: These bits deﬁne the number of TOF_DIFF measurement cycles to

be executed when the EVTMG1 or EVTMG2 command is executed.

Cycles = 1+ TDM[4:0]

TDM[4:0] (decimal)

CYCLES

11:7

TDM[4:0]

0

1

2

. . .

30

. . .

31

Temperature Measurement Frequency: These bits deﬁne the time delay between temperature

cycle measurements. It is a start-cycle to start-cycle time duration at which temperature

measurement cycles are executed when the EVTMG1 or EVTMG3 command is executed.

Rate = 1.0s + (TMF[3:0] * 1.0s) + randomizer value

6:1

TMF[5:0]

TMF[5:0] (decimal)

RATE (S)

0

1

2

. . .

62

. . .

63

0

X

Reserved

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Table 25. Event Timing 2 Register

EVENT TIMING 2 REGISTER

WRITE OPCODE

40h

READ OPCODE

C0h

POR DEFAULT VALUE

0000h

Bit

15

14

13

12

11

10

9

8

Name

TMM4

TMM3

TMM2

TMM1

TMM0

CAL_USE

CAL_CFG2

CAL_CFG1

Bit

7

6

5

4

3

2

1

0

Name

CAL_CFG0

X

PRECYC2

PRECYC1

PRECYC0

PORTCYC1 PORTCYC0

BIT

NAME

DESCRIPTION

Temperature Measurements: These bits deﬁne the number of temperature measurement

cycles to be executed when the EVTMG1 or EVTMG3 command is executed.

Cycles = 1+ TMM[4:0]

TMM[4:0] (decimal)

CYCLES

15:11

TMM[4:0]

CAL_USE

0

1

2

. . .

30

. . .

31

Calibration Usage: This bit, when set, causes the device to use the calibration data in the

CalibrationInt and CalibrationFrac registers during measurement, averaging and accumulation

of data while executing the EVTMG commands. All time measurements are scaled using the

calibration factors as described by the Calibrate command.

10

Calibration Conﬁguration: These bits deﬁne the point in the EVTMGx cycle/sequence where

the automatic Calibration command is executed.

DESCRIPTION

CAL_CFG[2:0]

During EVTMGx sequences, automatic execution of the Calibrate

command occurs at:

000b to 011b

100b

Auto Calibration Disabled

The beginning of each TOF_DIFF cycle

The beginning of each Temperature cycle

9:7

CAL_CFG[2:0]

The beginning of each TOF_DIFF cycle

The beginning of each Temperature sequence

101b

110b

111b

Once at the beginning of each TOF_DIFF sequence

The beginning of each Temperature cycle

Once at the beginning of each TOF_DIFF sequence

The beginning of each Temperature sequence

6:5

X

Reserved

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Table 25. Event Timing 2 Register (continued)

BIT

NAME

DESCRIPTION

Preamble Temperature Cycle: These 3 bits are used to set the number of cycles to use as

preamble for reducing dielectric absorption of the temperature measurement capacitor. Each

cycle is comprised of one temperature measurement sequence as deﬁned by the TP[1:0] bits.

PRECYC2

PRECYC1

PRECYC0

DESCRIPTION

0 Dummy Cycle

1 Dummy Cycles

2 Dummy Cycles

3 Dummy Cycles

4 Dummy Cycles

5 Dummy Cycles

6 Dummy Cycles

7 Dummy Cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4:2

PRECYC[2:0]

Port Cycle Time: These two bits deﬁne the time interval between successive individual

temperature port measurements. It is a start-to-start time. These bits also deﬁne the timeout

function of the temperature measurement ports. See the Temperature Operation Sections for

timeout details.

PORTCYC1

PORTCYC0

DESCRIPTION (µs)

1:0

PORTCYC[1:0]

0

1

0

1

0

1

128

256

384

512

Table 26. TOF Measurement Delay Register

TOF MEASUREMENT DELAY REGISTER

WRITE OPCODE

41h

READ OPCODE

C1h

POR DEFAULT VALUE

0000h

15

14

13

12

11

10

9

8

Bit

DLY15

DLY14

DLY13

DLY12

DLY11

DLY10

DLY9

DLY8

Name

7

6

5

4

3

2

1

0

Bit

DLY7

DLY6

DLY5

DLY4

DLY3

DLY2

DLY1

DLY0

Name

BIT

NAME

DESCRIPTION

This is hexadecimal value ranging from 0000h to FFFFh (Decimal 0 to 65535). It is a multiple

of the 4MHz crystal period (250ns). The minimum setting is 0064h, which is equivalent to 25µs.

The analog comparator driven by the bandpass ﬁlter does not generate a stop condition until

this delay, counted from the internally generated start pulse for the acoustic wave, has expired.

This delay applies to Early Edge Detect wave.

15:0

DLY[15:0]

Care must be taken to set the TIMOUT bits in the TOF2 register so that a timeout interrupt

does not occur before this delay expires.

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Table 27. Calibration and Control Register

CALIBRATION AND CONTROL REGISTER

WRITE OPCODE

42h

READ OPCODE

C2h

POR DEFAULT VALUE

0000h

Bit

15

X

14

X

13

12

X

11

10

9

8

Name

X

CMP_EN

CMP_SEL

INT_EN

ET_CONT

Bit

7

6

5

4

3

2

1

0

CAL_

PERIOD3

CAL_

PERIOD2

CAL_

PERIOD1

CAL_

PERIOD0

Name

CONT_INT

CLK_S2

CLK_S1

CLK_S0

BIT

NAME

DESCRIPTION

15:12

X

Reserved

Comparator/UP_DN Output Enable :

11

CMP_EN

1 = CMP_OUT/UP_DN output device pin is enabled.

0 = CMP_OUT/UP_DN output device pin is driven low.

Comparator/UP_DN Output Select: This bit selects the output function of the CMP_OUT/UP_DN pin

and is only used when CMP_EN = 1.

1 = CMP_EN: The output monitors the receiver front-end comparator output.

0 = UP_DN: The output monitors the launch direction of the pulse launcher.

High Output: Upstream measurement (TX_UP to TX_DN)

10

9

CMP_SEL

INT_EN

Low Output: Downstream measurement (TX_DN to TX_UP)

Interrupt Enable: This bit, when set, enables the INT pin. All interrupt sources are wire-ORed to the

INT pin.

Event Timing Continuous Operation: This bit, when set, causes the currently executing EVTMGx

command to continuously execute until the HALT command is received by the device.

This bit, when cleared, causes:

•ꢀ The currently executing EVTMG1 command to run one sequence of TOF_DIFF

measurement cycles and/or one sequence of temperature measurement.

•ꢀ The currently executing EVTMG2 command to run one sequence of TOF_DIFF measurements

cycles.

8

ET_CONT

•ꢀ The currently executing EVTMG3 command to run one sequence of temperature measurement

cycles.

Continuous Interrupt: This bit, when set, causes the currently executing EVTMGx command to assert

the INT pin (if enabled) after every TOF_DIFF or Temperature measurement cycle. This allows the host

microprocessor to interrogate the current Event for accuracy of measurements and hit data.

When this bit is cleared, the currently executing EVTMGx command interrupt-generation behavior is

controlled only by the setting of the ET_CONT bit.

7

CONT_INT

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Table 27. Calibration and Control Register (continued)

BIT

NAME

DESCRIPTION

Clock Settling Time: These bits deﬁne the time interval that the device waits after enabling the

4MHz clock for it to stabilize before making any measurements of time or temperature.

DESCRIPTION

CLK_S2

CLK_S1

CLK_S0

32kHz CLOCK CYCLES

TYPICAL TIME

488µs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16

48

1.46ms

6:4

CLK_S[2:0]

96

2.93ms

128

168

3.9ms

5.13ms

4MHz Osc On Continuously

4MHz Ceramic Oscillator Calibration Period: These bits deﬁne the number of 32.768kHz oscillator

periods to measure for determination of the 4MHz ceramic oscillator period.

32kHz Clock Cycles = 1+ CAL_PERIOD[3:0]

DESCRIPTION

CAL_PERIOD[3:0]

32kHz CLOCK CYCLES

(decimal)

TYPICAL TIME

CAL_PERI

OD[3:0]

(decimal)

3:0

(µs)

0

1

2

30.5

61

. . .

14

15

. . .

15

16

. . .

457.7

488.0

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Table 28. Real-Time Clock Register

REAL-TIME CLOCK REGISTER

WRITE OPCODE

43h

READ OPCODE

C3h

POR DEFAULT VALUE

0000h

Bit

15

X

14

X

13

X

12

X

11

X

10

9

8

Name

X

Bit

7

6

5

4

3

2

1

0

Name

X

32K_BP

32K_EN

EOSC

AM1

AM0

WF

WD_EN

BIT

15:7

NAME

DESCRIPTION

X

Reserved

32kHz Bypass: This bit, when set, allows an external CMOS-level 32.768kHz signal to be applied to

the 32KX1 device pin. The internal 32.768kHz oscillator is bypassed and the external signal is driven

into the device’s core.

6

32K_BP

32kHz Clock Output Enable: This bit enables the 32KOUT device pin to drive a CMOS-level square

wave representation of the 32kHz crystal.

5

4

32K_EN

EOSC

Enable Oscillator: This active-low bit when set to logic 0 starts the real time clock oscillator. When

this bit is set to logic 1, the oscillator is stopped.

Alarm Control: The device contains a time-of-day alarm. The alarm is activated when either the

AM1 or AM2 bits are set. When the RTC’s hours or minutes value increments to a value equal to the

alarm settings in Alarm registers, the AF bit in the Interrupt Status register is set and the INT device

pin is asserted (if enabled) and remains asserted until the Interrupt Status register is accessed by the

microprocessor with a Read register command.

3:2

AM[1:0]

AM1

AM0

ALARM FUNCTION

0

1

0

1

0

1

No alarm

Alarm when minutes match

Alarm when hours match

Alarm when hours and minutes match

Watchdog Flag: This bit is set when the watchdog counter reaches zero. This bit must be written to

a zero to clear the bit. Writing this bit to a zero when the WDO pin is asserted low releases the WDO

pin to its inactive high-impedance state.

1

0

WF

Watchdog Enable:

1 = Watchdog timer is enabled.

WD_EN

0 = Watchdog time is disabled and the WDO pin is high impedance.

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Table 29. Interrupt Status Register

INTERRUPT STATUS REGISTER

WRITE OPCODE

READ ONLY

READ OPCODE

POR DEFAULT VALUE

0000h

FEh

Bit

15

14

13

X

12

11

10

9

8

Name

TO

AF

TOF

TE

LDO

TOF_EVTMG

TEMP_EVTMG

Bit

7

6

5

4

3

2

1

0

Name

X

Cal

Halt

CSWI

X

PORX

X

Note: This register is read only and bits are self-clearing upon a read to this register, see the Interrupt Operations section for more

information.

BIT

NAME

DESCRIPTION

TimeOut: The TO bit is set if any one of the t , t , Hit1 thru Hit6, or temperature measurements do not

1

2

15

TO

occur causing the time set by the TIMOUT[2:0] bits in the TOF2 register to elapse.

Alarm Flag: Set when the RTC’s hours or minutes value increments to a value equal to the alarm

settings in Alarm registers.

14

13

AF

X

Reserved

Time of Flight: Set when the TOF_UP, TOF_DN, or TOF_DIFF command has completed.

During execution of The EVTMG1 or EVTMG2 command, this bit is set and the INT pin is asserted

(if enabled) upon completion of each of the cycles of the Event deﬁned by the TOF Diﬀerence

Measurements setting if the CONT_INT bit in the Calibration and Control register has been set.

12

11

TOF

Temperature: Set when the Temperature command has completed.

During execution of The EVTMG1 or EVTMG3 command, this bit is set and the INT pin is asserted

(if enabled) upon completion of each of the cycles of the Event deﬁned by the Temperature

Measurements setting if the CONT_INT bit in the Calibration and Control register has been set.

TE

Internal LDO Stabilized: Set when the internal low-dropout regulator is turned on by either the LDO_

Timed or LDO_ON and has stabilized.

10

9

LDO

Event Timing TOF Completed: Set when either the EVTMG1 or EVTMG2 commands have completed

its last TOF_DIFF measurement cycle. This indicates that the data in the T1, T2, T1_AVG, and T2_AVG

registers is valid.

TOF_

EVTMG

Event Timing Temperature Completed: Set when the EVTMG1 or EVTMG3 commands have

completed its last temperature measurements. This indicates that the data in the T1, T2, T3, T4, T1_

AVG, T2AVG, T3AVG, and T4_AVG Results registers is valid.

TEMP_

EVTMG

8

7

X

Reserved

Calibrate: Set after completion of the Calibrate command when the command is manually sent by the

host microprocessor. When Calibration occurs as a result of the setting of the Cal_Use, Cal_AUTO

and Cal_CFGx bits in the Event Timing 2 register and the device is automatically executing Calibration

commands as required during execution of any of the EVTMGx commands, this bit is not set.

6

CAL

5

4

3

HALT

CSWI

X

HALT: Set when the HALT command has completed

Case Switch: Set when a high logic level is detected on the CSW device pin.

Reserved

Power-On-Reset: Set when the device has been successfully powered by application of V . Upon

application of power, the SPI port is inactive until this bit has been set.

CC

2

POR

X

1:0

Reserved

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Table 30. Control Register

CONTROL REGISTER

WRITE OPCODE

FFh

READ OPCODE

7Fh

POR DEFAULT VALUE

000xh

Bit

15

X

14

X

13

12

X

11

X

10

9

8

Name

X

AFA

CSWA

Bit

7

6

5

4

3

2

1

0

Name

X

HWR3

HWR2

HWR1

HWR0

BIT

NAME

DESCRIPTION

15:10

X

Reserved

Alarm Flag Arm: This bit is set when the RTC’s hours and/or minutes value matched the alarm

settings in the Real-Time Clock register. This bit is set at the same time as the AF bit in the Interrupt

Status register. After resetting the RTC alarm settings, a 0 must be written to this bit to re-arm the

RTC Alarm. This bit can only be written to a 0.

9

AFA

Case Switch Arm: This bit is set when the CSW pin detects a logic-high, indicating the MAX35104

has detected a tamper condition. This bit is set at the same time as the CSWI bit in the Interrupt

Status register. Once set, this bit must be written to a 0 to re-arm the Case Switch Detection. The

Case Switch Detection must be re-armed before the CSWI interrupt can be set again. This bit can

only be written to a 0.

8

CSWA

7:0

3:0

X

Reserved

Hardware Revision: These 4 bits contain hardware revision code speciﬁc to the MAX35104 device.

Note: This value can be accessed and modiﬁed. Read this register directly after a POR to get the

correct hardware revision number.

HWR[3:0]

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Conversion Results Register Descriptions

The devices conversion results registers are all read only volatile SRAM. The POR default value for all registers is 0000h.

Table 31. Conversion Results Registers Description

READ-ONLY

ADDRESS

REGISTER

DESCRIPTION

Bit 15 to Bit 8 holds the 8 bit value of the pulse width ratio (t ÷ t ).for the upstream measurement.

1

2

Each bit is weighted as follows:

Bit15

Bit 14

Bit 13

Bit 12

Bit 11

0.0625

Bit 10

Bit 9

Bit 8

1

0.5

0.25

0.125

0.03125

0.015625 0.0078125

Bit 7 to bit 0 holds the 8 bit value of the pulse width ratio (t ÷ t

half the period of the Pulse Launch Frequency for the upstream measurement. Each bit is weighted

) where t AL is equal to one-

IDE

2

IDEAL

C4h

WVRUP

as follows:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

0.5

0.25

0.125

0.0625

0.03125

0.015625 0.0078125

The maximum value of each of these ratios is 1.9921875.

15-bit ﬁxed-point integer value of the ﬁrst hit in the upstream direction. This integer portion is a binary

C5h

C6h

C7h

C8h

C9h

Hit1UPInt representation of the number of t

15

periods that contribute to the time results. The maximum size

4MHz

of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the ﬁrst hit in the upstream direction. This fractional portion is a binary

Hit1UPFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the second hit in the upstream direction. This integer portion

Hit2UPInt is a binary representation of the number of t periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the second hit in the upstream direction. This fractional portion is a binary

Hit2UPFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the third hit in the upstream direction. This integer portion is a binary

Hit3UPInt representation of the number of t

15

periods that contribute to the time results. The maximum size

4MHz

of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the third hit in the upstream direction. This fractional portion is a binary

CAh

CBh

CCh

CDh

Hit3UPFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the fourth hit in the upstream direction. This integer portion is

Hit4UPInt a binary representation of the number of t

periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the fourth hit in the upstream direction. This fractional portion is a binary

Hit4UPFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the ﬁfth hit in the upstream direction. This integer portion is a binary

Hit5UPInt representation of the number of t

15

periods that contribute to the time results. The maximum size

4MHz

of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

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Table 31. Conversion Results Registers Description (continued)

READ-ONLY

ADDRESS

REGISTER

DESCRIPTION

16-bit fractional value of the ﬁfth hit in the upstream direction. This fractional portion is a binary

CEh

Hit5UPFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the sixth hit in the upstream direction. This integer portion is

CFh

D0Fh

D1h

Hit6UPInt a binary representation of the number of t

periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the sixth hit in the upstream direction. This fractional portion is a binary

Hit6UPFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the average of the hits recorded in the upstream direction This

AVGUPInt integer portion is a binary representation of the number of t

15

periods that contribute to the time

4MHz

results. The maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the average of the hits recorded in the upstream direction. This fractional

portion is a binary representation of one t4MHz period quantized to a 16-bit resolution. The maximum

AVGUP

Frac

D2h

16

size of the fraction is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

Bit 15 thru Bit 8 holds the 8 bit value of the pulse width ratio (t ÷ t2).for the downstream

1

measurement. Each bit is weighted as follows:

Bit15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

0.015625 0.0078125

) where t is equal to

IDEAL

Bit 8

1

0.5

0.25

0.125

0.0625

0.03125

Bit 7 to bit 0 holds the 8 bit value of the pulse width ratio (t ÷ t

2

IDEAL

D3h

WVRDN

one-half the period of the Pulse Launch Frequency for the downstream measurement. Each bit is

weighted as follows:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

0.5

0.25

0.125

0.0625

0.03125

0.015625 0.0078125

The maximum value of each of these ratios is 1.9921875.

15-bit ﬁxed-point integer value of the ﬁrst hit in the downstream direction. This integer portion is

D4h

D5h

D6h

D7h

D8h

Hit1DNInt a binary representation of the number of t

periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the ﬁrst hit in the downstream direction. This fractional portion is a binary

Hit1DNFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the second hit in the downstream direction. This integer portion

Hit2DNInt is a binary representation of the number of t periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the second hit in the downstream direction. This fractional portion is a binary

Hit2DNFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the third hit in the downstream direction. This integer portion

Hit3DNInt is a binary representation of the number of t periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

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Table 31. Conversion Results Registers Description (continued)

READ-ONLY

ADDRESS

REGISTER

DESCRIPTION

16-bit fractional value of the third hit in the downstream direction. This fractional portion is a binary

D9h

Hit3DNFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the fourth hit in the downstream direction. This integer portion

Hit4DNInt is a binary representation of the number of t periods that contribute to the time results. The

DAh

DBh

DCh

DDh

DEh

DFh

E0h

E1h

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the fourth hit in the downstream direction. This fractional portion is a binary

Hit4DNFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the ﬁfth hit in the downstream direction. This integer portion is

Hit5DNInt a binary representation of the number of t

periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

H

4M Z.

16-bit fractional value of the ﬁfth hit in the downstream direction. This fractional portion is a binary

Hit5DNFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the sixth hit in the downstream direction This integer portion is

Hit6DNInt a binary representation of the number of t

periods that contribute to the time results. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the sixth hit in the downstream direction. This fractional portion is a binary

Hit6DNFrac representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the average of the hit times recorded in the downstream direction

AVGDNInt This integer portion is a binary representation of the number of t

15

periods that contribute to the

4MHz

time results. The maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the average of the hit times recorded in the downstream direction. This

AVGDN

Frac

fractional portion is a binary representation of one t

16

period quantized to a 16-bit resolution. The

4MHz

16

maximum size of the fraction is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

16-bit ﬁxed-point two’s-complement integer portion of the diﬀerence of the averages for the hits

recorded in both the upstream and downstream directions. It is computed as:

AVGUP – AVGDN

TOF_

DIFFInt

E2h

E3h

This integer represents the number of t

periods that contribute to computation.

15

4MHz

The maximum size of the integer is 7FFFh or (2 - 1) x t

15

. The minimum size of this integer is

4MHZ

8000h or -2 x t

.

4MHz

16-bit fractional portion of the two’s complement diﬀerence of the averages for the hits recorded

in both the upstream and downstream directions. This fractional portion is a binary representation

TOF_

DIFFFrac

of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction is FFFFh or

4MHz

16

(2 - 1)/ 2 x t

.

4MHZ

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Table 31. Conversion Results Registers Description (continued)

READ-ONLY

ADDRESS

REGISTER

DESCRIPTION

Bit 15 thru Bit 8 holds the 8 bit value of the TOF_Range. The TOF_Range is an 8-bit binary integer

that indicates the range of valid error-free TOF_DIFF measurements that were made during

execution of either of the EVTMG1 or EVTMG2 commands. The maximum value of TOF_Range is

equal to 2 times the actual pulse launch period as conﬁgured by the Pulse Launch Divider bits in the

TOF1 register.

Bit15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

MSB

TOF_Range 8-bit binary integer

LSB

The formulas to calculate the Range and Resolution of the TOF_Range integer for a given DPL[3:0]

bit setting are shown below:

Maximum Range (µs) = DPL[3:0] + 1 Resolution = Maximum Range / 256

LAUNCH

FREQUENCY

MAXIMUM RANGE

RESOLUTION

DPL[3:0]

(µs)

(ns)

TOF_

Cycle_

Count/

TOF_

0001b

0002b

. . .

1 MHz

666.6kHz

. . .

2

3

7.8175

11.7185

. . .

E4h

. . .

15

16

Range

1110b

1111b

133.3kHz

125kHz

58.59375

62.5

Bit 7 to Bit 0 holds the 8-bit value of the TOF Cycle Count. The TOF Cycle Count is an 8-bit binary

integer that indicates the number of valid error-free cycles that either of the EVTMG1 or EVTMG2

commands has executed. It also represents the number of TOF_DIFF cycles that have been totaled

for the purpose of averaging, which aﬀects the results provided in the TOF_DIFF_AVGFrac and

TOF_DIFF_AVGInt registers. It is incremented every time an error-free TOF_DIFF command is

executed by either the EVTMG1 or EVTMG2 sequence. Because of this internal error checking, once

the complete number of cycles deﬁned by the TOF Diﬀerence Measurements bits in the Event Timing

1 register has been completed and the TOF_EVTMG bit has been set in the Interrupt Status register

causing the INT device pin to be asserted (if enabled), the TOF Cycle Count may not be equal to the

setting of the TOF Diﬀerence Measurements bits in the Event Timing 1 register.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

TOF Cycle Count 8-bit binary integer

LSB

16-bit ﬁxed-point two’s-complement integer portion of the average of the accumulated TOF_DIFF

measurements. It is computed as:

TOF_DIFF_

AVGInt

E5h

E6h

This integer represents the number of t

periods that contribute to the computation. The

4MHz

15

maximum size of the integer is 7FFFh or (2 - 1) x t

15

. The minimum size of this integer is 8000h

4MHZ

or -2 x t

.

4MHZ

16-bit fractional portion of the two’s complement average of the accumulated TOF_DIFF

TOF_DIFF_

AVGFrac

measurements. This fractional portion is a binary representation of one t

16

period quantized to a

4MHz

16

16-bit resolution. The maximum size of the fraction is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

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Table 31. Conversion Results Registers Description (continued)

READ-ONLY

ADDRESS

REGISTER

DESCRIPTION

15-bit ﬁxed-point integer value of the time taken to discharge the timing capacitor through the

temperature sensing element connected to the T1 device pin. This integer portion is a binary

E7h

T1Int

representation of the number of t

15

periods that contribute to the time results. The maximum size

4MHz

of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the time taken to charge the timing capacitor through the temperature

sensing element connected to the T1 device pin. This fractional portion is a binary representation

E8h

EBh

ECh

T1Frac

T2Int

of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction is FFFFh or

4MHz

16

(2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the time taken to charge the timing capacitor through the

temperature sensing element connected to the T2 device pin. This integer portion is a binary

representation of the number of t

15

periods that contribute to the time results. The maximum size

4MHz

of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the time taken to charge the timing capacitor through the temperature

sensing element connected to the T2 device pin. This fractional portion is a binary representation

T2Frac

of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction is FFFFh or

4MHz

16

(2 - 1)/ 2 x t

.

4MHZ

The Temp Cycle Count is an 8-bit binary integer that indicates the number of valid error-free cycles

that either of the EVTMG1 or EVTMG3 commands has executed. It also represents the number of

Temperature cycles that have been totaled for the purpose of averaging, which aﬀects the results

provided in the Tx_AVGFrac and Tx_AVGInt registers. It is incremented every time an error-free

Temperature command is executed by either the EVTMG1 or EVTMG3 sequence. Because of

this internal error checking, once the complete number of cycles deﬁned by the Temperature

Measurements bits in the Event Timing 2 register has been completed and the Temp_EVTMG bit

has been set in the Interrupt Status register causing the INT device pin to be asserted (if enabled),

the Temp Cycle Count may not be equal to the setting of the Temperature Measurements bits in the

Event Timing 2 register.

Temp_

Cycle_

Count

EFh

Bit15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

X

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

Temp Cycle Count

LSB

15-bit ﬁxed-point integer value of the average of the T1 port measurements. It is computed as:

F0h

F1h

T1_AVGInt

This integer portion is a binary representation of the number of t

15

periods that contribute to the

4MHz

time results. The maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional portion of the average of the T1 port measurements. This fractional portion is a binary

T1_AVG

Frac

representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

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Table 31. Conversion Results Registers Description (continued)

READ-ONLY

ADDRESS

REGISTER

DESCRIPTION

15-bit ﬁxed-point integer value of the average of the T2 port measurements. It is computed as:

F4h

T2_AVGInt

This integer portion is a binary representation of the number of t

15

periods that contribute to the

4MHz

time results. The maximum size of the integer is 7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional portion of the average of the T2 port measurements. This fractional portion is a binary

T2_AVG

Frac

F5h

F8h

representation of one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction

4MHz

16

is FFFFh or (2 - 1)/ 2 x t

.

4MHZ

15-bit ﬁxed-point integer value of the time taken to measure the period of the 32.768kHz crystal

Calibration oscillator during execution of the Calibrate command. This integer portion is a binary representation

Int

of the number of t

15

periods that contribute to the time results. The maximum size of the integer is

4MHz

7FFFh or (2 - 1) x t

.

4MHZ

16-bit fractional value of the time taken to measure the period of the 32.768kHz crystal oscillator

during execution of the Calibrate command. This fractional portion is a binary representation of

Calibration

Frac

F9h

one t

16

period quantized to a 16-bit resolution. The maximum size of the fraction is FFFFh or

16

4MHz

(2 - 1)/ 2 x t

.

4MHZ

FAh

FBh

FCh

FDh

Reserved

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Ordering Information

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PART

TEMP RANGE

PIN-PACKAGE

40 TQFN-EP*

MAX35104ETL+

-40°C to +85°C

MAX35104ETL+T -40°C to +85°C

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

*EP = Exposed pad.

40 TQFN-EP

T4055+2

21-0140

90-0016

Chip Information

PROCESS: CMOS

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Revision History

REVISION REVISION

PAGES

CHANGED

DESCRIPTION

NUMBER

DATE

0

1

2

3

3/16

Initial release

—

6/17

Corrected measurement range and clariﬁed notes about measurement accuracy

Updated ESD speciﬁcation

1, 35

2

7/17

12/17

Corrected register address for T2, removed references to T3 and T4

71, 77, 78

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2017 Maxim Integrated Products, Inc.

│ 80


型号：	MAX35104ETL+T
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Gas Flow Meter SoC
文件：	总80页 (文件大小：1299K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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