MAX3620CETT [MAXIM]
Delay Lines for High-Speed Clock Distribution Systems; 延迟线用于高速时钟分配系统
| 型号： | MAX3620CETT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Delay Lines for High-Speed Clock Distribution Systems |
| 文件： | 总6页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3550; Rev 0; 1/05
Delay Lines for High-Speed Clock
Distribution Systems
General Description
Features
The MAX3620 series is a family of high-performance
passive delay lines for use in QDR/QDRII synchronous
memory systems. These delay lines support high-speed
transceiver logic (HSTL) source terminated transmission
with an unterminated load at the receiver, and deliver
accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns
for the generation of the quarter clock phase. The
MAX3620 is offered in a small 3mm x 3mm package
which contains two delay lines of equal length that can
be driven either differentially or single-endedly.
♦ Supports HSTL Source Terminated Lines
♦ All-Passive Design
♦ Compatible with 100Ω Differential and 50Ω Single-
Ended Transmission Lines
♦ Small 3mm x 3mm Package
Ordering Information
Applications
QDR/QDRII Memory Systems
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
6 TDFN
Multiphase Clock Generation
MAX3620AETT
MAX3620BETT
MAX3620CETT
MAX3620DETT
6 TDFN
Pin Configuration
6 TDFN
6 TDFN
TOP VIEW
IN1
COMMON
IN2
1
2
3
6
5
4
OUT1
Selector Guide
COMMON
OUT2
PART
PKG CODE
TOP MARK
AJX
MAX3620
MAX3620AETT
MAX3620BETT
MAX3620CETT
MAX3620DETT
T633-2
T633-2
T633-2
T633-2
AIY
AIZ
*EP
AJA
TDFN
*EP—EXPOSED PAD. MUST BE CONNECTED TO THE
SAME POTENTIAL AS COMMON.
Typical Application Circuit
QDR II SRAM CLOCK OUTPUT
HSTL SOURCE TERMINATED
QDR II SRAM CLOCK INPUT
HSTL HIGH-Z CMOS
DELAY LINE
1/4 CLOCK PERIOD
50Ω
50Ω
50Ω
50Ω
90° PHASE
50Ω
IN1
OUT1
COMMON
IN2
COMMON
MAX3620
270° PHASE
50Ω
OUT2
180° PHASE
50Ω
0° PHASE
50Ω
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Delay Lines for High-Speed Clock
Distribution Systems
ABSOLUTE MAXIMUM RATINGS
Maximum DC Voltage between COMMON and IOs
Operating Temperature Range ...........................-45°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
(IN1, IN2, OUT1, OUT2)...................................................... 2.0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical ambient temperature is +25°C. See Table 1 for more information.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
50
MAX
UNITS
Characteristic Impedance
Z
See Table 1 clock frequency
Ω
0
MAX3620A
0.65
0.90
1.15
1.40
0.75
1.00
1.25
1.50
0.85
1.10
1.35
1.60
MAX3620B
MAX3620C
MAX3620D
Z
= Z
SOURCE
LOAD
Delay Values
ns
ps
(Note 1)
IN2-to-OUT2 relative to IN1-to-OUT1,
Z
Delay Matching
-20
+20
= Z
LOAD
SOURCE
MAX3620A
MAX3620B
MAX3620C
MAX3620D
MAX3620A
MAX3620B
MAX3620C
MAX3620D
MAX3620A
MAX3620B
MAX3620C
MAX3620D
2.5
2.1
2.3
2.2
4.6
3.8
3.1
3.4
450
370
320
300
Z
= Z
LOAD
SOURCE
(Notes 1, 2, 4)
Insertion Loss
dB
Z
>> Z
,
SOURCE
LOAD
source termination only
(Notes 5, 6)
Cutoff Frequency,
3dB Loss Relative to 10MHz
Z
= Z
LOAD SOURCE
MHz
(Note 3)
Z
= Z
, 50MHz to 1GHz
LOAD
SOURCE
Input Return Loss
Output Return Loss
12
15
dB
dB
(Note 3)
Z
= Z
, 50MHz to 1GHz
LOAD
SOURCE
(Note 3)
Input Leakage at 1.5V
Output Leakage at 1.5V
IN1 or IN2 to grounded COMMON
OUT1 or OUT2 to grounded COMMON
MAX3620A
-10
-10
+10
+10
µA
µA
540
620
700
760
590
720
810
890
MAX3620B
MAX3620C
MAX3620D
MAX3620A
MAX3620B
MAX3620C
MAX3620D
Z
= Z
SOURCE
LOAD
(Notes 1, 2)
Output Transition Time
(20% to 80%)
ps
Z
>> Z
,
SOURCE
LOAD
source termination only
(Note 5)
2
_______________________________________________________________________________________
Delay Lines for High-Speed Clock
Distribution Systems
ELECTRICAL CHARACTERISTICS (continued)
(Typical ambient temperature is +25°C. See Table 1 for more information.)
Note 1: Load and source resistance = 50Ω 1%, capacitance ≤ 1pF. Input transition time (20% to 80%) = 300ps.
Note 2: The clock frequency is the maximum operational clock frequency listed in Table 1.
Note 3: Load and source resistance = 50Ω 1%, capacitance ≤ 1pF.
Note 4: Insertion loss is relative to a lossless 50Ω transmission line. Ideally, an insertion loss of 0dB will result in 0.5 times the open-
circuit transmitter output.
Note 5: Source termination only (no-load termination), 5pF and 20kΩ at load, 300ps input transition time (20% to 80%). Load capac-
itance dominates performance.
Note 6: Insertion loss is relative to an ideal open 20kΩ load. Ideally, an insertion loss of 0dB will result in 0.998 times the open-circuit
transmitter output.
Table 1. Recommended Operating Conditions
PARAMETER
CONDITIONS
MIN
TYP
+25
5
MAX
UNITS
°C
Operating Ambient Temperature
Recommended Load Capacitance
Recommended Load Resistance
-40
+85
Z
Z
>> 50Ω, source termination only
>> 50Ω, source termination only
pF
LOAD
LOAD
20
kΩ
MAX3620A
MAX3620B
MAX3620C
MAX3620D
250
190
150
125
333
250
200
167
1.5
Clock Frequency
MHz
Input Amplitude
V
P-P
V
Input Voltage Range
-1.5
+1.5
_______________________________________________________________________________________
3
Delay Lines for High-Speed Clock
Distribution Systems
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
DELAY vs. C
(LOW LOAD RESISTANCE)
DELAY vs. R
(HIGH LOAD RESISTANCE)
LOAD
LOAD
DELAY vs. R
(LOW LOAD RESISTANCE)
LOAD
1.75
1.50
1.25
1.00
0.75
0.50
1.75
1.50
1.25
1.00
0.75
0.50
1.75
1.50
1.25
1.00
0.75
0.50
R
= 50Ω
C
= 5.0pF
LOAD
LOAD
C
= 1.0pF
LOAD
MAX3620D
MAX3620D
MAX3620D
MAX3620C
MAX3620B
MAX3620A
MAX3620C
MAX3620B
MAX3620C
MAX3620B
MAX3620A
MAX3620A
8
15 16 17 18 19 20 21 22 23 24 25
(kΩ)
0
2
4
6
10
30
40
50
(Ω)
60
70
R
C
(pF)
LOAD
LOAD
R
LOAD
DELAY vs. C
(HIGH LOAD RESISTANCE)
LOAD
MAX3620A S11
MAX3620B S11
0
-3
0
-3
1.75
1.50
1.25
1.00
0.75
0.50
R
= 20Ω
LOAD
MAX3620D
-6
-6
-9
-9
-12
-15
-18
-21
-24
-27
-30
-12
-15
-18
-21
-24
-27
-30
MAX3620C
MAX3620B
MAX3620A
8
50MHz
50MHz
10
100
1000
10
100
1000
0
2
4
6
10
FREQUENCY (MHz)
FREQUENCY (MHz)
C
(pF)
LOAD
MAX3620C S11
MAX3620D S11
MAX3620A S22
0
-3
0
-3
0
-3
-6
-6
-6
-9
-9
-9
-12
-15
-18
-21
-24
-27
-30
-12
-15
-18
-21
-24
-27
-30
-12
-15
-18
-21
-24
-27
-30
50MHz
50MHz
50MHz
10
100
1000
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
4
_______________________________________________________________________________________
Delay Lines for High-Speed Clock
Distribution Systems
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
MAX3620B S22
MAX3620C S22
MAX3620D S22
0
0
-3
0
-3
-3
-6
-6
-6
-9
-9
-9
-12
-15
-18
-21
-24
-12
-15
-18
-21
-24
-27
-30
-12
-15
-18
-21
-24
-27
-30
-27
-30
50MHz
50MHz
50MHz
10
100
FREQUENCY (MHz)
1000
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Pin Description
PIN
1
NAME
IN1
COMMON Common
FUNCTION
IN1
COMMON
IN2
OUT1
Single-Ended Input 1
2
COMMON
OUT2
3
IN2
Single-Ended Input 2
Single-Ended Output 2
4
OUT2
5
COMMON Common
6
OUT1
Single-Ended Output 1
Exposed
Pad
—
Connect to same potential as COMMON
Figure 1. Functional Diagram
Detailed Description
The MAX3620 delay lines are transmission lines con-
structed with a series of L-C sections. Figure 1 is a
functional diagram of the MAX3620. The distributed
architecture of the MAX3620 allows for symmetrical
impedance looking into each terminal. When the
MAX3620 is used in single-ended operation, leave
unused input/output open.
_______________________________________________________________________________________
5
Delay Lines for High-Speed Clock
Distribution Systems
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D
N
PIN 1
INDEX
AREA
E
E2
DETAIL A
C
L
C
L
A
L
L
e
e
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
1
-DRAWING NOT TO SCALE-
21-0137
G
2
COMMON DIMENSIONS
SYMBOL
MIN.
0.70
2.90
2.90
0.00
0.20
MAX.
0.80
3.10
3.10
0.05
0.40
A
D
E
A1
L
k
0.25 MIN.
0.20 REF.
A2
PACKAGE VARIATIONS
DOWNBONDS
ALLOWED
N
6
D2
E2
e
JEDEC SPEC
b
PKG. CODE
T633-1
[(N/2)-1] x e
1.90 REF
1.90 REF
1.95 REF
1.50±0.10
1.50±0.10
1.50±0.10
1.50±0.10
1.50±0.10
1.50±0.10
1.70±0.10
1.70±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
0.95 BSC
0.95 BSC
0.65 BSC
0.65 BSC
0.65 BSC
0.50 BSC
0.40 BSC
0.40 BSC
MO229 / WEEA
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEEC
MO229 / WEED-3
- - - -
0.40±0.05
0.40±0.05
0.30±0.05
0.30±0.05
0.30±0.05
0.25±0.05
0.20±0.05
0.20±0.05
NO
NO
T633-2
6
T833-1
8
NO
T833-2
8
1.95 REF
1.95 REF
2.00 REF
2.40 REF
2.40 REF
NO
T833-3
8
YES
NO
T1033-1
T1433-1
T1433-2
10
14
14
YES
NO
- - - -
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2
-DRAWING NOT TO SCALE-
21-0137
G
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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