MAX3681 [MAXIM]
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs; + 3.3V ， 622Mbps的， SDH / SONET 1 ： 4解串器，LVDS输出，
| 型号： | MAX3681 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs |
| 文件： | 总8页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1091; Rev 0; 6/96
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
MAX3681
_________________Ge n e ra l De s c rip t io n
______________________________Fe a t u re s
♦ Single +3.3V Supply
The MAX3681 d e s e ria lize r is id e a l for c onve rting
622Mbps serial data to 4-bit-wide, 155Mbps parallel
data in ATM and SDH/SONET applications. Operating
from a single +3.3V supply, this device accepts PECL
serial clock and data inputs, and delivers low-voltage
differential-signal (LVDS) clock and data outputs for
interfacing with high-speed digital circuitry. It also pro-
vides an LVDS synchronization input that enables data
realignment and reframing.
♦ 622Mbps Serial to 155Mbps Parallel Conversion
♦ 265mW Power
♦ LVDS Data Outputs and Synchronization Inputs
♦ Synchronization Input for Data Realignment and
Reframing
♦ Differential 3.3V PECL Clock and Data Inputs
The MAX3681 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 24-pin SSOP
package.
__________________________Ap p lic a t io n s
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
________________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
PIN-PACKAGE
MAX3681EAG
-40°C to +85°C
24 SSOP
Pin Configuration appears at end of data sheet.
Digital Cross Connects
___________________________________________________________________Typ ic a l Op e ra t in g Circ u it
V
CC
= +3.3V
V
CC
PD3+
100Ω*
V
CC
= +3.3V
V
CC
= +3.3V
PD3-
MAX3681
PD2+
130Ω
130Ω
100Ω*
100Ω*
100Ω*
100Ω*
SD+
SD-
PHOTODIODE
MAX3664
PD2-
MAX3675
OVERHEAD
TERMINATION
PD1+
82Ω
82Ω
DATA
AND
CLOCK
RECOVERY
PD1-
LIMITING
AMP
PREAMP
100Ω
PD0+
V
CC
= +3.3V
130Ω
130Ω
PD0-
PCLK+
SCLK+
SCLK-
PCLK-
82Ω
82Ω
SYNC+
SYNC-
GND
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z = 50Ω.
0
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +85°C)
A
V
CC
...........................................................................-0.5V to 5V
SSOP (derate 8.00mW/°C above +85°C) ......................520mW
PECL Inputs (SD+/-, SCLK+/-).................................V + 0.5V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
LVDS Inputs (SYNC+/-)............................................V + 0.5V
CC
Output Current, LVDS Outputs (PCLK+/-, PD_+/-).............10mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX3681
DC ELECTRICAL CHARACTERISTICS
(V = +3.0V to +3.6V, differential loads = 100Ω, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +3.3V,
CC
A
CC
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
CC
55
80
120
mA
PECL INPUTS (SD+/-, SCLK+/-)
Input High Voltage
Input Low Voltage
V
V
- 1.16
V
CC
- 0.88
- 1.48
V
V
IH
CC
V
IL
V
CC
- 1.81
V
CC
Input High Current
Input Low Current
I
V
= V
IH(MAX)
-10
10
10
µA
µA
IH
IN
I
V
IN
= V
IL(MAX)
-10
IL
LVDS INPUTS AND OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-)
Input Voltage Range
V
Differential input voltage = 100mV
Common-mode voltage = 50mV
0
2.4
V
mV
mV
Ω
I
Differential Input Threshold
Threshold Hysteresis
V
-100
100
IDTH
V
70
HYST
Differential Input Resistance
Output High Voltage
R
85
100
115
IN
V
OH
1.475
V
Output Low Voltage
V
0.925
250
V
OL
Differential Output Voltage
V
OD
400
25
mV
Change in Magnitude of Differential
Output Voltage for Complementary
States
∆V
mV
V
OD
Output Offset Voltage
V
OS
T
A
= +25°C
1.125
40
1.275
25
Change in Magnitude of Output
Offset Voltage for Complementary
States
∆V
mV
Ω
OS
Single-Ended Output Resistance
R
70
±1
140
±10
O
Change in Magnitude of Single-
Ended Output Resistance for
Complementary States
∆R
%
O
AC ELECTRICAL CHARACTERISTICS
(V = +3.0V to +3.6V, differential loads = 100Ω, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
622
800
50
TYP
MAX
UNITS
MHz
ps
Maximum Serial Clock Frequency
Serial Data Setup Time
f
SCLK
t
SU
Serial Data Hold Time
t
H
ps
Parallel Clock to Data Output Delay
t
200
550
900
ps
CLK-Q
Note 1: AC Characteristics guaranteed by design and characterization.
_______________________________________________________________________________________
2
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
MAX3681
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +3.0V to +3.6V, differential loads = 100Ω, unless otherwise noted.)
CC
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
MAXIMUM SERIAL CLOCK FREQUENCY
vs. TEMPERATURE
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
400
360
2.0
1.8
-100
-140
V
CC
= 3.6V
320
280
1.6
1.4
-180
-220
V
CC
= 3.0V
240
200
1.2
1.0
-260
-300
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
-25
0
25
50
100
-50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
PARALLEL CLOCK TO DATA
OUTPUT PROPAGATION DELAY
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
120
700
650
100
80
V
= +3.6V
= +3.3V
CC
V
CC
600
550
V
CC
= +3.0V
60
500
450
40
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1, 2, 5, 8, 12
V
CC
+3.3V Supply Voltage
3
SD+
SD-
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Noninverting PECL Serial Clock Input
4
6
7
SCLK+
SCLK-
GND
MAX3681
Inverting PECL Serial Clock Input
9, 15, 22
Ground
Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
10
11
SYNC+
SYNC-
Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
13
14
PCLK-
PCLK+
Inverting LVDS Parallel Clock Output
Noninverting LVDS Parallel Clock Output
Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
16, 18, 20, 23 PD0- to PD3-
17, 19, 21, 24 PD0+ to PD3+
Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
_______________De t a ile d De s c rip t io n
The MAX3681 deserializer uses a 4-bit shift register,
4-bit parallel output register, 2-bit counter, PECL input
b uffe rs , a nd low-volta g e d iffe re ntia l-s ig na l (LVDS)
input/output buffers to convert 622Mbps serial data to
4-bit-wide, 155Mbps parallel data (Figure 1).
PD3+
PD3-
SD+
SD-
PECL
PECL
LVDS
LVDS
LVDS
LVDS
LVDS
4-BIT
SHIFT
4-BIT
PARALLEL
OUTPUT
REGISTER
REGISTER
PD2+
PD2-
SCLK+
SCLK-
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 2-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by four, causing the output
register to latch every four bits of incoming serial data.
PD1+
PD1-
MAX3681
PD0+
PD0-
The synchronization inputs (SYNC+, SYNC-) are used
for data realignment and reframing. When the SYNC
signal is pulsed high for at least two SCLK cycles, the
parallel output data is delayed by one SCLK cycle. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC signal’s positive transition. As a
result, the first incoming bit of data during that PCLK
cycle is dropped, shifting the alignment between PCLK
and data by one bit.
SYNC+
SYNC-
PCLK+
PCLK-
2-BIT
COUNTER
LVDS
100Ω
Figure 1. Functional Diagram
See Figure 2 for the functional timing diagram and
Figure 3 for the timing parameters diagram.
4
_______________________________________________________________________________________
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
MAX3681
SCLK
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
SD
SYNC
PCLK
PD3
PD2
PD1
PD0
D4-
D0
D1
D2
D3
D5
D6
D7
D8
D3-
D2-
D1-
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2. Functional Timing Diagram
t
= 1 / f
SCLK
SCLK
SCLK
t
SU
t
H
SD
PCLK
t
CLK-Q
PD0–PD3
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 3. Timing Parameters
_______________________________________________________________________________________
5
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
Lo w -Vo lt a g e Diffe re n t ia l-S ig n a l (LVDS )
THEVENIN-EQUIVALENT TERMINATION
In p u t s a n d Ou t p u t s
The MAX3681 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 250mVp-p to 400mVp-p, dif-
ferential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immunity.
+3.3V
130Ω
130Ω
MAX3681
Z = 50Ω
O
PECL
INPUTS
Z = 50Ω
O
The parallel clock and data LVDS outputs (PCLK+,
PCLK-, PD_+, PD_-) require 100Ω differential DC termi-
nation between the inverting and noninverting outputs
for proper operation. Do not terminate these outputs to
ground.
MAX3681
82Ω
82Ω
The synchronization LVDS inputs (SYNC+, SYNC-) are
internally terminated with 100Ω of differential input
resistance, and therefore do not require external termi-
nation.
ECL AC-COUPLING TERMINATION
+3.3V
P ECL In p u t s
1.6k
1.6k
The s e ria l d a ta a nd c loc k PECL inp uts (SD+, SD-,
Z = 50Ω
O
MAX3681
SCLK+, SCLK-) require 50Ω termination to (V
- 2V)
CC
whe n inte rfa c ing with a PECL s ourc e (s e e the
Alternative PECL Input Termination section).
50Ω
PECL
INPUTS
-2V
-2V
__________Ap p lic a t io n s In fo rm a t io n
Z = 50Ω
O
Alt e rn a t ive P ECL In p u t Te rm in a t io n
Fig ure 4 s hows a lte rna tive PECL inp ut-te rmina tion
methods. Use Thevenin-equivalent termination when a
50Ω
2.7k
2.7k
(V
CC
- 2V) termination voltage is not available. If AC
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
Figure 4. Alternative PECL Input Termination
La yo u t Te c h n iq u e s
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3681 data inputs and outputs.
6
_______________________________________________________________________________________
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
MAX3681
__________________P in Co n fig u ra t io n
___________________Ch ip In fo rm a t io n
TOP VIEW
TRANSISTOR COUNT: 724
V
1
2
3
4
PD3+
PD3-
GND
24
23
22
CC
V
CC
SD+
SD-
21 PD2+
20 PD2-
MAX3681
V
CC
5
6
7
8
SCLK+
SCLK-
PD1+
PD1-
19
18
17
16
15
14
V
CC
PD0+
PD0-
GND
SYNC+
SYNC-
9
10
11
12
GND
PCLK+
V
CC
13 PCLK-
SSOP
_______________________________________________________________________________________
7
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :4 De s e ria lize r w it h LVDS Ou t p u t s
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
0.068
MAX
0.078
0.008
0.015
0.008
MIN
1.73
0.05
0.25
0.09
MAX
1.99
0.21
0.38
0.20
A
A1 0.002
B
C
D
E
e
0.010
0.004
SEE VARIATIONS
α
MAX3681
0.205
0.209
5.20
5.38
E
H
0.0256 BSC
0.65 BSC
H
L
0.301
0.311
0.037
8˚
7.65
0.63
0˚
7.90
0.95
8˚
0.025
0˚
C
α
L
INCHES
MILLIMETERS
DIM PINS
MIN MAX MIN
0.239 0.249 6.07
0.239 0.249 6.07
0.278 0.289 7.07
0.317 0.328 8.07
MAX
6.33
6.33
7.33
8.33
e
D
D
D
D
D
14
16
20
24
28
SSOP
SHRINK
A
SMALL-OUTLINE
PACKAGE
0.397 0.407 10.07 10.33
21-0056A
B
A1
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
___________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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