MAX3693ECJ+ [MAXIM]
3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs;
| 型号： | MAX3693ECJ+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总8页 (文件大小：572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4775; Rev 2; 5/04
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
General Description
Features
The MAX3693 serializer is ideal for converting 4-bit-
wide, 155Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers a 3.3V PECL serial-data output. A fully integrated
PLL synthesizes an internal 622Mbps serial clock from
a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz ref-
erence clock.
♦ Single +3.3V Supply
♦ 155Mbps (4-bit-wide) Parallel to
622Mbps Serial Conversion
♦ Clock Synthesis for 622Mbps
♦ 215mW Power
♦ Multiple Clock Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
♦ LVDS Parallel Clock and Data Inputs
♦ Differential 3.3V PECL Serial-Data Output
The MAX3693 is available in the extended temperature
range (-40°C to +85°C), in a 32-pin TQFP package.
Applications
Ordering Information
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
PART
MAX3693ECJ
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
MAX3693ECJ+
32 TQFP
+Denotes lead-free package.
Digital Cross Connects
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
(155MHz LVDS CRYSTAL REFERENCE)
V
= +3.3V
CC
PCLKI- PCLKI+ RCLK- RCLK+
V
CKSET
FIL+
CC
1µF
1µF
PD0+
PD0-
PD1+
OVERHEAD
GENERATION
PD1-
MAX3693
PD2+
PD2-
PD3+
FIL-
V
CC
= +3.3V
PD3-
PCLKO- PCLKO+
GND
SD- SD+
V
= +3.3V
CC
130Ω
130Ω
MAX3668
82Ω
82Ω
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z = 50Ω)
0
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +85°C)
A
V
.......................................................................-0.5V to +5V
TQFP (derate 10.20mW/°C above +85°C)...................663mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
All Inputs, FIL+, FIL-,
PCLKO+, PCLKO-..............................-0.5V to (V
Output Current
+ 0.5V)
CC
LVDS Outputs (PCLKO )................................................10mA
PECL Outputs (SD ).......................................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3V to +3.6V, differential LVDS loads = 100Ω 1ꢀ, PECL loads = 50Ω 1ꢀ to (V - 2V), T = -40°C to +85°C, unless other-
CC A
CC
wise noted. Typical values are at V
= +3.3V, T = +25°C.)
A
CC
PARAMETER
Supply Current
SYMBOL
CONDITIONS
PECL outputs unterminated
MIN
38
TYP
65
MAX
100
UNITS
mA
I
CC
PECL OUTPUTS (SD±)
T
A
T
A
T
A
T
A
= 0°C to +85°C
= -40°C
V
CC
V
CC
V
CC
V
CC
- 1.025
- 1.085
- 1.81
-1.83
V
V
V
- 0.88
- 0.88
- 1.62
- 1.555
CC
CC
CC
Output High Voltage
V
V
V
OH
= 0°C to +85°C
= -40°C
Output Low Voltage
V
OL
V
CC
LVDS INPUTS AND OUTPUTS (PCLKI±, RCLK±, PCLKO±, PD_±)
Differential input voltage =
100mV
Input Voltage Range
V
I
0
2.4
V
Common-mode voltage =
50mV
Differential Input Threshold
V
-100
85
100
mV
IDTH
Threshold Hysteresis
V
HYST
60
mV
Ω
Differential Input Resistance
Output High Voltage
R
100
115
IN
V
1.475
V
OH
Output Low Voltage
V
0.925
250
V
OL
Differential Output Voltage
|V
|
OD
OS
400
25
mV
OD
Change in Magnitude of Differential Output
Voltage for Complementary States
∆|V
|
mV
V
Output Offset Voltage
V
1.125
40
1.275
25
Change in Magnitude of Output Offset Voltage
for Complementary States
∆V
mV
Ω
OS
O
Single-Ended Output Resistance
R
95
140
10
Change in Magnitude of Single-Ended Output
Resistance for Complementary Outputs
∆R
2.5
ꢀ
O
PROGRAMMING INPUT (CKSET)
CKSET Input Current
I
CKSET = 0 or V
500
µA
CKSET
CC
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3V to +3.6V, differential LVDS load = 100Ω 1ꢀ, PECL loads = 50Ω 1ꢀ to (V
- 2V), T = -40°C to +85°C, unless other-
CC A
wise noted. Typical values are at V = +3.3V, T = +25°C.) (Note 1)
CC
A
PARAMETER
Serial Clock Rate
SYMBOL
CONDITIONS
MIN
TYP
622.08
MAX
UNITS
MHz
ps
f
SCLK
Parallel Data-Setup Time
Parallel Data-Hold Time
t
T
A
= +25°C
200
600
SU
t
H
ps
PCLKO to PCLKI Skew
t
0
+4.0
11
ns
SKEW
Φ
0
Output Random Jitter
ps
RMS
PECL Differential Output
Rise/Fall Time
t
t
200
ps
R, F
Note 1: AC characteristics guaranteed by design and characterization.
Typical Operating Characteristics
(V = +3.3V, differential LVDS loads = 100Ω 1ꢀ, PECL loads = 50Ω 1ꢀ to (V
CC
- 2V), T = +25°C, unless otherwise noted.)
A
CC
SUPPLY CURRENT
vs. TEMPERATURE
PARALLEL DATA-SETUP TIME
vs. TEMPERATURE
PARALLEL DATA-HOLD TIME
vs. TEMPERATURE
100
200
250
80
60
40
150
100
50
200
150
100
20
0
0
50
0
PECL OUTPUTS UNTERMINATED
-50
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Typical Operating Characteristics (continued)
(V = +3.3V, differential LVDS loads = 100Ω 1ꢀ, PECL loads = 50Ω 1ꢀ to (V
- 2V), T = +25°C, unless otherwise noted.)
A
CC
CC
SERIAL-DATA OUTPUT JITTER
SERIAL-DATA OUTPUT EYE DIAGRAM
1.0042V
1.1V
10mV/
div
57mV/
div
f
= 155.52MHz
RCLK
0.536V
0.904V
10ps/div
200ps/div
ꢀ
µ 1σ 70.373%
µ 2σ 95.357%
µ 3σ 99.759%
Mean 25.22ns
RMS∆ 4.073ps
PkPk 32.6ps
Pin Description
PIN
NAME
FUNCTION
1, 3, 5, 7
PD0+ to PD3+ Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
2, 4, 6, 8
PD0- to PD3-
GND
Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Ground
9, 17, 18, 19,
24, 25, 32
Inverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead man-
agement circuit.
10
11
PCLKO-
PCLKO+
Noninverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead
management circuit.
12, 13, 16,
21, 28, 29
V
CC
+3.3V Supply Voltage
14
15
SD-
Inverting PECL Serial-Data Output
SD+
Noninverting PECL Serial-Data Output
Reference Clock Rate Programming Pin.
CKSET = V : Reference Clock Rate = 155.52MHz
CC
20
CKSET
CKSET = Open: Reference Clock Rate = 77.76MHz
CKSET = 20kΩ to GND: Reference Clock Rate = 51.84MHz
CKSET = GND Reference Clock Rate = 38.88MHz
22
23
FIL-
Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
FIL+
Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to
the RCLK inputs.
26
27
30
31
RCLK+
RCLK-
Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the
RCLK inputs.
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
PCLKI+
PCLKI-
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
4
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
The incoming parallel data is clocked into the
_______________Detailed Description
MAX3693 on the rising transition of the parallel-clock-
The MAX3693 serializer comprises a 4-bit parallel input
input signal (PCLKI). The control and timing logic
register, a 4-bit shift register, control and timing logic, a
ensure proper operation if the parallel-input register is
PECL output buffer, LVDS input/output buffers, and a
latched within a window of time that is defined with
frequency-synthesizing PLL (consisting of a phase/
respect to the parallel-clock-output signal (PCLKO).
frequency detector, loop filter/amplifier, voltage-
PCLKO is the synthesized 622Mbps internal serial-
controlled oscillator, and prescaler). This device con-
clock signal divided by four. The allowable PCLKO-to-
verts 4-bit-wide, 155Mbps data to 622Mbps serial data
PCLKI skew is 0 to +4ns. This defines a timing window
(Figure 1).
at about the PCLKO rising edge, during which
a PCLKI rising edge may occur (Figure 2).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
PD3+
LVDS
PD3-
MAX3693
4-BIT
PARALLEL
INPUT
PD2+
PD2-
LVDS
LVDS
REGISTER
PD1+
PD1-
PD0+
PD0-
LVDS
LVDS
LVDS
PCLKI+
PCLKI-
PRESCALER
SHIFT
4-BIT
SD+
SD-
SHIFT
REGISTER
PECL
RCLK+
RCLK-
PHASE/FREQ
DETECT
VCO
CONTROL
LVDS
LATCH
FIL- CKSET
FIL+
PCLKO+ PCLKO-
Figure 1. Functional Diagram
_______________________________________________________________________________________
5
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
PCLKO
t
SKEW
PCLKI
PD_
SD
t
t
H
SU
VALID PARALLEL DATA*
D3
D2
D1
D0
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-).
*PD3 = D3; PD2 = D2; PD1 = D1; PD0 = D0.
Figure 2. Timing Diagram
nation between the inverting and noninverting outputs.
Do not terminate these outputs to ground.
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3693 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifi-
cation. This technology uses 250mV to 400mV differ-
ential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immu-
nity.
The parallel data and parallel clock LVDS inputs (PD_+,
PD_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are internally
terminated with 100Ω differential input resistance, and
therefore do not require external termination.
PECL Outputs
The serial-data PECL outputs (SD+, SD-) require 50Ω
DC termination to (V
- 2V) (see the Alternative PECL-
CC
For proper operation, the parallel-clock LVDS outputs
(PCLKO+, PCLKO-) require 100Ω differential DC termi-
Output Termination section).
6
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Applications Information
Pin Configuration
Alternative PECL-Output Termination
Figure 3 shows alternative PECL output-termination
methods. Use Thevenin-equivalent termination when a
TOP VIEW
(V
- 2V) termination voltage is not available. If AC
CC
coupling is necessary, be sure that the coupling capac-
itor is placed following the 50Ω or Thevenin-equivalent
DC termination.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3693 clock and data inputs and
outputs.
16
15
14
13
12
11
10
9
V
CC
SD+
SD-
GND
RCLK+
RCLK-
25
26
27
28
29
30
31
32
V
CC
V
CC
MAX3693
V
CC
V
CC
PCLKO+
PCLKO-
GND
PCLKI+
PCLKI-
GND
+3.3V
130Ω
130Ω
TQFP
MAX3693
SD+
SD-
Z = 50Ω
0
PECL
INPUTS
___________________Chip Information
TRANSISTOR COUNT: 2925
Z = 50Ω
0
82Ω
82Ω
MAX3693
SD+
SD-
Z = 50Ω
0
HIGH-
IMPEDENCE
INPUTS
Z = 50Ω
0
50Ω
50Ω
V
CC
- 2V
Figure 3. Alternative PECL-Output Termination
_______________________________________________________________________________________
7
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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