MAX3747AEUB+ [MAXIM]
155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers;
| 型号： | MAX3747AEUB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers |
| 文件： | 总11页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
General Description
Features
The MAX3747A/MAX3747B multirate limiting amplifiers
function as data quantizers for OC-3 through OC-48 syn-
chronous optical network (SONET), Fibre-Channel, and
Gigabit Ethernet optical receivers. They are pin-for-pin
compatible with the SY88993V from Micrel
Semiconductor, Inc. The amplifiers accept a wide range
of input voltages and provide constant-level, current-
mode logic (CML) output voltages with controlled edge
speeds. The MAX3747A/MAX3747B output voltages are
o Pin Compatible with Micrel SY88993V
o 155Mbps to 3.2Gbps Operation
o > 57dB of Gain
-
12
o < 10
BER with 2mV
Input Amplitude
P-P
o 18mA Supply Current
o Chatter-Free LOS with Programmable Threshold
o Output DISABLE Function
800mV . The MAX3747B has enhanced LOS operation
P-P
under overload conditions.
o PECL-Compatible Inputs
The MAX3747A/MAX3747B limiting amplifiers feature a
programmable loss-of-signal detect (LOS) and an
optional disable function (DISABLE) that can be com-
bined to implement squelch.
Ordering Information
The MAX3747A/MAX3747B are available in a 3mm, 10-
pin µMAX® package ideal for small form-
factor receivers.
PART
MAX3747AEUB+
MAX3747BEUB+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
10 µMAX
10 µMAX
Applications
Gigabit Ethernet SFP/SFF Optical Transceiver Modules
1G/2G Fibre-Channel SFP/SFF Optical Transceiver
Modules
+Denotes a lead(Pb)-free/RoHS-compliant package.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Multirate OC-3 to OC-48 FEC SFP/SFF Optical
Transceiver Modules
Pin Configuration appears at end of data sheet.
10G LX4 Transceiver Modules
Typical Application Circuit
SFP OPTICAL RECEIVER
HOST BOARD
3-INPUT
DIAGNOSTIC
MONITOR
SUPPLY FILTER
HOST FILTER
RX
V
CC
V
CC_
DS1859
MAX4004
V
CC
MAX3747A
MAX3747B
0.1µF
0.1µF
0.1µF
0.1µF
IN+
IN-
OUT+
OUT-
50Ω
SERDES
MAX3745
50Ω
5-PIN TO-HEADER
V
TH
GND LOS DISABLE
REF
50Ω
50Ω
4.7kΩ TO 10kΩ
V HOST
CC_
LOS
R
R
TH1
0.1µF
0.1µF
TH2
R
TH1
+ R ≥ 5kΩ
TH2
V
CC
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-0281; Rev 2; 8/12
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (V ).................................-0.5V to +4.5V
Continuous Power Dissipation (T = +70°C)
A
CC
Voltage at IN+, IN- ..........................(V
- 2.4V) to (V
+ 0.5V)
+ 0.5V)
10-Pin µMAX (derate 6.9mW/°C above +70°C) ...........552mW
CC
CC
CC
Voltage at DISABLE, LOS, TH, V
..........-0.5V to (V
Operating Junction Temperature Range (T ) .......-55°C to +150°C
REF
J
Current into LOS ...................................................-1mA to +9mA
Current into V ..................................................................2mA
Storage Ambient Temperature Range (T )...........-55°C to +150°C
S
Lead Temperature (soldering, 10s)......................................+300°C
Soldering Temperature (reflow)............................................+260°C
REF
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-) ..............................................-25mA to +25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
CC
unless otherwise specified.) (Note 1)
(V
= +2.97V to +3.63V, CML output load is 50Ω to V , T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C,
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
MAX3747A including the CML output current
MAX3747B including the CML output current
36
38
41
43
MAX3747A excluding the CML output
current
Supply Current (Note 2)
I
mA
dB
CC
18
24
26
MAX3747B excluding the CML output
current
20
30
Power-Supply Noise Rejection
INPUT SPECIFICATION
Input Sensitivity
PSNR
f < 2MHz
V
(Note 3)
(Note 3)
4
mV
P-P
IN-MIN
Input Overload
V
1200
42
mV
P-P
IN-MAX
OUTPUT SPECIFICATION
Output Resistance
R
OUT
(Note 4)
50
15
58
Ω
Differential Output Return Loss
DUT is powered on, f < 3GHz
dB
MAX3747A/MAX3747B
CML Differential Output Voltage
600
800
1000
mV
mV
P-P
4mV
≤ V ≤ 1200mV
IN P-P
P-P
Differential Output Signal When
Disabled
AC-coupled outputs, V
input (Note 4)
applied to the
IN-MAX
15
P-P
Data-Output Transition Time
20% to 80% (Note 4)
70
120
ps
TRANSFER CHARACTERISTIC
K28.5 pattern at 3.2Gbps
23
13.2
14
19
25
17
150
5
PRBS 2 - 1 equivalent pattern at 2.7Gbps
(Note 6)
Deterministic Jitter (Notes 4, 5)
DJ
ps
P-P
K28.5 pattern at 2.1Gbps
12
23
PRBS 2 - 1 equivalent pattern at 155Mbps
85
(Note 6)
Random Jitter
V
= 4mV
(Notes 4, 7)
3.5
ps
RMS
IN
P-P
Maxim Integrated
2
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.97V to +3.63V, CML output load is 50Ω to V , T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C,
CC A
CC
CC
A
unless otherwise specified.) (Note 1)
PARAMETER
Input-Referred Noise
Low-Frequency Cutoff
LOS Hysteresis
SYMBOL
CONDITIONS
(Note 4)
MIN
TYP
120
6.4
MAX
150
UNITS
µV
V
= 4mV
IN
P-P
RMS
kHz
10log(V
/ V
) (Note 4)
ASSERT
1.25
2.3
dB
DEASSERT
MAX3747A (Notes 4, 8)
LOS Assert/Deassert Time
40.0
µs
MAX3747B (Notes 4, 8, 9)
Low LOS Assert Level
Low LOS Deassert Level
Medium LOS Assert Level
Medium LOS Deassert Level
High LOS Assert Level
High LOS Deassert Level
TTL/CMOS I/O
V
V
V
V
V
V
= -1.3V (Notes 4, 10)
= -1.3V (Notes 4, 10)
= -0.68V (Notes 4, 10)
= -0.68V (Notes 4, 10)
= -0.114V (Notes 4, 10)
= -0.114V (Notes 4, 10)
2.5
4.1
6.2
5.9
9.3
mV
TH
TH
TH
TH
TH
TH
P-P
P-P
P-P
P-P
P-P
P-P
mV
mV
mV
mV
mV
22.0
36.0
29.0
44.8
53.7
86.0
36.0
62.0
63.6
115
V
-
V
-
V
-
CC
CC
CC
V
Voltage
V
V
REF
REF
1.35
1.3V
1.19
LOS Output High Voltage
LOS Output Low Voltage
DISABLE Input High
V
R
R
= 4.7kΩ to 10kΩ to V
= 4.7kΩ to 10kΩ to V
(3V)
2.4
2.0
V
V
OH
LOS
CC_HOST
V
(3.6V)
0.4
OL
LOS
CC_HOST
V
V
IH
DISABLE Input Low
V
0.8
10
V
IL
DISABLE Input Current
R
LOS
= 4.7kΩ to 10kΩ to V
µA
CC_HOST
Note 1: The data-input transition time is controlled by a 4th-order Bessel filter with f
= 0.75 x 2.667GHz for all data rates of
-3dB
2.667Gbps and below. The f
= 0.75 x 3.2GHz for a data rate of 3.2Gbps.
-3db
Note 2: Supply current is measured with unterminated outputs or with AC-coupled output termination (see Figure 1).
Note 3: Between sensitivity and overload, all AC specifications are met and the output is 0.95 x limited output amplitude.
Note 4: Guaranteed by design and characterization.
Note 5: The deterministic jitter (DJ) caused by the input filter is not included in the DJ generation specification.
23
Note 6: The PRBS 2 - 1 equivalent pattern consists of a K28.5 pattern plus 240 ones plus K28.5 pattern plus 240 zeros.
Note 7: Random jitter was measured without using a filter at the input.
Note 8: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2A.
Note 9: The signal at the input is switched between 1.2V
and Signal_OFF as shown in Figure 2B.
P-P
Note 10: V is the voltage at pin 5 referenced to V
(see Figure 5).
TH
CC
Maxim Integrated
3
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
V
CC
I
CC
(SUPPLY
CURRENT)
I
OUT
(CML OUTPUT
CURRENT)
50I
50I
MAX3747A
MAX3747B
Figure 1. Power-Supply Current Measurement
V
IN
V
IN
SIGNAL_ON = 1.2V (OVERLOAD)
P-P
SIGNAL_ON
1dB
6dB
MAXIMUM DEASSERT LEVEL FOR A GIVEN V
TH
MAXIMUM DEASSERT LEVEL FOR A GIVEN R /R RATIO
TH1 TH2
MAXIMUM POWER-DETECT WINDOW
MAXIMUM POWER-DETECT WINDOW
6dB
MINIMUM ASSERT LEVEL FOR A GIVEN V
TH
MINIMUM ASSERT LEVEL FOR A GIVEN R /R RATIO
TH1 TH2
SIGNAL_OFF
SIGNAL_OFF
0V
TIME
0V
TIME
Figure 2A. LOS Deassert Threshold—Set 1dB Below Receiver
Sensitivity
Figure 2B. LOS Deassert Threshold—Operating at Input
Overload
Maxim Integrated
4
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
MAX3747A/MAX3747B toc01
MAX3747A/MAX3747B toc02
MAX3747A/MAX3747B toc03
23
23
23
3.2Gbps, 2 - 1 PRBS, 4mV
3.2Gbps, 2 - 1 PRBS, 1200mV
2.7Gbps, 2 - 1 PRBS, 4mV
P-P
P-P
P-P
60mV/div
60mV/div
60mV/div
50ps/div
50ps/div
70ps/div
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES OUTPUT CURRENT)
°
OUTPUT EYE DIAGRAM AT +100 C
MAX3747A/MAX3747B toc04
MAX3747A/MAX3747B toc05
50
45
40
35
30
25
20
15
10
23
2.125Gbps, CJTPAT, 50mV
2.7Gbps, 2 - 1 PRBS, 1200mV
P-P
P-P
60mV/div
60mV/div
80ps/div
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
70ps/div
°
TEMPERATURE ( C)
TRANSFER FUNCTION
(OUTPUT VOLTAGE vs. INPUT VOLTAGE)
RANDOM JITTER vs. TEMPERATURE
RANDOM JITTER vs. INPUT AMPLITUDE
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
1000
900
800
700
600
500
400
300
200
100
0
5
4
3
2
1
0
V
= 50mV , FREQ = 2.7Gbps
P-P
IN
3.2Gbps
MAX3747A/MAX3747B
0.3
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
0
1
2
3
4
5
1
10
100
1000
10,000
°
TEMPERATURE ( C)
DIFFERENTIAL INPUT (mV
)
DIFFERENTIAL INPUT AMPLITUDE (mV
)
P-P
P-P
Maxim Integrated
5
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Typical Operating Characteristics (continued)
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
DETERMINISTIC JITTER
vs. TEMPERATURE
BIT-ERROR RATIO vs. INPUT VOLTAGE
40
35
30
25
20
15
10
5
25
20
15
10
5
FREQ = 3.2Gbps
PATTERN = K28.5
13,000
3.2Gbps, K28.5 PATTERN
MAXIM
MAX3747A/MAX3747B
12,000
11,000
10,000
9000
8000
7000
6000
5000
4000
3000
2000
1000
1
V
= 5mV
P-P
IN
MICREL
SY88993V
V
= 500mV
IN
P-P
0
0
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1000
10,000
-40 -30-20 -10
0
10 20 30 40 50 60 70 80
DIFFERENTIAL INPUT AMPLITUDE (mV
)
°
P-P
TEMPERATURE ( C)
DIFFERENTIAL INPUT AMPLITUDE (mV
)
P-P
LOS ASSERT/DEASSERT TIMES vs. INPUT
AMPLITUDE (HIGH R /R SETTINGS)
LOS ASSERT/DEASSERT TIMES vs. INPUT
AMPLITUDE (LOW R /R SETTINGS)
ASSERT/DEASSERT vs. V
TH1 TH2
TH
TH1 TH2
40
35
30
25
20
15
10
5
120
110
100
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
V
TH
(V) = VOLTAGE AT PIN 5 (V)
MAX3747B
MAX3747B
WITH RESPECT TO V
CC
DEASSERT
LOS ASSERT
LOS DEASSERT
LOS ASSERT
LOS DEASSERT
ASSERT
0
0
0
200 400 600 800 1000 1200 1400
INPUT AMPLITUDE (mV
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2
(V)
0
0
200 400 600 800 1000 1200 1400
INPUT AMPLITUDE (mV
)
V
TH
)
P-P
P-P
OUTPUT RETURN vs. FREQUENCY (SDD22)
(INPUT SIGNAL LEVEL = -60dBm)
INPUT RETURN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -60dBm)
ASSERT/DEASSERT vs. TEMPERATURE
40
35
30
25
20
15
10
5
30
20
30
20
V
= -1.1V, FREQ = 2.7Gbps
TH
23
PATTERN = PRBS 2 - 1
10
10
0
0
DEASSERT
ASSERT
-10
-20
-30
-10
-20
-30
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
100
1000
10,000
100
1000
10,000
°
TEMPERATURE ( C)
FREQUENCY (MHz)
FREQUENCY (MHz)
Maxim Integrated
6
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Pin Description
NAME
PIN
FUNCTION
MAX3747A/
MICREL
MAX3747B
SY8893V
Disable Function Pin. The data outputs are held static when this pin is asserted high,
transistor-to-transistor logic (TTL). The data outputs are enabled when this pin is held
low. LOS functions remain active when outputs are disabled. For normal operation
connect to GND.
1
DISABLE
EN
2
3
4
IN+
IN-
DIN
Noninverted Input Signal
DIN
Inverted Input Signal
V
V
Reference Voltage for LOS Threshold Setting
Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets
REF
REF
5
6
TH
LOSLVL
GND
the threshold level. Connect one resistor from this pin to V
and another from this pin
CC
to V
(see Figure 5).
REF
GND
Ground
Loss of Signal. Open collector for the MAX3747A; internal 100kΩ pullup to V
for the
CC
MAX3747B. LOS is high when the level of the input signal drops below the preset
threshold set by the TH input. LOS is deasserted low when the signal level is above
the threshold.
7
LOS
LOS
OUT-
8
9
DOUT
Inverted Data Output, CML
Noninverted Data Output, CML
Positive Power Supply
OUT+
DOUT
10
V
V
CC
CC
Detailed Description
The limiting amplifiers consist of a multistage amplifier,
offset-correction circuitry, an output buffer, and loss-of-
signal detect circuitry (see the Functional Diagram).
V
CC
MAX3747A
MAX3747B
Input Stage
The input stage is shown in Figure 3. It provides 50Ω ter-
mination to V
for each input signal, IN+ and IN-. The
REF
MAX3747A/MAX3747B should be AC-coupled.
ESD
STRUCTURES
Multistage Amplifier
The high-bandwidth multistage amplifier provides approx-
imately 61dB of gain for the MAX3747A/MAX3747B.
Offset Correction Loop
The MAX3747A/MAX3747B are susceptible to DC offsets
in the signal path because they have high gain. In com-
munication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or gener-
ated in the transimpedance amplifier appears as an input
offset and is reduced by the offset correction loop.
50Ω
50Ω
V
REF
The offset correction loop sets a low-frequency cutoff of
3.2kHz.
Figure 3. Differential Input Stage
Maxim Integrated
7
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Functional Diagram
V
CC
MAX3747A
MAX3747B
50Ω
50Ω
DIGITAL
OFFSET
CORRECTION
OUT+
OUT-
IN+
IN-
DISABLE
50Ω
50Ω
V
REF
V
SIGNAL DETECT
TH LOS
REF
V
REF
R
TH1
R
TH2
R
+ R ≥ 5kΩ
TH2
TH1
V
CC
CML Output Buffer
V
CC
The CML outputs of the MAX3747A/MAX3747B limiting
amplifiers provide high tolerance to impedance mis-
matches and inductive connectors. The output current
is approximately 16mA for the MAX3747A/MAX3747B.
50Ω
50Ω
Connecting the DISABLE pin to V
disables the out-
CC
OUT+
OUT-
put. If the LOS pin is connected to the DISABLE pin,
the outputs OUT+ and OUT- are at a static voltage
(squelch) whenever the input signal level drops below
the LOS threshold. The output buffer can be AC- or DC-
coupled to the load (Figure 4).
DISABLE
DATA
Q3 Q4
Q1
Q2
ESD
STRUCTURES
The MAX3747A/MAX3747B output is 800mV
.
P-P
DISABLE
DISABLE
Figure 4. CML Output Buffer
Maxim Integrated
8
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Loss-of-Signal Indicator
Applications Information
Program the LOS Assert Threshold
Program the LOS assert threshold according to Figure
The MAX3747A/MAX3747B are equipped with LOS cir-
cuitry that indicates when the input signal is below a pro-
grammable threshold, set by a voltage on the TH pin
(see the Typical Operating Characteristics). The voltage
on the TH pin is set by two resistors, one connecting
5. The combination of R
and R
should be
TH2
TH1
greater than or equal to 5kΩ, see the Assert/Deassert
vs. V graph in the Typical Operating Characteristics.
TH
from the TH pin to V
and the other connecting from TH
(Figure 5). An RMS power detector compares
CC
to V
REF
Select the Coupling Capacitor
the input signal amplitude with this threshold and feeds
the signal-detect information to the LOS output, which is
open collector. To prevent LOS chatter in the region of
the programmed threshold, approximately 2dB of hys-
teresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input
amplitude rises to the required level. Figure 6 shows the
LOS output circuit.
When AC-coupling is desired, coupling capacitors C
IN
and C
should be selected to minimize the receiv-
OUT
er’s deterministic jitter. Jitter is decreased as the input
low-frequency cutoff (f ) is decreased:
IN
f
IN
= 1/[2π(50)(C )]
IN
For all applications, the recommended value for C
IN
and C
is 0.1µF, which provides f equal to 32kHz.
OUT
IN
Refer to Application Note HFAN-1.1: Choosing AC-
Coupling Capacitors on the Maxim website
(www.maximintegrated.com).
V
CC
R
R
TH2
TH1
TH
V
REF
V
= (R x (V - V )) / (R + R
)
TH
TH2
REF
CC
TH1
TH2
V
TH
IS V REFERENCED
CC
R
TH1
+ R ≥ 5kΩ
TH2
Figure 5. MAX3747A/MAX3747B LOS Threshold Circuit
V
CC
*
LOS
ESD
STRUCTURE
*100kΩ PULLUP (MAX3747B ONLY)
Figure 6. MAX3747A/MAX3747B LOS Output Circuit
Maxim Integrated
9
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Pin Configuration
Chip Information
PROCESS: SiGe Bipolar
TOP VIEW
+
DISABLE
IN+
1
2
3
4
5
10
9
V
CC
OUT+
OUT-
LOS
Package Information
MAX3747A
MAX3747B
IN-
8
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
V
7
REF
TH
6
GND
µMAX
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
21-0061
90-0330
10 µMAX
U10CN+1
Maxim Integrated
10
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Revision History
REVISION REVISION
PAGES
DESCRIPTION
NUMBER
DATE
CHANGED
0
1
2
5/05
10/07
8/12
Initial release
—
Release of the MAX3747B.
1–10
1–10
Removed MAX3747 from data sheet, updated Electrical Characteristics.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 11
© 2012 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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