MAX3748 [MAXIM]
Compact 155Mbps to 3.2Gbps Limiting Amplifier; 紧凑的155Mbps至3.2Gbps的限幅放大器
| 型号： | MAX3748 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Compact 155Mbps to 3.2Gbps Limiting Amplifier |
| 文件： | 总11页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2717; Rev 1; 7/03
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
General Description
Features
The MAX3748/MAX3748A multirate limiting amplifier func-
tions as a data quantizer for SONET, Fibre Channel, and
Gigabit Ethernet optical receivers. The amplifier accepts
a wide range of input voltages and provides constant-
level current-mode logic (CML) output voltages with con-
trolled edge speeds.
ꢀ SFP Reference Design Available
ꢀ 16-Pin QFN Package with 3mm ✕ 3mm Footprint
ꢀ Single +3.3V Supply Voltage
ꢀ 86ps Rise and Fall Time
ꢀ Loss of Signal with Programmable Threshold
ꢀ RSSI Interface (with MAX3744 TIA)
ꢀ Output Disable
A received-signal-strength indicator (RSSI) is available
when the MAX3748/MAX3748A is combined with the
MAX3744 SFP transimpedance amplifier (TIA). A receiver
consisting of the MAX3744* and the MAX3748/
MAX3748A can provide up to 19dB RSSI dynamic range.
Additional features include a programmable loss-of-signal
(LOS) detect, an optional disable function (DISABLE),
and an output signal polarity reversal (OUTPOL). Output
disable can be used to implement squelch.
ꢀ Polarity Select
ꢀ 8.5ps
Deterministic Jitter (3.2Gbps)
P-P
Ordering Information
The combination of the MAX3748/MAX3748A and the
MAX3744 allows for the implementation of all the small-
form-factor SFF-8472 digital diagnostic specifications
using a standard 4-pin TO-46 header. The MAX3748/
MAX3748A is packaged in a 3mm ✕ 3mm 16-pin QFN
package with an exposed pad.
PIN-
PACKAGE
PACKAGE
CODE
PART
MAX3748ETE
TEMP RANGE
-40°C to +85°C 16 QFN-EP*
T1633-3
T1633-3
MAX3748AETE -40°C to +85°C 16 QFN-EP*
*Future product—contact factory for availability.
*EP = Exposed pad.
Applications
Gigabit Ethernet SFF/SFP Transceiver Modules
Functional Diagram and Pin Configuration appear at end of
data sheet.
Fibre Channel SFF/SFP Transceiver Modules
Multirate OC-3 to OC-48-FEC SFF/SFP
Transceiver Modules
Typical Operating Circuits
SFP OPTICAL RECEIVER
HOST BOARD
SUPPLY FILTER
HOST FILTER
_RX
0.1
F
4-PIN TO HEADER
V
CC
OUTPOL
V
CC
CAZ1 CAZ2
0.1
0.1
F
F
IN+
IN-
OUT+
OUT-
50
50
SERDES
MAX3744 TIA*
MAX3748/
MAX3748A
RSSI TH
GND
DISABLE LOS
4.7k TO 10k
V
_HOST
CC
DS1858
R
TH
3-INPUT DIAGNOSTIC
MONITOR
LOS
R1
3k
C1
0.1
F
*FUTURE PRODUCT.
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (V ).................................-0.5V to +6.0V
Continuous Current at CML Outputs
CC
Voltage at IN+, IN- ..........................(V
Voltage at DISABLE, OUTPOL, RSSI,
- 2.4V) to (V
+ 0.5V)
(OUT+, OUT-) ...............................................-25mA to +25mA
CC
CC
Continuous Power Dissipation (T = +70°C)
A
CAZ1, CAZ2, LOS, TH............................-0.5V to (V
+ 0.5V)
16-Pin QFN (derate 17.7mW above +70°C) ....................1.4W
CC
Current into LOS ...................................................-1mA to +9mA
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Operating Junction Temperature Range (T )....-55°C to +150°C
J
Storage Ambient Temperature Range (T )........-55°C to +150°C
s
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50 to V , C = 0.1µF, typical values are at
CC
CC AZ
+25°C, V
= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f
=
CC
-3dB
UNITS
dB
0.75 ✕ 2.667GHz for all data rates of 2.667Gbps and below, and with f
= 0.75 ✕ 3.2GHz for a data rate of 3.2Gbps.)
-3dB
PARAMETER
Single-Ended Input Resistance
Input Return Loss
SYMBOL
CONDITIONS
MIN
TYP
50
MAX
Single ended to V
42
58
CC
Differential, f < 3GHz, DUT is powered on
13
Input Sensitivity
V
(Note 1)
(Note 1)
5
mV
mV
IN-MIN
P-P
P-P
Input Overload
V
1200
42
IN-MAX
Single-Ended Output Resistance
Output Return Loss
Single ended to V
50
10
58
CC
Differential, f < 3GHz, DUT is powered on
dB
Differential Output Voltage
600
780
1200
10
mV
P-P
Differential Output Signal when
Disabled
Outputs AC-coupled, V
input (Note 2)
applied to
IN-MAX
mV
P-P
K28.5 pattern at 3.2Gbps
8.5
9.3
25
223- 1 PRBS equivalent pattern at 2.7Gbps
(Note 4)
30
Deterministic Jitter
(Notes 2, 3)
DJ
ps
P-P
K28.5 pattern at 2.1Gbps
7.8
25
6.5
3
25
50
223- 1 PRBS equivalent pattern at 155Mbps
Input = 5mV
P-P
Random Jitter
(Note 5)
ps
RMS
Input = 10mV
P-P
Data Output Transition Time
Input-Referred Noise
20% to 80% (Note 2)
86
185
70
0.8
32
115
ps
µV
RMS
C
C
= open
= 0.1µF
AZ
AZ
Low-Frequency Cutoff
kHz
(Note 6)
49
37
Power-Supply Current
I
mA
dB
CC
LOS disabled
f < 2MHz
Power-Supply Noise Rejection
PSNR
26
LOSS OF SIGNAL at 2.5Gbps (Notes 2, 7)
LOS Hysteresis
10log (V
(Note 8)
/V
)
1.25
2
2.2
dB
µs
DEASSERT ASSERT
LOS Assert/Deassert Time
Low LOS Assert Level
100
R
TH
R
TH
R
TH
= 20k
2.8
4.1
6.7
mV
P-P
P-P
P-P
Low LOS Deassert Level
Medium LOS Assert Level
= 20k
= 280
11.6
mV
mV
10.3
15.2
2
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50 to V , C = 0.1µF, typical values are at
CC
CC AZ
+25°C, V
= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f
=
CC
-3dB
0.75 ✕ 2.667GHz for all data rates of 2.667Gbps and below, and with f
= 0.75 ✕ 3.2GHz for data rate of 3.2Gbps.)
-3dB
PARAMETER
Medium LOS Deassert Level
High LOS Assert Level
SYMBOL
CONDITIONS
MIN
TYP
25
MAX
UNITS
R
TH
R
TH
R
TH
= 280
= 80
= 80
38.6
mV
mV
mV
P-P
P-P
P-P
22.8
38.3
65.2
High LOS Deassert Level
99.3
LOSS OF SIGNAL at 155Mbps (Note 7)
LOS Hysteresis
10log (V
(Note 8)
/V
)
2.1
20
dB
µs
mV
DEASSERT ASSERT
LOS Assert/Deassert Time
Low LOS Assert Level
Low LOS Deassert Level
Medium LOS Assert Level
Medium LOS Deassert Level
High LOS Assert Level
High LOS Deassert Level
RSSI
R
TH
R
TH
R
TH
R
TH
R
TH
R
TH
= 20k
3.5
P-P
P-P
P-P
P-P
P-P
P-P
= 20k
= 280
= 280
= 80
5.6
mV
mV
mV
mV
mV
13.3
21.2
33.3
55.5
= 80
RSSI Current Gain (Note 9)
A
A
RSSI
= I /I
RSSI CM_RSSI
0.03
RSSI
I
I
< 6.6mA
> 6.6mA
-31
-73
+33
+90
CM_INPUT
Input-Referred RSSI Current
Stability
I
/A
RSSI RSSI
µA
(Note 10)
CM_INPUT
TTL/CMOS I/O
LOS Output High Voltage
LOS Output Low Voltage
V
R
R
R
= 4.7k to10k to V
= 4.7k to10k to V
= 4.7k to10k to V
(3V)
2.4
V
V
OH
LOS
CC_host
V
(3.6V)
(3.3V);
0.4
40
OL
LOS
CC_host
LOS
CC_host
LOS Output Current
µA
IC is powered down
DISABLE Input High
DISABLE Input Low
DISABLE Input Current
V
2.0
V
V
IH
V
0.8
10
IL
R
= 4.7k to 10k to V
µA
LOS
CC_host
Note 1: Between sensitivity and overload, all AC specifications are met.
Note 2: Guaranteed by design and characterization.
Note 3: The deterministic jitter caused by this filter is not included in the DJ generation specifications (input).
23
Note 4:
2
- 1 PRBS pattern was substituted by K28.5 pattern to determine the high-speed portion of the deterministic jitter. The
low-speed portion of the DJ (baseline wander) was obtained by measuring the eye width difference between outputs gen-
23
erated using K28.5 and 2 - 1 PRBS patterns.
Note 5: Random jitter was measured without using a filter at the input.
Note 6: The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate V
(see Figure 1).
CC
23
Note 7: Unless otherwise specified, the pattern for all LOS detect specifications is 2 - 1 PRBS.
Note 8: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2.
Note 9:
I
is the input common mode. I
is the current at the RSSI output.
CM_INPUT
RSSI
Note 10: Stability is defined as variation over temperature and power supply with respect to the typical gain of the part.
_______________________________________________________________________________________
3
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Typical Operating Characteristics
(T = +25°C and V
A
= +3.3V, unless otherwise specified.)
CC
SUPPLY CURRENT
vs. TEMPERATURE
RANDOM JITTER vs. TEMPERATURE
TRANSFER FUNCTION
(INPUT LEVEL 10mV
)
P-P
100
90
80
70
60
50
40
30
20
10
0
900
800
700
600
500
400
300
200
100
0
10
OUTPUT VOLTAGE vs. INPUT VOLTAGE
9
8
7
6
5
4
3
2
1
0
-40-30-20-10 0 10 20 30 40 50 60 70 80 90 100
TEMPERATURE ( C)
1
2
3
4
5
6
-40-30-20-10 0 10 20 30 40 50 60 70 80 90 100
TEMPERATURE ( C)
DIFFERENTIAL INPUT (mV
)
P-P
RANDOM JITTER
vs. INPUT AMPLITUDE
DETERMINISTIC JITTER vs. INPUT
BIT-ERROR RATIO vs. INPUT VOLTAGE
COMMON-MODE VOLTAGE (V TO V - 0.8V)
CC CC
10
9
8
7
6
5
4
3
2
1
0
1200
1000
800
600
400
200
0
24
22
20
18
16
14
12
10
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0
0
10
20
30
40
2.0
2.5
3.0
3.5
4.0
4.5
5.0
COMMON-MODE VOLTAGE (V + x)
CC
DIFFERENTIAL INPUT AMPLITUDE (mV
)
INPUT VOLTAGE (mV
)
P-P
P-P
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)
MAX3748 toc07
MAX3748 toc09
MAX3748 toc08
23
23
23
3.2Gbps, 2 - 1 PRBS, 5mV
P-P
2.7Gbps, 2 - 1 PRBS, 5mV
P-P
3.2Gbps, 2 - 1 PRBS, 1200mV
P-P
100mV/div
100mV/div
100mV/div
50ps/div
100ps/div
50ps/div
4
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Typical Operating Characteristics (continued)
(T = +25°C and V
A
= +3.3V, unless otherwise specified.)
CC
OUTPUT EYE DIAGRAM AT +100 C
(MINIMUM INPUT)
OUTPUT EYE DIAGRAM WITH MAXIMUM INPUT
ASSERT/DEASSERT LEVELS vs. R
(DATA RATE OF 2.6667Gbps)
TH
MAX3748 toc11
MAX3748 toc10
100
10
1
23
3.2Gbps, 2 - 1 PRBS, 5mV
23
P-P
2.7Gbps, 2 - 1 PRBS, 1200mV
P-P
DEASSERT
100mV/div
100mV/div
ASSERT
50ps/div
0.1
10
50ps/div
0.01
1
100
R
TH
(k
)
DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE
INPUT RETURN GAIN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -40dBm)
OUTPUT RETURN GAIN vs. FREQUENCY (SDD22)
(2.667Gbps, K28.5)
(INPUT SIGNAL LEVEL = -40dBm)
20
30
30
OUTPUT
18
16
14
12
10
8
DISABLED
20
10
20
10
0
0
-10
-20
-30
-40
-10
-20
-30
-40
6
4
2
0
-6
-4
-2
0
2
4
)
6
100M
1G
10G
100M
1G
10G
INPUT OFFSET VOLTAGE (mV
FREQUENCY (Hz)
P-P
FREQUENCY (Hz)
LOS HYSTERESIS vs. TEMPERATURE
(2.667bps, 210 - 1 PRBS)
RSSI CURRENT GAIN vs. INPUT TIA CURRENT
(MAX3744 AND MAX3748)
700
6
5
4
3
2
1
0
600
500
400
300
200
100
0
R
TH
= 20k
R
TH
= 80
R
TH
= 280
-40-30-20-10 0 10 20 30 40 50 60 70 80 90 100
TEMPERATURE ( C)
0
100 200 300 400 500 600 700 800 900 1000
INPUT TIA CURRENT ( A)
_______________________________________________________________________________________
5
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Pin Description
PIN
NAME
FUNCTION
1, 4, 12
V
Supply Voltage
CC
2
3
IN+
IN-
Noninverted Input Signal, CML
Inverted Input Signal, CML
Loss-of-Signal Threshold Pin. Resistor to ground (R ) sets the LOS threshold. Connecting this pin to
TH
5
TH
V
disables the LOS circuitry and reduces power consumption.
CC
Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS
function remains active when the outputs are disabled, CMOS. On the MAX3748, this pin does not
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection
is required. On the MAX3748A, this pin has ESD protection.
6
DISABLE
Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert
threshold set by the TH input. The output is open collector (Figure 5). On the MAX3748, this pin does not
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection
is required. On the MAX3748A, this pin has ESD protection.
7
LOS
8, 16
9
GND
Supply Ground
Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting amplifier
and connect to V
OUTPOL
for normal operation.
CC
10
11
OUT-
Inverted Data Output, CML
OUT+
Noninverted Data Output, CML
Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced
voltage proportional to photodiode current with the MAX3744 by connecting an external resistor between
this pin and GND.
13
14
RSSI
CAZ2
CAZ1
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ1
extends the time constant of the offset correction loop. Typical value of C is 0.1µF. The offset
AZ
correction is disabled when the CAZ1 and CAZ2 pins are shorted together.
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 extends
the time constant of the offset correction loop. Typical value of C is 0.1µF. The offset correction is disabled
AZ
when the CAZ1 and CAZ2 pins are shorted together.
15
EP
Exposed
paddle
Connect the exposed paddle to board ground for optimal electrical and thermal performance.
Detailed Description
V
CC
The limiting amplifier consists of an input buffer, a multi-
stage amplifier, offset correction circuitry, an output
buffer, power-detection circuitry, and signal-detect cir-
cuitry (see Functional Diagram).
I
(CML
OUT
OUTPUT CURRENT)
I
(SUPPLY CURRENT)
50
CC
50
Input Buffer
The input buffer is shown in Figure 3. It provides 50
termination for each input signal IN+ and IN-. The
MAX3748/MAX3748A can be DC- or AC-coupled to a
TIA (TIA output offset degrades receiver performance if
DC-coupled). The CML input buffer is optimized for the
MAX3744 TIA.
MAX3748/
MAX3748A
R
TH
Gain Stage
The high-bandwidth gain stage provides approximately
53dB of gain.
Figure 1. Power-Supply Current Measurement
6
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
V
IN
V
CC
SIGNAL ON
1dB
6dB
MAX DEASSERT LEVEL
0.25pF
50
50
IN+
IN-
POWER-DETECT WINDOW
MIN DEASSERT LEVEL
75k
0.25pF
ESD
STRUCTURES
SIGNAL OFF
TIME
0V
Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum
by Receiver Sensitivity (for Selected R
Figure 3. CML Input Buffer
)
TH
Offset Correction Loop
The MAX3748/MAX3748A is susceptible to DC offsets
in the signal path because it has high gain. In commu-
nication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or
generated in the transimpedance amplifier appears as
an input offset and is reduced by the offset correction
loop. For Gigabit Ethernet and Fibre Channel applica-
tions, no capacitor is required. For SONET applications,
V
CC
50
50
OUT+
OUT-
Q3
Q4
Q1
Q2
ESD
STRUCTURES
C
= 0.1µF is recommended. This capacitor deter-
AZ
DISABLE
DATA
mines the lower 3dB frequency of the data path.
CML Output Buffer
18mA
18mA
The MAX3748/MAX3748A limiting amplifier’s CML out-
put provides high tolerance to impedance mismatches
and inductive connectors. The output current is approx-
imately 18mA. The output is disabled by connecting the
DISABLE
DISABLE
DISABLE pin to V . If the LOS pin is connected to the
CC
DISABLE pin, the outputs OUT+ and OUT- are at a stat-
ic voltage (squelch) whenever the input signal level
drops below the LOS threshold. The output buffer can
be AC- or DC-coupled to the load (Figure 4).
Figure 4. CML Output Buffer
deassert levels. To prevent LOS chatter in the region of
the programmed threshold, approximately 2dB of hys-
teresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input
amplitude rises to the required level (V
(Figure 5).
Power-Detect and
Loss-of-Signal Indicator
)
The MAX3748/MAX3748A is equipped with an LOS cir-
cuitry, which indicates when the input signal is below a
DEASSERT
programmable threshold, set by resistor R at the TH
TH
Design Procedure
pin (see Typical Operating Characteristics for appropri-
ate resistor sizing). An averaging peak-power detector
compares the input signal amplitude with this threshold
and feeds the signal detect information to the LOS out-
put, which is open collector. Two control voltages,
Program the LOS Assert Threshold
External resistor R programs the LOS threshold. See
TH
the Assert/Deassert Levels vs. R graph in the Typical
TH
Operating Characteristics to select the appropriate
V
and V
, define the LOS assert and
DEASSERT
ASSERT
resistor.
________________________________________________________________________________________
7
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
The MAX3744 preamp measures the average photodi-
V
CC
ode current and provides the information to the output
common mode. The MAX3748/MAX3748A RSSI detect
block senses the common-mode DC level of input sig-
nals IN+ and IN- and provides a ground-referenced out-
put signal (RSSI) proportional to the photodiode current.
The advantage of this implementation is that it allows the
TIA to be packaged in a low-cost conventional 4-pin TO-
46 header.
LOS
The MAX3748/MAX3748A RSSI output is connected to
an analog input channel of the DS1858/DS1859 SFP
controller to convert the analog information into a 16-bit
word. The DS1858/DS1859 provide the receive-power
information to the host board of the optical receiver
through a 2-wire interface. The DS1859 allows for internal
calibration of the receive-power monitor.
ESD
STRUCTURE
GND
Figure 5. MAX3748 LOS Output Circuit
The MAX3744 and the MAX3748/MAX3748A have been
optimized to achieve RSSI stability of 2.5dB within the
range of 6µA to 500µA of average input photodiode
current. To achieve the best accuracy, Maxim recom-
mends receive power calibration at the low end (6µA)
and the high end (500µA) of the required range; see
the RSSI Current Gain graph in the Typical Operating
Characteristics.
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors C
IN
and C
should be selected to minimize the receiver’s
OUT
deterministic jitter. Jitter is decreased as the input low-
frequency cutoff (f ) is decreased:
IN
f
IN
= 1 / [2 (50)(C )]
IN
For ATM/SONET or other applications using scrambled
NRZ data, select (C , C 0.1µF, which provides
< 32kHz. For Fibre Channel, Gigabit Ethernet, or
)
OUT
IN
Connecting to the DS1858/DS1859
For best use of the RSSI monitor, capacitor C1 and
resistor R1 shown in the first Typical Application Circuit
need to be placed as close as possible to the Dallas
diagnostic monitor with the ground of C1 and R1 the
same as the DS1858/DS1859 ground. Capacitor C1
suppresses system noise on the RSSI signal. R1 = 3k
and C1 = 0.1µF is recommended.
f
IN
other applications using 8B/10B data coding, select
(C , C 0.01µF, which provides f < 320kHz.
)
IN
OUT
IN
Refer to Application Note HFAN-1.1: Choosing AC-
Coupling Capacitors.
Select the Offset-Correction Capacitor
The capacitor between CAZ1 and CAZ2 determines the
time constant of the signal path DC offset cancellation
loop. To maintain stability, it is important to keep a one-
decade separation between f and the low-frequency
IN
V
CC
cutoff (f ) associated with the DC offset cancellation
OC
circuit. For ATM/SONET or other applications using
scrambled NRZ data, f < 32kHz, so f
< 3.2kHz.
IN
OCMAX
= 2kHz). For Fibre Channel
Therefore, C = 0.1µF (f
AZ
OC
or Gigabit Ethernet applications, leave pins CAZ1 and
CAZ2 open.
RSSI Implementation
The SFF-8472 Digital Diagnostic specification requires
monitoring of input receive power. The MAX3748/
MAX3748A and MAX3744 receiver chipset allows for
the monitoring of the average receive power by mea-
suring the average DC current of the photodiode.
LOS
ESD
STRUCTURE
GND
Figure 6. MAX3748A LOS Output Circuit
8
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Typical Operating Circuits (continued)
SFP OPTICAL RECEIVER
HOST BOARD
V
(+3.3V OR APD
CC
V
(+3.3V)
CC
SUPPLY FILTER
HOST FILTER
REFERENCE VOLTAGE)
0.1 F
V
CC_RX
5-PIN TO HEADER
OUTPOL
V
CC
CAZ1 CAZ2
0.1 F
0.1 F
PIN OR
APD
IN+
OUT+
OUT-
50
50
SERDES
MAX3744 TIA
IN-
MAX3748/
MAX3748A
RSSI
TH
GND
DISABLE LOS
4.7k TO 10k
V
CC_HOST
DS1858
3-INPUT DIAGNOSTIC
MONITOR
R
TH
LOS
R1
3k
C1
0.1 F
SFP OPTICAL RECEIVER
HOST BOARD
V
CC
(+3.3V OR APD
REFERENCE VOLTAGE)
V
CC
(+3.3V)
HIGH-SIDE
CURRENT SENSE
SUPPLY FILTER
HOST FILTER
0.1 F
V
CC_RX
5-PIN TO HEADER
OUTPOL
V
CC
CAZ1 CAZ2
C
C
OUT
0.1 F
IN
0.1 F
PIN OR
APD
IN+
IN-
OUT+
OUT-
50
SERDES
MAX3744 TIA
50
C
C
OUT
0.1 F
IN
0.1 F
MAX3748/
MAX3748A
RSSI TH
GND
DISABLE LOS
4.7k TO 10k
V
CC_HOST
DS1858
R
TH
3-INPUT DIAGNOSTIC
MONITOR
LOS
_______________________________________________________________________________________
9
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Functional Diagram
C
AZ
V
CC
V
CC
CAZ1
CAZ2
50
50
50
50
MAX3748/
MAX3748A
OFFSET
CORRECTION
OUT-
OUT+
IN+
IN-
18mA
DISABLE
RSSI
DETECT
POWER
DETECT
RSSI
TH
LOS
OUTPOL
Pin Configuration
Chip Information
TRANSISTOR COUNT: 1468
PROCESS: SiGe Bipolar
GND CAZ1 CAZ2 RSSI
16 15 14 13
V
1
2
3
4
12
11
10
9
V
CC
CC
IN+
IN-
OUT+
MAX3748/
MAX3748A
OUT-
V
CC
OUTPOL
5
6
7
8
TH DISABLE LOS GND
3mm x 3mm QFN
10 ______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
b
0.10 M
C
A
B
D
D2/2
D/2
E/2
E2/2
-
A -
(NE - 1)
X e
C
E2
E
L
L
-
B -
k
e
C
L
(ND - 1)
X e
C
L
C
L
0.10
C
0.08
C
A
A2
A1
L
L
e
e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0136
C
2
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0136
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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