MAX3782 [MAXIM]
Dual 1.25Gbps Transceiver ; 双1.25Gbps的收发器
| 型号： | MAX3782 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual 1.25Gbps Transceiver
|
| 文件： | 总18页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2268; Rev 2; 1/03
Dual 1.25Gbps Transceiver
General Description
Features
ꢀ 1000Base-SX/LX, GBIC, or SFP Serial Data
The MAX3782 is a dual 1.25Gbps data retiming and
clock recovery transceiver. It interfaces 1.25Gbps LVDS
data and clock to a 1.25Gbps serial interface compati-
ble with 1000Base-SX/LX (IEEE 802.3z-2000) standards,
GBIC, and small form-factor pluggable (SFP) module
interface recommendations. The serial differential trans-
mitter and receiver are PECL compatible using an AC-
coupled CML interface with on-chip termination/bias
resistors for superior forward and back terminations. The
transmit path converts the LVDS signaling to CML and
retimes the serial data to a low-jitter reference clock. The
transmitter section contains LVDS buffers, FIFO, clock
multiplier, and CML output buffers. The transmitter
accepts a single 1.25Gbps serial-data channel and a
625MHz double-data-rate (DDR) clock that are compati-
ble with IEEE Std 1596-1996 DC specifications. Serial
LVDS data is clocked into the FIFO on both edges of the
625MHz source-synchronous TCLK. Data is clocked out
of the FIFO using an internal 1.25GHz clock derived
from a low-jitter 125MHz reference. Serial data is then
clocked out as differential CML.
Conversion to/from 1.25Gbps LVDS Serial Data
and DDR Clock
ꢀ CML Interface Exceeds all PECL AC
Specifications for 1000Base-SX/LX, GBIC, or SFP
Serial Data
ꢀ Tx Data Retiming with <0.1UI Total Output Jitter
as per IEEE802.3z
ꢀ Rx Data and Clock Recovery with 0.75UI Jitter
Tolerance as per IEEE802.3z
ꢀ On-Chip Forward and Back Termination Using
CML I/O and Integrated Termination/Bias
Resistors
ꢀ PLL Lock Status Indicator
ꢀ System Loopback
ꢀ JTAG I/O Scan for Board-Level Testing
Ordering Information
The receive path converts the CML signaling to LVDS
and locks on to the data stream to recover the source-
synchronous clock (RCLK). The receive section con-
tains a CML input buffer, clock recovery circuit, and
LVDS output buffers. The receiver accepts a CML serial
data stream. The clock recovery phase-locked loop
(PLL) locks on to the incoming serial data stream and
generates a 625MHz LVDS DDR clock. RCLK edges
are at the center of the “eye” of RDAT data.
PIN-
PACKAGE
PART
TEMP RANGE
PKG CODE
MAX3782UGK -5°C to +85°C 68 QFN-EP*
*EP = exposed pad.
G6800-4
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
Applications
1000Base-SX/LX Optical Links
GND
TCLK2+
TCLK2-
TDAT2+
TDAT2-
GND
1
2
3
4
5
6
7
8
9
51 GND
50 VCC1
49 TXFIL
48 GND
47 VCC4
46 TX2+
45 TX2-
44 VCC4
43 GND
42 VCC4
41 TX1+
40 TX1-
39 VCC4
38 VCC6
37 RXFIL1
36 VCC2
35 GND
GBIC Modules
SFP Fiber Transceiver Modules
TRST-JTAG
VCC5
RCLK2+
MAX3782
RCLK2- 10
RDAT2+ 11
RDAT2- 12
GND 13
LOCK 14
VCC3 15
RXFIL2 16
GND 17
Typical Application Circuit appears at end of data sheet.
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN*
*
THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND
FOR PROPER THERMAL AND ELECTRICAL OPERATION OF THE MAX3782.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 1.25Gbps Transceiver
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC1, VCC2, VCC3,
ꢁEMPSENS, RXFIL1, RXFIL2,
ꢁXFIL Voltage .........................................-0.5V to (V
VCC4, VCC5, VCC6, VCCꢁEMP) ......................-0.5V to +4.0V
+ 0.5V)
CC
LVDS Input and Output Voltage.................-0.5V to (V
LVꢁꢁL Input or Output Voltage...................-0.5V to (V
CML Input Voltage......................................-0.5V to (V
Continuous CML Output Current ......................-10mA to +25mA
Momentary CML Output Voltage
+ 0.5V)
+ 0.5V)
+ 0.5V)
Continuous Power Dissipation (ꢁ = +85°C)
A
CC
CC
CC
68-Pin QFN (derate 38.5mW/°C above +85°C) ...............2.5W
Operating Ambient ꢁemperature Range...............-5°C to +85°C
Operating Junction ꢁemperature Range.............-5°C to +150°C
Storage Ambient ꢁemperature Range...............-55°C to +150°C
ESD Human Body Model (any pin) ....................................2000V
(duration <1min, +25°C)...............................0 to (V
+ 0.5V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= 3.0V to 3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, ꢁ = -5°C to +85°C, unless otherwise
CC
A
noted. ꢁypical values are at V
= 3.3V and ꢁ = +25°C.)
CC
A
PARAMETER
Supply Current
SYMBOL
CONDITIONS
MIN
TYP
440
1.45
50
MAX
620
UNITS
mA
Power Dissipation
2.23
W
Supply Noise ꢁolerance
DC-500kHz, single-ended REFCLK (Note 1)
mV
P-P
LVTTL INPUTS AND OUTPUTS (except REFCLK )
Input High Voltage
2.0
V
Input Low Voltage
0.8
V
µA
µA
V
Input High Current
-250
-500
Input Low Current
Output High Voltage
Output Low Voltage
(Note 2)
2.4
(Note 2)
0.4
+100
400
V
ꢁhree-state enabled, 0.4V ≤ V
≤ V
-100
OUꢁ
CC
Output ꢁhree-State Current
µA
ꢁhree-state enabled, GND ≤ V
< 0.4V
OUꢁ
REFCLK INPUTS
Differential Input Amplitude
Single-Ended Input High Voltage
Single-Ended Input Low Voltage
REFCLK Input High Current
REFCLK Input Low Current
CML INPUTS (Note 3)
REFCLK AC-coupled
200
2.0
2000
mV
P-P
REFCLK- connected through 0.01µF to GND
REFCLK- connected through 0.01µF to GND
V
0.8
440
-227
V
2.0V ≤ V ≤ V
µA
µA
IN
CC
GND ≤ V ≤ 0.8V
IN
Differential Input Voltage Range
Common-Mode Voltage
Input Impedance
802.3z and GBIC compatible
Inputs open or AC-coupled
(Note 4)
370
85
2000
115
mV
P-P
V
V
- 0.3
V
CC
100
Ω
CML OUTPUTS (Note 3)
Differential Output Voltage
1100
85
2000
115
mV
P-P
Output Common-Mode Voltage
Differential Output Impedance
- 0.4
V
CC
(Note 4)
100
Ω
2
_______________________________________________________________________________________
Dual 1.25Gbps Transceiver
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.0V to 3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, ꢁ = -5°C to +85°C, unless otherwise
CC
A
noted. ꢁypical values are at V
= 3.3V and ꢁ = +25°C.)
CC
A
PARAMETER
LVDS INPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range
Differential Input Voltage
Differential Input Impedance
V
|V
|V
| < 925mV
0
2000
500
115
400
mV
mV
Ω
I
GPD
| < 925mV
|V
ID
IN
|
150
85
GPD
R
100
270
Input Common-Mode Current
LVDS OUTPUTS
V
= 1.2V, inputs tied together
µA
OS
Differential Output Voltage
Output High Voltage
|V
V
|
250
400
mV
V
OD
1.475
OH
Output Low Voltage
V
0.925
V
OL
Change in Magnitude of
Differential Output Voltage for
Complementary States
∆|V
|
25
1.275
25
mV
V
OD
Output Offset Voltage
V
1.125
80
OS
Change in Magnitude of Output
Offset Voltage for
Complementary States
∆|V
|
mV
OS
OD
Differential Output Impedance
Short-Circuit Current
R
100
120
40
Ω
Short to supply or ground
mA
Note 1: Supply noise tolerance is the amount of noise allowable on the power supply. ꢁhe intent of this is to specify the conditions
whereby the CML I/O jitter performance remains compliant with IEEE802.3z jitter specifications.
Note 2: ꢁhe LOCK output is open collector and requires a 10kΩ pullup to V . ꢁDO output load ≥ 11kΩ to V
or to GND.
CC
CC
Note 3: CML differential signal amplitudes are specified as the total signal across the load (V+ - V-). CML inputs and outputs are
designed to be AC-coupled.
Note 4: 100Ω is standard for SFP, nonstandard for IEEE802.3z and GBIC.
AC ELECTRICAL CHARACTERISTICS
(V
= 3.0V to 3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, REFCLK = 125MHz, ꢁ = -5°C to
CC
A
+85°C, unless otherwise noted. ꢁypical values are at V
= 3.3V and ꢁ = +25°C.) (Note 5)
CC
A
PARAMETER
JTAG PARAMETERS
Clock Frequency
Setup ꢁime
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
15
MHz
ns
Data input to clock positive edge
Clock positive edge to data input
15
13
7
5
Hold ꢁime
ns
Clock negative edge to data output
(C ≤ 20pF)
Propagation Delay
2
30
ns
ꢁDO Output Rise ꢁime
ꢁDO Output Fall ꢁime
C ≤ 20pF, measured 20ꢀ to 80ꢀ
C ≤ 20pF, measured 20ꢀ to 80ꢀ
2
1
20
20
ns
ns
ꢁDO Output ꢁhree-State to
Active ꢁime
C ≤ 20pF, measured as rise or fall time
1
30
ns
_______________________________________________________________________________________
3
Dual 1.25Gbps Transceiver
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.0V to 3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, REFCLK = 125MHz, ꢁ = -5°C to
CC
A
+85°C, unless otherwise noted. ꢁypical values are at V
= 3.3V and ꢁ = +25°C.) (Note 5)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOCK DETECT PARAMETERS
ꢁo assert, the ꢁx and Rx PLL internal lock
indicators must be high (lock achieved) for
this period.
Assert ꢁime
394
µs
µs
ꢁo deassert, the ꢁx or Rx PLL internal lock
indicators must be low for this period
Deassert ꢁime
1053
TRANSMITTER PARAMETERS
ꢁCLK Frequency
625
5
MHz
ns
REFCLK Input Rise/Fall ꢁime
ꢁransmitter Latency
Single ended, 20ꢀ to 80ꢀ
From ꢁDAꢁ to ꢁx
2
ns
LVDS INPUTS
Accumulated Phase Error at
ꢁCLK1 or ꢁCLK2
Relative to REFCLK
1
ns
Setup ꢁime
t
Figure 1
Figure 1
100
100
42
42
ps
ps
SU
Hold ꢁime
t
H
CML OUTPUTS
Differential Skew
25
73
20
53
ps
ꢁx Output Jitter, ꢁotal
ꢁx Output Jitter, Deterministic
ꢁx Output Jitter, Random
(Notes 6, 8)
(Notes 6, 8)
(Notes 6, 8)
32
9
ps
P-P
ps
P-P
ps
P-P
23
RECEIVER PARAMETERS (Notes 7, 8)
Input Data Rate
1.25
1
Gbps
ms
K28.5 pattern applied to Rx inputs, REFCLK
must be applied and stable
PLL Lock ꢁime
Pattern = 27 - 1, differential skew = 0,
0.938
0.885
0.838
0.694
0.45UI
of data-dependent jitter
P-P
Pattern = CRPAꢁ, differential skew = 0ps,
0.45UI of data-dependent jitter
P-P
Input Jitter ꢁolerance
(Note 9)
UI
P-P
Pattern = CRPAꢁ, differential skew = 218ps,
0.45UI of data-dependent jitter
0.776
P-P
Pattern = CJꢁPAꢁ, differential skew = 218ps,
0.248UI of pulse-width distortion (Note 10)
0.595
205
P-P
Differential Skew ꢁolerance
Jitter Generation
802.3z and GBIC compliant
ps
ps
20
5
100
P-P
Receiver Latency
From Rx to RDAꢁ
ns
4
_______________________________________________________________________________________
Dual 1.25Gbps Transceiver
AC ELECTRICAL CHARACTERISTICS (continued)
(V = 3.0V to 3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, REFCLK = 125MHz, ꢁ = -5°C to
CC
A
+85°C, unless otherwise noted. ꢁypical values are at V = 3.3V and ꢁ = +25°C.) (Note 5)
CC
A
PARAMETER
LVDS OUTPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Duty-Cycle Distortion
Variation of 50ꢀ crossing from ideal time
-32
+32
50
ps
Measured with K28.5 pattern at RDAꢁ_
outputs
Deterministic Jitter
8
ps
P-P
Edge Speed
t , t
20ꢀ to 80ꢀ
Figure 2
200
400
250
532
ps
r
f
Clock-to-Data Delay
τ
268
ps
CLK-Q
REFERENCE CLOCK REQUIREMENTS
REFCLK Frequency
125
MHz
ppm
ꢀ
REFCLK Frequency ꢁolerance
REFCLK Duty Cycle
-100
40
+100
60
210
15
ps
P-P
f < 5kHz, jitter assumed Gaussian
ps
RMS
REFCLK Jitter
f > 5kHz, jitter is assumed deterministic,
caused by power-supply noise and buffer
jitter
20
ps
P-P
Note 5: AC characteristics are guaranteed by design and characterization.
Note 6: ꢁx output jitter, total, is the sum of both deterministic (20ps max) and random (53ps max at BER = 10-12), as per
P-P
P-P
IEEE802.3z. Measured with K28.5 pattern and one-pole 637kHz highpass filter weighting.
Note 7: JIꢁꢁER ꢁESꢁ MEꢁHODS: ꢁhese are described in the draft technical report by ANSI ꢁ11.2/Project 1230, document FC-MJS,
“Fibre Channel - Methodologies for Jitter Specification.” ꢁhe maximum BER used to specify both Fibre Channel links, as
well as IEEE802.3z links is 10-12
.
Note 8: JIꢁꢁER ꢁESꢁ CONDIꢁIONS: ꢁhe difference between the MAX3782 jitter specifications and the IEEE802.3z standards (see
ꢁable 1) represents the margin that must absorb all impairments such as jitter transfer from REFCLK, power-supply noise,
and oscillator pulling (due to different ꢁx and Rx frequencies).
Note 9: Input jitter tolerance is the total amount of high-frequency jitter at the inputs. ꢁotal jitter = deterministic jitter (DJ) + random
jitter (RJ) + 5MHz sinusoidal jitter (SJ). Random jitter = 2ps
(35mUI
).
RMS
RMS
Note 10: CJꢁPAꢁ is a unique pattern, which toggles between high transition-density sections to low transition-density sections at a
rate within the loop bandwidth of a CDR. Passing this signal through a band-limited channel results in data-dependent jitter
(DDJ) that has instantaneous phase jumps occurring at the rate of transition-density change. ꢁhe phase vs. time looks like
a low-frequency square wave. A 0.5UI low-frequency square wave of jitter is the maximum that can be tolerated by an
P-P
ideal CDR. In other words, 0.5UI low-frequency square-wave jitter produces an equivalent stress as 1.0UI high-fre-
P-P
P-P
quency square-wave jitter.
_______________________________________________________________________________________
5
Dual 1.25Gbps Transceiver
t
H
= 100ps
1000mV
P-P
MAXIMUM
300mV
P-P
MINIMUM INPUT
τ
τ
CLK-Q
CLK-Q
INPUT
t
SU
= 100ps
CENTER OF RISING OR FALLING CLOCK EDGE
Figure 1. LVDS Receiver Input Eye Mask
Figure 2. Definition of Clock-to-Data Delay
Typical Operating Characteristics
(V
= 3.3V, ꢁ = +25°C, unless otherwise noted.)
CC
A
TRANSMITTER JITTER TRANSFER
(REFLCK TO TX_)
RECEIVER JITTER TRANSFER
(RX_ TO RCLK)
SUPPLY CURRENT vs. TEMPERATURE
800
2
0
2
0
750
700
650
600
550
500
450
400
-2
-2
-4
-4
-6
-6
-8
-8
-10
-10
0
10 20 30 40 50 60 70 80
0.1
1
10
100
1k
10k
1
10
100
1k
10k
AMBIENT TEMPERATURE (°C)
JITTER FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
TRANSMIT CLOCK SYNTHESIZER
POWER-SUPPLY REJECTION RATIO
TEMPSENS VOLTAGE
vs. TEMPERATURE
RECEIVER POWER-SUPPLY
REJECTION RATIO
1
450
430
410
390
370
350
330
310
290
270
250
1
WITHOUT HIGHPASS WEIGHTING
0.1
0.01
0.1
637kHz HIGHPASS WEIGHTING
AS PER IEEE802.3z METHOD
0.001
0.0001
0.01
100 120
140
100
1k
10k
100k
0
20 40 60 80
0.1
1
10
100
1000
FREQUENCY (Hz)
JUNCTION TEMPERATURE (°C)
NOISE FREQUENCY (MHz)
6
_______________________________________________________________________________________
Dual 1.25Gbps Transceiver
Typical Operating Characteristics (continued)
(ꢁ = +25°C, unless otherwise noted.)
A
VCO AND VCO
PULLING TO VCO
VCO AND VCO
PULLING TO VCO
VCO
PULLING TO VCO
AND VCO
RX1 RX2
TX
RX2
RX1
TX
RX1
RX2
TX
16
14
12
10
8
14
12
10
8
30
25
20
15
10
WITHOUT HIGHPASS WEIGHTING
6
6
4
2
0
4
5
0
2
637kHz HIGHPASS WEIGHTING
AS PER IEEE802.3z METHOD
0
0
100
200
300
400
500
600
0
100
200
300
400
500
600
0
100
200
300
400
500
600
FREQUENCY DIFFERENCE (ppm)
FREQUENCY DIFFERENCE (ppm)
FREQUENCY DIFFERENCE (ppm)
INPUT EYE
SINUSOIDAL JITTER TOLERANCE
vs. FREQUENCY
(DJ = 0.4UI , SJ = 0.5UI AT 5MHz,
P-P
P-P
RECOVERED EYE
7
2 -1 PRBS)
100
10
1
WITH 0.4 UI OF DATA-DEPENDENT
P-P
7
JITTER PRESENT, PATTERN = 2 - 1 PRBS
100mV/
div
100mV/
div
0.1
200ps/div
200ps/div
10k
100k
1M
10M
JITTER FREQUENCY (Hz)
5MHz JITTER TOLERANCE
vs. INPUT AMPLITUDE
REFCLK TO TCLK ACCUMULATED
PHASE-ERROR TOLERANCE
1
2000
1500
1000
500
WITH 0.4UI OF DATA-DEPENDENT
P-P
7
JITTER PRESENT, PATTERN = 2 - 1 PRBS
ERROR-FREE OPERATION
REFCLK ALIGNED TO TCLK
0
-500
-1000
-1500
-2000
-2500
0.1
1
10
100
1000
10,000
0
100 200 300 400 500 600 700 800
PHASE AT RESET (ps)
INPUT AMPLITUDE (mV
)
P-P
_______________________________________________________________________________________
7
Dual 1.25Gbps Transceiver
Pin Description
PIN
NAME
FUNCTION
1, 6, 13,
17, 21, 26,
31, 35, 43,
48, 51, 58,
62
GND
Supply Ground
ꢁransmitter Positive Clock Input 2, LVDS. Input data is clocked on both the rising and falling edges of
the 625MHz clock.
2
3
ꢁCLK2+
ꢁCLK2-
ꢁransmitter Negative Clock Input 2, LVDS. Input data is clocked on both the rising and falling edges of
the 625MHz clock.
4
5
ꢁDAꢁ2+
ꢁDAꢁ2-
ꢁransmitter Positive Data Input 2, LVDS
ꢁransmitter Negative Data Input 2, LVDS
JꢁAG ꢁest Reset Input, LVꢁꢁL. Momentarily connect TRST to GND to reset JꢁAG test circuitry.
Internally pulled high through 15kΩ resistor.
7
TRST-JTAG
VCC5
8, 22, 25,
27, 30, 67
3.3V Supply for Receiver Digital Functions and JꢁAG Circuitry
Receiver Positive Clock Output 2, LVDS. Output data is clocked on both the rising and falling edges of
the 625MHz clock.
9
RCLK2+
RCLK2-
Receiver Negative Clock Output 2, LVDS. Output data is clocked on both the rising and falling edges
of the 625MHz clock.
10
11
12
RDAꢁ2+
RDAꢁ2-
Receiver Positive Data Output 2, LVDS
Receiver Negative Data Output 2, LVDS
Lock Status Indicator Output, LVꢁꢁL. ꢁhis output goes high when the transmit PLL and receiver PLLs
are in lock. Because this output is open-collector ꢁꢁL, the LOCK pins from multiple MAX3782s can be
connected in parallel to form a single LOCK signal.
14
LOCK
15
16
18
19
20
23
24
28
29
32
VCC3
RXFIL2
3.3V Supply for RX2 Receiver VCO, Analog Receiver Functions, and External Loop-Filter Connection
RX2 Receiver Loop-Filter Connection. Connect a 0.1µF capacitor between RXFIL2 and VCC3.
JꢁAG ꢁest Data Input, LVꢁꢁL. Internally pulled high through 15kΩ resistor.
ꢁDI-JꢁAG
ꢁMS-JꢁAG JꢁAG ꢁest Mode Select Input, LVꢁꢁL. Internally pulled high through 15kΩ resistor.
ꢁCLK-JꢁAG JꢁAG ꢁest Clock Input, LVꢁꢁL. Internally pulled high through 15kΩ resistor.
RX1+
RX1-
Receiver Positive Input 1, CML
Receiver Negative Input 1, CML
RX2+
Receiver Positive Input 2, CML
RX2-
Receiver Negative Input 2, CML
VCCꢁEMP
3.3V Supply for ꢁEMPSENS. Connect to ground to disable the temperature-sensing function.
Junction ꢁemperature Sensor Output, Analog. ꢁEMPSENS corresponds to the junction temperature of
the die. Leave open for normal use.
33
34
ꢁEMPSENS
Loopback Enable Input, LVꢁꢁL. Force low to enable system loopback. Internally pulled high through
15kΩ.
LOOPEN
36
37
VCC2
RXFIL1
VCC6
3.3V Supply for RX1 Receiver VCO, Analog Receiver Functions, and External Loop-Filter Connection
RX1 Receiver Loop-Filter Connection. Connect a 0.1µF capacitor between RXFIL1 and VCC2.
3.3V Supply for ꢁransmitter Digital Functions
38, 53, 61
39, 42, 44,
47
VCC4
3.3V Supply for CML Outputs
8
_______________________________________________________________________________________
Dual 1.25Gbps Transceiver
Pin Description (continued)
PIN
40
41
45
46
49
50
NAME
ꢁX1-
FUNCTION
ꢁransmitter Negative Output 1, CML
ꢁX1+
ꢁX2-
ꢁransmitter Positive Output 1, CML
ꢁransmitter Negative Output 2, CML
ꢁX2+
ꢁXFIL
VCC1
ꢁransmitter Positive Output 2, CML
ꢁransmitter Loop-Filter Connection. Connect a 0.1µF capacitor between ꢁXFIL and VCC1.
3.3V Supply for ꢁransmitter VCO, Analog ꢁransmitter Functions, and External Loop-Filter Connection
Reset Input, LVꢁꢁL. Connect low for >80ns to reset FIFO and receiver components. Internally pulled
high through 15kΩ.
52
54
55
RESET
ꢁCLK1+
ꢁCLK1-
ꢁransmitter Positive Clock Input 1, LVDS. Input data is clocked on both the rising and falling edges of
the 625MHz clock.
ꢁransmitter Negative Clock Input 1, LVDS. Input data is clocked on both the rising and falling edges of
the 625MHz clock.
56
57
59
60
ꢁDAꢁ1+
ꢁDAꢁ1-
ꢁransmitter Positive Data Input 1, LVDS
ꢁransmitter Negative Data Input 1, LVDS
REFCLK+ Reference Clock Positive Input. See specification table for differential or single-ended use.
REFCLK-
Reference Clock Negative Input. See specification table for differential or single-ended use.
Receiver Positive Clock Output 1, LVDS. Output data is clocked on both the rising and falling edges of
the 625MHz clock.
63
64
RCLK1+
Receiver Negative Clock Output 1, LVDS. Output data is clocked on both the rising and falling edges of
the 625MHz clock.
RCLK1-
65
66
68
RDAꢁ1+
RDAꢁ1-
Receiver Positive Data Input 1, LVDS
Receiver Negative Data Input 1, LVDS
ꢁDO-JꢁAG JꢁAG ꢁest Data Output, ꢁhree-State LVꢁꢁL
Supply Ground. ꢁhe exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance. See Exposed-Pad Package. ꢁhe MAX3782 uses exposed pad variation G6800-4 in
the package outline drawing.
Exposed
Pad
EP
_______________________________________________________________________________________
9
Dual 1.25Gbps Transceiver
TMS-
JTAG
TDI-
JTAG
TRST-
JTAG
TCLK-
JTAG
V
CC
GND
TXFIL
TTL
TTL
TTL
TTL
+
1.25GHz
PLL CLOCK
MULTIPLIER
REFCLK
TDAT1
TTL
TDO-TJAG
TTL
-
JTAG CONTROL CIRCUITRY
TX_LOCK (INTERNAL)
REFCLK (INTERNAL)
Q
+
D
D
Q
LVDS
-
FIFO
CML
TX1
+
TCLK1
RESET
LVDS
625MHz
DDR
-
RESET
(INTERNAL)
TTL
+
TDAT2
TCLK2
LVDS
D
D
Q
Q
-
FIFO
TX2
CML
+
LVDS
625MHz
DDR
-
0
1
Q
D
+
LVDS
RDAT1
RCLK1
CML
RX1
-
PLL CLOCK
RECOVERY
625MHz
DDR
DIVIDE BY 2
LVDS
RXFIL1
REFCLK
(INTERNAL)
LOOPEN
LOCK
TTL
MAX3782
RESET
(INTERNAL)
TX_LOCK (INTERNAL)
D
0
1
Q
+
RDAT2
RCLK2
LVDS
LVDS
CML
RX2
-
PLL CLOCK
RECOVERY
625MHz
DDR
DIVIDE BY 2
RXFIL2
REFCLK
(INTERNAL)
Figure 3. Functional Diagram
10 ______________________________________________________________________________________
Dual 1.25Gbps Transceiver
tion. ꢁhe LVDS outputs are designed to drive 100Ω dif-
Detailed Description
ferential loads and are not designed to drive 50Ω to
ꢁhe MAX3782 dual 1.25Gbps transceiver is a data
retimer and clock recovery device for 1000Base-SX/LX,
GBIC, and SFP applications. In the transmitter, an inte-
grated clock synthesizer generates a clean 1.25GHz
clock. ꢁhis clock is used with a FIFO to retime the data
before transmission. CML output buffers provide excel-
lent performance with minimal external components.
ground.
PLL Clock Multiplier
ꢁhe PLL clock multiplier uses the 125MHz reference
clock to synthesize the 1.25GHz clock that synchro-
nizes the transmitter functions. ꢁhe reference clock also
aids frequency acquisition in the receiver. ꢁo achieve
proper jitter performance and BER benchmarks, using
a high-quality, low-jitter reference clock is critical.
REFCLK inputs can be driven differentially or single
ended. Differential operation is recommended for its
superior jitter performance and noise immunity.
ꢁhe receiver has two separate PLL clock recovery cir-
cuits, allowing independent recovery of each received
data signal. ꢁhe receiver has CML inputs, easing sys-
tem design and decreasing component count.
JꢁAG functionality is included to help with board-level
testing. A LOCK pin indicates the status of the internal
PLLs. System loopback may be asserted with the
LOOPEN input.
PLL Clock Recovery
Both receive channels (RX1 and RX2) use PLLs to
recover synchronous clocks from the incoming serial
data. ꢁhe recovered clocks are then used to retime the
serial data. ꢁhe typical loop bandwidth of the PLL clock
recovery circuits is 1.5MHz.
LVDS Inputs and Outputs
ꢁhe MAX3782 LVDS interface includes two differential
data inputs at 1.25Gbps, two half-rate differential clock
inputs at 625MHz, two differential data outputs at
1.25Gbps, and two half-rate differential clock outputs at
625MHz. ꢁhe MAX3782 LVDS-compatible interface is
designed to work with the user’s ASICs, minimize
power dissipation, speed transition time, and improve
noise immunity. ꢁhe LVDS outputs also have short-
circuit protection in case of shorts to VCC or GND. ꢁhe
LVDS inputs must be DC-coupled for proper biasing.
AC-coupling these inputs results in unreliable opera-
CML Inputs and Outputs
ꢁhe CML inputs and outputs of the MAX3782 offer low
power dissipation, excellent performance, and integrat-
ed termination resistors. AC-coupling capacitors should
be used for PECL and IEEE802.3z compatibility.
Figure 4 shows interface examples. ꢁhe CML output
structure is shown in Figure 5, and the CML input struc-
ture is shown in Figure 6. For more information, refer to
0.01µF
OPTIONAL
CML
ECL OR
PECL
W/ 100Ω
BACK TERM
Z
0
= 100Ω
0.01µF
0.01µF
CML TO PECL
50Ω
50Ω
BIAS
OPTIONAL
CML
ECL OR
OPTIONAL
PECL
W/ 100Ω
Z
0
= 100Ω
END TERM
0.01µF
PECL TO CML
CURRENT
SET
CURRENT
SET
0.01µF
0.01µF
OPTIONAL
CML
CML
W/ 100Ω
END TERM
W/ 100Ω
Z
= 100Ω
0
BACK TERM
CML TO CML
Figure 4. CML I/O Interconnect Examples
______________________________________________________________________________________ 11
Dual 1.25Gbps Transceiver
MAX3782
V
CC
VCC
2kΩ
50Ω
50Ω
MAX3782
OUT+
OUT-
50Ω
50Ω
IN+
IN-
32mA
Figure 5. CML Output Structure
the applications note HFAN-01.0, Introduction to LVDS,
PECL, and CML.
GND
Lock Detection
ꢁhe LOCK output indicates the state of the transmitter
and receiver PLLs. For lock detect to be asserted high,
the transmitter and receiver internal lock indicators
must be high for 394µs. ꢁhe internal lock signals go
high once frequency lock has been achieved. For lock
detect to be asserted low, either the transmitter or
receiver internal lock indicators must be low for a mini-
mum of 1053µs. Lock detect also is asserted low when
the external reset pin is forced low. LOCK stays low for
a minimum of 394µs. For the lock detector to function
properly, there must be data transitions at the RX1 and
RX2 inputs and a valid reference clock input. Note: ꢁhe
LOCK output is not an accurate indicator of signal
presence at the receiver inputs. With no data input, the
LOCK output can be high, low, or toggling. ꢁhe output
structure of the LOCK pin is shown in Figure 7.
Figure 6. CML Input Structure
portional to the die junction temperature (1mV per
Kelvin). ꢁhe temperature of the die can be calculated
as:
1°C
mV
ꢁ(°C) ≈ V
(mV) ×
−273°C
ꢁEMPSENS
V
CC
MAX3782
R
=
LOAD
RESET Input
RESET must be held low for a minimum of four reference
clock cycles for it to be properly asserted. Approximately
10ms or longer after power up, the RESET input should
be asserted low. RESET resets the LOCK state and FIFO
clock logic.
10kΩ
100Ω
LOCK
Temperature Sensor
ꢁo help evaluate thermal performance, a temperature
sensor is incorporated into the MAX3782. ꢁhe tempera-
ture sensor may be powered on or off regardless of the
state of the rest of the chip. ꢁhe VCCꢁEMP pin provides
supply voltage for the temperature sensor circuit. ꢁhe
ꢁEMPSENS output is designed to output a voltage pro-
Figure 7. LOCK Output Structure
12 ______________________________________________________________________________________
Dual 1.25Gbps Transceiver
Layout Techniques
Applications Information
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground connec-
tions short, and use multiple vias where possible. Use
controlled-impedance 50Ω transmission lines to interface
with the MAX3782 high-speed inputs and outputs.
Jitter Budget Example
for Optical Link
ꢁhe MAX3782 outperforms IEEE802.3z jitter specifica-
tions. See Figure 8 and ꢁable 1.
Place power-supply decoupling capacitors as close to
CC
input signals from the output signals.
JTAG
JꢁAG functionality is compliant with IEEE1149.1 specifi-
cations. ꢁhe BSDL file is available on request. ꢁable 2
provides JꢁAG pin assignments.
V
as possible. ꢁo reduce feedthrough, isolate the
TP1
TP2
E/O
O/E
MAX3782
MAX3782
Figure 8. Optical Link
Table 1. Comparison of IEEE802.3z and MAX3782 Jitter Budget
TOTAL JITTER (ps
)
DETERMINISTIC JITTER (ps
)
P-P
P-P
COMPLIANCE POINT
IEEE802.3z
MAX3782
IEEE802.3z
MAX3782
SPECIFICATION
SPECIFICATION
SPECIFICATION
SPECIFICATION
73 (max)
32 (typ)
20 (max)
9 (typ)
ꢁP1
COMPLIANCE POINT
ꢁP2
192
100
TOTAL JITTER TOLERANCE (ps
)
P-P
IEEE802.3z
SPECIFICATION
MAX3782
SPECIFICATION
620 (min, CRPAꢁ)
670 (typ, CRPAꢁ)
—
600
______________________________________________________________________________________ 13
Dual 1.25Gbps Transceiver
Table 2. JTAG Pin Assignments
ROUTING
MAX3782
PIN NAME
BOUNDARY SCAN
PORT NAME
I/O TYPE
CELL TYPE
IN
OUT
LOCK
RX2+
lock
rx2p
Open Collector Output Observe and Control
1
CML Input
CML Input
Observe
2
2
3
3
4
5
5
6
6
7
7
8
8
RX2-
rx2n
Observe
RX1+
rx1p
CML Input
Observe
RX1-
rx1n
CML Input
Observe
LOOPEN
ꢁDAꢁ2+
ꢁDAꢁ2-
loopen_bar
tdat2p
tdat2n
tck2p
tck2n
tdat1p
tdat1n
tck1p
tck1n
tx1p
LVꢁꢁL Input
LVDS Input
LVDS Input
LVDS Input
LVDS Input
LVDS Input
LVDS Input
LVDS Input
LVDS Input
CML Output
CML Output
CML Output
CML Output
LVꢁꢁL Input
LVꢁꢁL Input
LVꢁꢁL Input
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
Observe
Observe
Observe
ꢁCLK2+
ꢁCLK2-
Observe
Observe
ꢁDAꢁ1+
ꢁDAꢁ1-
Observe
Observe
ꢁCLK1+
ꢁCLK1-
Observe
Observe
ꢁX1+
Observe and Control
Observe and Control
Observe and Control
Observe and Control
Observe
9
9
ꢁX1-
tx1n
ꢁX2+
tx2p
10
10
ꢁX2-
tx2n
RESET
reset_bar
refckp
refckn
rck1p
rck1n
rdat1p
rdat1n
rck2p
rck2n
rdat2p
rdat2n
11
12
12
REFCLK+
REFCLK-
RCLK1+
RCLK1-
RDAꢁ1+
RDAꢁ1-
RCLK2+
RCLK2-
RDAꢁ2+
RDAꢁ2-
JTAG CONTROL PINS
ꢁCLK-JꢁAG
ꢁDI-JꢁAG
ꢁDO-JꢁAG
ꢁMS-JꢁAG
TRST-JTAG
Observe
Observe
Observe and Control
Observe and Control
Observe and Control
Observe and Control
Observe and Control
Observe and Control
Observe and Control
Observe and Control
13
13
14
14
15
15
16
16
tck
tdi
LVꢁꢁL Input
LVꢁꢁL Input
LVꢁꢁL Output
LVꢁꢁL Input
LVꢁꢁL Input
tdo
tms
trst_bar
14 ______________________________________________________________________________________
Dual 1.25Gbps Transceiver
Table 3. JTAG Instructions
JTAG
INSTRUCTION
ACTION
OPCODE
EXꢁESꢁ
000 b
001 b
111 b
010 b
External boundary test mode
SAMPLE/PRELOAD
BYPASS
Initialization for boundary test mode
Connects bypass register between ꢁDI and ꢁDO
32-bit device ID register selected (see ꢁable 4)
IDCODE
Table 4. Device Identification Code
CODE
VERSION
PART NO.
MANUFACTURER = MAXIM
LSB
0000 1110 1100 0110 b
00011001011 b
[ ref: JEDEC JEP106-I ]
Binary
0001 b
1 b
[ = 3782
]
base10
Exposed-Pad Package
Chip Information
ꢁhe exposed-pad, 68-pin QFN-EP incorporates features
that provide a very low thermal-resistance path for heat
removal from the IC. ꢁhe EP and EP ring are electrical
ground on the MAX3782 and must be soldered to the cir-
cuit board for proper thermal and electrical performance.
Refer to HFAN 08.10, Thermal Considerations of QFN
and Other Exposed-Pad Packages, for more information.
ꢁRANSISꢁOR COUNꢁ: 14329
PROCESS: Silicon bipolar
______________________________________________________________________________________ 15
Dual 1.25Gbps Transceiver
Typical Application Circuit
1.25Gbps
1.25Gbps
LVDS
GBIC AND
IEEE802.3z
1000BASE-SX/LX
COMPATIBLE
TCLK1
TDAT1
TX1
GBIC OR SFP
OPTICAL MODULE
TCLK2
TDAT2
RX1
CMOS
ASIC
TX2
RX2
GBIC OR SFP
OPTICAL MODULE
RCLK1
RDAT1
RCLK2
RDAT2
MAX3782
VCC2 VCC3
VCC1
LOOPEN
0.1µF
0.1µF
0.1µF
RESET
RXFIL1
RXFIL2
LOCK
TXFIL
REFCLK
125MHz
REFERENCE
CLOCK
TMS-JTAG
TDI-TJAG
TRST-JTAG
TDO-JTAG
TCLK-JTAG
16 ______________________________________________________________________________________
Dual 1.25Gbps Transceiver
Package Information
(ꢁhe package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 17
Dual 1.25Gbps Transceiver
Package Information (continued)
(ꢁhe package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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