MAX3805 [MAXIM]
10.7Gbps Adaptive Receive Equalizer; 10.7Gbps之间的自适应接收均衡器
| 型号： | MAX3805 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10.7Gbps Adaptive Receive Equalizer |
| 文件： | 总10页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2936; Rev 0; 7/03
10.7Gbps Adaptive Receive Equalizer
General Description
Features
The MAX3805 is designed to provide up to 30in
(0.75m) reach on 6-mil differential FR-4 transmission
line, or up to 24ft (8m) on RG-188A/U type coaxial
cable, for PRBS data from 9.95Gbps to 10.7Gbps. The
MAX3805 adaptive equalizer reduces intersymbol inter-
ference, resulting in 20ps residual jitter after equaliza-
tion. An internal feedback network controls the
equalizer to automatically match frequency-dependent
skin effect and dielectric losses. The MAX3805 pro-
vides LVCMOS-compatible output-enable and signal-
detect functions.
ꢀ 3mm x 3mm Package
ꢀ Spans 30in (0.75m) of 6-mil FR-4
ꢀ Spans 24ft (8m) of Coax
ꢀ Automatic Receive Equalization to Reduce ISI
Caused by Path Losses
ꢀ Up to 10.7Gbps NRZ Data Operating Range
ꢀ Signal-Detect Output
ꢀ Output-Enable Control
The MAX3805 has separate supply connections for the
internal logic and I/O circuits. This allows the current-
mode logic (CML) input and CML output to be connect-
ed to isolated supplies for independent DC-coupled
interfaces to 1.8V, 2.5V, or 3.3V ICs. The MAX3805
comes in a very small 3mm x 3mm package and con-
sumes only 135mW.
ꢀ 135mW Power Consumption
ꢀ DC-Coupled Input and Output to Terminations as
Low as 1.65V
ꢀ Differential or Single-Ended Operation
ꢀ +3.3V Core Power Supply
Ordering Information
Applications
PIN-
PACKAGE
PACKAGE
CODE
PART
TEMP RANGE
OC-192, 10GbE Switches and Routers
OC-192, 10GbE Serial Modules
High-Speed Signal Distribution
MAX3805ETE -40°C to +85°C 16 Thin QFN
T1633F-3
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
LINE CARD
SWITCH CARD
2.5V
1.8V
+3.3V
10Gbps
CDR/SERDES
10Gbps
SWITCH
V
CC1
V
CC
V
CC2
MAX3805
Tx
SDI
Rx
FR-4 STRIPLINE
SDO
2
2
2
2
SD EN
+3.3V
V
CC
2
2
2
2
MAX3805
Rx
FR-4 STRIPLINE
SDO
SDI
Tx
V
CC2
SD EN V
CC1
2.5V
1.8V
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10.7Gbps Adaptive Receive Equalizer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) ............................................-0.5V to +4.0V
Continuous Power Dissipation (T = +85°C)
A
CC
CML Supply Voltage
16-Lead QFN-EP (derate 17.5mW/°C
(V
, V ) ..........................................-0.5V to (V
CC1 CC2
+ 0.5V)
CC
above +85°C) ............................................................1398mW
Operating Ambient Temperature Range.............-40°C to +85°C
Storage Ambient Temperature Range...............-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Current at SDO ............................................................... 25mA
SDI , EN, SD, HFPD, LFPD........................-0.5V to (V + 0.5V)
Current at HFPD, LFPD......................................................400µA
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER
SYMBOL
CONDITIONS
MIN
3.0
TYP
MAX
UNITS
Supply Voltage
V
3.3
3.6
V
V
CC
Input Termination Voltage
V
V
1.65
1.65
-40
V
V
CC1
CC2
CC
CC
Output Termination Voltage
Operating Ambient Temperature
V
+25
+85
°C
ELECTRICAL CHARACTERISTICS
(Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at V
= +3.3V, V
= V = 1.8V, T = +25°C, unless
CC2 A
CC
CC1
otherwise noted.) (Values at -40°C are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS
Supply Current = V
MIN
TYP
MAX
UNITS
I
V
= V
41
60
mA
CC
CC
CC1
CC2
AC-coupled or DC-coupled at transmission
line input (Notes 1, 6)
CML Input Differential Voltage
V
400
1200
mV
P-P
IN
CML Input Common-Mode
Voltage
1.3
85
V
V
CC1
CML Input Resistance
CML Input Return Loss
CML Output Differential Voltage
CML Output Resistance
CML Output Transition Time
CML Output Return Loss
Equalizer Time Constant
Output Residual Jitter
Differential
100
10
115
Ω
100MHz to 10GHz
dB
V
V
= 1.65V to 3.6V
400
85
500
100
600
115
35
mV
P-P
OUT
CC2
Differential
Ω
t /t
20% to 80% (Notes 2, 6)
100MHz to 5GHz
ps
dB
µs
r f
10
10
(Notes 3–6)
21
30
ps
P-P
31
Signal-Detect Assert
PRBS2 - 1 at 10.7Gbps (Note 1)
200
220
mV
mV
P-P
P-P
31
Signal-Detect Deassert
PRBS2 - 1 at 10.7Gbps (Note 1)
LVCMOS Input-High Leakage
Current
I
H
+10
+60
µA
2
_______________________________________________________________________________________
10.7Gbps Adaptive Receive Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at V
= +3.3V, V
= V = 1.8V, T = +25°C, unless
CC2 A
CC
CC1
otherwise noted.) (Values at -40°C are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
-30
1.5
TYP
MAX
UNITS
LVCMOS Input-Low Leakage
Current
I
+30
µA
L
LVCMOS Input High
LVCMOS Input Low
LVCMOS Output High
LVCMOS Output Low
V
V
V
V
V
IH
V
0.5
0.2
IL
V
I
I
= 12.5µA
= 0.5mA
2.1
OH
OH
V
OL
OL
Note 1: Differential input sensitivity is defined at the input to a transmission line with path length up to 30in.
Note 2: Measured using 10 ones and 10 zeros at 10.7Gbps.
Note 3: Residual jitter is the difference in total jitter between the signal at the input to the transmission line and the equalizer output.
Total residual jitter is DJ + 14.1 × RJ
.
RMS
P-P
10
10
Note 4: Measured at 10.7Gbps using a pattern of 100 ones, PRBS 2 - 1, 100 zeros, PRBS 2 - 1.
Note 5: V = 400mV
Note 6: Guaranteed by design and characterization.
to 1200mV , input path is 0 to 30in, 6-mil microstrip in FR-4, ε = 4.5, and tan δ = 0.02.
IN
P-P
P-P
r
Typical Operating Characteristics
(V
= 3.3V, V
= 1.8V, V
= 1.8V, and T = +25°C, unless otherwise noted.)
CC2 A
CC
CC1
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
EQUALIZER INPUT EYE AFTER 30in OF FR-4
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(210 - 1PRBS WITH 100 CIDs AT 9.953Gbps)
(210 - 1PRBS WITH 100 CIDs AT 9.953Gbps)
(231 - 1PRBS AT 10.7Gbps)
MAX3805 toc02
MAX3805 toc01
MAX3805 toc03
65mV/div
65mV/div
65mV/div
20ps/div
20ps/div
20ps/div
_______________________________________________________________________________________
3
10.7Gbps Adaptive Receive Equalizer
Typical Operating Characteristics (continued)
(V
= 3.3V, V
= 1.8V, V
= 1.8V, and T = +25°C, unless otherwise noted.)
CC
CC1
CC2
A
EQUALIZER OUTPUT EYE AFTER
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(CJTPAT 10.0Gbps LFPD/(HFPD + LFPD) = 0.6)
24ft OF RG-188/U COAXIAL CABLE,
SINGLE ENDED (223 - 1PRBS AT 10.7Gbps)
SUPPLY CURRENT vs. TEMPERATURE
MAX3805 toc04
MAX3805 toc05
65
60
55
50
45
40
35
V
CC
= V
= V
= +3.3V
CC1
CC2
65mV/div
65mV/div
20ps/div
20ps/div
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
RESIDUAL JITTER
vs. FR-4 PATH LENGTH
RESIDUAL JITTER vs. AMPLITUDE
50
50
45
40
35
30
25
DATA RATE = 10.7Gbps
PATTERN = PRBS 210 -1
= 400mV
DATA RATE = 9.953Gbps
PATTERN = PRBS 210 -1
45
40
35
30
25
20
15
V
IN
P-P
RESIDUAL JITTER = DJ + 14.1 x RJ
FR4 = 30in
20
15
RESIDUAL JITTER = DJ + 14.1 x RJ
FR4 = 18in
3
6
9
12 15 18 21 24 27 30
FR-4 PATH LENGTH (in)
400 500 600 700 800 900 1000 1100 1200
AMPLITUDE (mV
)
P-P
RESIDUAL JITTER
vs. R
/(R
+ R
)
LFPD HFPD
LFPD
RESIDUAL JITTER vs. DATA RATE
50
45
40
35
50
45
40
35
30
25
20
15
10
V
= 400mV
V
IN
= 400mV
IN
P-P
P-P
PATTERN = 100 1's PRBS 210-1
PATTERN = CJTPAT
100 0's PRBS 210-1
DATA RATE = 10.0Gbps
(R
+ R ) = 100kΩ
RESIDUAL JITTER = DJ + 14.1 x RJ
LFPD
HFPD
18in FR4
30
25
30in FR4
20
15
30in FR4
18in FR4
RESIDUAL JITTER = DJ + 14.1 x RJ
0.5 0.6 0.7
0.8
0.9
6
7
8
9
10
11
R
/(R
+ R
LFPD
)
LFPD HFPD
DATA RATE (Gbps)
4
_______________________________________________________________________________________
10.7Gbps Adaptive Receive Equalizer
Pin Description
PIN
1
NAME
FUNCTION
V
Supply Voltage, CML Input (1.8V to V
)
CC
CC1
2
SDI+
SDI-
Positive Differential Serial Data Input, CML
Negative Differential Serial Data Input, CML
3
4
V
Supply Voltage, CML Input (1.8V to V
)
CC
CC1
5
GND
SD
Supply Ground
6
Signal-Detect Output, LVCMOS. Low indicates <200mV , high indicates >220mV
.
P-P
P-P
7
EN
Enable Input, LVCMOS. Low disables output, high enables output, typically connected to SD.
Supply Ground
8
GND
9, 12
10
11
13
14
15
16
V
Supply Voltage, CML Output (1.8V to V
)
CC
CC2
SDO-
SDO+
HFPD
LFPD
Negative Differential Serial Data Output, CML
Positive Differential Serial Data Output, CML
High-Frequency Power Detector. Leave open for 9.953Gbps to 10.7Gbps PRBS NRZ data.
Low-Frequency Power Detector. Leave open for 9.953Gbps to 10.7Gbps PRBS NRZ data.
Supply Voltage, Equalizer Core, 3.3V
V
CC
GND
Supply Ground
Exposed Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and
Pad electrical performance.
EP
CML Input and Output Buffers
Detailed Description and
Applications Information
The MAX3805 CML input and output buffers are inter-
nally terminated with 50Ω to V
and V
, respec-
CC2
CC1
The MAX3805 adaptive equalizer is designed to oper-
ate with 9.95Gbps to 10.7Gbps PRBS nonreturn-to-zero
(NRZ) data at the receive end of a transmission line,
typically differential 6-mil FR-4 PC board. It adaptively
corrects intersymbol interference caused by frequency-
dependent path loss. It can also be used with coaxial
cable links and with transmission lines that include well-
engineered connectors, as long as the total path loss is
relatively smooth and does not exceed 20dB at 5GHz.
tively. The input and output circuitry have separate
voltage connections to control noise coupling and pro-
vide DC-coupling to +1.8V, +2.5V, or +3.3V CML. If
desired, the CML inputs and outputs can be AC-cou-
pled. See Figure 1 for the output structure.
The low-frequency cutoff of the input-stage offset-can-
cellation circuit is nominally 21kHz.
For single-ended operation (typically coaxial cable
links), the input must be AC-coupled; connect the
The signal path for the MAX3805 consists of a CML
input stage, two amplifiers feeding a pair of variable
attenuators controlled by feedback, and a limiting
amplifier with a CML output stage. An enable input, EN,
is used to control the output stage. A signal-detect out-
put, SD, indicates when input signal to the transmission
unused input to V
using a series combination of an
CC1
AC-coupling capacitor and a 50Ω resistor, as shown in
Figure 2. Note that the MAX3805 is specified for differ-
ential operation, and the performance may be reduced
in single-ended operation.
line is above 220mV
or below 200mV , typically.
P-P
P-P
See the Functional Diagram.
_______________________________________________________________________________________
5
10.7Gbps Adaptive Receive Equalizer
Functional Diagram
V
V
CC2
V
CC
CC1
VARIABLE
ATTENUATOR
FLAT
AMP
SDO+
SDI+
SDI-
LIMITING
AMP
CML OUT
∑
CML IN
SDO-
EN
VARIABLE
ATTENUATOR
BOOST
AMP
MAX3805
SIGNAL
DETECT
LOOP
FILTER
SD
LFPD
HFPD
Input Stage with Equalization
The low-noise input stage of the MAX3805 includes two
amplifiers, one with flat frequency response and the
other with a highpass frequency response compensat-
ing for the loss characteristic of 6-mil FR-4 PC board
transmission line. A current-steering network, imple-
mented with a pair of variable attenuators feeding into a
common summing node, provides the means to contin-
uously vary the amount of equalization. The amount of
equalization is controlled by feedback from two power-
detector blocks that set the variable attenuators to
match the loss of a particular transmission path.
V
CC
V
CC2
50Ω
50Ω
OUT+
OUT-
ESD
STRUCTURES
Dual Power-Detector Feedback Loop
The MAX3805 adapts the equalizer to a specific path
loss by sampling the output of the summing node with a
pair of frequency-dependent power detectors. The first
power detector has a lowpass bandwidth of 500MHz; the
second power detector has full bandwidth.
NRZ PRBS data has a sin2(f)/f2 spectral characteristic.
When this data is passed through a lossy FR-4 path,
high-frequency components are attenuated, while low-
Figure 1. CML Output Structure
6
_______________________________________________________________________________________
10.7Gbps Adaptive Receive Equalizer
V
CC
50Ω
0.01µF
0.01µF
TRANSMISSION LINE
500kΩ
IN+
IN-
V
CC1
50Ω
MAX3805
LFPD
HFPD
MAX3805
Figure 2. Single-Ended Operation
Figure 3. Connecting a Potentionmeter Across HFPD and LFPD
frequency components remain essentially intact. These
changes in the spectral characteristic of the signal at
the output of the path are measured with the two power
detectors to provide a means to determine the path
loss.
Signal Detect
The output of the high-frequency power detector is
used to generate an LVCMOS-compatible signal-detect
(SD) output. The SD output asserts when the input sig-
nal at the transmission line falls below 200mV , and
P-P
deasserts when the input signal at the transmission line
rises above 220mV . The SD output can be directly
P-P
connected to the EN input to disable the MAX3805 out-
put when no data signal is available. The SD output has
an LVCMOS fanout of one.
The dual power-detector feedback loop measures the
ratio between the outputs of the two power detectors
and adjusts the attenuation to restore the sin2(f)/f2
characteristic. The time constant for this feedback loop
is nominally 10µs.
Package and Layout Considerations
The MAX3805 is packaged in a 3mm x 3mm plastic-
encapsulated 16-lead thin QFN package with exposed
pad for signal integrity. The exposed pad provides ther-
mal and electrical connectivity to the IC, and must be
soldered to a high-frequency ground plane. Use good
layout techniques for the10Gbps SDI and SDO PC
board transmission lines, and configure the trace geom-
etry near the IC package to minimize impedance dis-
continuities. Power-supply decoupling capacitors
should be provided for each supply connection and
located as close as practical to the IC package.
Operating with Different Data Rates and
Codes
The MAX3805 equalizer feedback loop is optimized for
9.95Gbps to 10.7Gbps NRZ PRBS data; however, it
can also be used at a lower data rate or with a different
coding type by adjusting the feedback loop. The rela-
tive gain of the two power detectors can be adjusted by
connecting a 500kΩ trimmer potentiometer between
HFPD and LFPD pins, with the wiper connected to V
,
CC
as shown in Figure 3. Set the trimmer potentiometer for
the best eye opening.
Adding the potentiometer between HFPD and LFPD
can change the assert and deassert levels of the signal
detector, which could render the signal-detect output
invalid. For normal operation with 9.953Gbps to
10.7Gbps PRBS NRZ data, these signals should be left
open with no connections to pin 13 (HFPD) or pin 14
(LFPD). Note that excessive capacitance on pin 13 or
pin 14 can affect the operation of the feedback loop.
Make certain that the PC board traces from these pins
to the trimmer potentiometer are kept short.
V
CC
60kΩ
SD
Enable Function
The EN output is an LVCMOS-compatible pin that
enables the output stage of the MAX3805. Connect EN
ESD
STRUCTURES
to V
or LVCMOS high to enable the output stage of
CC
the device or to GND or LVCMOS low to disable the
output stage of the device.
Figure 4. Signal-Detect Output Circuit
_______________________________________________________________________________________
7
10.7Gbps Adaptive Receive Equalizer
Pin Configuration
Chip Information
TRANSISTOR COUNT: 1647
PROCESS: SiGe Bipolar
16 15 14 13
V
1
2
3
4
12
V
CC2
CC1
SDI+
SDI-
11 SDO+
10 SDO-
MAX3805
V
CC1
9
V
CC2
5
6
7
8
*EXPOSED PAD IS CONNECTED TO GND
8
_______________________________________________________________________________________
10.7Gbps Adaptive Receive Equalizer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
b
0.10 M
C
A
B
D
D2/2
D/2
E/2
E2/2
- A -
(NE - 1)
X e
C
E2
E
L
L
- B -
k
e
C
L
(ND - 1)
X e
C
L
C
L
0.10
C
0.08
C
A
A2
A1
L
L
e
e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0136
C
2
_______________________________________________________________________________________
9
10.7Gbps Adaptive Receive Equalizer
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0136
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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