MAX3822_V01 [MAXIM]
3.3V, 2.5Gbps Quad Limiting Amplifier;
| 型号： | MAX3822_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.3V, 2.5Gbps Quad Limiting Amplifier |
| 文件： | 总14页 (文件大小：624K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2144; Rev 2; 7/06
+3.3V, 2.5Gbps Quad Limiting Amplifier
General Description
Features
The MAX3822 quad limiting amplifier is ideal for multi-
channel systems with data rates up to 2.5Gbps. The
MAX3822 operates from a single +3.3V supply, over
temperatures ranging from 0°C to +85°C. A channel-
select (CS) pin is provided to program single-, dual-, or
quad-channel operation. The disabled channels are
shut down to reduce power consumption. The output
interface for all four channels is CML.
♦ Single +3.3V Supply
♦ Single-, Dual-, or Quad-Channel Operation at
2.5Gbps
♦ 700mW Total Power Dissipation (Quad-Channel
Operation)
♦ 120ps Maximum Output Edge Speed
♦ Overall and Individual Channel Loss-of-Power
(LOP) Indicator
The input can be driven from 20mVp-p to 1000mVp-p
differentially. The threshold voltage control is common
for all four channels and is programmable by an exter-
nal resistor. Four separate power detectors are incorpo-
rated to monitor the received signal level for each
channel. Individual TTL-compatible loss-of-power (LOP)
indicators assert low if the channel signal input is below
the programmed threshold. Typically 4dB LOP hystere-
sis (2dB optical) is provided to prevent chattering when
the input signal level is close to the threshold. A general
LOP indicator is also provided which asserts low if one
or more of the four inputs is in the LOP condition.
♦ Differential CML Outputs with On-Chip Back
Termination Resistors
♦ 30ps Maximum Deterministic Jitter
♦ 2ps Random Jitter
♦ Power-Down Feature Shuts Down Unused
Channels
♦ Operating Temperature Range: 0°C to +85°C
Ordering Information
PART
TEMP RANGE
0°C to +85°C
0°C to +85°C
0°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
48 TQFP-EP*
Dice**
Applications
MAX3822UCM
MAX3822UCM+
MAX3822U/D
Optical System Interconnects
Multichannel Receiver Modules
Dense Digital Cross-Connects
ATM Switch Networks
*Exposed pad.
**Contact factory for availability. Dice are designed to operate
from T = 0°C to T = +85°C, but are tested and guaranteed
A
A
High-Speed Parallel Links
only at T = +25°C.
A
+Denotes lead-free package.
Pin Configuration
TOP VIEW
Typical Operating Circuit appears at end of data sheet.
IN1+
IN1-
1
2
36 OUT1+
35 OUT1-
V
CC
3
34
V
CC
IN2+
IN2-
4
33 OUT2+
32 OUT2-
5
V
V
6
31
30
V
V
CC
CC
CC
CC
MAX3822
7
IN3+
IN3-
8
29 OUT3+
28 OUT3-
9
V
10
27
V
CC
CC
IN4+ 11
IN4- 12
26 OUT4+
25 OUT4-
TQFP-EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 2.5Gbps Quad Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) ........................................... -0.5V to +6.0V
Current into OUT1+, OUT1-, OUT2+, OUT2-,
OUT3+, OUT3-, OUT4+, OUT4-,.................................. 22mA
CC
Differential Input Voltage Swing (IN1+ - IN1-), (IN2+ - IN2-),
(IN3+ - IN3-), (IN4+ - IN4-)..............................................2Vp-p
Voltage at LOP1, LOP2, LOP3,
Continuous Power Dissipation (T = +85°C)
A
48-Pin TQFP-EP (derate 29.4mW/°C above +85°C)......2.35W
Operating Junction Temperature Range(die) ...-55°C to +150°C
Processing Temperature (die) .........................................+400°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
LOP4, LOP, CS........................................-0.5V to (V
+ 0.5V)
CC
Voltage at IN1+, IN1-, IN2+, IN2-, IN3+,
IN3-, IN4+, IN4- .............................(V
- 1V) to (V
+ 0.5V)
CC
CC
Voltage at VTH .....................................................+0.5V to +2.3V
Voltage at CZ1+, CZ1-, CZ2+, CZ2-,
CZ3+, CZ3-, CZ4+, CZ4- ........................-0.5V to (V
+ 0.5V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = 0°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V and T = +25°C.) (Note 1)
A
CC
CC
A
PARAMETER
SYMBOL
CONDITIONS
Single channel (Note 2)
MIN
TYP
60
MAX
72
UNITS
Power-Supply Current
I
Dual channel (Note 2)
Quad channel
110
210
137
265
mA
CC
Single-Ended Data Input
Voltage Range
V
0.5
-
V
0.25
+
CC
CC
V
V
IS
Single-Ended Data Input
Resistance
40
50
60
Ω
R
TH
R
TH
R
TH
R
TH
R
TH
R
TH
= 1kΩ
14
18.5
34
Data Input Voltage for LOP
Assert
= 649Ω
= 400Ω
= 1kΩ
11.5
32.5
6.0
mVp-p
dB
4.5
LOP Hysteresis
= 649Ω
= 400Ω
3.0
3.4
CML Differential Output
V
V
R = 50Ω to V
CC
640
40
740
1000
60
mVp-p
OD
OH
L
Single-Ended Data Output
Resistance
50
Ω
CML Output Common-Mode
Voltage
V
-
CC
V
0.2
TTL Output High
TTL Output Low
Sourcing 200µA
Sinking 2mA
2.4
V
V
V
CC
V
0.4
OL
2
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = 0°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V and T = +25°C.) (Notes 1, 3)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1000
9.5
UNITS
Data Input Voltage Range
Random Jitter
V
20
mVp-p
IN
(Note 4)
2
8
ps
RMS
V
V
= 20mVp-p (Notes 5, 6)
IN
IN
Deterministic Jitter
psp-p
= 1000mVp-p to 1000mVp-p (Notes 5, 6)
4
30
Data Output Edge Speed
LOP Assert/Deassert Time
Input-Referred Noise
(20% to 80%)
90
120
ps
ns
100
(Note 7)
105
150
20
594
70
µV
RMS
Offset Correction Low-
Frequency Cutoff
CZ1 = CZ2 = CZ3 = CZ4 = 0.033µF
(Note 8)
kHz
ps
Channel-to-Channel Skew
Note 1: Characteristics at 0°C are guaranteed by design and characterization. Dice are tested at T = +25°C.
A
Note 2: When power is first applied, all four channels are briefly active.
Note 3: AC characteristics are guaranteed by design and characterization.
Note 4: Input data edge speed of 150ps (20% to 80%).
Note 5: Data rate = 2.5Gbps. Measured with 213 -1 PRBS plus 100 consecutive identical digits.
Note 6: Deterministic jitter (p-p) equals total jitter (p-p) minus random jitter (p-p).
Note 7: Input-referred noise is specified (differential output noise)/(small-signal gain).
Note 8: Measured by applying the same input signal to all channels. Skew measurements are made at 50% point of the transition.
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps Quad Limiting Amplifier
Typical Operating Characteristics
(V = +3.3V, T = +25°C, unless otherwise noted.)
CC
A
RANDOM JITTER
vs. DIFFERENTIAL INPUT VOLTAGE
ELECTRICAL EYE DIAGRAM
(V = 1V DIFFERENTIAL)
IN
DETERMINISTIC JITTER
vs. DIFFERENTIAL INPUT VOLTAGE
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
100mV/div
0
100 200 300 400 500 600 700 800 900 1000
DIFFERENTIAL INPUT VOLTAGE (mVp-p)
0
100 200 300 400 500 600 700 800 900 1000
DIFFERENTIAL INPUT VOLTAGE (mV)
75ps/div
ELECTRICAL EYE DIAGRAM
(V = 100mV DIFFERENTIAL)
IN
ELECTRICAL EYE DIAGRAM
(V = 20mV DIFFERENTIAL)
IN
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
100mV/div
100mV/div
75ps/div
75ps/div
1
10
100
1000
FREQUENCY (MHz)
LOSS-OF-POWER THRESHOLD LEVEL
vs. THRESHOLD RESISTANCE
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
70
60
50
40
30
20
10
0
15
10
5
0
-5
DEASSERT THRESHOLD
-10
-15
-20
-25
ASSERT
THRESHOLD
0
400
800
1200
(Ω)
1600
2000
1
10
100
R
TH
FREQUENCY (MHz)
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Limiting Amplifier
Pin Description
PIN
1
NAME
DESCRIPTION
IN1+
IN1-
Noninverted Data Input for Channel 1
Inverted Data Input for Channel 1
2
3, 6, 7, 10,
27, 30, 31, 34
V
+3.3V Supply Voltage
CC
4
5
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
Noninverted Data Input for Channel 2
Inverted Data Input for Channel 2
Noninverted Data Input for Channel 3
Inverted Data Input for Channel 3
Noninverted Data Input for Channel 4
Inverted Data Input for Channel 4
8
9
11
12
13, 16, 19,
37, 39, 40,
42, 45, 48
GND
Supply Ground
A capacitor connected between this pin and CZ4+ extends the time constant for the offset-
correction loop associated with channel 4. Maxim recommends a capacitor value of 0.033µF.
14
15
17
CZ4-
CZ4+
CZ3-
A capacitor connected between this pin and CZ4- extends the time constant for the offset-
correction loop associated with channel 4. Maxim recommends a capacitor value of 0.033µF.
A capacitor connected between this pin and CZ3+ extends the time constant for the offset-
correction loop associated with channel 3. Maxim recommends a capacitor value of 0.033µF.
A capacitor connected between this pin and CZ3- extends the time constant for the offset-
correction loop associated with channel 3. Maxim recommends a capacitor value of 0.033µF.
18
20
21
CZ3+
LOP
LOP is low when any of the individual power detectors (LOP1, LOP2, LOP3, LOP4) are low.
LOP1 asserts low when the data input signal level to channel 1 drops below the programmed
threshold.
LOP1
LOP2 asserts low when the data input signal level to channel 2 drops below the programmed
threshold.
22
23
LOP2
LOP3
LOP3 asserts low when the data input signal level to channel 3 drops below the programmed
threshold.
LOP4 asserts low when the data input signal level to channel 4 drops below the programmed
threshold.
24
25
LOP4
OUT4-
Inverted Data Output for Channel 4
_______________________________________________________________________________________
5
+3.3V, 2.5Gbps Quad Limiting Amplifier
Pin Description (continued)
PIN
26
28
29
32
33
35
36
NAME
OUT4+
OUT3-
OUT3+
OUT2-
OUT2+
OUT1-
OUT1+
DESCRIPTION
Noninverted Data Output for Channel 4
Inverted Data Output for Channel 3
Noninverted Data Output for Channel 3
Inverted Data Output for Channel 2
Noninverted Data Output for Channel 2
Inverted Data Output for Channel 1
Noninverted Data Output for Channel 1
A resistor connected from this pin to ground sets the data input signal level at which the loss-of-
power outputs will be asserted.
38
41
43
44
46
47
EP
VTH
CS
Channel-Select Input. To enable channel 1 only, leave CS open. To enable channels 1 and 2,
connect CS to V . To enable all four channels, connect CS to GND.
CC
A capacitor connected between this pin and CZ2+ extends the time constant for the offset-
correction loop associated with channel 2. Maxim recommends a capacitor value of 0.033µF.
CZ2-
CZ2+
CZ1-
CZ1+
A capacitor connected between this pin and CZ2- extends the time constant for the offset-
correction loop associated with channel 2. Maxim recommends a capacitor value of 0.033µF.
A capacitor connected between this pin and CZ1+ extends the time constant for the offset-
correction loop associated with channel 1. Maxim recommends a capacitor value of 0.033µF.
A capacitor connected between this pin and CZ1- extends the time constant for the offset-
correction loop associated with channel 1. Maxim recommends a capacitor value of 0.033µF.
Exposed
Pad
Ground. This must be soldered to a circuit board for proper thermal and electrical performance (see
Exposed Pad (EP) Package).
The power-detection circuitry is used to indicate that
Detailed Description
the data input voltage has fallen below the pro-
grammed threshold level. Each individual channel has
a power detector output (LOP1, LOP2, LOP3, LOP4).
The LOP output is low when any of the individual power-
detector outputs are low. A threshold adjustment pin
(VTH) programs the signal-detect threshold for all four
channels with a single external resistor. The offset-cor-
rection loop adjusts the input buffer bias until the CML
output buffer has a zero offset. This offset-correction
loop acts as a high-pass filter where signal components
below 150kHz are attenuated.
The MAX3822 is a 2.5Gbps quad limiting amplifier
designed for fiber applications with input sensitivities
as low as 20mVp-p. This device has internally terminat-
ed CML inputs with loss-of-power circuitry for each
channel, as well as a general loss-of-power indicator
valid for the whole part. Offset correction ensures low
pulse-width distortion (PWD) and reduced pattern-
dependent jitter (PDJ). A channel-select (CS) pin is
used to control the device’s mode of operation as sin-
gle, dual, or quad.
The inputs of the MAX3822 are typically connected to a
transimpedance amplifier (TIA) (MAX3825) found within
a fiber-optic link. The output signal from a TIA can con-
tain significant amounts of noise, and may vary in
amplitude over time. The MAX3822 limiting amplifier
quantizes the input signal, and outputs a voltage-limit-
ed waveform over a 40dB input dynamic range. Signal
input to this device passes through a buffer to a linear-
gain amplifier. This linear-gain amplifier (Figure 1) dri-
ves the power-detection circuitry and a chain of limiting
amplifiers leading to the CML output buffer.
Input Buffer and Gain Stages
The MAX3822’s inputs are terminated with 50Ω to V
CC
(Figure 2). The inputs do not need to be AC-coupled if
the upstream TIA has CML outputs, but should be AC-
coupled if the differential logic levels are in any other
format. The differential input signal is passed through a
buffer, and then continues through two sets of differen-
tial amplifiers, each with an emitter-follower output
stage. The first differential amplifier provides approxi-
mately 10dB gain and a linear output for input signals
6
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Limiting Amplifier
CZ1-
CZ1+
LOW PASS
OFFSET CORRECTION
LIMITING AMPLIFIER #1
OUT1+
OUT1-
IN1+
IN1-
BUFF
GAIN
GAIN
CML
LOSS-OF-POWER LOGIC
R
RECTIFIER AND
LOW-PASS FILTER
Q
LOP1
S
VTH
THRESHOLD
CONTROL
R
TH
LOSS OF POWER
LOP
CS
CHANNEL
SELECT
LIMITING
LIMITING
LIMITING
AMPLIFIER
#2
AMPLIFIER
#3
AMPLIFIER
#4
MAX3822
LOP3
LOP2
LOP4
CZ2+ CZ2-
CZ3+ CZ3-
CZ4+ CZ4-
IN2+ IN2-
OUT2+ OUT2- IN3+ IN3-
OUT3+ OUT3-
IN4+ IN4-
OUT4+ OUT4-
Figure 1. Functional Diagram
up to 80mVp-p. This differential amplifier is designed to
work with the power-detect circuitry.
cols, refer to Application Note HFAN-1.0, Introduction
to LVDS, PECL, and CML.
The next high-gain amplifier provides an additional gain
of approximately 22dB. This gain stage functions simi-
larly to the input-gain stage. The output signal from this
gain stage is applied to the CML output buffer shown in
Figure 3, and is used in the offset-correction loop.
Be sure the MAX3822 is placed as close as possible to
the TIA when using this device near sensitivity. If you
are using a TIA with CML outputs, such as the
MAX3825, AC-coupling capacitors are not required.
Taking these precautions will ensure the best possible
sensitivity.
The input voltage range is limited to V
+ 0.5V by the
CC
CC
ESD structure, and to a minimum of V
- 1V by the
Output Buffer
The MAX3822’s CML output buffer is designed to drive
50Ω lines that are used to feed the input of a clock- and
data-recovery device (CDR). Figure 3 shows a model of
the output stage showing some important details. The
outputs of the device are terminated internally with 50Ω
internal resistor. Figure 2 shows a model of the input
stage of the MAX3822, including the package capaci-
tance and the bond wire inductance. The additional
0.4pF capacitance on the inputs represents the ESD
diode’s junction capacitance and a small contribution
by the bond pad. For more information about the CML
electrical specifications and interfacing to other proto-
to V . ESD diode structures are connected to V
CC
CC
and GND. Figure 3 also shows the model of the output
_______________________________________________________________________________________
7
+3.3V, 2.5Gbps Quad Limiting Amplifier
PACKAGE
DIE
V
CC
ESD
DIODES
50Ω
50Ω
1.5nH
0.2pF
1.5nH
IN+
IN-
0.4pF
0.2pF
0.4pF
GND
Figure 2. Input Structure
and may cause deterministic jitter through an increase
of PWD.
ESD
DIODES
V
CC
Each of the MAX3822’s integrated limiting amplifiers
includes a DC cancellation loop that provides offset
correction to the CML output signal in addition to low-
frequency power-supply noise rejection. The DC can-
cellation loop consists of a low-pass filter and a
high-gain amplifier. The input voltage difference of the
CML output buffer is amplified, sent through a low-pass
filter, inverted, and summed up with the input signal
that drives the high-gain input stage. This removes from
the output signal all frequency components between
the cutoff frequency and DC. The low-frequency cutoff
of the DC cancellation loop is set by an external capac-
itor connected between CZ_+ and CZ_-.
50Ω
50Ω
1.5nH
OUT+
OUT-
0.4pF
0.2pF
0.2pF
1.5nH
0.4pF
DIE PACKAGE
Power Detection and Threshold Control
The MAX3822 incorporates a chatter-free loss-of-power
function that is used to determine if the input signal has
dropped below the programmed threshold level. The
power detector is implemented by comparing the DC-
rectified output of the first gain stage to the pro-
grammed loss-of-power threshold.
GND
Figure 3. Output Structure
stage of the MAX3822, including package capacitance
and bond-wire inductance. The additional 0.4pF
capacitance on the output represents the ESD diode’s
junction capacitance and a small contribution by the
bond pad. For more information about the CML electri-
cal specifications and interfacing to other protocols,
refer to Application Note HFAN-1.0, Introduction to
LVDS, PECL, and CML.
The threshold control circuitry enables programming of
LOP_ assert and deassert reference voltages by using
one external resistor, R (Figure 4). An internal amplifi-
TH
er guarantees a voltage at V
of approximately 0.5V.
TH
The external resistor (R ) connected to GND converts
TH
this voltage into a current. The current through this
resistor sets the power threshold level for the device
(see Typical Operating Characteristics, Loss-of-Power
Offset Correction
Each limiting amplifier on the MAX3822 provides
approximately 50dB of gain. An input offset as small as
1mV reduces the power-detection circuitry’s accuracy
Threshold Level vs. R ).
TH
8
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Limiting Amplifier
device is placed into single-mode operation with channel
1 enabled, and channels 2, 3, and 4 disabled. Dual-
mode operation is programmed by connecting CS
Loss-Of-Power Logic (LOP)
The loss-of-power logic circuitry is asserted anytime the
input power of one of the limiting amplifiers is observed
directly to V . In dual-mode operation, channels 1 and
CC
below the threshold set by R . The logic of this is
TH
2 are enabled and channels 3 and 4 are disabled. Quad-
mode operation is programmed by connecting CS
directly to GND. In quad-mode operation, all four chan-
nels are enabled. Figure 6 shows the input circuitry of
the CS pin.
comprised of two comparators and an S-R flip-flop to
compare the outputs of the threshold-control and
power-detect circuitry for each of the limiting amplifiers
on the MAX3822. The LOP_ output corresponding to a
given input is asserted if the input power is too low. A
general LOP output is also given for the whole part; if
any LOP_ signal is low, the LOP output will also go low.
Applications Information
Set Up the DC Cancellation Loop
The value of the offset-correction capacitor (CZ_)
affects the maximum speed at which the DC cancella-
tion loop can adjust to changes in DC offset at the
input. PWD and pattern-dependent jitter (PDJ) are both
error sources that can be minimized by the proper
selection of CZ_. Therefore, the loop should be as slow
as possible to reduce PDJ while performing its DC can-
cellation function. Select the CZ_ capacitor to set the
bandwidth of the DC cancellation loop. The input
impedance between CZ+ and CZ- is approximately
10kΩ. This impedance is in series with CZ_. Therefore,
the low-frequency cutoff (foc) associated with the DC
offset-correction loop is computed as follows:
Once a LOP_ signal has been asserted, the input
power must rise above the threshold before resetting.
This prevents the LOP_ output from turning on and off
when the input signal is near the programmed thresh-
old level, an effect called chatter. The LOP_ indicator
will return to its unasserted state when the input power
level is increased (4dB typ). Figure 5 shows the output
structure.
Channel Select
The channel-select circuitry controls the operating mode
of the MAX3822 by shutting down unused amplifiers.
Single-, dual-, and quad-mode operation is programmed
by the channel-select (CS) pin. When CS is left open, the
V
CC
ESD
DIODES
V
CC
V
REF
I
CTAL
2kΩ
ESD
DIODES
4kΩ
LOP
VTH
R
TH
18kΩ
GND
GND
Figure 4. Threshold Set Structure
GND
Figure 5. TTL Output Structure
_______________________________________________________________________________________
9
+3.3V, 2.5Gbps Quad Limiting Amplifier
In an optical receiver, the dB change at the MAX3822
V
CC
ESD
DIODES
will equal twice the optical dB change. The MAX3822’s
typical voltage hysteresis is 4dB. This provides an opti-
cal hysteresis of 2dB.
30kΩ
Exposed-Pad (EP) Package
The exposed-pad, 48-pin TQFP-EP incorporates fea-
tures that provide a very low thermal resistance path for
heat removal from the IC. The pad is electrical ground
on the MAX3822 and should be soldered to the circuit
board for proper thermal and electrical performance.
CS
40kΩ
20kΩ
Chip Information
TRANSISTOR COUNT: 813
SUBSTRATE CONNECTED TO GND
PROCESS: Bipolar
DIE SIZE: 90mil ✕ 102mil
GND
Figure 6. Channel-Select Interface
50dB
20
10
foc =
Bond Pad Information
2π × 10kΩ × Cz_
(1804.6, 1966.6)
(125.2, 2090.8)
B
where 50dB is the gain of the offset-correction loop.
Maxim recommends a value of 0.033µF for the filter
capacitor. This value will set the lower cutoff frequency
of the DC cancellation loop to approximately 150kHz.
HF65Z
(46.9, 1804.6)
(1947.6, 1804.6)
Optical Hysteresis
Power and hysteresis are often expressed in decibels.
By definition, decibels are always 10log (ratio power).
MAX3822
A
C
At the inputs to the MAX3822 limiting amplifier, the
2
power is V
/ R. If a receiver’s optical input power (x)
IN
increases by a factor of two, and the preamplifier is lin-
ear, then the voltage input to the MAX3822 will also
increase by a factor of two.
INDEX PAD
The optical power change is:
(46.9, 46.9)
Y
(1947.6, 46.9)
2x
x
D
10log
= 10log(2) = + 3dB
(125.5, -215)
(1985.5, -215)
X
*ORIENT PLOT, USING
HF65Z AS A KEY.
At the MAX3822, the voltage change is:
2V 2 /R
• ALL DIMENSIONS ARE IN MICRONS
• GST2 PROCESS
• PAD DIMENSIONS: (BONDING AREA)
H = 93.8MICRONS
W = 93.8MICRONS
• ALL MEASUREMENTS SPECIFY THE CENTER OF THE PAD.
(
)
IN
10log
= 10log 22 = 20log 2 = + 6dB
( )
(
)
V
2 /R
IN
• ORIGIN IS DEFINED AS THE BOTTOM LEFT CORNER OF THE INDEX PAD
10 ______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Limiting Amplifier
Bond Pad Information (continued)
MAX3822 (HF65Z) DIMENSIONS
SIDE A
SIDE B
SIDE C
SIDE D
46.9
46.9
46.9
46.9
46.9
46.9
46.9
46.9
46.9
46.9
46.9
46.9
46.9
206.2
125.2
292.6
2090.8
2090.8
2090.8
2090.8
2090.8
2090.8
2090.8
2090.8
2090.8
2090.8
2090.8
2090.8
1947.6
1947.6
1947.6
1947.6
1947.6
1947.6
1947.6
1947.6
1947.6
1947.6
1947.6
1947.6
46.9
206.2
125.2
279.1
-215
-215
-215
-215
-215
-215
-215
-215
-215
-215
-215
-215
-215
365.5
460.0
365.5
433.0
524.8
627.4
524.8
586.9
684.1
794.8
684.1
740.8
846.1
962.2
846.1
894.7
1005.4
1167.4
1326.7
1486.0
1645.3
1804.6
1129.6
1297.0
1464.4
1631.8
1799.2
1966.6
1005.4
1167.4
1326.7
1486.0
1645.3
1804.6
1048.6
1202.5
1356.4
1510.3
1664.2
1818.1
1985.5
Typical Operating Circuit
CZ1
CZ1
CZ2 CZ3
CZ4
V
CC
V
CC
CS
CZ2 CZ3 CZ4
IN1+
OUT1+
OUT1-
IN1+
50Ω
50Ω
50Ω
IN1-
50Ω
IN1-
V
CC
CC
IN2+
IN2-
OUT2+
OUT2-
IN2+
50Ω
50Ω
50Ω
IN2-
50Ω
V
V
MAX3822
IN3+
IN3-
OUT3+
OUT3-
IN3+
50Ω
50Ω
50Ω
IN3-
50Ω
CC
IN4+
OUT4+
OUT4-
IN4+
50Ω
50Ω
50Ω
IN4-
VTH
IN4-
PHOTODIODE
ARRAY
50Ω
R
MAX3825
TH
LOP1 LOP2 LOP3 LOP4 LOP GND
______________________________________________________________________________________ 11
+3.3V, 2.5Gbps Quad Limiting Amplifier
Chip Topography
(90mil)
OUT1+
OUT1-
IN1+
IN1-
V
V
CC
CC
OUT2+
OUT2-
IN2+
IN2-
V
CC
V
CC
V
CC
V
CC
(102mil)
OUT3+
OUT3-
IN3+
IN3-
V
CC
V
CC
OUT4+
OUT4-
IN4+
IN4-
12 ______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
1
21-0065
G
2
______________________________________________________________________________________ 13
+3.3V, 2.5Gbps Quad Limiting Amplifier
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
2
21-0065
G
2
Revision History
Rev 0; 8/01:
Rev 1; 7/04:
Rev 2; 7/06:
Original data sheet release.
Page 1: Added lead-free package to Ordering Information table.
Page 11: Removed MAX3827 from Typical Operating Circuit.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
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