MAX3840_07 [MAXIM]

+3.3V, 2.7Gbps Dual 2 ✕ 2 Crosspoint Switch; + 3.3V , 2.7Gbps的双通道2 ✕ 2交叉点开关
MAX3840_07
型号: MAX3840_07
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

+3.3V, 2.7Gbps Dual 2 ✕ 2 Crosspoint Switch
+ 3.3V , 2.7Gbps的双通道2 ✕ 2交叉点开关

开关
文件: 总8页 (文件大小:121K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
19-1854; Rev 5; 9/07  
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
General Description  
Features  
The MAX3840 is a dual 2 2 asynchronous crosspoint  
Single +3.3V Supply  
switch for SDH/SONET DWDM and other high-speed  
data switching applications where serial data stream  
loop-through and protection channel switching are  
required. It is ideal for OC-48 systems with forward  
error correction. A high-bandwidth, fully differential sig-  
nal path minimizes jitter accumulation, crosstalk, and  
460mW Power Consumption  
2ps  
7ps  
Random Jitter  
RMS  
Deterministic Jitter  
P-P  
Power-Down Feature for Deselected Outputs  
CML Inputs/Outputs  
signal skew. Each 2 2 crosspoint switch can fan out  
and/or multiplex up to 2.7Gbps data and 2.7GHz clock  
signals. All inputs and outputs are current mode logic  
(CML) compatible and easily adaptable to interface  
with an AC-coupled LVPECL signal. When not used,  
each CML output stage can be powered down with an  
enable control to conserve power. The typical power  
consumption is 460mW with all outputs enabled.  
6ps Channel-to-Channel Skew  
100ps Output Edge Speed  
5mm 5mm 32 QFN or Thin QFN Package  
The MAX3840 is compatible with the MAX3876  
2.5Gbps clock and data recovery (CDR) circuit.  
Ordering Information  
The MAX3840 is available in a 32-pin exposed-pad  
QFN package (5mm 5mm footprint) and operates  
PIN-  
PACKAGE  
PKG  
CODE  
PART  
TEMP RANGE  
from a +3.3V supply over a temperature range of -40°C  
to +85°C.  
MAX3840ETJ+ -40°C to +85°C  
MAX3840EGJ -40°C to +85°C  
+Denotes a lead-free package.  
32 TQFN  
32 QFN  
T3255-3  
G3255-1  
________________________Applications  
SDH/SONET and DWDM Transport Systems  
Add-Drop Multiplexers  
ATM Switch Cores  
WDM Cross-Connects  
Pin Configurations appear at end of data sheet.  
High-Speed Backplanes  
Typical Application Circuit  
VCC = +3.3V  
MAX3869  
DATA  
MAX3866  
TIA AND LA  
MAX3876  
CDR  
LASER  
DRIVER  
CLOCK  
MAX3840  
CROSSPOINT  
SWITCH  
MAX3869  
LASER  
DATA  
MAX3866  
TIA AND LA  
MAX3876  
CDR  
DRIVER  
CLOCK  
Z
= 50Ω TRANSMISSION LINE  
O
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage, V  
.............................................-0.5V to +5.0V  
32-Pin QFN  
CC  
Input Voltage (CML) .........................(VCC - 1.0) to (V  
TTL Control Input Voltage...........................-0.5V to (V  
Output Currents (CML) .......................................................22mA  
+ 0.5V)  
+ 0.5V)  
(derate 21.3mW/°C above +85°C).................................1.38W  
Operating Temperature Range ...........................-40°C to +85°C  
Operating Junction Temperature Range...........-55°C to +150°C  
Storage Temperature Range.............................-65°C to +160°C  
Lead Temperature (soldering, 10s) .................................+300°C  
CC  
CC  
Continuous Power Dissipation (T = +85°C)  
A
32-Pin TQFN  
(derate 21.3mW/°C above +85°C).................................1.38W  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
DC ELECTRICAL CHARACTERISTICS  
(V  
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V  
= +3.3V, T = +25°C, unless otherwise noted.)  
CC A  
CC  
A
MIN  
TYP  
MAX  
PARAMETER  
Supply Current  
SYMBOL  
CONDITIONS  
All outputs enabled  
UNITS  
140  
190  
I
mA  
CC  
CML INPUT AND OUTPUT SPECIFICATIONS  
CML Differential Output Swing  
640  
85  
800  
100  
1000  
115  
R = 50Ω to V (Figure 2)  
mV  
P-P  
L
CC  
Differential Output Impedance  
Ω
CML Output Common-Mode  
Voltage  
R = 50Ω to V  
V
- 0.2  
CC  
V
V
L
CC  
CML Single-Ended Input  
Voltage Range  
V
V
- 0.8  
V
CC  
+ 0.5  
IS  
CC  
CML Differential Input Voltage  
Swing  
300  
2000  
57.5  
mV  
P-P  
CML Single-Ended Input  
Impedance  
42.5  
2.0  
50  
Ω
TTL SPECIFICATIONS  
TTL Input High Voltage  
TTL Input Low Voltage  
TTL Input High Current  
TTL Input Low Current  
V
V
IH  
V
0.8  
+10  
V
IL  
I
-10  
-10  
µA  
µA  
IH  
I
+10  
IL  
2
_______________________________________________________________________________________  
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
AC ELECTRICAL CHARACTERISTICS  
(V  
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V  
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)  
CC A  
CC  
A
MIN  
TYP  
MAX  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS  
CML Input and Output Data  
Rate  
2.7  
Gbps  
CML Input and Output Clock  
Rate  
2.7  
GHz  
ps  
CML Output Rise and Fall Time  
CML Output Random Jitter  
t , t  
20% to 80%  
(Note 2)  
100  
2
136  
r
f
RJ  
DJ  
ps  
RMS  
CML Output Deterministic Jitter  
CML Output Differential Skew  
(Note 3)  
7
20  
25  
ps  
P-P  
t
t
Any differential pair  
7
ps  
skew1  
CML Output Channel-to-  
Channel Skew  
Any two outputs  
15  
40  
ps  
ps  
skew2  
Propagation Delay from Input-  
to-Output  
t
d
185  
CML Differential Output Swing  
for 2.7Gbps Input Data  
R = 50Ω to V  
(Note 4)  
L
CC  
CC  
600  
520  
mV  
P-P  
P-P  
CML Differential Output Swing  
for 2.7GHz Input Clock  
R = 50Ω to V  
L
mV  
(Note 5)  
Note 1: AC characteristics are guaranteed by design and characterization.  
Note 2: Measured with 100mV noise (f 2MHz) on the power supply.  
P-P  
Note 3: Deterministic jitter (DJ) is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.  
Note 4: Measured with 300mV  
Note 5: Measured with 300mV  
differential 1010... data pattern driving the inputs.  
differential clock at 2.7GHz driving the inputs.  
P-P  
P-P  
_______________________________________________________________________________________  
3
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
Typical Operating Characteristics  
(V  
= +3.3V, T = +25°C, unless otherwise noted.)  
A
CC  
SUPPLY CURRENT vs. TEMPERATURE  
CML DIFFERENTIAL VOLTAGE  
160  
800  
750  
700  
650  
600  
550  
500  
450  
400  
350  
300  
4 OUTPUTS ENABLED  
140  
3 OUTPUTS ENABLED  
120  
2 OUTPUTS ENABLED  
100  
1 OUTPUT ENABLED  
80  
0 OUTPUTS ENABLED  
60  
40  
20  
0
250  
200  
-50 -30 -10  
10  
50  
70  
90  
-50 -30 -10  
10  
50  
70  
90  
30  
30  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
CHANNEL-TO-CHANNEL SKEW  
vs. TEMPERATURE  
2.7Gbps EYE DIAGRAM  
20  
18  
16  
14  
12  
10  
8
23  
INPUT = 2 - 1PRBS  
CHANNEL B  
6
4
2
CHANNEL A  
0
-50 -30 -10  
10  
30  
50  
70  
90  
54ps/div  
TEMPERATURE (°C)  
4
_______________________________________________________________________________________  
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
Pin Description  
PIN  
NAME  
FUNCTION  
1
ENB1  
Channel B1 Output Enable, TTL Input. A TTL low input powers down B1 output stage.  
2
DIB1+  
DIB1-  
ENB0  
SELB0  
DIB0+  
DIB0-  
SELB1  
GND  
Channel B1 Positive Signal Input, CML  
3
Channel B1 Negative Signal Input, CML  
4
Channel B0 Output Enable, TTL Input. A TTL low input powers down B0 output stage.  
Channel B0 Output Select, TTL Input. See Table 1.  
Channel B0 Positive Signal Input, CML  
5
6
7
Channel B0 Negative Signal Input, CML  
8
Channel B1 Output Select, TTL Input. See Table 1.  
Supply Ground  
9, 24  
10, 13, 16, 17,  
20, 23  
V
Positive Supply  
CC  
11  
12  
14  
15  
18  
19  
21  
22  
25  
26  
27  
28  
29  
30  
31  
32  
DOB0-  
DOB0+  
DOB1-  
DOB1+  
DOA1-  
DOA1+  
DOA0-  
DOA0+  
SELA1  
DIA0+  
DIA0-  
Channel B0 Negative Output, CML  
Channel B0 Positive Output, CML  
Channel B1 Negative Output, CML  
Channel B1 Positive Output, CML  
Channel A1 Negative Output, CML  
Channel A1 Positive Output, CML  
Channel A0 Negative Output, CML  
Channel A0 Positive Output, CML  
Channel A1 Output Select, TTL Input. See Table 1.  
Channel A0 Positive Signal Input, CML  
Channel A0 Negative Signal Input, CML  
SELA0  
ENA0  
Channel A0 Output Select, TTL Input. See Table 1.  
Channel A0 Output Enable, TTL Input. A TTL low input powers down A0 output stage.  
Channel A1 Positive Signal Input, CML  
DIA1+  
DIA1-  
Channel A1 Negative Signal Input, CML  
ENA1  
Channel A1 Output Enable, TTL Input. A TTL low input powers down A1 output stage.  
Ground. The exposed pad must be soldered to the circuit board ground for proper  
electrical and thermal operation.  
EP  
Exposed Pad  
_______________________________________________________________________________________  
5
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
Table 1. Output Routing  
ROUTING CONTROLS  
OUTPUT CONTROLS  
OUTPUT SIGNALS  
SELA0/SELB0  
SELA1/SELB1 ENA0/ENA1 ENB0/ENB1  
Signal at DOA0/DOB0  
Signal at DOA1/DOB1  
DIA0/DIB0  
0
0
1
1
X
0
1
0
1
X
1
1
1
1
0
1
1
1
1
0
DIA0/DIB0  
DIA0/DIB0  
DIA1/DIB1  
DIA1/DIB1  
Power Down  
DIA1/DIB1  
DIA0/DIB0  
DIA1/DIB1  
Power Down  
DIA0+  
DIA0-  
CML+  
CML  
DOA0+  
0
1
CML  
DOA0-  
ENA0  
SELA0  
500mV  
MAX  
320mV MIN  
DOA1+  
0
1
CML  
DIA1+  
DIA1-  
CML  
CML  
DOA1-  
ENA1  
CML-  
SELA1  
DIB0+  
DIB0-  
DOB0+  
0
1
CML  
CML  
DOB0-  
ENB0  
640mV  
MIN  
SELB0  
1000mV  
MAX  
DOB1+  
0
1
DIB1+  
DIB1-  
(CML+) - (CML-)  
CML  
DOB1-  
ENB1  
SELB1  
Figure 1. Functional Block Diagram  
Figure 2. CML Output Levels  
CML Inputs and Outputs  
_______________ Detailed Description  
CML is used to simplify high-speed interfacing. On-  
chip input and output terminations minimize the number  
of external components required while improving signal  
integrity. The CML output signal swing is small, result-  
ing in lower power consumption. The internal 50Ω input  
and output terminations minimize reflections and elimi-  
nate the need for external terminations.  
The block diagram in Figure 1 shows the MAX3840  
architecture. The SELA_ and SELB_ pins control the rout-  
ing of the signals through the crosspoint switch. Each  
output of the crosspoint switch drives a CML output dri-  
ver. Each of the outputs, DOA_ and DOB_, is enabled or  
disabled by the respective ENA_ and ENB_ pins.  
6
_______________________________________________________________________________________  
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
Layout Techniques  
Applications Information  
For best performance, use good high-frequency layout  
Interfacing PECL Inputs and  
Outputs to the MAX3840  
For information on interfacing with CML, refer to Maxim  
Application Note HFAN-01.0, Introduction to LVDS,  
PECL, and CML.  
techniques, filter V  
supplies, and keep ground con-  
CC  
nections short. Use multiple vias where possible. Also,  
use controlled-impedance transmission lines to inter-  
face with the MAX3840 data inputs and outputs.  
___________________ Interface Models  
Figure 3 shows the interface model for the CML inputs,  
and Figure 4 shows the model for CML outputs.  
V
CC  
MAX3840  
V
CC  
V
CC  
50Ω  
50Ω  
50Ω  
DIA0+  
DOA0-  
DOA0+  
V
CC  
50Ω  
DIA0-  
MAX3840  
Figure 4. CML Output Model  
Figure 3. CML Input Model  
_______________________________________________________________________________________  
7
+3.3V, 2.7Gbps Dual 2 2 Crosspoint Switch  
Pin Configurations  
TOP VIEW  
TOP VIEW  
24 23 22 21 20 19 18 17  
ENB1  
DIB1+  
DIB1-  
ENB0  
1
2
3
4
5
6
7
8
24 GND  
23  
V
16  
CC  
SELA1 25  
V
CC  
DIA0+ 26  
DIA0- 27  
SELA0 28  
15 DOB1+  
14 DOB1-  
22 DOA0+  
21 DOA0-  
V
CC  
13  
MAX3840  
SELB0  
DIB0+  
DIB0-  
SELB1  
20  
V
CC  
MAX3840  
ENA0 29  
DIA1+ 30  
DIA1- 31  
ENA1 32  
12 DOB0+  
11 DOB0-  
19 DOA1+  
18 DOA1-  
V
10  
9
CC  
17  
V
CC  
GND  
1
2
3
4
5
6
7
8
QFN  
THIN QFN  
NOTE: THE EXPOSED PAD MUST BE SOLDERED  
TO THE SUPPLY GROUND.  
NOTE: THE EXPOSED PAD MUST BE SOLDERED  
TO THE SUPPLY GROUND.  
Package Information  
Chip Information  
For the latest package outline information, go to  
TRANSISTOR COUNT: 1200  
PROCESS: Bipolar (SiGe)  
www.maxim-ic.com/packages.  
PACKAGE TYPE  
32 QFN  
DOCUMENT NO.  
21-0091  
32 TQFN  
21-0140  
Revision History  
Rev 1; 11/01: Corrected specification.  
Rev 2; 5/03:  
Rev 3; 5/05:  
Added package code (page 1); updated package drawing (page 10).  
Added lead-free package (pages 1, 2, 8, 11, 12).  
Rev 4; 12/05: Changed input voltage swing from 1.5V  
(max) to 2.0V  
(max).  
P-P  
P-P  
Rev 5; 9/07:  
Added two AC amplitude specifications to increase test coverage for 2.5Gbps and 2.7GHz  
clock inputs (page 3); removed package drawings and added package table (page 8).  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2007 Maxim Integrated Products  
is a registered trademark of Maxim Integrated Products, Inc.  

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