MAX3872_V01 [MAXIM]
Multirate Clock and Data Recovery with Limiting Amplifier;
| 型号： | MAX3872_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multirate Clock and Data Recovery with Limiting Amplifier |
| 文件： | 总15页 (文件大小：1001K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2709; Rev 3; 2/07
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
General Description
Features
♦ Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps,
1.244Gbps, 622.08Mbps, 155.52Mbps,
1.25Gbps/2.5Gbps (Ethernet)
The MAX3872 is a compact, multirate clock and data
recovery with limiting amplifier for OC-3, OC-12, OC-24,
OC-48, OC-48 with FEC SONET/SDH and Gigabit
Ethernet (1.25Gbps/2.5Gbps) applications. Without using
an external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by the recovered clock, providing a clean data
output. An additional serial input (SLBI ) is available for
system loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain a
valid clock output in the absence of data transitions. The
device also includes a loss-of-lock (LOL) output.
♦ Reference Clock Not Required for Data
Acquisition
♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH
Jitter Specifications
♦ 2.7mUI
Jitter Generation
RMS
♦ 10mV
Input Sensitivity Without Threshold
P-P
Adjust
♦ 0.65UI
High-Frequency Jitter Tolerance
170mV Input Threshold Adjust Range
♦ Clock Holdover Capability Using Frequency-
P-P
♦
The MAX3872 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ω back termination on
each line. Its jitter performance exceeds all
SONET/SDH specifications.
Selectable Reference Clock
♦ Serial Loopback Input Available for System
Diagnostic Testing
♦ Loss-of-Lock (LOL) Indicator
The MAX3872 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm x
5mm 32-pin thin QFN with exposed-pad package and
operates over a -40°C to +85°C temperature range.
Applications
Ordering Information
SONET/SDH Receivers and Regenerators
PKG
CODE
PART
TEMP RANGE PIN-PACKAGE
Add/Drop Multiplexers
MAX3872EGJ
-40°C to +85°C 32 QFN-EP*
G3255-1
T3255-3
Digital Cross-Connects
MAX3872ETJ+ -40°C to +85°C 32 TQFN-EP*
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
*EP = Exposed pad.
+Denotes lead-free package.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
+3.3V
CAZ
0.1μF
C
+3.3V +3.3V
FIL
0.82μF
V
CC
FIL VCC_VCO CAZ- CAZ+ FREFSET V
CC
FILTER
OUT+
OUT-
SDI+
MAX3745
SDO+
SDO-
SDI-
CML
CML
IN
SLBI+
SLBI-
MAX3872
GND
SCLKO+
SCLKO-
+3.3V
V
V
CTRL
REF
SYSTEM
LOOPBACK DATA
SIS LREF LOL RS1 RS2 RATESET GND
+3.3V
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multirate Clock and Data Recovery
with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V ..............................................-0.5V to +5.0V
CC
Continuous Power Dissipation (T = +85°C)
A
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-) ..........(V
Input Current Levels
(SDI+, SDI-, SLBI+, SLBI-)............................................ 20mA
CML Output Current
32-Pin QFN (derate 21.3mW/°C above +85°C) .........1384mW
Operating Junction Temperature Range...........-55°C to +150°C
Storage Temperature Range.............................-55°C to +150°C
Processing Temperature (die) .........................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
- 1.0V) to (V
+ 0.5V)
CC
CC
(SDO+, SDO-, SCLKO+, SCLKO-) ............................... 22mA
Voltage at LOL, LREF, SIS, FIL,
RATESET, FREFSET, RS1, RS2,
MAX3872
V
, V
, CAZ+, CAZ-......................-0.5V to (V
+ 0.5V)
CC
CTRL REF
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC A
A
PARAMETER
Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
(Note 2)
175
215
mA
CC
INPUT SPECIFICATIONS (SDI , SLBI )
Single-Ended Input Voltage
Range
V
- 0.8
V
CC
+ 0.4
CC
V
Figure 1
Figure 1
V
IS
V
- 0.4
CC
Input Common-Mode Voltage
V
V
CC
Input Termination to V
R
42.5
50
57.5
Ω
CC
IN
THRESHOLD-SETTING SPECIFICATIONS (SDI )
Differential Input Voltage Range
(SDI )
Threshold adjust enabled
50
600
mV
P-P
Threshold Adjustment Range
Threshold Control Voltage
Threshold Control Linearity
Threshold Setting Accuracy
V
Figure 2
-170
0.3
+170
2.1
mV
TH
V
Figure 2 (Note 3)
V
%
CTRL
5
Figure 2
-18
-6
+18
+6
mV
15mV ≤ |V | ≤ 80mV
TH
Threshold Setting Stability
mV
80mV < |V | ≤ 170mV
-12
-10
2.14
+12
+10
2.24
TH
Maximum Input Current
I
µA
V
CTRL
Reference Voltage Output
V
2.2
REF
CML OUTPUT SPECIFICATIONS (SDO , SCLKO )
CML Differential Output Swing
(Note 4)
600
85
800
100
1000
115
mV
P-P
CML Differential Output
Impedance
R
O
Ω
CML Output Common-Mode
Voltage
V
CC
- 0.2
(Note 4)
V
2
_______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVTTL INPUT/OUTPUT SPECIFICATIONS (LOL, LREF, RATESET, RS1, RS2, FREFSET)
LVTTL Input High Voltage
LVTTL Input Low Voltage
LVTTL Input Current
V
2.0
V
V
IH
V
0.8
IL
-10
2.4
+10
µA
V
LVTTL Output High Voltage
LVTTL Output Low Voltage
V
I
I
= +20µA
= -1mA
OH
OH
OL
V
0.4
V
OL
Note 1: At -40°C, DC characteristics are guaranteed by design and characterization.
Note 2: CML outputs open.
Note 3: Voltage applied to V
pin is from +0.3V to +2.1V when input threshold is adjusted from +170mV to -170mV.
CTRL
Note 4: R = 50Ω to V
.
L
CC
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless otherwise noted.) (Note 5)
CC A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Input Data Rate
Table 2
Differential Input Voltage (SDI )
Differential Input Voltage (SLBI )
V
Threshold adjust disabled, Figure 1 (Note 6)
10
50
1600
800
130
500
2000
0.1
mV
mV
ID
P-P
P-P
-10
BER ≤ 10
OC-3
80
Jitter Transfer Bandwidth
Jitter Peaking
J
OC-12
OC-48
370
kHz
BW
1500
J
f ≤ J
dB
UI
P
BW
f = 100kHz
f = 1MHz
3.1
0.62
0.44
2.9
8.0
0.93
0.65
8.3
Sinusoidal Jitter Tolerance
OC-48
P-P
P-P
P-P
P-P
f = 10MHz
f = 25kHz
f = 250kHz
f = 2.5MHz
f = 6.5kHz
f = 65kHz
f = 650kHz
f = 100kHz
f = 1MHz
Sinusoidal Jitter Tolerance
OC-12
0. 59
0.42
2.9
1.03
0.63
7.8
UI
UI
UI
Sinusoidal Jitter Tolerance
OC-3
0.59
0.42
1.05
0.64
7.1
Sinusoidal Jitter Tolerance with
Threshold Adjust Enabled
OC-48 (Note 7)
0.82
0.54
f = 10MHz
Jitter Generation
J
(Note 8)
2.7
16
15
4.0
mUI
RMS
GEN
100kHz to 2.5GHz
2.5GHz to 4.0GHz
Differential Input Return Loss
(SDI , SLBI )
-20log
| S
dB
|
11
_______________________________________________________________________________________
3
Multirate Clock and Data Recovery
with Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless otherwise noted.) (Note 5)
CC A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CML OUTPUT SPECIFICATIONS (SDO , SCLKO )
Output Edge Speed
t , t
20% to 80%
= 100Ω differential
110
1000
+50
ps
r
f
CML Output Differential Swing
Clock-to-Q Delay
R
600
-50
800
mV
P-P
C
t
(Note 9)
ps
CLK-Q
MAX3872
PLL ACQUISITION/LOCK SPECIFICATIONS
Tolerated Consecutive Identical
Digits
-10
BER ≤ 10
2000
5.5
bits
Acquisition Time
Figure 4 (Note 10)
Figure 4
ms
µs
LOL Assert Time
2.3
100.0
400
Low-Frequency Cutoff for
DC-Offset Cancellation
CAZ = 0.1µF
4
kHz
CLOCK HOLDOVER SPECIFICATIONS
Reference Clock Frequency
Table 3
Maximum VCO Frequency Drift
(Note 11)
ppm
Note 5: AC characteristics are guaranteed by design and characterization.
-10
Note 6: Jitter tolerance is guaranteed (BER ≤ 10 ) within this input voltage range. Input threshold adjust is disabled with VCTRL
connected to V
.
CC
Note 7: Measured at OC-48 data rate using a 100mV
differential swing with a 20mVDC offset and an edge speed of 145ps (4th-
P-P
order Bessel filter with f
= 1.8GHz).
3dB
23
Note 8: Measured with 10mV
differential input, 2 - 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz.
P-P
Note 9: Relative to the falling edge of the SCLKO+ (Figure 3).
Note 10: Measured using a 0.82µF loop-filter capacitor initialized to +3.6V.
Note 11: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock.
Timing Diagrams
V (mV)
TH
V
+ 0.4V
CC
5mV
5mV
+188
800mV
THRESHOLD-SETTING STABILITY
(OVERTEMPERATURE AND POWER SUPPLY)
+170
+152
V
CC
V
CC
- 0.4V
1.3
(a) AC-COUPLED SINGLE-ENDED INPUT
800mV
V
(V)
CTRL
V
CC
0.3
2.10
1.1
THRESHOLD-
SETTING
ACCURACY
(PART-TO-PART
VARIATION OVER
PROCESS)
V
V
- 0.4V
- 0.8V
CC
-152
-170
-188
CC
(b) DC-COUPLED SINGLE-ENDED INPUT
Figure 1. Definition of Input Voltage Swing
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
4
_______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
Timing Diagrams (continued)
DATA
DATA
t
CLK
INPUT DATA
LOL OUTPUT
SCLKO+
SDO
t
CLK-Q
ACQUISITION TIME
LOL ASSERT TIME
Figure 3. Definition of Clock-to-Q Delay
Figure 4. LOL Assert Time and PLL Acquisition Time
Measurement
Typical Operating Characteristics
(V
CC
= +3.3V, T = +25°C, unless otherwise noted.)
A
RECOVERED CLOCK AND DATA
23
RECOVERED CLOCK AND DATA
23
(2.488Gbps, 2 - 1 PATTERN, V = 10mV
)
(2.67Gbps, 2 - 1 PATTERN, V = 10mV
)
IN
P-P
IN
P-P
200mV/
200mV/
div
div
100ps/div
100ps/div
JITTER GENERATION
vs. POWER-SUPPLY WHITE NOISE
RECOVERED CLOCK JITTER
(2.488Gbps)
RECOVERED CLOCK JITTER
(622.08Mbps)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
OC-48
PRBS = 2 - 1
23
0.0
0
5
10
15
20
25
30
10ps/div
10ps/div
WHITE-NOISE AMPLITUDE (mV
)
RMS
TOTAL WIDEBAND RMS JITTER = 1.60ps
PEAK-TO-PEAK JITTER = 12.20ps
TOTAL WIDEBAND RMS JITTER = 2.17ps
PEAK-TO-PEAK JITTER = 15.80ps
_______________________________________________________________________________________
5
Multirate Clock and Data Recovery
with Limiting Amplifier
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, T = +25°C, unless otherwise noted.)
A
JITTER TOLERANCE
JITTER TOLERANCE vs. INPUT AMPLITUDE
JITTER TOLERANCE
vs. INPUT DETERMINISTIC JITTER
23
23
(2.488Gbps, 2 - 1 PATTERN, V = 10mV
)
(2.488Gbps, 2 - 1 PATTERN)
IN
P-P
100
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
23
2
- 1 PATTERN
WITH ADDITIONAL 0.15UI
DETERMINISTIC JITTER
2.488Gbps
= 10mV
P-P
JITTER FREQUENCY = 1MHz
JITTER FREQUENCY = 10MHz
f
= 1MHz
V
IN
JITTER
MAX3872
10
f
= 10MHz
JITTER
1
BELLCORE
MASK
WITH ADDITIONAL 0.15UI
DETERMINISTIC JITTER
0.1
10k
100k
1M
10M
1
10
100
1000
10,000
0
0.05 0.10
0.15 0.20
0.25 0.30
)
JITTER FREQUENCY (Hz)
INPUT AMPLITUDE (mV
)
P-P
DETERMINISTIC JITTER (UI
P-P
BIT-ERROR RATIO
vs. INPUT AMPLITUDE
JITTER TOLERANCE
vs. THRESHOLD ADJUST
JITTER TRANSFER
-2
-3
10
0.5
0
0.7
OC-48
PRBS = 2 - 1
JITTER FREQUENCY = 10MHz
23
10
0.6
-4
-5
10
10
BELLCORE
MASK
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0.5
0.4
0.3
0.2
0.1
V
= 100mV
P-P
IN
2.488Gbps
23
-6
2
- 1 PATTERN
10
-7
-8
-9
10
10
10
INPUT DATA FILTERED BY
A 1870MHz 4TH-ORDER
BESSEL FILTER
C
= 0.82μF
FIL
-10
23
10
10
PRBS = 2 - 1
2.488Gbps
-11
0
0
1
2
3
4
5
1k
10k
100k
1M
10M
10 20
30 40 50 60
70 80 90
INPUT VOLTAGE (mV
)
FREQUENCY (Hz)
P-P
INPUT THRESHOLD (% AMPLITUDE)
SUPPLY CURRENT vs. TEMPERATURE
DIFFERENTIAL S11 vs. FREQUENCY
PULLIN RANGE (RATESET = 0)
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
200
195
190
185
180
175
170
165
160
155
150
145
140
0
-5
-10
-15
-20
-25
-30
-35
-40
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FREQUENCY (GHz)
TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
6
_______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
Pin Description
PIN
NAME
FUNCTION
+3.3V Supply Voltage
1, 4, 27
V
CC
2
3
5
6
7
SDI+
SDI-
Positive Serial Data Input, CML
Negative Serial Data Input, CML
SLBI+
SLBI-
SIS
Positive System Loopback Input or Reference Clock Input, CML
Negative System Loopback Input or Reference Clock Input, CML
Signal Selection Input, LVTTL. Set low for normal operation, set high for system loopback.
Lock to Reference Clock Input, LVTTL. Set high for PLL lock to serial data, set low for PLL lock to
reference clock.
8
LREF
LOL
GND
FIL
9
Loss-of-Lock Output, LVTTL. Active low.
10, 11, 16,
25, 32
Supply Ground
12
13, 18
14
PLL Loop Filter Capacitor Input. Connect a 0.82µF capacitor between FIL and VCC_VCO.
VCC_VCO +3.3V Supply Voltage for the VCO
RS1
RS2
Multirate Select Input 1, LVTTL (Table 2)
Multirate Select Input 2, LVTTL (Table 2)
VCO Frequency Select Input, LVTTL (Table 2)
Negative Serial Clock Output, CML
15
17
RATESET
SCLKO-
SCLKO+
19
20
Positive Serial Clock Output, CML
21, 24
22
VCC_OUT +3.3V Supply Voltage for the CML Outputs
SDO-
SDO+
Negative Serial Data Output, CML
23
Positive Serial Data Output, CML
26
FREFSET
Reference Clock Frequency Select Input, LVTTL (Tables 2 and 3)
Positive Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+
and CAZ-.
28
29
CAZ+
CAZ-
Negative Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+
and CAZ-.
30
31
V
+2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment.
REF
V
Analog Control Input for Threshold Adjustment. Connect to V
to disable threshold adjust.
CTRL
CC
Exposed
Pad
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
EP
_______________________________________________________________________________________
7
Multirate Clock and Data Recovery
with Limiting Amplifier
SLBI Input Amplifier
Detailed Description
The SLBI input amplifier accepts either NRZ loopback
data or a reference clock signal. This amplifier can
The MAX3872 consists of a fully integrated phase-
locked loop (PLL), limiting amplifier with threshold
adjust, DC-offset cancellation loop, data retiming block,
and CML output buffers (Figure 5). The PLL consists of
a phase/frequency detector, a loop filter, and a voltage-
controlled oscillator (VCO) with programmable dividers.
accept a differential input amplitude from 50mV
to
P-P
800mV
.
P-P
Phase Detector
The phase detector incorporated in the MAX3872 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
MAX3872
SDI Input Amplifier
The SDI inputs of the MAX3872 accept serial NRZ data
Frequency Detector
The digital frequency detector (FD) acquires frequency
lock without the use of an external reference clock. The
frequency difference between the received data and
the VCO clock is derived by sampling the in-phase and
quadrature VCO outputs on both edges of the data
input signal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequency
detector.
with a differential input amplitude from 10mV
up
P-P
to1600mV . The input sensitivity is 10mV , at which
P-P
P-P
the jitter tolerance is met for a BER of 10-10 with thresh-
old adjust disabled. The input sensitivity can be as low
as 4mV
and still maintain a BER of 10-10. The
P-P
MAX3872 inputs are designed to directly interface with
a transimpedance amplifier such as the MAX3745.
For applications in which vertical threshold adjustment
is needed, the MAX3872 can be connected to the out-
put of an AGC amplifier such as the MAX3861. When
using the threshold adjust, the input voltage range is
to 600mV . See the Design Procedure sec-
P-P
tion for decision threshold adjust.
50mV
P-P
V
REF
LOL
CAZ+
CAZ-
FIL
RATESET
BANDGAP
REFERENCE
THRESHOLD
ADJUST
V
CTRL
MAX3872
SDI+
SDI-
DC-OFFSET
CANCELLATION
LOOP
AMP
SDO+
SDO-
0
1
D
CML
CML
Q
PHASE AND
FREQUENCY
DETECTOR
SCLKO+
SCLKO-
SLBI+
SLBI-
÷ BY
LOOP
FILTER
AMP
VCO
N
SIS
LREF
LOGIC
FREFSET
RS1
RS2
Figure 5. Functional Diagram
_______________________________________________________________________________________
8
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
Loop Filter
Modes of Operation
The MAX3872 has three operational modes controlled
by the LREF and SIS inputs. The three operational
modes are normal, system loopback, and clock
holdover. Normal operation mode requires a serial data
stream at the SDI input, system loopback mode
requires a serial data stream at the SLBI input, and
clock holdover mode requires a reference clock signal
at the SLBI inputs. See Table 1 for the required LREF
and SIS settings. Once an operational mode is chosen,
the remaining logic inputs (RATESET, RS1, RS2, and
FREFSET) program the input data rate or reference
clock frequency.
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor (C
)
FIL
connected from FIL to VCC_VCO is required to set the
PLL damping ratio. Note that the PLL jitter bandwidth
does not change as the external capacitor changes,
but the jitter peaking, acquisition time, and loop stability
are affected. See the Design Procedure section for
guidelines on selecting this capacitor.
VCOs with Programmable Dividers
The loop filter output controls the two on-chip VCOs.
The VCOs provide low phase noise and are trimmed to
the frequency of 2.488GHz and 2.667GHz. The RATE-
SET pin is used to select the appropriate VCO. The
VCO output is connected to programmable dividers
controlled by inputs RS1 and RS2. See Tables 2 and 3
for the proper settings.
Normal and System Loopback Settings
Three pins (RS1, RS2, and RATESET) are available for
setting the SDI and SLBI input to receive the appropri-
ate data rate. The FREFSET pin can be set to a zero or 1
while in normal or system loopback mode (Table 2).
LOL Monitor
The LOL output indicates a PLL lock failure, either
because of excessive jitter present at the data input or
because of loss of input data. The LOL output is asserted
low when the PLL loses lock.
Clock Frequencies in Holdover Mode
Set the incoming reference clock frequency and outgoing
serial clock frequency by setting RS1, RS2, RATESET,
and FREFSET appropriately (Table 3).
DC-Offset Cancellation Loop
A DC-offset cancellation loop is implemented to remove
the DC offset of the limiting amplifier. To minimize the
low-frequency pattern-dependent jitter associated with
this DC-cancellation loop, the low-frequency cutoff is
10kHz (typ) with CAZ = 0.1µF, connected from CAZ+ to
CAZ-. The DC-offset cancellation loop operates only
when threshold adjust is disabled.
Table 1. Operational Modes
MODE
LREF
SIS
0
Normal
1
1
0
System loopback
Clock holdover
1
1 or 0
Design Procedure
Decision Threshold Adjust
In applications in which the noise density is not bal-
anced between logical zeros and ones (i.e., optical
amplification using EDFA amplifiers), lower bit-error
ratios (BERs) can be achieved by adjusting the input
Table 2. Data Rate Settings
INPUT DATA RATE
RS1 RS2 RATESET FREFSET
(bps)
2.667G
2.488G/2.5G
1.25G/1.244G
666.51M
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
1
0
1
0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
threshold. Varying the voltage at V
from +0.3V to
CTRL
+2.1V achieves a vertical decision threshold adjust-
ment of +170mV to -170mV, respectively (Figure 2).
Use the provided bandgap reference voltage output
(V
) with a voltage-divider circuit or the output of a
REF
622.08M
DAC to set the voltage at V
. V
can be used to
CTRL REF
166.63M
generate the voltage for V
(Figure 10). If threshold
CTRL
adjust is not required, disable it by connecting V
155.52M
CTRL
directly to V
and leave V
floating.
CC
REF
_______________________________________________________________________________________
9
Multirate Clock and Data Recovery
with Limiting Amplifier
Table 3. Holdover Frequency Settings
REFERENCE CLOCK FREQUENCY (MHz)
SCLKO FREQUENCY
RS1
0
RS2
0
RATESET
FREFSET
666.51
666.51
2.667GHz
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
666.51MHz
0
1
666.51
166.63MHz
1
0
622.08/625
622.08/625
622.08
1.244/1.25GHz
2.488GHz/2.5GHz
622.08MHz
1
1
0
0
MAX3872
0
1
622.08
155.52MHz
1
0
166.63
2.67GHz
0
0
166.63
666.51MHz
0
1
166.63
166.63MHz
1
0
155.52/156.25
155.52/156.25
155.52
1.244/1.25GHz
2.488GHz/2.5GHz
622.08MHz
1
1
0
0
0
1
155.52
155.52MHz
1
0
Excessive reduction of C
FIL
X7R or better.
might cause PLL instability.
Setting the Loop Filter
FIL
C
must be a low-TC, high-quality capacitor of type
The MAX3872 is designed for regenerator and receiver
applications. Its fully integrated PLL is a classic 2nd-order
feedback system, with a jitter transfer bandwidth (J
)
BW
below 2.0MHz. The external capacitor (C ) connected
FIL
H (j2πf) (dB)
O
from FIL to VCC_VCO sets the PLL loop damping. Note
that the PLL jitter transfer bandwidth does not change as
FIL
DATA RATE: 2.488Gbps
C
changes, but the jitter peaking, acquisition time, and
loop stability are affected. Figures 6 and 7 show the
open-loop and closed-loop transfer functions.
The PLL zero frequency, f , is a function of external
Z
capacitor C , and can be approximated according to:
FIL
C
= 0.01μF
= 24.5kHz
FIL
f
Z
C
= 0.82μF
FIL
f
Z
= 299Hz
1
f =
Z
2π(650Ω)C
FIL
f (kHz)
100
1000
1
10
For an overdamped system (f / J
< 0.25), the jitter
BW
Z
peaking (J ) of a 2nd-order system can be approximat-
P
Figure 6. Open-Loop Transfer Function
ed by:
⎛
⎞
f
Z
J
= 20log 1+
C
= 0.01μF
P
⎜
⎟
H(j2πf) (dB)
FIL
J
⎝
⎠
BW
0
where J
is the jitter transfer bandwidth for a given
BW
data rate.
-3
C
= 0.82μF
FIL
The recommended value of C = 0.82µF is to guarantee
FIL
a maximum jitter peaking of less than 0.1dB for all data
DATA RATE: 2.488Gbps
rates. Decreasing C
from the recommended value
FIL
decreases acquisition time, with the tradeoff of increased
peaking. For data rates greater than OC-3, C can be
f (kHz)
1
100
10
1000
FIL
less than 0.82µF and still meet the jitter-peaking specifi-
cation.
Figure 7. Closed-Loop Transfer Function
10 ______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
Input Terminations
The SDI and SLBI inputs of the MAX3872 are current-
mode logic (CML) compatible. The inputs all provide
internal 50Ω termination to reduce the required number
of external components. AC-coupling is recommended.
See Figure 8 for the input structure. For additional infor-
mation on logic interfacing, refer to Maxim Application
Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
MAX3872
V
CC
50Ω
50Ω
Output Terminations
The MAX3872 uses CML for its high-speed digital out-
puts (SDO and SCLKO ). The configuration of the out-
put circuit includes internal 50Ω back terminations to
SDO+
SDO-
V
CC
. See Figure 9 for the output structure. CML outputs
can be terminated by 50Ω to V , or by 100Ω differen-
CC
tial impedance. For additional information on logic inter-
facing, refer to Maxim Application Note HFAN 1.0:
Introduction to LVDS, PECL, and CML.
Figure 9. CML Output Model
Applications Information
V
CC
Clock Holdover Capability
Clock holdover is required in some applications in
which a valid clock must be provided to the upstream
device in the absence of data transitions. To provide
this function, an external reference clock signal must
be applied to the SLBI inputs and the proper control
signals set (see the Modes of Operation section). To
enter holdover mode automatically when there are no
transitions applied to the SDI inputs, LOL or the sys-
tem LOS can be directly connected to LREF.
50Ω
50Ω
SDI+
SDI-
System Loopback
The MAX3872 is designed to allow system loopback
testing. When the device is set for system loopback
mode, the serial output data of a transmitter may be
directly connected to the SLBI inputs to run system
diagnostics. See Table 1 for selecting system loopback
operation mode. While in system loopback mode, LREF
should not be connected to LOL.
MAX3872
Figure 8. CML Input Model
______________________________________________________________________________________ 11
Multirate Clock and Data Recovery
with Limiting Amplifier
Pin Configuration
+3.3V
0.1μF
+3.3V +3.3V
TOP VIEW
0.82μF
+3.3V
FIL VCC_VCO CAZ- CAZ+ VCC FREFSET
SDI+
TIA OUTPUT
(2.488Gbps)
MAX3861
AGC AMPLIFIER
V
1
2
3
4
5
6
7
8
24 VCC_OUT
SDI-
SDO+
CC
CML
CML
SLBI+
SLBI-
SDO-
SCLKO+
SCLKO-
SDI+
SDI-
23
22
SDO+
SDO-
MAX3872
MAX3872
V
CTRL
R1
V
CC
21 VCC_OUT
V
REF
155.52MHz
REFERENCE CLOCK
MAX3872
SIS LREF LOL RS1 RS2 RATESET GND
20
19
SLBI+
SLBI-
SIS
SCLKO+
SCLKO-
R2
18 VCC_VCO
17
TTL
R1 + R2 ≥ 50kΩ
LREF
RATESET
Figure 10. Interfacing with the MAX3861 AGC Using Threshold
Adjust
Consecutive Identical Digits (CIDs)
The MAX3872 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER better than 10-10. The CID tolerance
is tested using a 213 - 1 PRBS with long runs of ones
and zeros inserted in the pattern. A CID tolerance of
2000 bits is typical.
5mm x 5mm
QFN
Chip Information
Exposed Pad (EP) Package
The EP 32-pin QFN incorporates features that provide a
very-low thermal-resistance path for heat removal from
the IC. The pad is electrical ground on the MAX3872
and should be soldered to the circuit board for proper
thermal and electrical performance.
TRANSISTOR COUNT: 5142
PROCESS: SiGe BiPOLAR
SUBSTRATE: SOI
Layout Considerations
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3872 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
V
as possible. To reduce feedthrough, isolate the
CC
input signals from the output signals. If a bare die is
used, mount the back of die to ground (GND) potential.
12 ______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 13
Multirate Clock and Data Recovery
with Limiting Amplifier
Package Information (continued)
((The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informa-
tion, go to www.maxim-ic.com/packages
MAX3872
14 ______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
Revision History
Rev 0; 1/03: Initial data sheet release.
Rev 1; 5/03: Updated Ordering Information table (page 1).
Updated package drawing (page 13).
Rev 2; 1/05: Added lead-free package to Ordering Information table (page 1).
Rev 3; 2/07: Updated Typical Application Circuit figure (page 1).
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
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