MAX3880ECB+T [MAXIM]
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-64;
| 型号： | MAX3880ECB+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-64 时钟 |
| 文件： | 总12页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1467; Rev 1; 12/99
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
General Description
Features
The MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low-
voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.
ꢀ Single +3.3V Supply
ꢀ 910mW Operating Power
ꢀ Fully Integrated Clock Recovery and Data
Retiming
ꢀ Exceeds ANSI, ITU, and Bellcore Specifications
The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.
ꢀ Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
ꢀ 2.488Gbps Serial to 155Mbps Parallel Conversion
ꢀ LVDS Data Outputs and Synchronization Inputs
ꢀ Tolerates >2000 Consecutive Identical Digits
ꢀ Loss-of-Lock Indicator
Ordering Information
The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.
PART
TEMP. RANGE
PIN-PACKAGE
MAX3880ECB
*Exposed pad
-40°C to +85°C
64 TQFP-EP*
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Pin Configuration appears at end of data sheet.
Digital Cross-Connects
Typical Application Circuit
+3.3V
0.01µF
PHADJ+
PHADJ-
V
CC
V
CC
PD15+
+3.3V
100Ω*
PD15-
PD0+
V
CC
OUT+
SDI+
SDI-
FIL
OVERHEAD
TERMINATION
MAX3866
PRE/POSTAMPLIFIER
IN+
100Ω*
100Ω*
MAX3880
PD0-
OUT-
LOP
PCLK+
SLBI-
SLBI+
PCLK-
TTL
SYNC+
SYNC-
LOL
TTL
SIS
TTL
FIL-
GND
FIL+
SYSTEM
LOOPBACK
C
F
1µF
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z = 50Ω.
0
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V )...............................-0.5V to +7.0V
Continuous Power Dissipation (T = +85°C)
A
CC
Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-,
TQFP (derate 33.3mW/°C above +85°C).......................1.44W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
SYNC+, SYNC-)........................... (V
- 0.5V) to (V
+ 0.5V)
CC
CC
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................ 10mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL-.................................................-0.5V to (V
+ 0.5V)
CC
Output Current LVDS Outputs ............................................10mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, differential loads = 100Ω 1ꢀ, T = -40°C to +85°C, unless otherwise noted. Typical values are at
A
CC
V
CC
= +3.3V, T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
275
380
mA
CC
SERIAL DATA INPUTS (SDI , SLBI ꢀ
Differential Input Voltage
Single-Ended Input Voltage
Input Termination to Vcc
V
Figure 1
50
800
mVp-p
ID
V
V
- 0.4
V + 0.2
CC
V
IS
CC
R
50
Ω
IN
LVDS INPUTS AND OUTPUTS (SYNC , PCLK , PD_ ꢀ
Input Voltage Range
V
Differential input voltage = 100mV
Common-mode voltage = 50mV
0
2.4
V
mV
mV
Ω
I
Differential Input Threshold
Threshold Hysteresis
V
-100
100
IDTH
HYST
V
78
Differential Input Resistance
Output High Voltage
R
IN
85
100
115
V
OH
1.475
V
Output Low Voltage
V
0.925
250
V
OL
Differential Output Voltage
Figure 2
400
25
mV
|V
OD
|
Change in Magnitude of
Differential Output Voltage for
Complementary States
mV
V
∆|V
|
OD
Output Offset Voltage
V
OS
1.125
40
1.275
25
Change in Magnitude of Output
Offset Voltage for
Complementary States
mV
∆V
OS
Single-Ended Output
Resistance
R
95
140
10
Ω
O
Change in Magnitude of Single-
Ended Output Resistance for
Complementary Outputs
2.5
ꢀ
∆R
O
TTL INPUTS AND OUTPUTS (SIS, LOLꢀ
Input High Voltage
Input Low Voltage
Input Current
V
2.0
V
V
IH
V
0.8
IL
-10
2.4
+10
µA
V
Output High Voltage
Output Low Voltage
V
OH
V
CC
V
OL
0.4
V
2
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, differential loads = 100Ω 1ꢀ, T = -40°C to +85°C, unless otherwise noted. Typical values are at
A
CC
V
CC
= +3.3V, T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.488
155.52
MAX
UNITS
Gbps
Mbps
Serial Data Rate
SDI
Parallel Output Data Rate
Parallel Clock-to-Data Output
Delay
t
Figure 5
200
450
900
ps
CLK-Q
f = 70kHz (Note 2)
f = 100kHz
2.31
1.74
0.38
0.28
3.3
2.41
0.57
0.46
Jitter Tolerance
UIp-p
f = 1MHz
f = 10MHz
Tolerated Consecutive Identical
Digits
>2,000
Bits
dB
100kHz to 2.5GHz
2.5GHz to 4.0GHz
-18
-11
Input Return Loss (SDI , SLBI )
Note 1: AC characteristics are guaranteed by design and characterization.
Note 2: At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency
jitter tolerance outperforms the instrument’s measurement capability.
SDI+
25mV MIN
400mV MAX
SDI-
(SDI+) - (SDI-)
50mVp-p MIN
800mVp-p MAX
V
ID
Figure 1. Input Amplitude
PD+
PD-
V
V
R = 100Ω
L
OD
D
V
V
V
PD-
OH
SINGLE-ENDED OUTPUT
V
OS
OL
| OD|
V
V
PD+
+V
OD
V
- V
PD-
PD+
0V
0V (DIFF)
V
,
= V - V
OD p-p PD+ PD-
DIFFERENTIAL OUTPUT
-V
OD
Figure 2. Driver Output Levels
_______________________________________________________________________________________
3
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
A
CC
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)
SUPPLY CURRENT vs. TEMPERATURE
JITTER TOLERANCE
MAX3880-01
300
10
290
DATA
23
2
- 1 PATTERN
V
= 3.6V
CC
280
270
260
250
240
1
V
= 3.0V
CC
CLOCK
0.1
-50
-25
0
25
50
75
100
1.64ns/div
10
100
1,000
10,000
TEMPERATURE (°C)
JITTER FREQUENCY (kHz)
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
JITTER TOLERANCE vs. INPUT VOLTAGE
BIT ERROR RATE vs. INPUT VOLTAGE
-3
0.8
0.7
10
700
600
JITTER FREQUENCY = 1MHz
-4
10
0.6
0.5
-5
10
500
400
300
200
-6
10
0.4
0.3
0.2
0.1
0
JITTER FREQUENCY
= 5MHz
-7
10
-8
10
-9
10
SONET SPEC
-10
10
10
100
1,000
6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
INPUT VOLTAGE (mVp-p)
-50
-25
0
25
50
75
100
INPUT VOLTAGE (mVp-p)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
PIN
NAME
FUNCTION
1, 17, 25, 33,
41, 49, 56,
62, 64
GND
Ground
2
3
FIL+
FIL-
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
4, 7, 10, 13,
24, 32, 40,
48, 57
V
CC
+3.3V Supply Voltage
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
used.
if not
CC
5
6
PHADJ+
PHADJ-
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
used.
if not
CC
8
9
SDI+
SDI-
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
11
12
SLBI+
SLBI-
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
14
15
16
SIS
Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
SYNC-
SYNC+
Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
18
19
PCLK-
Negative Parallel Clock LVDS Output
Positive Parallel Clock LVDS Output
PCLK+
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
52, 54, 58, 60
PD0- to
PD15-
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PD0+ to
PD15+
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pull-up resistor). The
LOL monitor is valid only when a data stream is present on the inputs to the MAX3880.
63
EP
LOL
Ground. This must be soldered to a circuit board for proper thermal performance (see Package
Information).
Exposed Pad
_______________________________________________________________________________________
5
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
PHADJ+ PHADJ-
FIL+ FIL-
V
CC
50Ω
PD15+
PD15-
Q
D
SDI+
SDI-
LVDS
CK
AMP
16-BIT
DEMULTIPLEXER
MUX
PHASE &
FREQUENCY
DETECTOR
LOOP
FILTER
VCO
SLBI+
SLBI-
PD1+
PD1-
AMP
LVDS
LVDS
50Ω
PD0+
PD0-
V
CC
SIS
MAX3880
SYNC-
PCLK+
PCLK-
CLOCK
DIVIDER
LVDS
LVDS
100Ω
SYNC+
TTL
LOL
Figure 3. MAX3880 Functional Diagram
dissipation by using a fully differential signal architec-
ture and low-noise design techniques. The PLL recov-
ers the serial clock from the serial input data stream.
The demultiplexer generates a 16-bit-wide 155Mbps
parallel data output.
Detailed Description
The MAX3880 deserializer with clock recovery converts
2.488Gbps serial data to 16-bit-wide, 155Mbps parallel
data. The device combines a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
16-bit demultiplexer, clock divider, and LVDS output
buffer (Figure 3). The PLL consists of a phase/frequen-
cy detector (PFD), a loop filter, and a voltage-controlled
oscillator (VCO). The MAX3880 is designed to deliver
the best combination of jitter performance and power
The synchronization inputs (SYNC+, SYNC-) realign the
output data word. Realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. During synchronization, the first
incoming bit of data during that PCLK cycle is
6
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
dropped, shifting the alignment between PCLK and
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on both edges of the data input sig-
nal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
data by 1 bit. The SYNC signal must be at least four
serial bit periods wide (4 x 402ps). See Figure 4 for the
timing diagram and Figure 5 for the timing parameters
diagram.
Input Amplifier
The input amplifiers on both the main data and system
loopback accept a differential input amplitude from
50mVp-p to 800mVp-p. The bit error rate (BER) is bet-
ter than 1 x 10-10 for input signals as small as 9.5mVp-
p, although the jitter tolerance performance will be
degraded. For interfacing with PECL signal levels, see
Applications Information.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. A 1.0µF capacitor, C , is
F
required to set the PLL damping ratio.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency.
Phase Detector
The phase detector in the MAX3880 produces a volt-
age proportional to the phase difference between the
incoming data and the internal clock. Because of its
feedback nature, the PLL drives the error voltage to
zero, aligning the recovered clock to the center of the
incoming data eye for retiming. The external phase
adjust pins (PHADJ+, PHADJ-) allow the user to vary
the internal phase alignment.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is included in the
MAX3880 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency-locked, LOL switches to TTL high in approxi-
mately 800ns.
Note that the LOL monitor is only valid when a data
stream is present on the inputs to the MAX3880. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal.
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
D15 D14
D13
SDI
SYNC
PCLK
D0
D1
D16
D17
D32
D33
D48
D49
D65
D66
(LSB) PD0
PD1
•
•
•
1 BIT HAS SLIPPED
IN THIS TIME SLICE
D15
D31
D47
D64
D80
PD15
(MSB)
TRANSMITTED FIRST
Figure 4. Timing Diagram
_______________________________________________________________________________________
7
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
PCLK
MAX3880
t
CLK-Q
3.3V
PD0–PD15
PHADJ+ (PIN 5)
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-).
PHADJ- (PIN 6)
Figure 5. Timing Parameters
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
Figure 6. Phase-Adjust Resistor-Divider
The MAX3880 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. For proper operation, the parallel clock and
data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-)
require 100Ω differential DC termination between the
positive and negative outputs. Do not terminate these
outputs to ground. The synchronization LVDS inputs
(SYNC+, SYNC-) are internally terminated with 100Ω
differential input resistance and therefore do not require
external termination.
Applications Information
Consecutive Identical Digits (CIDs)
The MAX3880 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER of 1 x 10-10. The CID tolerance is
tested using a 213 - 1 pseudorandom bit stream
(PRBS), substituting a long run of zeros to simulate the
worst case. A CID tolerance of greater than 2,000 bits
is typical.
Phase Adjust
The internal clock is aligned to the center of the data
eye. For specific applications, this sampling position
can be shifted using the PHADJ inputs to optimize BER
performance. The PHADJ inputs operate with differen-
tial input voltages up to 1.5V. A simple resistor-divider
with a bypass capacitor is sufficient to set these levels
(Figure 6). When the PHADJ inputs are not used, they
Design Procedure
Jitter Tolerance and Input
Sensitivity Trade-Offs
When the received data amplitude is higher than
50mVp-p, the MAX3880 provides a typical jitter toler-
ance of 0.46 UI at jitter frequencies greater than
10MHz. The SDH/SONET jitter tolerance specification is
0.15UI, leaving a jitter allowance of 0.31UI for receiver
preamplifier and postamplifier design.
should be tied directly to V
.
CC
System Loopback
The MAX3880 is designed to allow system loopback
testing. The user can connect a serializer output
(MAX3890) in a transceiver directly to the SLBI+ and
SLBI- inputs of the MAX3880 for system diagnostics. To
select the SLBI inputs, apply a TTL logic high to the
SIS pin.
The BER is better than 1 x 10-10 for input signals
greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will
be degraded, but will still be above the SDH/SONET
requirement. Trade-offs can be made between jitter tol-
erance and input sensitivity according to the specific
application. See the Typical Operating Characteristics
for Jitter Tolerance and BER vs. Input Voltage graphs.
8
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Interfacing with PECL Input Levels
When interfacing with differential PECL input levels, it is
important to attenuate the signal while still maintaining
50Ω termination (Figure 7). AC-coupling is also
required to maintain the input common-mode level.
V
CC
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled impedance transmission lines to inter-
face with the MAX3880 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
50Ω
50Ω
0.1µF
0.1µF
25Ω
25Ω
SDI+
SDI-
PECL
LEVELS
100Ω
V
as possible. To reduce feedthrough, take care to
CC
isolate the input signals from the output signals.
Chip Information
MAX3880
TRANSISTOR COUNT: 4102
Figure 7. Interfacing with PECL Input Levels
_______________________________________________________________________________________
9
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Configuration
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
FIL+
FIL-
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
CC
PD10+
PD10-
PD9+
PD9-
PD8+
PD8-
GND
3
V
4
CC
PHADJ+
PHADJ-
5
6
V
CC
7
SDI+
SDI-
8
MAX3880
9
V
CC
V
10
11
12
13
14
15
16
CC
PD7+
PD7-
PD6+
PD6-
PD5+
PD5-
SLBI+
SLBI-
V
CC
SIS
SYNC-
SYNC+
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP-EP
10 ______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Package Information
______________________________________________________________________________________ 11
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX3880ECB+TD
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD-HD, TQFP-64
MAXIM
MAX3880ECB-D
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MS-026ACD-HD, TQFP-64
MAXIM
MAX3880ECB-T
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MS-026ACD-HD, TQFP-64
MAXIM
MAX3880ECB-TD
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MS-026ACD-HD, TQFP-64
MAXIM
MAX3881ECB+D
ATM/SONET/SDH Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-64
MAXIM
MAX3881ECB+TD
Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-64
MAXIM
MAX3881ECB-D
Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, TQFP-64
MAXIM
MAX3881ECB-T
Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, TQFP-64
MAXIM
MAX3881ECB-TD
Clock Recovery Circuit, 1-Func, Bipolar, PQFP64, 10 X 10 MM, 1 MM HEIGHT, TQFP-64
MAXIM
©2020 ICPDF网 联系我们和版权申明