MAX3892 [MAXIM]
+3.3V.2.5Gbps/2.7Gbps.SDH/SONET 4:1 Serializer with Clock Synthesis ; + 3.3V.2.5Gbps / 2.7Gbps.SDH / SONET 4 ： 1串行器，带有时钟合成\n
| 型号： | MAX3892 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +3.3V.2.5Gbps/2.7Gbps.SDH/SONET 4:1 Serializer with Clock Synthesis
|
| 文件： | 总12页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2215; Rev 0; 11/01
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
General Description
Features
The MAX3892 serializer is ideal for converting 4-bit-
wide, 622Mbps parallel data to 2.5Gbps serial data in
DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO
allows for any static delay between the parallel output
clock and parallel input clock. Delay variation up to a
unit interval (UI) is allowed after reset. A fully integrated
phase-locked loop (PLL) synthesizes an internal
2.5GHz serial clock from a 622MHz, 155.5MHz,
77.8MHz, or 38.9MHz reference clock. A selectable
dual VCO allows excellent jitter performance at both
SONET and forward-error correction (FEC) data rates.
ꢀ Single +3.3V Supply
ꢀ 455mW Power Consumption
ꢀ 1.4ps
Maximum Jitter Generation
RMS
ꢀ 4 ✕ 4-Bit FIFO Input Buffer
ꢀ 622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps
Serial Conversion
ꢀ 622MHz/667MHz or 311MHz/333MHz Clock Input
ꢀ On-Chip Clock Synthesizer
Operating from a single 3.3V supply, this device
accepts low-voltage differential-signal (LVDS) clock
and data inputs for interfacing with high-speed digital
circuitry, and delivers current-mode logic (CML) serial
data and clock outputs. A loopback data output is pro-
vided to facilitate system diagnostic testing. The
MAX3892 is available in the extended temperature
range (-40°C to +85°C) in a 44-pin QFN package.
ꢀ Multiple Clock Reference Frequencies:
(622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or
(666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz)
ꢀ LVDS Parallel Clock and Data Inputs
ꢀ CML Serial Data and Clock Outputs
ꢀ Additional CML Output for System Loopback
Testing
Applications
Ordering Information
SONET/SDH OC-48 Transmission Systems
WDM Transponders
PART
TEMP. RANGE
PIN-PACKAGE
Add/Drop Multiplexers
MAX3892EGH
-40°C to +85°C
44 QFN-EP*
Dense Digital Cross-Connects
Backplane Interconnects
*EP = exposed pad
Typical Application Circuit
V
CC
LVPECL
V
CC
C
Z
100Ω
RCLK- RCLK+ FIL
V
CC
CLKSET MODE RATESET
CML
CML
LVDS
MAX3273
SDO+
SDO-
PDI0+
PDI0-
SCLKO+
SCLKO-
LASER
DRIVER
SONET/SDH
FRAMER
PDI3+
PDI3-
SLBEN
TTL
MAX3892
SLBPD
LVDS
LVDS
CML
SLBO+
SLBO-
PCLKI+
PCLKI-
MAX3882 †
1:4 DESERIALIZER
WITH CDR
OPTIONAL
FOR
PCLKO+
SYSTEM
LOOPBACK
TEST
PCLKO-
RESET
FIFOERROR
LOL
†
Future product
THIS SYMBOL REPRESENTS A TRANSMISSION
LINE OF CHARACTERISTIC IMPEDANCE Z = 50Ω.
O
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V , VCCO, VCCVCO.....................-0.5V to +5V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
All Inputs and FIL .......................................-0.5V to (V
LVDS Output Voltage (PCLKO )................-0.5V to (V
+ 0.5V)
+ 0.5V)
CC
CC
CML Output Current (SDO , SCLKO , SLꢁO )................22mA
Continuous Power Dissipation (T = +85°C)
A
44-Pin QFN (derate 25mW/°C above +85°C) ............1625mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, differential LVDS load = 100Ω 1ꢀ, T = +25°C,
CC A
CC
A
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
(Note 2)
138
190
mA
CC
LVDS INPUT SPECIFICATIONS (PDI[3..0] , PCLKI )
Input Voltage Range
V
0
2400
117
mV
mV
µA
mV
Ω
I
Differential Input Voltage
Input Common-Mode Current
Threshold Hysteresis
|V
ID
|
100
LVDS input V = 1.2V
61
45
OS
Differential Input Resistance
R
83
100
IN
LVPECL INPUT SPECIFICATIONS (RCLK )
V
1.16
-
V
0.88
-
CC
CC
Input High Voltage
Input Low Voltage
V
V
V
IH
V
1.81
-
V
1.48
-
CC
CC
V
IL
Input ꢁias Voltage
V
- 1.3
V
CC
Single-Ended Input Resistance
Differential Input Voltage Swing
>1.0
kΩ
300
1900
1.475
400
mVp-p
LVDS OUTPUT SPECIFICATIONS (PCLKO )
Output High Voltage
Output Low Voltage
V
V
V
OH
V
0.925
250
OL
Differential Output Voltage
|V
|
mV
OD
Change in Magnitude of
Differential Output Voltage for
Complementary States
∆|V
|
|
25
mV
V
OD
Offset Output Voltage
1.125
1.275
25
Change in Magnitude of Output
Offset Voltage for Complementary
States
∆|V
mV
OS
2
_______________________________________________________________________________________
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, differential LVDS load = 100Ω 1ꢀ, T = +25°C,
CC
A
CC A
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
140
12
UNITS
Ω
Differential Output Resistance
Output Current
80
Shorted together
Shorted to ground
mA
Output Current
40
mA
CML OUTPUT SPECIFICATIONS (SDO , SCLKO , SLꢁO )
Differential Output
R = 100Ω differential
640
83
800
100
1000
117
mVp-p
L
Differential Output Resistance
Output Common-Mode Voltage
Ω
R = 50Ω to V
V - 0.2
CC
V
L
CC
LVTTL SPECIFICATIONS (RESET, RATESET, SLꢁEN, SLꢁPD FIFOERROR, LOL)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
2.0
V
V
IH
V
0.8
+10
+10
IL
I
-30
-50
2.4
µA
µA
V
IH
I
IL
V
I
I
= 20µA
= 1mA
V
CC
OH
OH
OL
V
0.4
V
OL
PROGRAMMING INPUTS (CLKSET, MODE)
Input Current
Input = 0 or V
-500
+500
µA
CC
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, differential LVDS loads = 100Ω 1ꢀ, CML loads =
CC
A
CC
50Ω 1ꢀ, T = +25°C, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL INPUT SPECIFICATIONS (PDI , PCLKI )
RATESET = GND
RATESET = V
622
666
622
311
Parallel Input Data Rate
Parallel Input Clock Rate
Mbps
MHz
CC
MODE = OPEN or V
CC
MODE = SHORT or 30kΩ to GND
Parallel Input Setup Time
Parallel Input Hold Time
t
(Note 4)
(Note 4)
-94
ps
ps
SU
t
300
H
PARALLEL CLOCK OUTPUT SPECIFICATIONS (PCLKO )
Parallel Clock Output Rise/Fall
Time
t , t
r
20ꢀ to 80ꢀ
100
46
200
54
ps
ꢀ
f
Parallel Clock Output Duty Cycle
SERIAL OUTPUT SPECIFICATIONS (SDO , SCLKO )
RATESET = GND
2.488
2.666
Serial Output Data Rate
Gbps
RATESET = V
20ꢀ to 80ꢀ
(Note 5)
CC
Serial Data Output Rise/Fall Time
Serial Output Clock to Data Delay
t , t
80
25
ps
ps
r
f
t
-25
CLK-Q
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, differential LVDS loads = 100Ω 1ꢀ, CML loads =
CC
A
CC
50Ω 1ꢀ, T = +25°C, unless otherwise noted.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1.4
1.4
19
UNITS
Serial Clock Output Jitter
Generation
JG
RJ
DJ
(Note 6)
1.2
ps
RMS
ps
RMS
Serial Data Output Random Jitter
Serial Data Output Deterministic
Jitter
(Note 7)
ps
p-p
REFERENCE CLOCK INPUT SPECIFICATIONS (RCLK)
Reference Clock Frequency
Tolerance
100
30
ppm
ꢀ
Reference Clock Input Duty Cycle
70
RESET INPUTS (RESET)
Minimum Pulse Width of FIFO
Reset
UI is PCLKO period
4
1
UI
UI
Tolerated Drift ꢁetween PCLKI
and PCLKO After Reset
UI is PCLKO period
Note 1: Specifications at -40°C are guaranteed by design and characterization.
Note 2: Measured with SLꢁO/CLK622 and SCLK outputs disabled and CML outputs open.
Note 3: AC characteristics are guaranteed by design and characterization.
Note 4: In 622MHz clock mode, the parallel data is clocked in by the rising edge of the 622MHz/666MHz parallel clock input. In the
311MHz clock mode, the parallel data is clocked in on both the rising and falling edges of the clock. The parallel input
setup and hold time increases by 60ps if the duty cycle is between 48ꢀ to 52ꢀ in 311MHz mode (Figure 1).
Note 5: Relative to the falling edge of the SCLKO.
Note 6: Measurement bandwidth is ꢁW = 12kHz to 20MHz.
Note 7: Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured using a 27 - 1 PRꢁS pattern with
96 consecutive identical digits.
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Typical Operating Characteristics
(V
= +3.3V, CML loads AC-coupled to 50Ω 1ꢀ, T = +25°C, unless otherwise noted.)
A
CC
POWER-SUPPLY JITTER GENERATION
vs. RIPPLE FREQUENCY
ELECTRICAL EYE DIAGRAM
SUPPLY CURRENT vs. TEMPERATURE
MAX3892 toc02
170
40
35
30
165
160
155
150
145
140
135
130
125
120
13
PATTERN 2 -1 PRBS
25
20
DATA RATE = 2.5Gbps
15
10
5
100mVp-p
50mVp-p
0
50ps/div
-40 -20
0
20
40
60
80 100
10
100
1k
10k
TEMPERATURE (°C)
RIPPLE FREQUENCY (Hz)
JITTER GENERATION vs. POWER SUPPLY
NOISE AMPLITUDE (BW = 2MHz)
SERIAL-DATA OUTPUT JITTER
MAX3892 toc05
5.0
f
= 622MHz
RCLK
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5ps/div
0
50
100
150
200
250
TOTAL WIDEBAND RMS JITTER = 1.3ps
PEAK-TO-PEAK JITTER = 15.8ps
NOISE AMPLITUDE (Vp-p)
Pin Description
PIN
NAME
FUNCTION
1, 16, 22, 27,
33, 44
GND
Supply Ground
Supply Voltage for Outputs +3.3V. Add bypass capacitors near these pins before connecting to
the V power plane.
2, 5, 8, 11
VCCO
CC
3
4
6
7
SCLKO-
SCLKO+
SDO-
Negative Serial Clock Output, CML 2.488GHz or 2.666GHz
Positive Serial Clock Output, CML 2.488GHz or 2.666GHz
Negative Serial Data Output, CML 2.488Gbps or 2.666Gbps
Positive Serial Data Output, CML 2.488Gbps or 2.666Gbps
SDO+
_______________________________________________________________________________________
5
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Pin Description (continued)
PIN
NAME
FUNCTION
Negative System Loop-ꢁack Output or 622MHz/666MHz Clock Output. Select CML data or clock
as shown in Table 1.
9
SLꢁO-
Positive System Loop-ꢁack Output or 622MHz/666MHz Clock Output. Select CML data or clock as
shown in Table 1.
10
12
13
14
SLꢁO+
SLꢁPD
System Loopback Power Down, TTL Input. SLPD = high activates the system loopback output
driver; SLꢁPD = low powers down the loop-back output driver
System Loop-ꢁack Enable Input, TTL Input. SLꢁEN = high activates the system loop-back output;
SLꢁEN = lowactivates the 622MHz/666MHz reference clock output.
SLꢁEN
FIFO Reset, TTL Input. An active-high reset recenters the FIFO to tolerate maximum skew between
PCLKI and PCLKO.
RESET
FIFO Error Indicator, TTL Output. Active high when the read/write clocks access the same FIFO
address. This signal may be used to control RESET.
15
17, 28, 36, 41
18
FIFOERROR
V
Supply Voltage, +3.3V
CC
Loss of Lock, TTL Output. An active low indicates that the VCO and reference frequency differ by
500ppm.
LOL
Clock Control Input:
MODE = GND; f
= 311.04MHz/333MHz with SCLKO active
PCLKI
19
MODE
MODE = 30kΩ to GND; f
= 311.04MHz/333MHz with SCLKO off
PCLKI
MODE = OPEN (float); f
= 622.08MHz/666MHz with SCLKO off
PCLKI
MODE = V ; f
= 622.08MHz/666MHz with SCLKO active
CC PCLKI
Positive Parallel Clock, LVDS Input. Data is written to the input register on the clock rising edge in
622Mbps mode and on both rising and falling edges in 311Mbps mode (Figure 1).
20
21
PCLKI+
PCLKI-
Negative Parallel Clock, LVDS Input (Figure 1).
PDI3+ to
PDI0+
23, 25, 29, 31
Positive Data Inputs, LVDS (622Mbps or 666Mbps)
PDI3- to
PDI0-
24, 26, 30, 32
Negative Data Inputs, LVDS (622Mbps or 666Mbps)
34
35
37
38
PCLKO+
PCLKO-
RCLK+
RCLK-
Positive Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz.
Negative Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz.
Positive Reference Clock Input, LVPECL
Negative Reference Clock Input, LVPECL
Reference Clock Rate Programming Pin:
CLKSET = V ; RCLK = 622.08MHz/666MHz
CC
39
CLKSET
CLKSET = OPEN (float); RCLK = 155.52MHz/167MHz
CLKSET = 30kΩ to GND; RCLK = 77.76MHz/83.3MHz
CLKSET = GND; RCLK = 38.88MHz/41.6MHz
40
42
RATESET
FIL
Data Rate Select, TTL Input. RATESET = high for 2.666Gbps, RATESET = low for 2.488Gbps.
PLL Capacitor Pin. Connect a 0.1µF capacitor from this pin to VCCVCO.
Supply Voltage for VCO +3.3V. Add bypass capacitors near this pin before connecting to the V
power plane.
CC
43
EP
VCCVCO
Exposed
Paddle
The exposed paddle must be soldered to ground for proper thermal and electrical operation.
6
_______________________________________________________________________________________
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
PECL Inputs
Detailed Description
The reference clock (RCLK+, RCLK-) has PECL inputs
The MAX3892 converts 4-bit-wide, 622Mbps/667Mbps
for interfacing to a crystal oscillator with AC or DC con-
data to 2.5Gbps/2.7Gbps serial data (Figure 2). Data is
loaded into the 4:1 MUX through a 4 ✕ 4-bit FIFO buffer
for wide tolerance to clock skew. Clock and data inputs
are LVDS levels while high-speed serial outputs are
CML. An internal PLL frequency synthesizer generates
a serial clock from a low-speed reference clock.
nections. The RCLK inputs are self-biasing to V
-
CC
1.3V for AC-coupled inputs. Only a 100Ω differential
termination resistance must be added when inputs are
AC-coupled.
Current-Mode Logic Outputs
The 2.5Gbps/2.7Gbps data, clock, and system loop-
back outputs (SDO+, SDO-, SCLKO+, SCLKO-,
SLꢁO+, SLꢁO-) of the MAX3892 are designed using
current-mode logic (CML). The configuration of the
MAX3892 CML output circuit includes internal 50Ω
Low-Voltage Differential-Signal
Inputs and Outputs
The MAX3892 has LVDS inputs and outputs for inter-
facing with high-speed digital circuitry. The LVDS stan-
dard is based on the IEEE 1596.3 LVDS specification.
This technology uses differential low-voltage swings to
achieve fast transition times, minimized power dissipa-
tion, and noise immunity. For proper operation, the par-
allel clock LVDS outputs (PCLKO+, PCLKO-) require
100Ω differential DC termination between the positive
and negative outputs. Do not terminate these outputs to
ground. The parallel data and parallel clock LVDS
inputs (PDI+, PDI-, PCLKI+, PCLKI-) are internally ter-
minated with 100Ω differential input resistance, and
therefore do not require external termination.
back termination to V
(Figure 3). These outputs are
intended to drive a 50Ω transmission line terminated
CC
with a matched load impedance.
FIFO Buffer
Data is latched into the MAX3892 by the parallel input
clock PCLKI. The parallel input clock serves as the
FIFO write clock. The parallel output clock PCLKO acts
as the FIFO read clock that loads the 4:1 MUX. The
FIFO allows the read and write clocks to vary by up to
1UI. Conditions that result in the read and write clock
accessing the same FIFO address are indicated by
1.608ns
DATA
PDI_
IN
622MHz
CLOCK
311MHz
CLOCK
PCLKI+ - PCLKI-
T
T
T
T
H
SU
H
SU
DATA
OUT
SDO
D3 D2 D1 D0
t
CLK-Q
2.5GHz
CLOCK
SCLKO
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK0 = (PCLK0+) - (PCLKO-).
*PDI3 = D3; PDI2 = D2...PDI0 = D0. PDI3 IS THE MSB AND IS TRANSMITTED FIRST.
THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL
INPUT DATA AND SERIAL OUTPUT DATA.
Figure 1. Timing Diagram
_______________________________________________________________________________________
7
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Table 1. Loop-Back Operation Mode
Table 3. Setting the Clock Mode
PCLKI
FREQUENCY
(MHz)
SCLKO
FREQUENCY
(GHz)
SLBPD
SLBEN
SLBO OUTPUT
MODE
RATESET
V
X
Power-Down SLꢁO Output
IL
622MHz/667MHz Clock
Output
V
V
V
666Hz
622Hz
666Hz
622Hz
2.666
2.488
IH
IH
IL
CC
V
CC
GND
2.5Gbps/2.7Gbps System
Loop-ꢁack Output
V
V
V
Disabled
Disabled
IH
CC
OPEN
GND
30kΩ
to
GND
V
333Hz
Disabled
CC
Table 2. Setting the Reference Clock
Frequency
GND
311Hz
333Hz
311Hz
Disabled
2.666
V
CC
CLKSET
RATESET RCLK FREQUENCY (MHz)
GND
GND
2.488
V
666
622
CC
V
CC
GND
This reference clock can provide a clock hold-over sig-
nal to a clock and data recovery (CDR) circuit in the
event of loss of signal (LOS).
V
166.5
155.52
83.25
77.76
41.63
38.88
CC
OPEN
30kΩ to GND
GND
GND
V
CC
Design Procedure
GND
Clock Mode Selection
The frequencies of the MAX3892 can be set up using
CLKSET, RATESET, and MODE as shown in Tables 2
and 3.
V
CC
GND
latching high FIFOERROR. To clear this condition,
RESET must be asserted high for at least 4UI. FIFOER-
ROR may be tied directly to the RESET input to recen-
ter the FIFO. After reset, the full elastic range of the
FIFO is available again.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3892 clock and data inputs and
outputs.
Frequency Synthesizer
The PLL synthesizes a 2.5Gbps/2.7Gbps clock (SCLKO) from
an external reference clock. The PLL reference clock (RCLK)
may be 622.08MHz/666.53MHz, 155.52MHz/166.6MHz,
77.76MHz/83.3MHz or 38.88MHz/41.65MHz as determined
by CLKSET and RATESET. See Table 2 for the reference fre-
quency selection. The parallel output clock PCLKO is also
derived from the synthesizer to be SCLKO divided by 4. A
TTL-compatible loss-of-lock indicator, LOL, goes low when the
VCO is unable to lock to the reference frequency. Frequency
difference on RCLK with respect to the divided down SCLKO
greater than 500ppm is indicated by a low state on LOL.
When the frequency difference between the clocks is less
than 250ppm, LOL high indicates a lock condition.
Exposed-Pad Package
The EP 44-pin QFN incorporates features that provide a
very low thermal-resistance path for heat removal from
the IC to a PC board. The MAX3892’s EP must be sol-
dered directly to a ground plane with good thermal
conductance.
System Loopback
The MAX3892 is designed to allow system loop-back
testing. The loop-back outputs (SLꢁO+, SLꢁO-) of the
MAX3892 may be directly connected to the loop-back
inputs of a deserializer (such as the MAX3882) for sys-
tem diagnostics. Alternatively, the SLꢁO pins can be
programmed to provide a 622MHz reference clock.
8
_______________________________________________________________________________________
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
FIFOERROR RESET
PDI[3..0]+
MAX3892
4
D
LVDS
LVDS
SDO+
SDO-
PDI[3..0]-
PCLKI+
4-BIT
REG
4 x 4
FIFO
4:1
MUX
CML
CLK
WR/RD
PCLKI-
SLBO+
SLBO-
PCLKO+
CML
CML
LVDS
PCLKO-
SLBPD
SLBEN
RCLK+
RCLK-
SCLKO+
FREQUENCY
GENERATOR
LVPECL
SCLKO-
LOGIC
MODE
CLKSET
RATESET LOL
Figure 2. Functional Diagram
V
CC
V
CC
50Ω
50Ω
50Ω
50Ω
OUTPUT CIRCUIT
INPUT CIRCUIT
Figure 3. Current-Mode Logic
_______________________________________________________________________________________
9
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
V
OD
V
V
OH
OL
|V
|
SINGLE-ENDED OUTPUT
V
OD
OS
+V
(VPD+) - (VPD-)
DIFFERENTIAL OUTPUT
OD
0 (DIFF)
V
ODp-p
-V
OD
Figure 4. Differential Output Levels
Pin Configuration
Chip Information
TRANSISTOR COUNT: 6210
TOP VIEW
GND
VCCO
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
GND
PDI0-
PDI0+
PDI1-
PDI1+
SCLKO-
SCLKO+
VCCO
SDO-
V
CC
MAX3892
SDO+
GND
PDI2-
PDI2+
PDI3-
PDI3+
VCCO
SLBO-
SLBO+ 10
VCCO 11
QFN
*THE EXPOSED PADDLE MUST BE SOLDERED TO SUPPLY
GROUND ON THE CIRCUIT BOARD.
10 ______________________________________________________________________________________
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Package Information
______________________________________________________________________________________ 11
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX3892EGH-T
ATM/SONET/SDH Serial to Parallel/Parallel to Serial Converter, 1-Func, Bipolar, QFN-44
MAXIM
MAX3892EGH-TD
ATM/SONET/SDH Serial to Parallel/Parallel to Serial Converter, 1-Func, Bipolar, QFN-44
MAXIM
MAX3892ETH+T
Serial to Parallel/Parallel to Serial Converter, 1-Func, Bipolar, ROHS COMPLIANT, TQFN-44
MAXIM
©2020 ICPDF网 联系我们和版权申明